1
®
ADS7808
12-Bit 10µs Serial CMOS Sampling
ANALOG-to-DIGITAL CONVERTER
FEATURES
●100kHz SAMPLING RATE
●72dB SINAD WITH 45kHz INPUT
●±1/2 LSB INL AND DNL
●SIX SPECIFIED INPUT RANGES
●SERIAL OUTPUT
●SINGLE +5V SUPPLY OPERATION
●PIN-COMPATIBLE WITH 16-BIT ADS7809
●USES INTERNAL OR EXTERNAL
REFERENCE
●100mW MAX POWER DISSIPATION
●20-PIN 0.3" PLASTIC DIP AND SOIC
●SIMPLE DSP INTERFACE
ADS7808
DESCRIPTION
The ADS7808 is a complete 12-bit sampling analog-
to-digital using state-of-the-art CMOS structures. It
contains a 12-bit capacitor-based SAR A/D with S/H,
reference, clock, and a serial data interface. Data can
be output using the internal clock, or can be synchro-
nized to an external data clock. The ADS7808 also
provides an output synchronization pulse for ease of
use with standard DSP processors.
The ADS7808 is specified at a 100kHz sampling rate,
and guaranteed over the full temperature range. Laser-
trimmed scaling resistors provide various input ranges
including ±10V and 0V to 5V, while an innovative
design operates from a single +5V supply, with power
dissipation under 100mW.
The 20-pin ADS7808 is available in a plastic 0.3" DIP
and in an SOIC, both fully specified for operation over
the industrial –40°C to +85°C range.
10kΩ
CDAC
4kΩ
20kΩ
5kΩ
Internal
+2.5V Ref
Clock
BUSY
Data Clock
Serial Data
Successive Approximation Register and Control Logic
Serial
Data
Out
Comparator
Buffer
20kΩ
R/C CS
R1
IN
R2
IN
R3
IN
REF
Power Down
CAP
ADS7808
ADS7808
®
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1992 Burr-Brown Corporation PDS-1155B Printed in U.S.A. January 1997
®
ADS7808 2
SPECIFICATIONS
ELECTRICAL
At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors as shown in Figure 4, unless otherwise specified.
ADS7808P, U ADS7808PB, UB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
RESOLUTION 12 ✻Bits
ANALOG INPUT
Voltage Ranges ±10V, 0V to 5V, etc. (See Table I)
Impedance See Table I
Capacitance 35 ✻pF
THROUGHPUT SPEED
Conversion Time 5.7 8 ✻✻µs
Complete Cycle Acquire and Convert 10 ✻µs
Throughput Rate 100 ✻kHz
DC ACCURACY
Integral Linearity Error ±0.9 ±0.45 LSB(1)
Differential Linearity Error ±0.9 ±0.45 LSB
No Missing Codes Guaranteed ✻
Transition Noise(2) 0.1 ✻LSB
Full Scale Error(3,4) ±0.5 ±0.25 %
Full Scale Error Drift ±7±5 ppm/°C
Full Scale Error(3,4) Ext. 2.5000V Ref ±0.5 ±0.25 %
Full Scale Error Drift Ext. 2.5000V Ref ±2✻ppm/°C
Bipolar Zero Error(3) Bipolar Ranges ±10 ✻mV
Bipolar Zero Error Drift Bipolar Ranges ±2±2 ppm/°C
Unipolar Zero Error(3) 0V to 10V Range ±5✻mV
0V to 4V Range ±3✻mV
0V to 5V Range ±3✻mV
Unipolar Zero Error Drift Unipolar Ranges ±2✻ppm/°C
Recovery to Rated Accuracy 1µF Capacitor to CAP 1 ✻ms
after Power Down
Power Supply Sensitivity +4.75V < VD < +5.25V ±0.5 ✻LSB
(VDIG = VANA = VD)
AC ACCURACY
Spurious-Free Dynamic Range fIN = 45kHz 80 90 ✻✻ dB(5)
Total Harmonic Distortion fIN = 45kHz –90 –80 ✻✻dB
Signal-to-(Noise+Distortion) fIN = 45kHz 70 73 72 ✻dB
Signal-to-Noise fIN = 45kHz 70 73 72 ✻dB
Full-Power Bandwidth(6) 250 ✻kHz
SAMPLING DYNAMICS
Aperture Delay 40 ✻ns
Aperture Jitter Sufficient to meet AC specs ✻ns
Transient Response FS Step 2 ✻µs
Overvoltage Recovery(7) 150 ✻ns
REFERENCE
Internal Reference Voltage No Load 2.48 2.5 2.52 ✻✻✻ V
Internal Reference Source Current 1 ✻µA
(Must use external buffer)
External Reference Voltage Range 2.3 2.5 2.7 ✻✻✻ V
for Specified Linearity
External Reference Current Drain Ext. 2.5000V Ref 100 ✻µA
DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.8 ✻✻V
V
IH +2.0 VD +0.3V ✻✻V
IIL VIL = 0V ±10 ✻µA
IIH VIH = 5V ±10 ✻µA
3
®
ADS7808
DIGITAL OUTPUTS
Data Format
Data Coding
Pipeline Delay
Data Clock
Internal EXT/INT LOW 2.3 ✻MHz
(Output Only When
Transmitting Data)
External EXT/INT HIGH 0.1 10 ✻✻MHz
(Can Run Continually)
VOL ISINK = 1.6mA +0.4 ✻V
VOH ISOURCE = 500µA+4 ✻V
Leakage Current High-Z State, ±5✻µA
VOUT = 0V to VDIG
Output Capacitance High-Z State 15 15 pF
POWER SUPPLIES
Specified Performance
VDIG Must be ≤ VANA +4.75 +5 +5.25 ✻**V
V
ANA +4.75 +5 +5.25 ✻**V
I
DIG 0.3 * mA
IANA 16 * mA
Power Dissipation: PWRD LOW VDIG = VANA = 5V, fS = 100kHz 100 * mW
PWRD HIGH 50 * µW
TEMPERATURE RANGE
Specified Performance –40 +85 * * °C
Derated Performance –55 +125 * * °C
Storage –65 +150 * * °C
Thermal Resistance (
θ
JA)
Plastic DIP 75 * °C/W
SOIC 75 * °CW
NOTES: (1) LSB means Least Significant Bit. For the ±10V input range, one LSB is 4.88mV. (2) Typical rms noise at worst case transitions and temperatures. (3)
As measured with fixed resistors in Figure 4. Adjustable to zero with external potentiometer. (4) For bipolar input ranges, full scale error is the worst case of –Full
Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes
the effect of offset error. For unipolar input ranges, full scale error is the deviation of the last code transition divided by the transition voltage. It also includes the
effect of offset error. (5) All specifications in dB are referred to a full-scale ±10V input. (6) Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-
to (Noise + Distortion) degrades to 60dB. (7) Recovers to specified performance after 2 x FS input overvoltage.
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-Brown
Corporation recommends that this integrated circuit be handled
and stored using appropriate ESD protection methods.
SPECIFICATIONS (CONT)
ELECTRICAL
At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 4, unless otherwise specified.
ADS7808P/U ADS7808PB/UB
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Analog Inputs: R1IN .......................................................................... ±25V
R2IN .......................................................................... ±25V
R3IN .......................................................................... ±25V
CAP .....................................VANA+0.3V to AGND2 –0.3V
REF ....................................... Indefinite Short to AGND2,
Momentary Short to VANA
Ground Voltage Differences: DGND, AGND2 .................................±0.3V
VANA ...................................................................................................... 7V
VDIG to VANA ....................................................................................... +0.3
VDIG ....................................................................................................... 7V
Digital Inputs .............................................................–0.3V to VDIG +0.3V
Maximum Junction Temperature .................................................. +165°C
Internal Power Dissipation ............................................................ 700mW
Lead Temperature (soldering, 10s) .............................................. +300°C
ABSOLUTE MAXIMUM RATINGS
ORDERING INFORMATION
MINIMUM
MAXIMUM SIGNAL-TO- SPECIFICATION
LINEARITY (NOISE + DISTORTION) TEMPERATURE
PRODUCT ERROR (LSB) RATIO(dB) RANGE (°C) PACKAGE
ADS7808P ±0.9 70 –40°C to +85°C 20-Pin Plastic DIP
ADS7808PB ±0.45 72 –40°C to +85°C 20-Pin Plastic DIP
ADS7808U ±0.9 70 –40°C to +85°C 20-Pin SOIC
ADS7808UB ±0.45 72 –40°C to +85°C 20-Pin SOIC
PACKAGE INFORMATION
PACKAGE DRAWING
PRODUCT PACKAGE NUMBER(1)
ADS7808P 20-Pin Plastic DIP 222
ADS7808PB 20-Pin Plastic DIP 222
ADS7808U 20-Pin SOIC 221
ADS7808UB 20-Pin SOIC 221
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
Serial 12 bits
Binary Two's Complement or Straight Binary
Conversion results only available after completed conversion.
Selectable for internal or external data clock
®
ADS7808 4
PIN # NAME DESCRIPTION
PIN ASSIGNMENTS
PIN CONFIGURATION
V
DIG
V
ANA
PWRD
BUSY
CS
R/C
TAG
DATA
DATACLK
SYNC
R1
IN
AGND1
R2
IN
R3
IN
CAP
REF
AGND2
SB/BTC
EXT/INT
DGND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
ADS7808
ANALOG CONNECT R1IN CONNECT R2IN
INPUT VIA 200ΩVIA 100ΩCONNECT R3IN
RANGE TO TO TO IMPEDANCE
±10V VIN AGND CAP 22.9kΩ
±5V AGND VIN CAP 13.3kΩ
±3.33 VIN VIN CAP 10.7kΩ
0V to 10V AGND VIN AGND 13.3kΩ
0V to 5V AGND AGND VIN 10.0kΩ
0V to 4V VIN AGND VIN 10.7kΩ
TABLE I. Input Range Connections. See Figure 4 for
complete information.
1R1
IN Analog Input. See Table I and Figure 4 for input range connections.
2 AGND1 Analog Ground. Used internally as ground reference point. Minimal current flow.
3R2
IN Analog Input. See Table I and Figure 4 for input range connections.
4R3
IN Analog Input. See Table I and Figure 4 for input range connections.
5 CAP Reference Buffer Capacitor. 2.2µF Tantalum to ground.
6 REF Reference Input/Output. Outputs internal 2.5V reference. Can also be driven by external system reference. In both cases,
bypass to ground with a 2.2µF Tantalum capacitor.
7 AGND2 Analog Ground.
8 SB/BTC Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be output in a Straight Binary format. If
LOW, data will be output in a Binary Two’s complement format.
9 EXT/INT Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized to the clock input on DATACLK. If
LOW, a convert command will initiate the transmission of the data from the previous conversion, along with 12 clock pulses output
on DATACLK.
10 DGND Digital Ground.
11 SYNC Synch Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on CS with R/C HIGH will output a
pulse on SYNC synchronized to the external DATACLK.
12 DATACLK Either an input or an output depending on the EXT/INT level. Output data will be synchronized to this clock. If EXT/INT is LOW,
DATACLK will transmit 12 pulses after each conversion, and then remain LOW between conversions.
13 DATA Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the level of SB/BTC. In the external clock
mode, after 12-bits of data, the ADS7808 will output the level input on TAG as long as CS is LOW and R/C is HIGH (see Figure 3.) If
EXT/INT is LOW, data will be valid on both the rising and falling edges of DATACLK, and between conversions DATA will stay at the
level of the TAG input when the conversion was started.
14 TAG Tag Input for use in external clock mode. If EXT/INT is HIGH, digital data input on TAG will be output on DATA with a delay of 12
DATACLK pulses as long as CS is LOW and R/C is HIGH. See Figure 3.
15 R/C Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion.
When EXT/INT is LOW, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is HIGH, a
rising edge on R/C with CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the transmission of
data from the previous conversion.
16 CS Chip Select. Internally OR’ed with R/C.
17 BUSY Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the
output shift register. CS or R/C must be HIGH when BUSY rises, or another conversion will start without time for signal acquisition.
18 PWRD Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous
conversion are maintained in the output shift register.
19 VANA Analog Supply Input. Nominally +5V. Connect directly to pin 20, and decouple to ground with 0.1µF ceramic and 10µF Tantalum
capacitors.
20 VDIG Digital Supply Input. Nominally +5V. Connect directly to pin 19. Must be ≤ VANA.
5
®
ADS7808
FIGURE 1. Basic Conversion Timing.
MODE Acquire
t
4
t
5
t
1
t
3
t
7
t
6
Convert Acquire
t
2
BUSY
CS, R/C
TABLE II. Conversion and Data Timing TA = –40°C to
+85°C.
FIGURE 2. Serial Data Timing Using Internal Clock. (CS, EXT/INT and TAG Tied LOW.)
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t1Convert Pulse Width 40 4500 ns
t2BUSY Delay 65 ns
t3BUSY LOW 8 µs
t4BUSY Delay after 220 ns
End of Conversion
t5Aperture Delay 40 ns
t6Conversion Time 5.7 8 µs
t7Acquisition Time 2 µs
t6 + t7Throughput Time 9 10 µs
t8R/C LOW to DATACLK Delay 450 ns
t9DATACLK Period 440 ns
t10 Data Valid to DATACLK 20 75 ns
HIGH Delay
t11 Data Valid after 100 125 ns
DATACLK LOW Delay
t12 External DATACLK Period 100 ns
t13 External DATACLK HIGH 20 ns
t14 External DATACLK LOW 30 ns
t15 DATACLK HIGH 20 t12 + 5 ns
Setup Time
t16 R/C to CS 10 ns
Setup Time
t17 SYNC Delay After 15 35 ns
DATACLK HIGH
t18 Data Valid Delay 25 55 ns
t19 CS to Rising Edge Delay 25 ns
t20 Data Available after CS LOW 4.5 µs
1
MSB Valid
R/C
DATACLK
SDATA
t
8
t
11
t
10
t
9
2 3 11 12
Bit 10 Valid Bit 1 ValidBit 9 Valid LSB Valid
t
2
t
3
BUSY
®
ADS7808 6
HEX HEX
DESCRIPTION BINARY CODE CODE BINARY CODE CODE
Full-Scale Range ±10 ±5±3.33V 0V to 5V 0V to 10V 0V to 4V
Least Significant Bit (LSB) 4.88mV 2.44mV 1.63mV 1.22mV 2.44mV 0.98mV
+Full Scale (FS – 1LSB) 9.99512V 4.99756V 3.33171V 4.99878V 9.99756V 3.99902V 0111 1111 1111 7FF 1111 1111 1111 FFF
Midscale 0V 0V 0V 2.5V 5V 2V 0000 0000 0000 000 1000 0000 0000 800
One LSB Below Midscale –4.88mV –2.44mV –1.63mV 2.49878V 4.99756V 1.99902V 1111 1111 1111 FFF 0111 1111 1111 7FF
–Full Scale –10V –5V –3.333333V 0V 0V 0V 1000 0000 0000 800 0000 0000 0000 000
BINARY TWO’S
COMPLEMENT STRAIGHT BINARY
(SB/BTC LOW) (SB/BTC HIGH)
Initiate Conversion and
Output Data Using External
Clock
Power Down
Selecting Output Format
Incorrect Conversions
SPECIFIC FUNCTION CS R/C BUSY EXT/INT DATACLK PWRD SB/BTC OPERATION
Initiate Conversion and 1>0 0 1 0 Output 0 x Initiates conversion “n”. Data from conversion “n–1”
Output Data Using clocked out on DATA synchronized to 12 clock
Internal Clock pulses output on DATACLK.
0 1>0 1 0 Output 0 x Initiates conversion “n”. Data from conversion “n–1”
clocked out on DATA synchronized to 12 clock
pulses output on DATACLK.
1>0 0 1 1 Input 0 x Initiates conversion “n”.
0 1>0 1 1 Input 0 x Initiates conversion “n”.
1>0 1 1 1 Input x x Outputs a pulse on SYNC followed by data from
conversion “n” clocked out synchronized to external
DATACLK.
1>0 1 0 1 Input 0 x Outputs a pulse on SYNC followed by data from
conversion “n–1” clocked out synchronized to
external DATACLK.(1) Conversion “n” in process.
0 0>1 0 1 Input 0 x Outputs a pulse on SYNC followed by data from
conversion “n–1” clocked out synchronized to
external DATACLK .(1) Conversion “n” in process.
0 0 0>1 x x 0 x CS or R/C must be HIGH or a new conversion will
be initiated without time for acquisition.
x x x x x 0 x Analog circuitry powered. Conversion can proceed.
x x x x x 1 x Analog circuitry disabled. Data from previous
conversion maintained in output registers.
x x x x x x 0 Serial data is output in Binary Two’s Complement
format.
x x x x x x 1 Serial data is output in Straight Binary format.
NOTE: (1) See Figure 3b for constraints on previous data valid during conversion.
Table III. Control Truth Table.
ANALOG INPUT
DIGITAL OUTPUT
Table IV. Output Codes and Ideal Input Voltages.
7
®
ADS7808
FIGURE 3a. Conversion and Read Timing with External Clock. (EXT/INT Tied HIGH). Read After Conversion.
EXTERNAL
DATACLK
CS
0
Bit 11 (MSB)
R/C
BUSY
DATA
TAG
SYNC
12 34 1314
Bit 10 Bit 1 Bit 0 (LSB) Tag 0 Tag 1
Tag 1 Tag 2 Tag 11 Tag 12 Tag 13 Tag 14Tag 0 Tag 15
t
19
t
18
t
17
t
12
t
16
t
16
t
2
t
12
t
13
t
14
t
15
t
1
®
ADS7808 8
FIGURE 3b. Conversion and Read Timing with External Clock. (EXT/INT Tied HIGH.) Read During Conversion (Previous
Conversion Results).
EXTERNAL
DATACLK
CS
Bit 11 (MSB)
R/C
BUSY
DATA
TAG
SYNC
Bit 0 (LSB) Tag 0 Tag 1
Tag 1 Tag 12 Tag 13 Tag 14 Tag 15
Tag 0
t
19
t
18
t
17
t
12
t
16
t
2
t
12
t
13
t
14
t
1
t
20
t
15
9
®
ADS7808
With Trim
Input Range Without Trim (Adjust offset first at 0V, then adjust gain)
FIGURE 4a. Offset/Gain Circuits for Unipolar Input Ranges.
0V – 10V
0V – 5V
0V – 4V
200Ω
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
R3
IN
100Ω
2.2µF
2.2µF
V
IN
33.2kΩ
+
+
200Ω
AGND2
REF
CAP
R2IN
AGND1
R1IN
VIN
R3IN
100Ω
33.2kΩ
2.2µF
2.2µF
+
+
200Ω
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
R3
IN
100Ω
2.2µF
V
IN
+5V
+5V
33.2kΩ
2.2µF
576kΩ
50kΩ
50kΩ
+
+
200Ω
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
V
IN
R3
IN
100Ω
33.2kΩ
2.2µF
2.2µF
+5V
50kΩ50kΩ576kΩ
+5V +
+
200Ω
AGND2
REF
CAP
R2IN
AGND1
R1IN
R3IN
100Ω
2.2µF
2.2µF
VIN
33.2kΩ
+
+
200Ω
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
R3
IN
100Ω
2.2µF
V
IN
+5V
+5V
33.2kΩ
576kΩ
50kΩ
50kΩ2.2µF +
+
®
ADS7808 10
200Ω
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
R3
IN
100Ω
2.2µF
V
IN
+5V
+5V
33.2kΩ
2.2µF
576kΩ
50kΩ
50kΩ
+
+
200Ω
AGND2
REF
CAP
R2IN
AGND1
R1IN
R3IN
100Ω
2.2µF
2.2µF
VIN
33.2kΩ
+
+
200Ω
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
V
IN
R3
IN
100Ω
33.2kΩ
2.2µF
2.2µF
+5V
50kΩ
50kΩ576kΩ
+5V
+
+
With Trim
Input Range Without Trim (Adjust offset first at 0V, then adjust gain)
±10V
±5V
±3.33V
FIGURE 4b. Offset/Gain Circuits for Bipolar Input Ranges.
200Ω
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
V
IN
R3
IN
100Ω
33.2kΩ
2.2µF
2.2µF
+
+
200Ω
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
V
IN
R3
IN
33.2kΩ
2.2µF
2.2µF
100Ω
+
+
200Ω
AGND2
REF
CAP
R2
IN
AGND1
R1
IN
V
IN
R3
IN
33.2kΩ2.2µF
2.2µF
100Ω
+5V
50kΩ+5V
50kΩ576kΩ
+
+
