FEATURES True 16-bit voltage output DAC, 0.5 LSB INL 8 nV/Hz output noise spectral density 0.00625 LSB long-term linearity error stability 0.018 ppm/C gain error temperature coefficient 2.5 s output voltage settling time 3.5 nV-sec midscale glitch impulse Integrated precision reference buffers Operating temperature range: -40C to +125C 4 mm x 5 mm LFCSP package Wide power supply range of up to 16.5 V 35 MHz Schmitt triggered digital interface 1.8 V-compatible digital interface FUNCTIONAL BLOCK DIAGRAM VCC VDD VREFP A1 IOVCC SDIN SCLK SYNC SDO INPUT SHIFT REGISTER AND CONTROL LOGIC CLR DAC REG RFB RFB 16 16-BIT DAC VOUT 6k POWER-ON RESET AND CLEAR LOGIC DGND VSS AD5760 AGND VREFN Figure 1. APPLICATIONS Medical instrumentation Test and measurement Industrial control Scientific and aerospace instrumentation Data acquisition systems Digital gain and offset adjustment Power supply control R1 INV 16 LDAC RESET 6.8k 6.8k 09650-001 Data Sheet Ultra Stable, 16-Bit 0.5 LSB INL, Voltage Output DAC AD5760 Table 1. Related Devices Part No. AD5790 AD5791 AD5780 AD5781 AD5541A/AD5542A Description 20-bit, 2 LSB accurate DAC 20-bit, 1 LSB accurate DAC 18-bit, 1 LSB accurate DAC 18-bit, 0.5 LSB INL 16-bit, 1 LSB accurate 5 V DAC GENERAL DESCRIPTION The AD57601 is a true 16-bit, unbuffered voltage output DAC that operates from a bipolar supply of up to 33 V. The AD5760 accepts a positive reference input range of 5 V to VDD - 2.5 V and a negative reference input range of VSS + 2.5 V to 0 V. The AD5760 offers a relative accuracy specification of 0.5 LSB maximum range, and operation is guaranteed monotonic with a 0.5 LSB DNL maximum range specification. The part uses a versatile 3-wire serial interface that operates at clock rates of up to 35 MHz and is compatible with standard SPI, QSPITM, MICROWIRETM, and DSP interface standards. The part incorporates a power-on reset circuit that ensures that the DAC output powers up to 0 V in a known output impedance state and remains in this state until a valid write to the device takes place. The part provides an output clamp feature that places the output in a defined load state. 1 PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. True 16-bit accuracy. Wide power supply range of up to 16.5 V. -40C to +125C operating temperature range. Low 8 nV/Hz noise. Low 0.018 ppm/C gain error temperature coefficient. COMPANION PRODUCTS Output Amplifier Buffer: AD8675, ADA4898-1, ADA4004-1 External Reference: ADR445 DC-to-DC Design Tool: ADIsimPowerTM Additional companion products on the AD5780 product page Protected by U.S. Patent No. 7,884,747. Other patents pending. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2011-2012 Analog Devices, Inc. All rights reserved. AD5760 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DAC Architecture....................................................................... 20 Applications....................................................................................... 1 Serial Interface ............................................................................ 20 Functional Block Diagram .............................................................. 1 Hardware Control Pins.............................................................. 21 General Description ......................................................................... 1 On-Chip Registers...................................................................... 22 Product Highlights ........................................................................... 1 AD5760 Features ............................................................................ 25 Companion Products ....................................................................... 1 Power-On to 0 V......................................................................... 25 Revision History ............................................................................... 2 Configuring the AD5760 .......................................................... 25 Specifications..................................................................................... 3 DAC Output State ...................................................................... 25 Timing Characteristics ................................................................ 5 Output Amplifier Configuration.............................................. 25 Absolute Maximum Ratings............................................................ 8 Applications Information .............................................................. 27 ESD Caution.................................................................................. 8 Typical Operating Circuit ......................................................... 27 Pin Configuration and Function Descriptions............................. 9 Evaluation Board ........................................................................ 28 Typical Performance Characteristics ........................................... 11 Outline Dimensions ....................................................................... 29 Terminology .................................................................................... 19 Ordering Guide .......................................................................... 29 Theory of Operation ...................................................................... 20 REVISION HISTORY 2/12--Rev. A to Rev. B Deleted Linearity Compensation Section ..................................... 3 12/11--Rev. 0 to Rev. A Changes to Table 2............................................................................ 3 Changes to Figure 48...................................................................... 18 Changes to DAC Register Section ................................................ 22 Changes to Table 10 and Table 11 ................................................ 23 11/11--Revision 0: Initial Version Rev. B | Page 2 of 32 Data Sheet AD5760 SPECIFICATIONS VDD = +12.5 V to +16.5 V, VSS = -16.5 V to -12.5 V, VREFP = +10 V, VREFN = -10 V, VCC = 2.7 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE 2 Resolution Integral Nonlinearity Error (Relative Accuracy) Differential Nonlinearity Error Long-Term Linearity Error Stability 3 Full-Scale Error Full-Scale Error Temperature Coefficient Zero-Scale Error Zero-Scale Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient R1, RFB Matching OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Output Noise Spectral Density Output Voltage Noise Midscale Glitch Impulse4 MSB Segment Glitch Impulse4 Output Enabled Glitch Impulse Digital Feedthrough DC Output Impedance (Normal Mode) DC Output Impedance (Output Clamped to Ground) Min A, B Versions 1 Typ Max 16 -0.5 +0.5 -2 -0.5 -1 +2 +0.5 +1 -0.75 -1.4 -2.5 0.00625 0.2 0.17 0.1 0.026 +0.75 +1.4 +2.5 Unit Test Conditions/Comments Bits LSB B grade, VREFx = 10 V, +10 V and +5 V LSB LSB LSB LSB LSB LSB LSB ppm/C A grade, VREFx = 10 V, +10 V and +5 V B grade, VREFx = 10 V, +10 V and +5 V A grade, VREFx = 10 V, +10 V and +5 V After 750 hours at TA = 135C VREFP = +10 V, VREFN = -10 V VREFP = 10 V, VREFN = 0 V VREFP = 5 V, VREFN = 0 V VREFP = +10 V, VREFN = -10 V -1.2 -2.5 -5.2 0.0812 0.044 0.056 0.025 +1.2 +2.5 +5.2 LSB LSB LSB ppm/C VREFP = +10 V, VREFN = -10 V VREFP = 10 V, VREFN = 0 V VREFP = 5 V, VREFN = 0 V VREFP = +10 V, VREFN = -10 V -19 -35 -68 2.3 1.9 0.9 0.018 0.015 +19 +35 +68 ppm FSR ppm FSR ppm FSR ppm/C % VREFP = +10 V, VREFN = -10 V VREFP = 10 V, VREFN = 0 V VREFP = 5 V, VREFN = 0 V VREFP = +10 V, VREFN = -10 V VREFP 2.5 V s 3.5 8 8 1.1 s nV/Hz nV/Hz V p-p 14 3.5 4 14 3.5 4 57 0.27 3.4 nV-sec nV-sec nV-sec nV-sec nV-sec nV-sec nV-sec nV-sec k 6 k VREFN Rev. B | Page 3 of 32 10 V step to 0.02%, using the ADA4898-1 buffer in unity-gain mode 125 code step to 1 LSB 4 At 1 kHz, DAC code = midscale At 10 kHz, DAC code = midscale DAC code = midscale, 0.1 Hz to 10 Hz bandwidth VREFP = +10 V, VREFN = -10 V VREFP = 10 V, VREFN = 0 V VREFP = 5 V, VREFN = 0 V VREFP = +10 V, VREFN = -10 V, see Figure 43 VREFP = 10 V, VREFN = 0 V, see Figure 44 VREFP = 5 V, VREFN = 0 V, see Figure 45 On removal of output ground clamp AD5760 Parameter REFERENCE INPUTS VREFP Input Range VREFN Input Range Input Bias Current Input Capacitance LOGIC INPUTS Input Current 5 Input Low Voltage, VIL Input High Voltage, VIH Pin Capacitance LOGIC OUTPUT (SDO) Output Low Voltage, VOL Output High Voltage, VOH High Impedance Leakage Current High Impedance Output Capacitance POWER REQUIREMENTS VDD VSS VCC IOVCC IDD ISS ICC IOICC DC Power Supply Rejection Ratio AC Power Supply Rejection Ratio Data Sheet Min 5 VSS + 2.5 -20 -4 A, B Versions 1 Typ Max -0.63 -0.63 1 -1 VDD - 2.5 0 +20 +4 Unit V V nA pF +1 0.3 x IOVCC A V V pF 0.4 V V A pF 0.7 x IOVCC 5 IOVCC - 0.5 1 3 Test Conditions/Comments TA = 0C to 105C VREFP, VREFN IOVCC = 1.71 V to 5.5 V IOVCC = 1.71 V to 5.5 V IOVCC = 1.71 V to 5.5 V, sinking 1 mA IOVCC = 1.71 V to 5.5 V, sourcing 1 mA All digital inputs at DGND or IOVCC 7.5 VDD - 33 2.7 1.71 10.3 -10 600 52 7.5 1.5 90 90 VSS + 33 -2.5 5.5 5.5 14 -14 900 140 1 V V V V mA mA A A V/V V/V dB dB IOVCC VCC SDO disabled VDD 10%, VSS = -15 V VSS 10%, VDD = 15 V VDD 200 mV, 50 Hz/60 Hz, VSS = -15 V VSS 200 mV, 50 Hz/60 Hz, VDD = 15 V Temperature range: -40C to +125C, typical conditions: TA = 25C, VDD = +15 V, VSS = -15 V, VREFP = +10 V, VREFN = -10 V. Performance characterized with the AD8675ARZ output buffer. Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified. 4 The AD5760 is configured in unity-gain mode with a low-pass RC filter on the output. R = 300 , C = 143 pF (total capacitance seen by the output buffer, lead capacitance, and so forth). 5 Current flowing in an individual logic pin. 2 3 Rev. B | Page 4 of 32 Data Sheet AD5760 TIMING CHARACTERISTICS VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 1 2 Limit 1 IOVCC = 1.71 V to 3.3 V IOVCC = 3.3 V to 5.5 V 40 28 92 60 15 10 9 5 5 5 2 2 48 40 8 6 9 7 12 7 13 10 20 16 14 11 130 130 130 130 50 50 140 140 0 0 65 60 62 45 0 0 35 35 150 150 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns typ ns typ ns min ns typ ns min ns max ns max ns min ns typ ns typ Test Conditions/Comments SCLK cycle time SCLK cycle time (readback and daisy-chain modes) SCLK high time SCLK low time SYNC to SCLK falling edge setup time SCLK falling edge to SYNC rising edge hold time Minimum SYNC high time SYNC rising edge to next SCLK falling edge ignore Data setup time Data hold time LDAC falling edge to SYNC falling edge SYNC rising edge to LDAC falling edge LDAC pulse width low LDAC falling edge to output response time SYNC rising edge to output response time (LDAC tied low) CLR pulse width low CLR pulse activation time SYNC falling edge to first SCLK rising edge SYNC rising edge to SDO tristate (CL = 50 pF) SCLK rising edge to SDO valid (CL = 50 pF) SYNC rising edge to SCLK rising edge ignore RESET pulse width low RESET pulse activation time All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modes. Rev. B | Page 5 of 32 AD5760 Data Sheet t7 t1 SCLK 1 2 24 t3 t6 t2 t4 t5 SYNC t9 t8 SDIN DB23 DB0 t10 t12 t11 LDAC t13 VOUT t14 VOUT t15 CLR t16 VOUT t21 RESET 09650-002 t22 VOUT Figure 2. Write Mode Timing Diagram t1 t17 SCLK 1 2 24 t3 t6 t20 t7 1 2 24 t2 t5 t4 t5 t17 SYNC SDIN t9 DB23 DB0 INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION t18 t19 DB23 SDO REGISTER CONTENTS CLOCKED OUT Figure 3. Readback Mode Timing Diagram Rev. B | Page 6 of 32 DB0 09650-003 t8 Data Sheet AD5760 SCLK t20 t1 t17 1 2 24 t3 t6 26 25 48 t2 t5 t4 SYNC SDIN t9 DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N - 1 INPUT WORD FOR DAC N t19 SDO DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N UNDEFINED Figure 4. Daisy-Chain Mode Timing Diagram Rev. B | Page 7 of 32 t18 09650-004 t8 AD5760 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Parameter VDD to AGND VSS to AGND VDD to VSS VCC to DGND IOVCC to DGND Digital Inputs to DGND VOUT to AGND VREFP to AGND VREFN to AGND DGND to AGND Operating Temperature Range, TA Industrial Storage Temperature Range Maximum Junction Temperature, TJ max Power Dissipation LFCSP Package JA Thermal Impedance Lead Temperature Soldering ESD (Human Body Model) Rating -0.3 V to +34 V -34 V to +0.3 V -0.3 V to +34 V -0.3 V to +7 V -0.3 V to VCC + 3 V or +7 V (whichever is less) -0.3 V to IOVCC + 0.3 V or +7 V (whichever is less) -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V VSS - 0.3 V to +0.3 V -0.3 V to +0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance integrated circuit with an ESD rating of 1.6 kV, and it is ESD sensitive. Proper precautions must be taken for handling and assembly. ESD CAUTION -40C to +125C -65C to +150C 150C (TJ max - TA)/JA 31.0C/W JEDEC industry standard J-STD-020 1.6 kV Rev. B | Page 8 of 32 Data Sheet AD5760 24 23 22 21 20 INV DNC DNC DNC RFB PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD5760 TOP VIEW (Not to Scale) 19 18 17 16 15 14 13 AGND VSS VSS VREFN DGND SYNC SCLK NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. NEGATIVE ANALOG SUPPLY CONNECTION (VSS). A VOLTAGE IN THE RANGE OF -16.5 V TO -2.5 V CAN BE CONNECTED. VSS SHOULD BE DECOUPLED TO AGND. THE PADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION IS MADE AT THE VSS PINS. IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. 09650-005 VCC 8 IOVCC 9 DNC 10 SDO 11 SDIN 12 VOUT 1 VREFP 2 VDD 3 RESET 4 VDD 5 CLR 6 LDAC 7 Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3, 5 Mnemonic VOUT VREFP VDD 4 6 RESET CLR 7 LDAC 8 9 VCC IOVCC 10, 21, 22, 23 11 12 DNC SDO SDIN 13 SCLK 14 SYNC 15 16 17, 18 DGND VREFN VSS 19 AGND Description Analog Output Voltage. Positive Reference Voltage Input. A voltage in the range of 5 V to VDD - 2.5 V can be connected to this pin. Positive Analog Supply Connection. A voltage in the range of 7.5 V to 16.5 V can be connected to this pin. VDD must be decoupled to AGND. Active Low Reset. Asserting this pin returns the AD5760 to its power-on status. Active Low Input. Asserting this pin sets the DAC register to a user defined value (see Table 12) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. Active Low Load DAC Logic Input. This pin is used to update the DAC register and, consequently, the analog output. When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. Do not leave the LDAC pin unconnected. Digital Supply. Voltage range is from 2.7 V to 5.5 V. VCC should be decoupled to DGND. Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. Voltage range is from 1.71 V to 5.5 V. Do Not Connect. Do not connect to these pins. Serial Data Output. Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 35 MHz. Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks. The DAC is updated on the rising edge of SYNC. Ground Reference Pin for Digital Circuitry. Negative Reference Voltage Input. Negative Analog Supply Connection. A voltage in the range of -16.5 V to -2.5 V can be connected to this pin. VSS must be decoupled to AGND. Ground Reference Pin for Analog Circuitry. Rev. B | Page 9 of 32 AD5760 Pin No. 20 24 EPAD Data Sheet Mnemonic RFB INV VSS Description Feedback Connection for External Amplifier. See the AD5760 Features section for further details. Inverting Input Connection for External Amplifier. See the AD5760 Features section for further details. Negative Analog Supply Connection (VSS). A voltage in the range of -16.5 V to -2.5 V can be connected to this pin. VSS must be decoupled to AGND. The paddle can be left electrically unconnected provided that a supply connection is made at the VSS pins. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance. Rev. B | Page 10 of 32 Data Sheet AD5760 TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.10 VREFP = +5V VREFN = 0V VDD = +15V 0.05 VSS = -15V VREFP = +10V VREFN = -10V VDD = +15V VSS = -15V 0.08 0.06 0 0.02 INL (LSB) 0 -0.02 -0.05 -0.10 -0.04 -0.06 -0.15 -0.08 0 10000 20000 30000 40000 50000 60000 70000 DAC CODE Figure 6. Integral Nonlinearity Error vs. DAC Code, 10 V Span 0.15 -0.20 09650-006 -0.10 AD8675 OUTPUT BUFFER TA = 25C 0 10000 20000 30000 40000 50000 60000 70000 DAC CODE Figure 9. Integral Nonlinearity Error vs. DAC Code, 5 V Span, x2 Gain Mode 0.10 VREFP = +10V VREFN = 0V VDD = +15V VSS = -15V 0.10 AD8675 OUTPUT BUFFER TA = 25C 09650-009 INL (LSB) 0.04 VREFP = +10V VREFN = -10V VDD = +15V VSS = -15V 0.08 0.06 0.05 DNL (LSB) INL (LSB) 0.04 0 0.02 0 -0.02 -0.04 -0.05 -0.08 0 10000 20000 30000 40000 50000 60000 70000 DAC CODE -0.10 0.20 30000 40000 50000 60000 70000 DNL (LSB) 0.10 -0.05 -0.10 0.05 0 -0.15 -0.05 0 10000 20000 30000 40000 50000 60000 70000 DAC CODE Figure 8. Integral Nonlinearity Error vs. DAC Code, 5 V Span -0.10 AD8675 OUTPUT BUFFER TA = 25C 0 10000 20000 30000 40000 50000 60000 70000 DAC CODE Figure 11. Differential Nonlinearity Error vs. DAC Code, 10 V Span Rev. B | Page 11 of 32 09650-011 AD8675 OUTPUT BUFFER TA = 25C 09650-008 INL (LSB) 20000 VREFP = +10V VREFN = 0V VDD = +15V VSS = -15V 0.15 0 -0.20 10000 Figure 10. Differential Nonlinearity Error vs. DAC Code, 10 V Span VREFP = +5V VREFN = 0V VDD = +15V VSS = -15V 0.05 0 DAC CODE Figure 7. Integral Nonlinearity Error vs. DAC Code, 10 V Span 0.10 AD8675 OUTPUT BUFFER TA = 25C 09650-010 AD8675 OUTPUT BUFFER TA = 25C 09650-007 -0.10 -0.06 AD5760 Data Sheet 0.10 0.09 VREFP = +5V VREFN = 0V VDD = +15V VSS = -15V 0.08 0.06 VDD = +15V VSS = -15V AD8675 OUTPUT BUFFER 0.07 DNL ERROR (LSB) 0.02 0 -0.02 -0.04 0.05 50000 60000 70000 DAC CODE -0.01 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 09650-014 40000 09650-012 -0.08 AD8675 OUTPUT BUFFER TA = 25C -0.10 0 10000 20000 30000 Figure 15. Differential Nonlinearity Error vs. Temperature Figure 12. Differential Nonlinearity Error vs. DAC Code, 5 V Span 0.08 AD8675 OUTPUT BUFFER 0.09 T = 25C A INL MAX 0.06 0.07 0.04 INL ERROR (LSB) 0.05 DNL (LSB) 10V SPAN MIN INL +10V SPAN MIN INL +5V SPAN MIN INL 0.01 -0.06 0.03 0.01 -0.01 10000 20000 30000 40000 50000 60000 TA = 25C VREFP = +10V VREFN = -10V AD8675 OUTPUT BUFFER 0 -0.02 -0.04 INL MIN -0.08 70000 DAC CODE -0.1.0 12.5 09650-013 0 0.02 -0.06 VREFP = +5V VREFN = 0V VDD = +15V VSS = -15V -0.03 -0.05 10V SPAN MAX INL +10V SPAN MAX INL +5V SPAN MAX INL 0.03 Figure 13. Differential Nonlinearity Error vs. DAC Code, 5 V Span, x2 Gain Mode 13.0 13.5 14.0 14.5 15.0 VDD/|VSS| (V) 15.5 16.0 16.5 09650-016 DNL (LSB) 0.04 Figure 16. Integral Nonlinearity Error vs. Supply Voltage, 10 V Span 0.20 0.15 VDD = +15V VSS = -15V AD8675 OUTPUT BUFFER 0.15 0.10 INL MAX INL ERROR (LSB) 0.05 10V SPAN MAX INL +10V SPAN MAX INL +5V SPAN MAX INL 0 10V SPAN MIN INL +10V SPAN MIN INL +5V SPAN MIN INL -0.05 0.05 0 TA = 25C VREFP = 5V VREFN = 0V AD8675 OUTPUT BUFFER -0.05 INL MIN -0.10 -0.15 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 Figure 14. Integral Nonlinearity Error vs. Temperature -0.15 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VDD/|VSS| (V) Figure 17. Integral Nonlinearity Error vs. Supply Voltage, 5 V Span Rev. B | Page 12 of 32 09650-017 -0.10 09650-015 INL ERROR (LSB) 0.10 Data Sheet AD5760 0.8 0.09 DNL MAX 0.6 ZERO-SCALE ERROR (LSB) 0.07 TA = 25C VREFP = +10V VREFN = -10V AD8675 OUTPUT BUFFER 0.05 0.04 0.03 0.02 0.01 13.0 13.5 14.0 14.5 15.0 VDD/|VSS| (V) 15.5 16.0 16.5 0 -0.4 7.5 09650-018 -0.01 12.5 0.2 -0.2 DNL MIN 0 0.4 Figure 18. Differential Nonlinearity Error vs. Supply Voltage, 10 V Span 14.5 15.5 16.5 -0.04 0.06 TA = 25C VREFP = 5V VREFN = 0V AD8675 OUTPUT BUFFER 0.03 0.02 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5 VDD/|VSS| (V) 09650-019 DNL MIN 0 -0.06 -0.07 -0.08 -0.09 -0.10 T = 25C A VREFP = +10V -0.11 V REFN = -10V AD8675 OUTPUT BUFFER -0.12 12.5 13.0 13.5 14.0 14.5 15.0 VDD/|VSS| (V) 0.01 -0.01 7.5 -0.05 Figure 19. Differential Nonlinearity Error vs. Supply Voltage, 5 V Span 0.4 MIDSCALE ERROR (LSB) 0.3 0.05 0 0.2 0.1 0 -0.1 -0.2 -0.3 -0.05 14.0 14.5 15.0 VDD/|VSS| (V) 15.5 16.0 16.5 09650-020 -0.4 13.5 16.5 0.5 TA = 25C VREFP = +10V VREFN = -10V 0.10 AD8675 OUTPUT BUFFER 13.0 16.0 Figure 22. Midscale Error vs. Supply Voltage, 10 V Span 0.15 -0.10 12.5 15.5 09650-022 MIDSCALE ERROR (LSB) DNL ERROR (LSB) 11.5 12.5 13.5 VDD/|VSS| (V) -0.03 DNL MAX 0.07 ZERO-SCALE ERROR (LSB) 10.5 -0.02 0.08 0.04 9.5 Figure 21. Zero-Scale Error vs. Supply Voltage, 5 V Span 0.09 0.05 8.5 TA = 25C VREFP = 5V VREFN = 0V AD8675 OUTPUT BUFFER -0.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 VDD/|VSS| (V) 14.5 15.5 Figure 23. Midscale Error vs. Supply Voltage, 5 V Span Figure 20. Zero-Scale Error vs. Supply Voltage, 10 V Span Rev. B | Page 13 of 32 16.5 09650-023 DNL ERROR (LSB) 0.06 TA = 25C VREFP = 5V VREFN = 0V AD8675 OUTPUT BUFFER 09650-021 0.08 AD5760 Data Sheet 0.14 0.38 TA = 25C VREFP = 5V VREFN = 0V 0.36 AD8675 OUTPUT BUFFER 0.10 GAIN ERROR (LSB) 0.08 0.06 0.04 0.34 0.32 0.30 13.0 13.5 14.0 14.5 15.0 VDD/|VSS| (V) 15.5 16.0 16.5 0.26 7.5 09650-024 0 12.5 8.5 Figure 24. Full-Scale Error vs. Supply Voltage, 10 V Span 10.5 11.5 12.5 13.5 VDD/|VSS| (V) 14.5 15.5 16.5 Figure 27. Gain Error vs. Supply Voltage, 5 V Span 0.5 0.08 TA = 25C VREFP = 5V 0.3 VREFN = 0V AD8675 OUTPUT BUFFER INL MAX 0.06 0.04 0.1 INL ERROR (LSB) FULL-SCALE ERROR (LSB) 9.5 09650-027 0.28 0.02 -0.1 -0.3 -0.5 0.02 TA = 25C 0 VDD = +15V VSS = -15V AD8675 OUTPUT BUFFER -0.02 -0.04 -0.06 -0.7 INL MIN -0.08 8.5 9.5 10.5 11.5 12.5 13.5 VDD/|VSS| (V) 14.5 15.5 16.5 -0.10 5.0 09650-025 -0.9 7.5 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 VREFP /|VREFN | (V) 09650-028 FULL-SCALE ERROR (LSB) TA = 25C VREFP = +10V 0.12 VREFN = -10V AD8675 OUTPUT BUFFER Figure 28. Integral Nonlinearity Error vs. Reference Voltage Figure 25. Full-Scale Error vs. Supply Voltage, 5 V Span 0.10 0.08 TA = 25C VREFP = +10V 0.08 VREFN = -10V AD8675 OUTPUT BUFFER INL MAX 0.06 DNL ERROR (LSB) 0.04 0.02 0 0.04 TA = 25C VDD = +15V VSS = -15V AD8675 OUTPUT BUFFER 0.02 -0.02 INL MIN 0 -0.06 12.5 13.0 13.5 14.0 14.5 15.0 VDD/|VSS| (V) 15.5 16.0 16.5 -0.02 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 VREFP /|VREFN | (V) Figure 29. Differential Nonlinearity Error vs. Reference Voltage Figure 26. Gain Error vs. Supply Voltage, 10 V Span Rev. B | Page 14 of 32 09650-029 -0.04 09650-026 GAIN ERROR (LSB) 0.06 Data Sheet AD5760 -0.02 -0.03 -0.30 -0.04 GAIN ERROR (LSB) -0.05 -0.06 -0.07 -0.35 -0.40 -0.08 -0.45 TA = 25C VDD = +15V VSS = -15V AD8675 OUTPUT BUFFER -0.09 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 VREFP /|VREFN | (V) -0.50 5.0 09650-030 -0.10 5.0 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 VREFP /|VREFN | (V) Figure 33. Gain Error vs. Reference Voltage Figure 30. Zero-Scale Error vs. Reference Voltage 0.50 -0.05 TA = 25C -0.07 VDD = +15V VSS = -15V AD8675 OUTPUT BUFFER -0.09 10V SPAN +10V SPAN +5V SPAN 0.45 FULL-SCALE ERROR (LSB) MIDSCALE ERROR (LSB) 5.5 09650-033 ZERO-SCALE ERROR (LSB) -0.25 TA = 25C VDD = +15V VSS = -15V AD8675 OUTPUT BUFFER -0.11 -0.13 -0.15 -0.17 -0.19 0.40 0.35 0.30 0.25 -0.21 0.20 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 VREFP /|VREFN | (V) 0.15 -40 09650-031 20 40 60 TA = 25C VDD = +15V VSS = -15V AD8675 OUTPUT BUFFER 0.38 100 10V SPAN +10V SPAN +5V SPAN 0.10 0.05 MIDSCALE ERROR (LSB) 0.36 80 Figure 34. Full-Scale Error vs. Temperature 0.15 0.40 0.34 0.32 0.3 0.28 0.26 0 -0.05 -0.10 -0.15 -0.20 0.24 -0.25 0.22 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 VREFP /|VREFN | (V) 10.0 09650-032 FULL-SCALE ERROR (LSB) 0 TEMPERATURE (C) Figure 31. Midscale Error vs. Reference Voltage 0.20 5.0 -20 VDD = +15V VSS = -15V AD8675 OUTPUT BUFFER -0.30 -40 -20 0 20 40 60 TEMPERATURE (C) Figure 35. Midscale Error vs. Temperature Figure 32. Full-Scale Error vs. Reference Voltage Rev. B | Page 15 of 32 80 100 09650-035 -0.25 5.0 VDD = +15V VSS = -15V AD8675 OUTPUT BUFFER 09650-034 -0.23 AD5760 0.4 0.010 10V SPAN +10V SPAN +5V SPAN 0.2 0.008 IDD 0.006 0.004 IDD/ISS (mA) 0 -0.2 -0.4 0.002 0 -0.002 -0.004 -0.006 -0.8 -40 VDD = +15V VSS = -15V AD8675 OUTPUT BUFFER -20 0 20 40 60 80 100 TEMPERATURE (C) -0.010 -20 Figure 36. Zero-Scale Error vs. Temperature 0 -15 -10 -5 0 5 VDD/VSS (V) 10 15 20 Figure 39. Power Supply Currents vs. Power Supply Voltages 6 10V SPAN +10V SPAN +5V SPAN -0.1 ISS -0.008 09650-039 -0.6 09650-036 ZERO-SCALE ERROR (LSB) Data Sheet 4 -0.2 0 -0.4 VOUT (V) -0.5 -0.6 -2 -4 -0.7 -6 -0.8 VDD = +15V VSS = -15V AD8675 OUTPUT BUFFER -20 0 20 40 60 80 100 TEMPERATURE (C) -10 -1 TA = 25C 800 700 2 3 4 5 5 Figure 40. Rising Full-Scale Voltage Step 6 IOVCC = 5V, LOGIC VOLTAGE INCREASING IOVCC = 5V, LOGIC VOLTAGE DECREASING IOVCC = 3V, LOGIC VOLTAGE INCREASING IOVCC = 3V, LOGIC VOLTAGE DECREASING VDD = +15V VSS = -15V VREFP = +10V VREFN = -10V ADA4808-1 BUFFERED LOAD = 10M | | 20pF 4 2 0 VOUT (V) 600 1 TIME (s) Figure 37. Gain Error vs. Temperature 900 0 09650-040 -1.0 -40 -8 09650-037 -0.9 500 400 -2 -4 300 -6 200 -8 100 0 0 1 2 3 4 LOGIC INPUT VOLTAGE (V) 5 6 09650-038 IOICC (A) VDD = +15V VSS = -15V VREFP = +10V VREFN = -10V ADA4808-1 BUFFERED LOAD = 10M | | 20pF 09650-041 GAIN ERROR (LSB) 2 -0.3 -10 -1 0 1 2 3 TIME (s) Figure 41. Falling Full-Scale Voltage Step Figure 38. IOICC vs. Logic Input Voltage Rev. B | Page 16 of 32 4 Data Sheet AD5760 6 10 VREFP = 5V VREFN = 0V UNITY-GAIN MODE 5 ADA4898-1 RC LOW-PASS FILTER 9 OUTPUT GLITCH (nV-s) 8 6 5 4 3 VREFP = +10V VREFN = -10V RC LOW-PASS FILTER UNITY-GAIN MODE ADA4898-1 0 -1 0 1 2 3 4 3 2 1 5 TIME (s) 0 09650-046 1 09650-042 2 4 16384 65536 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 VOUT (mV) 7 NEGATIVE POSITIVE CODE Figure 45. 6 MSB Segment Glitch Energy for 5 V VREF Figure 42. 500 Code Step Settling Time 25 55 NEGATIVE POSITIVE 10V REF 10V REF 5V REF 45 NEGATIVE CODE CHANGE POSITIVE CODE CHANGE 35 OUTPUT GLITCH (V) OUTPUT GLITCH (nV-s) VREFP = +10V VREFN = -10V UNITY-GAIN MODE ADA4898-1 20 RC LOW PASS FILTER 15 10 25 15 5 -5 5 800 OUTPUT VOLTAGE (nV) 2.5 2.0 1.5 1.0 TA = 25C VDD = +15V V 600 SS = -15V VREFP = +10V VREFN = -10V 400 3 0 -200 -400 0 -600 09650-045 MIDSCALE CODE LOADED OUTPUT UNBUFFERED AD8676 REFERENCE BUFFERS 200 0.5 CODE 2 Figure 46. Midscale Peak-to-Peak Glitch for 10 V NEGATIVE POSITIVE 16384 65536 114688 163840 212992 262144 311296 360448 409600 458752 507904 557056 606208 655360 704512 753664 802816 851968 901120 950272 999424 OUTPUT GLITCH (nV-s) VREFP = 10V VREFN = 0V 3.5 UNITY-GAIN MODE ADA4898-1 RC LOW-PASS FILTER 3.0 1 TIME (s) Figure 43. 6 MSB Segment Glitch Energy for 10 V VREF 4.0 0 0 1 2 3 4 5 6 TIME (Seconds) 7 8 9 10 Figure 47. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth Figure 44. 6 MSB Segment Glitch Energy for 10 V VREF Rev. B | Page 17 of 32 09650-048 CODE -25 -1 09650-044 16384 49152 81920 114688 147456 180224 212992 245760 278528 311296 344064 376832 409600 442368 475136 507904 540672 573440 606208 638976 671744 704512 737280 770048 802816 835584 868352 901120 933888 966656 999424 1032192 0 09650-047 -15 AD5760 Data Sheet 0.20 VDD = +15V VSS = -15V VREFP = +10V VREFN = -10V VDD = +15V VSS = -15V VREFP = +10V VREFN = -10V UNITY GAIN ADA4898-1 0.18 OUTPUT VOLTAGE (V) 0.16 10 0.14 0.12 0.10 0.08 0.06 0.04 0.02 1 10 100 1k FREQUENCY (Hz) 10k Figure 48. Noise Spectral Density vs. Frequency -0.02 0 1 2 3 4 5 TIME (s) Figure 49. Glitch Impulse on Removal of Output Clamp Rev. B | Page 18 of 32 6 09650-049 0 1 0.1 09650-056 NSD (nV/Hz) 100 Data Sheet AD5760 TERMINOLOGY Relative Accuracy Relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. A typical INL error vs. code plot is shown in Figure 6. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic. A typical DNL error vs. code plot is shown in Figure 10. Linearity Error Long-Term Stability Linearity error long-term stability is a measure of the stability of the linearity of the DAC over a long period of time. It is specified in LSB for a time period of 500 hours and 1000 hours at an elevated ambient temperature. Zero-Scale Error Zero-scale error is a measure of the output error when zero-scale code (0x00000) is loaded to the DAC register. Ideally, the output voltage should be VREFN. Zero-scale error is expressed in LSBs. Zero-Scale Error Temperature Coefficient Zero-scale error temperature coefficient is a measure of the change in zero-scale error with a change in temperature. It is expressed in ppm FSR/C. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0x3FFFF) is loaded to the DAC register. Ideally, the output voltage should be VREFP - 1 LSB. Full-scale error is expressed in LSBs. Full-Scale Error Temperature Coefficient Full-scale error temperature coefficient is a measure of the change in full-scale error with a change in temperature. It is expressed in ppm FSR/C. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed in ppm of the full-scale range. Gain Error Temperature Coefficient Gain error temperature coefficient is a measure of the change in gain error with a change in temperature. It is expressed in ppm FSR/C. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output voltage to settle to a specified level for a specified change in voltage. For fast settling applications, a high speed buffer amplifier is required to buffer the load from the 3.4 k output impedance of the AD5760, in which case, it is the amplifier that determines the settling time. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (see Figure 49). Output Enabled Glitch Impulse Output enabled glitch impulse is the impulse injected into the analog output when the clamp to ground on the DAC output is removed. It is specified as the area of the glitch in nV-sec (see Figure 49). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa. Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of the harmonics of the DAC output to the fundamental value. Only the second to fifth harmonics are included. DC Power Supply Rejection Ratio. DC power supply rejection ratio is a measure of the rejection of the output voltage to dc changes in the power supplies applied to the DAC. It is measured for a given dc change in power supply voltage and is expressed in V/V. AC Power Supply Rejection Ratio (AC PSRR) AC power supply rejection ratio is a measure of the rejection of the output voltage to ac changes in the power supplies applied to the DAC. It is measured for a given amplitude and frequency change in power supply voltage and is expressed in decibels. Midscale Error Midscale error is a measure of the output error when midscale code (0x20000) is loaded to the DAC register. Ideally, the output voltage should be (VREFP - VREFN)/2 +VREFN. Midscale error is expressed in LSBs. Rev. B | Page 19 of 32 AD5760 Data Sheet THEORY OF OPERATION R 2R VREFP R R VOUT 2R 2R ... 2R 2R 2R ... 2R S0 S1 ... S9 E62 E61... E0 VREFN 10-BIT R-2R LADDER DAC ARCHITECTURE 09650-050 The AD5760 is a high accuracy, fast settling, single, 16-bit, serial input, voltage output DAC. It operates from a VDD supply voltage of 7.5 V to 16.5 V and a VSS supply of -16.5 V to -2.5 V. Data is written to the AD5760 in a 24-bit word format via a 3-wire serial interface. The AD5760 incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V with the VOUT pin clamped to AGND through a ~6 k internal resistor. SIX MSBs DECODED INTO 63 EQUAL SEGMENTS Figure 50. DAC Ladder Structure Serial Interface The architecture of the AD5760 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 50. The six MSBs of the 16-bit data-word are decoded to drive 63 switches, E0 to E62. Each of these switches connects one of 63 matched resistors to either the buffered VREFP or buffered VREFN voltage. The remaining 10 bits of the data-word drive the S0 to S9 switches of a 10-bit voltage mode R-2R ladder network. SERIAL INTERFACE The AD5760 has a 3-wire serial interface (SYNC, SCLK, and SDIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards, as well as most DSPs (see Figure 2 for a timing diagram). Input Shift Register The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK, which can operate at up to 35 MHz. The input register consists of a R/W bit, three address bits, and 20 data bits as shown in Table 6. The timing diagram for this operation is shown in Figure 2. Table 6. Input Shift Register Format MSB DB23 R/W LSB DB22 DB21 Register address DB20 DB19 to DB0 Register data Table 7. Decoding the Input Shift Register R/W X1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 Register Address 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Description No operation (NOP). Used in readback operations. Write to the DAC register. Write to the control register. Write to the clearcode register. Write to the software control register. Read from the DAC register. Read from the control register. Read from the clearcode register. X is don't care. Rev. B | Page 20 of 32 Data Sheet AD5760 Standalone Operation CONTROLLER The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can be used only if SYNC is held low for the correct number of clock cycles. SERIAL CLOCK SCLK CONTROL OUT SYNC DATA OUT In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and SYNC must be taken high after the final clock to latch the data. The first falling edge of SYNC starts the write cycle. Exactly 24 falling clock edges must be applied to SCLK before SYNC is brought high again. If SYNC is brought high before the 24th falling SCLK edge, the data written is invalid. If more than 24 falling SCLK edges are applied before SYNC is brought high, the input data is also invalid. AD5760* SDIN DATA IN SDO SDIN AD5760* SCLK SYNC The input shift register is updated on the rising edge of SYNC. For another serial transfer to take place, SYNC must be brought low again. After the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register. When the write cycle is complete, the output can be updated by taking LDAC low while SYNC is high. SDO SDIN AD5760* SCLK SYNC Daisy-Chain Operation A continuous SCLK source can be used only if SYNC is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and SYNC must be taken high after the final clock to latch the data. In any one daisy-chain sequence, do not mix writes to the DAC register with writes to any of the other registers. All writes to the daisy-chained parts must be either writes to the DAC registers or writes to the control, clearcode, or software control register. SDO *ADDITIONAL PINS OMITTED FOR CLARITY. 09650-051 For systems that contain several devices, the SDO pin can be used to daisy chain several devices together. Daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. The first falling edge of SYNC starts the write cycle. SCLK is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the SDIN input of the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24 x N, where N is the total number of AD5760 devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. The serial clock can be a continuous or a gated clock. Figure 51. Daisy-Chain Block Diagram Readback The contents of all the on-chip registers can be read back via the SDO pin. Table 7 outlines how the registers are decoded. After a register has been addressed for a read, the next 24 clock cycles clock the data out on the SDO pin. The clocks must be applied while SYNC is low. When SYNC is returned high, the SDO pin is placed in tristate. For a read of a single register, the NOP function can be used to clock out the data. Alternatively, if more than one register is to be read, the data of the first register to be addressed can be clocked out at the same time that the second register to be read is being addressed. The SDO pin must be enabled to complete a readback operation. The SDO pin is enabled by default. HARDWARE CONTROL PINS Load DAC Function (LDAC) After data has been transferred into the input register of the DAC, there are two ways to update the DAC register and DAC output. Depending on the status of both SYNC and LDAC, one of two update modes is selected: synchronous DAC update or asynchronous DAC update. Synchronous DAC Update In this mode, LDAC is held low while data is being clocked into the input shift register. The DAC output is updated on the rising edge of SYNC. Rev. B | Page 21 of 32 AD5760 Data Sheet Asynchronous DAC Update In this mode, LDAC is held high while data is being clocked into the input shift register. The DAC output is asynchronously updated by taking LDAC low after SYNC has been taken high. The update now occurs on the falling edge of LDAC. is high) until a new value is loaded to the DAC register. The output cannot be updated with a new value while the CLR pin is low. A clear operation can also be performed by setting the CLR bit in the software control register (see Table 13). ON-CHIP REGISTERS Reset Function (RESET) DAC Register The AD5760 can be reset to its power-on state by two means: either by asserting the RESET pin or by using the reset function in the software control register (see Table 13). If the RESET pin is not used, hardwire it to IOVCC. Table 9 outlines how data is written to and read from the DAC register. The following equation describes the ideal transfer function of the DAC: Asynchronous Clear Function (CLR) VOUT = The CLR pin is an active low clear that allows the output to be cleared to a user defined value. The 16-bit clearcode value is programmed to the clearcode register (see Table 12). It is necessary to maintain CLR low for a minimum amount of time to complete the operation (see Figure 2). When the CLR signal is returned high, the output remains at the clear value (if LDAC (VREFP - VREFN ) x D + V 216 REFN where: VREFN is the negative voltage applied at the VREFN input pin. VREFP is the positive voltage applied at the VREFP input pin. D is the 16-bit code programmed to the DAC. Table 8. Hardware Control Pins Truth Table LDAC CLR RESET X1 X1 0 0 1 X1 X1 0 1 0 1 0 1 0 0 X X 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 Function The AD5760 is in reset mode. The device cannot be programmed. The AD5760 is returned to its power-on state. All registers are set to their default values. The DAC register is loaded with the clearcode register value, and the output is set accordingly. The output is set according to the DAC register value. The DAC register is loaded with the clearcode register value, and the output is set accordingly. The output is set according to the DAC register value. The output remains at the clearcode register value. The output remains set according to the DAC register value. The output remains at the clearcode register value. The DAC register is loaded with the clearcode register value and the output is set accordingly. The DAC register is loaded with the clearcode register value and the output is set accordingly. The output remains at the clearcode register value. The output is set according to the DAC register value. X is don't care. Table 9. DAC Register MSB DB23 R/W DB22 R/W 0 1 LSB DB21 DB20 Register address 0 1 DB19 to DB4 DAC register data DB3 DB2 DB1 DB0 16 bits of data X1 X1 X1 X1 X is don't care. Rev. B | Page 22 of 32 Data Sheet AD5760 Control Register is asserted. The output value depends on the DAC coding that is being used, either binary or twos complement. The default register value is 0. The control register controls the mode of operation of the AD5760. Clearcode Register The clearcode register sets the value to which the DAC output is set when the CLR pin or CLR bit in the software control register Table 10. Control Register MSB DB23 LSB DB19 to DB11 DB10 R/W DB22 DB21 DB20 Register address R/W 0 Reserved Reserved 1 0 DB9 DB8 DB7 DB6 DB5 DB4 Control register data 0000 SDODIS BIN/2sC DB3 DB2 DB1 DB0 DACTRI OPGND RBUF Reserved Table 11. Control Register Functions Bit Name Reserved RBUF OPGND DACTRI Description These bits are reserved and should be programmed to zero. Output amplifier configuration control. 0: the internal amplifier, A1, is powered up and Resistors RFB and R1 are connected in series, as shown in Figure 54. This allows an external amplifier to be connected in a gain of two configuration. See the AD5760 Features section for further details. 1: (default) the internal amplifier, A1, is powered down and Resistors RFB and R1 are connected in parallel, as shown in Figure 53, so that the resistance between the RFB and INV pins is 3.4 k, equal to the resistance of the DAC. This allows the RFB and INV pins to be used for input bias current compensation for an external unity-gain amplifier. See the AD5760 Features section for further details. Output ground clamp control. 0: the DAC output clamp to ground is removed, and the DAC is placed in normal mode. 1: (default) the DAC output is clamped to ground through a ~6 k resistance, and the DAC is placed in tristate mode. Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated. Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit. DAC tristate control. 0: the DAC is in normal operating mode. 1: (default) the DAC is in tristate mode. BIN/2sC DAC register coding selection. 0: (default) the DAC register uses twos complement coding. 1: the DAC register uses offset binary coding. SDODIS SDO pin enable/disable control. 0: (default) the SDO pin is enabled. 1: the SDO pin is disabled (tristate). R/W Read/write select bit. 0: AD5760 is addressed for a write operation. 1: AD5760 is addressed for a read operation. Table 12. Clearcode Register MSB DB23 R/W DB22 R/W 0 1 LSB DB21 DB20 Register address 1 1 DB19 to DB4 Clearcode register data DB3 DB2 DB1 DB0 16 bits of data X1 X1 X1 X1 X is don't care. Rev. B | Page 23 of 32 X X X AD5760 Data Sheet Software Control Register This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low. Table 13. Software Control Register MSB DB23 R/W DB22 0 1 1 2 LSB DB21 DB20 Register address 0 0 DB19 to DB3 Reserved DB2 DB1 Software control register data Reset CLR 1 DB0 LDAC 2 The CLR function has no effect when the LDAC pin is low. The LDAC function has no effect when the CLR pin is low. Table 14. Software Control Register Functions Bit Name LDAC CLR Reset Description Setting this bit to 1 updates the DAC register and, consequently, the DAC output. Setting this bit to 1 sets the DAC register to a user defined value (see Table 12) and updates the DAC output. The output value depends on the DAC register coding that is being used, either binary or twos complement. Setting this bit to 1 returns the AD5760 to its power-on state. Rev. B | Page 24 of 32 Data Sheet AD5760 AD5760 FEATURES The AD5760 contains a power-on reset circuit that, as well as resetting all registers to their default values, controls the output voltage during power-up. Upon power-on, the DAC is placed in tristate (its reference inputs are disconnected), and its output is clamped to AGND through a ~6 k resistor. The DAC remains in this state until programmed otherwise via the control register. This is a useful feature in applications where it is important to know the state of the DAC output while it is in the process of powering up. CONFIGURING THE AD5760 After power-on, the AD5760 must be configured to put it into normal operating mode before programming the output. To do this, the control register must be programmed. The DAC is removed from tristate by clearing the DACTRI bit, and the output clamp is removed by clearing the OPGND bit. At this point, the output goes to VREFN unless an alternative value is first programmed to the DAC register. A second unity-gain configuration for the output amplifier is one that removes an offset from the input bias currents of the amplifier. It does this by inserting a resistance in the feedback path of the amplifier that is equal to the output resistance of the DAC. The DAC output resistance is 3.4 k. By connecting R1 and RFB in parallel, a resistance equal to the DAC resistance is available on chip. Because the resistors are all on one piece of silicon, they are temperature coefficient matched. To enable this mode of operation, the RBUF bit of the control register must be set to Logic 1. Figure 53 shows how the output amplifier is connected to the AD5760. In this configuration, the output amplifier is in unity gain, and the output spans from VREFN to VREFP. This unity-gain configuration allows a capacitor to be placed in the amplifier feedback path to improve dynamic performance. VREFP RFB R1 6.8k DAC OUTPUT STATE 16-BIT DAC The DAC output can be placed in one of three states, controlled by the DACTRI and OPGND bits of the control register, as shown in Table 15. OPGND 0 1 0 1 There are a number of different ways that an output amplifier can be connected to the AD5760, depending on the voltage references applied and the desired output voltage span. Unity-Gain Configuration Figure 52 shows an output amplifier configured for unity gain. In this configuration, the output spans from VREFN to VREFP. VREFP RFB RFB INV VOUT AD8675 ADA4898-1 ADA4004-1 VOUT AD5760 VREFN 09650-052 16-BIT DAC R1 VOUT VOUT AD8675 ADA4898-1 ADA4004-1 AD5760 OUTPUT AMPLIFIER CONFIGURATION 6.8k 6.8k 10pF Figure 53. Output Amplifier in Unity-Gain with Amplifier Input Bias Current Compensation Output State Normal operating mode. Output is clamped via ~6 k to AGND. Output is in tristate. Output is clamped via ~6 k to AGND. A1 INV VREFN = 0V Table 15. Output State Truth Table DACTRI 0 0 1 1 RFB 6.8k Figure 52. Output Amplifier in Unity-Gain Configuration Rev. B | Page 25 of 32 09650-053 POWER-ON TO 0 V AD5760 Data Sheet VREFP Figure 54 shows an output amplifier configured for a gain of two. The gain is set by the internal matched 6.8 k resistors, which are exactly twice the DAC resistance, having the effect of removing an offset from the input bias current of the external amplifier. In this configuration, the output spans from 2 x VREFN - VREFP to VREFP. This configuration is used to generate a bipolar output span from a single-ended reference input, with VREFN = 0 V. For this mode of operation, the RBUF bit of the control register must be cleared to Logic 0. A1 16-BIT DAC 6.8k 6.8k R1 RFB RFB INV 10pF VOUT VOUT AD8675 ADA4898-1 ADA4004-1 AD5760 VREFN Figure 54. Output Amplifier in Gain of Two Configuration Rev. B | Page 26 of 32 09650-054 Gain of Two Configuration (x2 Gain Mode) Data Sheet AD5760 APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT 09650-055 Figure 55. Typical Operating Circuit Rev. B | Page 27 of 32 AD5760 Figure 55 shows a typical operating circuit for the AD5760 using an AD8675 as an output buffer. Because the output impedance of the AD5760 is 3.4 k, an output buffer is required for driving low resistive, high capacitive loads. EVALUATION BOARD Refer to the evaluation board available for the AD5780 or AD5790 to evaluate a 18-bit version or 20-bit version of the AD5760. An evaluation board is available for the AD5780 Data Sheet to aid designers in evaluating the high performance of the part with minimum effort. The evaluation kit includes a populated and tested AD5780 printed circuit board (PCB). The evaluation board interfaces to the USB port of a PC. Software is available with the evaluation board to allow the user to easily program the AD5780. The software runs on any PC that has Microsoft(R) Windows(R) XP (SP2), Vista (32-bit or 64-bit), or Windows 7 installed. The UG-256 is available, which gives full details on the operation of the evaluation board Rev. B | Page 28 of 32 Data Sheet AD5760 OUTLINE DIMENSIONS 2.75 2.65 2.50 4.00 BSC PIN 1 INDICATOR 20 PIN 1 INDICATOR 1 19 5.00 BSC 0.50 BSC 3.75 3.65 3.50 EXPOSED PAD 7 13 1.00 0.90 0.80 SEATING PLANE 0.30 0.25 0.20 0.50 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 8 12 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 122409-B TOP VIEW (Chamfer 0.225) 24 Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 5 mm, Very Thin Quad (CP-24-5) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5760BCPZ AD5760BCPZ-REEL7 AD5760ACPZ AD5760ACPZ-REEL7 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C INL 0.5 LSB 0.5 LSB 2 LSB 2 LSB Z = RoHS Compliant Part. Rev. B | Page 29 of 32 Package Description 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ Package Option CP-24-5 CP-24-5 CP-24-5 CP-24-5 AD5760 Data Sheet NOTES Rev. B | Page 30 of 32 Data Sheet AD5760 NOTES Rev. B | Page 31 of 32 AD5760 Data Sheet NOTES (c)2011-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09650-0-2/12(B) Rev. B | Page 32 of 32