Ultra Stable, 16-Bit ±0.5 LSB INL,
Voltage Output DAC
Data Sheet AD5760
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011-2012 Analog Devices, Inc. All rights reserved.
FEATURES
True 16-bit voltage output DAC, ±0.5 LSB INL
8 nV/√Hz output noise spectral density
0.00625 LSB long-term linearity error stability
±0.018 ppm/°C gain error temperature coefficient
2.5 μs output voltage settling time
3.5 nV-sec midscale glitch impulse
Integrated precision reference buffers
Operating temperature range: −40°C to +125°C
4 mm × 5 mm LFCSP package
Wide power supply range of up to ±16.5 V
35 MHz Schmitt triggered digital interface
1.8 V-compatible digital interface
APPLICATIONS
Medical instrumentation
Test and measurement
Industrial control
Scientific and aerospace instrumentation
Data acquisition systems
Digital gain and offset adjustment
Power supply control
FUNCTIONAL BLOCK DIAGRAM
A1
6.8kΩ
6kΩ
6.8kΩ
R1 R
FB
DAC
REG
16
16
INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC
POWER-ON RESET
AND CLEAR LOGIC
AD5760
IOV
CC
SDIN
V
CC
V
DD
V
REFP
AGNDV
SS
DGND
SCLK
SYNC
SDO
LDAC
CLR
RESET
R
FB
INV
V
OUT
16-BIT
DAC
V
REFN
09650-001
Figure 1.
Table 1. Related Devices
Part No. Description
AD5790 20-bit, 2 LSB accurate DAC
AD5791 20-bit, 1 LSB accurate DAC
AD5780 18-bit, 1 LSB accurate DAC
AD5781 18-bit, 0.5 LSB INL
AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC
GENERAL DESCRIPTION
The AD57601 is a true 16-bit, unbuffered voltage output DAC
that operates from a bipolar supply of up to 33 V. The AD5760
accepts a positive reference input range of 5 V to VDD − 2.5 V
and a negative reference input range of VSS + 2.5 V to 0 V. The
AD5760 offers a relative accuracy specification of ±0.5 LSB
maximum range, and operation is guaranteed monotonic with a
±0.5 LSB DNL maximum range specification.
The part uses a versatile 3-wire serial interface that operates at
clock rates of up to 35 MHz and is compatible with standard
SPI, QSPI™, MICROWIRE™, and DSP interface standards. The
part incorporates a power-on reset circuit that ensures that the
DAC output powers up to 0 V in a known output impedance
state and remains in this state until a valid write to the device
takes place. The part provides an output clamp feature that
places the output in a defined load state.
1 Protected by U.S. Patent No. 7,884,747. Other patents pending.
PRODUCT HIGHLIGHTS
1. True 16-bit accuracy.
2. Wide power supply range of up to ±16.5 V.
3. −40°C to +125°C operating temperature range.
4. Low 8 nV/√Hz noise.
5. Low ±0.018 ppm/°C gain error temperature coefficient.
COMPANION PRODUCTS
Output Amplifier Buffer: AD8675, ADA4898-1, ADA4004-1
External Reference: ADR445
DC-to-DC Design Tool: ADIsimPower™
Additional companion products on the AD5780 product page
AD5760 Data Sheet
Rev. B | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights........................................................................... 1
Companion Products....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 20
DAC Architecture....................................................................... 20
Serial Interface............................................................................ 20
Hardware Control Pins.............................................................. 21
On-Chip Registers...................................................................... 22
AD5760 Features ............................................................................ 25
Power-On to 0 V......................................................................... 25
Configuring the AD5760 .......................................................... 25
DAC Output State ...................................................................... 25
Output Amplifier Configuration.............................................. 25
Applications Information.............................................................. 27
Typical Operating Circuit ......................................................... 27
Evaluation Board........................................................................ 28
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
2/12—Rev. A to Rev. B
Deleted Linearity Compensation Section ..................................... 3
12/11—Rev. 0 to Rev. A
Changes to Table 2............................................................................ 3
Changes to Figure 48...................................................................... 18
Changes to DAC Register Section................................................ 22
Changes to Table 10 and Table 11 ................................................ 23
11/11—Revision 0: Initial Version
Data Sheet AD5760
Rev. B | Page 3 of 32
SPECIFICATIONS
VDD = +12.5 V to +16.5 V, VSS = −16.5 V to −12.5 V, VREFP = +10 V, VREFN = −10 V, VCC = 2.7 V to 5.5 V, IOVCC = 1.71 V to 5.5 V,
RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted.
Table 2.
A, B Versions1
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE2
Resolution 16 Bits
Integral Nonlinearity Error (Relative
Accuracy)
−0.5 +0.5 LSB B grade, VREFx = ±10 V, +10 V and +5 V
−2 +2 LSB A grade, VREFx = ±10 V, +10 V and +5 V
Differential Nonlinearity Error −0.5 +0.5 LSB B grade, VREFx = ±10 V, +10 V and +5 V
−1 +1 LSB A grade, VREFx = ±10 V, +10 V and +5 V
Long-Term Linearity Error Stability3 0.00625 LSB After 750 hours at TA = 135°C
Full-Scale Error −0.75 ±0.2 +0.75 LSB VREFP = +10 V, VREFN = −10 V
−1.4 ±0.17 +1.4 LSB VREFP = 10 V, VREFN = 0 V
−2.5 ±0.1 +2.5 LSB VREFP = 5 V, VREFN = 0 V
Full-Scale Error Temperature
Coefficient
±0.026 ppm/°C VREFP = +10 V, VREFN = −10 V
Zero-Scale Error −1.2 ±0.0812 +1.2 LSB VREFP = +10 V, VREFN = −10 V
−2.5 ±0.044 +2.5 LSB VREFP = 10 V, VREFN = 0 V
−5.2 ±0.056 +5.2 LSB VREFP = 5 V, VREFN = 0 V
Zero-Scale Error Temperature
Coefficient
±0.025 ppm/°C VREFP = +10 V, VREFN = −10 V
Gain Error −19 ±2.3 +19 ppm FSR VREFP = +10 V, VREFN = −10 V
−35 ±1.9 +35 ppm FSR VREFP = 10 V, VREFN = 0 V
−68 ±0.9 +68 ppm FSR VREFP = 5 V, VREFN = 0 V
Gain Error Temperature Coefficient ±0.018 ppm/°C VREFP = +10 V, VREFN = −10 V
R1, RFB Matching 0.015 %
OUTPUT CHARACTERISTICS
Output Voltage Range VREFN V
REFP V
Output Voltage Settling Time 2.5 μs 10 V step to 0.02%, using the ADA4898-1
buffer in unity-gain mode
3.5 μs 125 code step to ±1 LSB4
Output Noise Spectral Density 8 nV/√Hz At 1 kHz, DAC code = midscale
8 nV/√Hz At 10 kHz, DAC code = midscale
Output Voltage Noise 1.1 μV p-p DAC code = midscale, 0.1 Hz to 10 Hz
bandwidth
Midscale Glitch Impulse4 14 nV-sec VREFP = +10 V, VREFN = −10 V
3.5 nV-sec VREFP = 10 V, VREFN = 0 V
4 nV-sec VREFP = 5 V, VREFN = 0 V
MSB Segment Glitch Impulse4 14 nV-sec VREFP = +10 V, VREFN = −10 V, see Figure 43
3.5 nV-sec VREFP = 10 V, VREFN = 0 V, see Figure 44
4 nV-sec VREFP = 5 V, VREFN = 0 V, see Figure 45
Output Enabled Glitch Impulse 57 nV-sec On removal of output ground clamp
Digital Feedthrough 0.27 nV-sec
DC Output Impedance (Normal
Mode)
3.4 kΩ
DC Output Impedance (Output
Clamped to Ground)
6 kΩ
AD5760 Data Sheet
Rev. B | Page 4 of 32
A, B Versions1
Parameter Min Typ Max Unit Test Conditions/Comments
REFERENCE INPUTS
VREFP Input Range 5 VDD − 2.5 V
VREFN Input Range VSS + 2.5 0 V
Input Bias Current −20 −0.63 +20 nA
−4 −0.63 +4 TA = 0°C to 105°C
Input Capacitance 1 pF VREFP, VREFN
LOGIC INPUTS
Input Current5 −1 +1 μA
Input Low Voltage, VIL 0.3 × IOVCC V IOVCC = 1.71 V to 5.5 V
Input High Voltage, VIH 0.7 × IOVCC V IOVCC = 1.71 V to 5.5 V
Pin Capacitance 5 pF
LOGIC OUTPUT (SDO)
Output Low Voltage, VOL 0.4 V IOVCC = 1.71 V to 5.5 V, sinking 1 mA
Output High Voltage, VOH IOVCC − 0.5 V IOVCC = 1.71 V to 5.5 V, sourcing 1 mA
High Impedance Leakage Current ±1 μA
High Impedance Output
Capacitance
3 pF
POWER REQUIREMENTS All digital inputs at DGND or IOVCC
VDD 7.5 VSS + 33 V
VSS V
DD − 33 −2.5 V
VCC 2.7 5.5 V
IOVCC 1.71 5.5 V IOVCC ≤ VCC
IDD 10.3 14 mA
ISS −10 −14 mA
ICC 600 900 μA
IOICC 52 140 μA SDO disabled
DC Power Supply Rejection Ratio ±7.5 μV/V ∆VDD ± 10%, VSS = −15 V
±1.5 μV/V ∆VSS ± 10%, VDD = 15 V
AC Power Supply Rejection Ratio 90 dB ∆VDD ± 200 mV, 50 Hz/60 Hz, VSS = −15 V
90 dB ∆VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V
1 Temperature range: −40°C to +125°C, typical conditions: TA = 25°C, VDD = +15 V, VSS = −15 V, VREFP = +10 V, VREFN = −10 V.
2 Performance characterized with the AD8675ARZ output buffer.
3 Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified.
4 The AD5760 is configured in unity-gain mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer, lead
capacitance, and so forth).
5 Current flowing in an individual logic pin.
Data Sheet AD5760
Rev. B | Page 5 of 32
TIMING CHARACTERISTICS
VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Limit1
Parameter IOVCC = 1.71 V to 3.3 V IOVCC = 3.3 V to 5.5 V Unit Test Conditions/Comments
t12 40 28 ns min SCLK cycle time
92 60 ns min SCLK cycle time (readback and daisy-chain modes)
t2 15 10 ns min SCLK high time
t3 9 5 ns min SCLK low time
t4 5 5 ns min
SYNC to SCLK falling edge setup time
t5 2 2 ns min
SCLK falling edge to SYNC rising edge hold time
t6 48 40 ns min
Minimum SYNC high time
t7 8 6 ns min
SYNC rising edge to next SCLK falling edge ignore
t8 9 7 ns min Data setup time
t9 12 7 ns min Data hold time
t10 13 10 ns min
LDAC falling edge to SYNC falling edge
t11 20 16 ns min
SYNC rising edge to LDAC falling edge
t12 14 11 ns min
LDAC pulse width low
t13 130 130 ns typ
LDAC falling edge to output response time
t14 130 130 ns typ
SYNC rising edge to output response time (LDAC tied low)
t15 50 50 ns min
CLR pulse width low
t16 140 140 ns typ
CLR pulse activation time
t17 0 0 ns min
SYNC falling edge to first SCLK rising edge
t18 65 60 ns max
SYNC rising edge to SDO tristate (CL = 50 pF)
t19 62 45 ns max SCLK rising edge to SDO valid (CL = 50 pF)
t20 0 0 ns min
SYNC rising edge to SCLK rising edge ignore
t21 35 35 ns typ
RESET pulse width low
t22 150 150 ns typ
RESET pulse activation time
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modes.
AD5760 Data Sheet
Rev. B | Page 6 of 32
t
7
2421
DB23 DB0
t
10
t
8
t
4
t
6
t
5
t
3
t
1
t
2
t
9
t
11
t
12
t
13
t
14
t
15
t
16
t
21
t
22
V
OUT
V
OUT
V
OUT
V
OUT
RESET
CLR
LDAC
SDIN
SYNC
SCLK
09650-002
Figure 2. Write Mode Timing Diagram
DB23 DB0
NOP CONDITION
REGISTER CONTENTS CLOCKED OUT
t
1
t
17
t
2
t
5
t
17
t
5
t
19
t
18
t
20
t
3
t
4
t
8
t
9
t
6
t
7
24221241
DB23 DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
SDO
SDIN
SYNC
SCLK
09650-003
Figure 3. Readback Mode Timing Diagram
Data Sheet AD5760
Rev. B | Page 7 of 32
12 24 4825 26
INPUT WORD FOR DAC N INPUT WORD FOR DAC N – 1
INPUT WORD FOR DAC N
UNDEFINED
t
20
t
1
t
2
t
19
t
3
t
17
t
4
t
9
t
8
t
6
t
18
t
5
DB23
DB23
DB0 DB23 DB0
DB0 DB23 DB0
SDO
SDIN
SYNC
SCLK
09650-004
Figure 4. Daisy-Chain Mode Timing Diagram
AD5760 Data Sheet
Rev. B | Page 8 of 32
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter Rating
VDD to AGND −0.3 V to +34 V
VSS to AGND −34 V to +0.3 V
VDD to VSS −0.3 V to +34 V
VCC to DGND −0.3 V to +7 V
IOVCC to DGND −0.3 V to VCC + 3 V or +7 V
(whichever is less)
Digital Inputs to DGND −0.3 V to IOVCC + 0.3 V or
+7 V (whichever is less)
VOUT to AGND −0.3 V to VDD + 0.3 V
VREFP to AGND −0.3 V to VDD + 0.3 V
VREFN to AGND VSS − 0.3 V to +0.3 V
DGND to AGND −0.3 V to +0.3 V
Operating Temperature Range, TA
Industrial −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature,
TJ max
150°C
Power Dissipation (TJ max − TA)/θJA
LFCSP Package
θJA Thermal Impedance 31.0°C/W
Lead Temperature JEDEC industry standard
Soldering J-STD-020
ESD (Human Body Model) 1.6 kV
This device is a high performance integrated circuit with an
ESD rating of 1.6 kV, and it is ESD sensitive. Proper precautions
must be taken for handling and assembly.
ESD CAUTION
Data Sheet AD5760
Rev. B | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INV
IOVCC
VCC
AGND
VSS
VSS
VREFN
SDO
DNC
DNC
DNC
DNC
SDIN RFB
AD5760
TOP VIEW
(Not to Scale)
VOUT
VREFP
RESET
VDD
VDD
CLR
LDAC
SYNC
DGND
SCLK
2
1
3
4
5
6
7
18
19
17
16
15
14
13
9
10
11
12
8
21
20
22
23
24
09650-005
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2
. NEGATIVE ANALOG SUPPLY CONNECTION (V
SS
).
A VOLTAGE IN THE RANGE OF –16.5 V TO –2.5 V
CAN BE CONNECTED. V
SS
SHOULD BE DECOUPLED
TO AGND. THE PADDLE CAN BE LEFT ELECTRICALLY
UNCONNECTED PROVIDED THAT A SUPPLY
CONNECTION IS MADE AT THE V
SS
PINS. IT IS
RECOMMENDED THAT THE PADDLE BE THERMALLY
CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 VOUT Analog Output Voltage.
2 VREFP Positive Reference Voltage Input. A voltage in the range of 5 V to VDD − 2.5 V can be connected to this pin.
3, 5 VDD Positive Analog Supply Connection. A voltage in the range of 7.5 V to 16.5 V can be connected to this pin.
VDD must be decoupled to AGND.
4 RESET Active Low Reset. Asserting this pin returns the AD5760 to its power-on status.
6 CLR Active Low Input. Asserting this pin sets the DAC register to a user defined value (see Table 12) and updates
the DAC output. The output value depends on the DAC register coding that is being used, either binary or
twos complement.
7 LDAC Active Low Load DAC Logic Input. This pin is used to update the DAC register and, consequently, the analog
output. When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high
during the write cycle, the input register is updated, but the output update is held off until the falling edge
of LDAC. Do not leave the LDAC pin unconnected.
8 VCC Digital Supply. Voltage range is from 2.7 V to 5.5 V. VCC should be decoupled to DGND.
9 IOVCC Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. Voltage
range is from 1.71 V to 5.5 V.
10, 21, 22, 23 DNC Do Not Connect. Do not connect to these pins.
11 SDO Serial Data Output.
12 SDIN
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling
edge of the serial clock input.
13 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates of up to 35 MHz.
14 SYNC Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When
SYNC goes low, it enables the input shift register, and data is then transferred in on the falling edges of the
following clocks. The DAC is updated on the rising edge of SYNC.
15 DGND Ground Reference Pin for Digital Circuitry.
16 VREFN Negative Reference Voltage Input.
17, 18 VSS Negative Analog Supply Connection. A voltage in the range of −16.5 V to −2.5 V can be connected to this
pin. VSS must be decoupled to AGND.
19 AGND Ground Reference Pin for Analog Circuitry.
AD5760 Data Sheet
Rev. B | Page 10 of 32
Pin No. Mnemonic Description
20 RFB Feedback Connection for External Amplifier. See the AD5760 Features section for further details.
24 INV Inverting Input Connection for External Amplifier. See the AD5760 Features section for further details.
EPAD VSS Negative Analog Supply Connection (VSS). A voltage in the range of −16.5 V to −2.5 V can be connected to
this pin. VSS must be decoupled to AGND. The paddle can be left electrically unconnected provided that a
supply connection is made at the VSS pins. It is recommended that the paddle be thermally connected to a
copper plane for enhanced thermal performance.
Data Sheet AD5760
Rev. B | Page 11 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0 10000 20000 30000 40000 50000 60000 70000
INL (LSB)
DAC CODE
AD8675 OUTPUT BUFFER
T
A
= 25°C
09650-009
V
REFP
= +5V
V
REFN
= 0V
V
DD
= +15V
V
SS
= –15V
INL (LSB)
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
0 10000 20000 30000 40000 50000 60000 70000
DAC CODE
V
REFP
= +10V
V
REFN
= –10V
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
T
A
= 25°C
09650-006
Figure 6. Integral Nonlinearity Error vs. DAC Code, ±10 V Span Figure 9. Integral Nonlinearity Error vs. DAC Code, 5 V Span, ×2 Gain Mode
INL (LSB)
–0.10
–0.05
0
0.05
0.10
0.15
0 10000 20000 30000 40000 50000 60000 70000
DAC CODE
V
REFP
= +10V
V
REFN
= 0V
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
T
A
= 25°C
09650-007
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
0 10000 20000 30000 40000 50000 60000 70000
DNL (LSB)
DAC CODE
09650-010
V
REFP
= +10V
V
REFN
= –10V
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
T
A
= 25°C
Figure 7. Integral Nonlinearity Error vs. DAC Code, 10 V Span Figure 10. Differential Nonlinearity Error vs. DAC Code, ±10 V Span
INL (LSB)
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0 10000 20000 30000 40000 50000 60000 70000
DAC CODE
VREFP = +5V
VREFN = 0V
VDD = +15V
VSS = –15V
AD8675 OUTPUT BUFFER
TA = 25°C
09650-008
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0 10000 20000 30000 40000 50000 60000 70000
DNL (LSB)
DAC CODE
09650-011
V
REFP
= +10V
V
REFN
= 0V
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
T
A
= 25°C
Figure 8. Integral Nonlinearity Error vs. DAC Code, 5 V Span Figure 11. Differential Nonlinearity Error vs. DAC Code, 10 V Span
AD5760 Data Sheet
Rev. B | Page 12 of 32
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
0 10000 20000 30000 40000 50000 60000 70000
DNL (LSB)
DAC CODE
V
REFP
= +5V
V
REFN
= 0V
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
T
A
= 25°C
09650-012
Figure 12. Differential Nonlinearity Error vs. DAC Code, 5 V Span
–0.05
–0.03
–0.01
0.01
0.03
0.05
0.07
0.09
0 10000 20000 30000 40000 50000 60000 70000
DNL (LSB)
DAC CODE
V
REFP
= +5V
V
REFN
= 0V
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
T
A
= 25°C
09650-013
Figure 13. Differential Nonlinearity Error vs. DAC Code, 5 V Span,
×2 Gain Mode
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
INL ERROR (LSB)
TEMPERATURE (°C)
–40 –20 0 20 40 60 80 100
±10V SPAN MAX INL
+10V SPAN MAX INL
+5V SPAN MAX INL
±10V SPAN MIN INL
+10V SPAN MIN INL
+5V SPAN MIN INL
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
09650-015
Figure 14. Integral Nonlinearity Error vs. Temperature
–0.01
0.01
0.03
0.05
0.07
0.09
DNL ERROR (LSB)
TEMPERATURE (°C)
–40 –200 20406080100
±10V SPAN MAX INL
+10V SPAN MAX INL
+5V SPAN MAX INL
±10V SPAN MIN INL
+10V SPAN MIN INL
+5V SPAN MIN INL
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
09650-014
Figure 15. Differential Nonlinearity Error vs. Temperature
–0.1.0
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
INL ERROR (LSB)
V
DD
/|V
SS
| (V)
INL MAX
INL MIN
T
A
= 25°C
V
REFP
= +10V
V
REFN
= –10V
AD8675 OUTPUT BUFFER
09650-016
Figure 16. Integral Nonlinearity Error vs. Supply Voltage, ±10 V Span
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
INL ERROR (LSB)
V
DD
/|V
SS
| (V)
INL MAX
INL MIN
T
A
= 25°C
V
REFP
= 5V
V
REFN
= 0V
AD8675 OUTPUT BUFFER
09650-017
Figure 17. Integral Nonlinearity Error vs. Supply Voltage, 5 V Span
Data Sheet AD5760
Rev. B | Page 13 of 32
–0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
DNL ERROR (LSB)
V
DD
/|V
SS
| (V)
DNL MAX
DNL MIN
T
A
= 25°C
V
REFP
= +10V
V
REFN
= –10V
AD8675 OUTPUT BUFFER
09650-018
Figure 18. Differential Nonlinearity Error vs. Supply Voltage, ±10 V Span
–0.01
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
DNL ERROR (LSB)
V
DD
/|V
SS
| (V)
DNL MAX
DNL MIN
T
A
= 25°C
V
REFP
= 5V
V
REFN
= 0V
AD8675 OUTPUT BUFFER
09650-019
Figure 19. Differential Nonlinearity Error vs. Supply Voltage, 5 V Span
–0.10
–0.05
0
0.05
0.10
0.15
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
ZERO-SCALE ERROR (LSB)
V
DD
/|V
SS
| (V)
09650-020
T
A
= 25°C
V
REFP
= +10V
V
REFN
= –10V
AD8675 OUTPUT BUFFER
Figure 20. Zero-Scale Error vs. Supply Voltage, ±10 V Span
–0.4
–0.2
0
0.2
0.4
0.6
0.8
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
ZERO-SCALE ERROR (LSB)
V
DD
/|V
SS
| (V)
09650-021
T
A
= 25°C
V
REFP
= 5V
V
REFN
= 0V
AD8675 OUTPUT BUFFER
Figure 21. Zero-Scale Error vs. Supply Voltage, 5 V Span
–0.12
–0.11
–0.10
–0.09
–0.08
–0.07
–0.06
–0.05
–0.04
–0.03
–
0.02
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
MIDSCALE ERROR (LSB)
V
DD
/|V
SS
| (V)
T
A
= 25°C
V
REFP
= +10V
V
REFN
= –10V
AD8675 OUTPUT BUFFER
09650-022
Figure 22. Midscale Error vs. Supply Voltage, ±10 V Span
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
MIDSCALE ERROR (LSB)
V
DD
/|V
SS
| (V)
09650-023
T
A
= 25°C
V
REFP
= 5V
V
REFN
= 0V
AD8675 OUTPUT BUFFER
Figure 23. Midscale Error vs. Supply Voltage, 5 V Span
AD5760 Data Sheet
Rev. B | Page 14 of 32
12.5 13.
0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
FULL-SCALE ERROR (LSB)
V
DD
/|V
SS
| (V)
09650-024
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14 T
A
= 25°C
V
REFP
= +10V
V
REFN
= –10V
AD8675 OUTPUT BUFFER
Figure 24. Full-Scale Error vs. Supply Voltage, ±10 V Span
–0.9
–0.7
–0.5
–0.3
–0.1
0.1
0.3
0.5
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
FULL-SCALE ERROR (LSB)
V
DD
/|V
SS
| (V)
09650-025
T
A
= 25°C
V
REFP
= 5V
V
REFN
= 0V
AD8675 OUTPUT BUFFER
Figure 25. Full-Scale Error vs. Supply Voltage, 5 V Span
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
GAIN ERROR (LSB)
V
DD
/|V
SS
| (V)
09650-026
T
A
= 25°C
V
REFP
= +10V
V
REFN
= –10V
AD8675 OUTPUT BUFFER
Figure 26. Gain Error vs. Supply Voltage, ±10 V Span
0.26
0.28
0.30
0.32
0.34
0.36
0.38
7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
V
DD
/|V
SS
| (V)
GAIN ERROR (LSB)
09650-027
T
A
= 25°C
V
REFP
= 5V
V
REFN
= 0V
AD8675 OUTPUT BUFFER
Figure 27. Gain Error vs. Supply Voltage, 5 V Span
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
INL ERROR (LSB)
V
REFP
/|V
REFN
| (V)
INL MAX
INL MIN
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
09650-028
Figure 28. Integral Nonlinearity Error vs. Reference Voltage
DNL ERROR (LSB)
–0.02
0
0.02
0.04
0.06
0.08
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
V
REFP
/|V
REFN
| (V)
INL MAX
INL MIN
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
09650-029
Figure 29. Differential Nonlinearity Error vs. Reference Voltage
Data Sheet AD5760
Rev. B | Page 15 of 32
5.05.56.06.57.07.58.08.59.09.510.0
ZERO-SCALE ERROR (LSB)
V
REFP
/|V
REFN
| (V)
09650-030
–0.10
–0.09
–0.08
–0.07
–0.06
–0.05
–0.04
–0.03
–
0.02 T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
Figure 30. Zero-Scale Error vs. Reference Voltage
–0.25
–
0.05
5.05.56.06.57.07.58.08.59.09.510.0
MIDSCALE ERROR (LSB)
V
REFP
/|V
REFN
| (V)
09650-031
–0.23
–0.21
–0.19
–0.17
–0.15
–0.13
–0.11
–0.09
–0.07
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
Figure 31. Midscale Error vs. Reference Voltage
0.20
0.22
0.24
0.26
0.28
0.3
0.32
0.34
0.36
0.38
0.40
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
FULL-SCALE ERROR (LSB)
V
REFP
/|V
REFN
| (V)
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
09650-032
Figure 32. Full-Scale Error vs. Reference Voltage
–0.50
–0.45
–0.40
–0.35
–0.30
–
0.25
5.05.56.06.57.07.58.08.59.09.510.0
GAIN ERROR (LSB)
V
REFP
/|V
REFN
| (V)
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
09650-033
Figure 33. Gain Error vs. Reference Voltage
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
–40 –20 0 20 40 60 80 100
±10V SPAN
+10V SPAN
+5V SPAN
FULL-SCALE ERROR (LSB)
TEMPERATURE (°C)
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
09650-034
Figure 34. Full-Scale Error vs. Temperature
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
–40 –20 0 20 40 60 80 100
MIDSCALE ERROR (LSB)
TEMPERATURE (°C)
±10V SPAN
+10V SPAN
+5V SPAN
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
09650-035
Figure 35. Midscale Error vs. Temperature
AD5760 Data Sheet
Rev. B | Page 16 of 32
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
–40 –20 0 20 40 60 80 100
ZERO-SCALE ERROR (LSB)
TEMPERATURE (°C)
±10V SPAN
+10V SPAN
+5V SPAN
VDD = +15V
VSS = –15V
AD8675 OUTPUT BUFFER
09650-036
Figure 36. Zero-Scale Error vs. Temperature
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
–40 –20 0 20 40 60 80 100
GAIN ERROR (LSB)
TEMPERATURE (°C)
±10V SPAN
+10V SPAN
+5V SPAN
V
DD
= +15V
V
SS
= –15V
AD8675 OUTPUT BUFFER
09650-037
Figure 37. Gain Error vs. Temperature
900
800
700
600
500
400
300
200
100
001
T
A
= 25°C
2345 6
LOGIC INPUT VOLTAGE (V)
IOI
CC
(µA)
IOV
CC
= 5V, LOGIC VOLTAGE
INCREASING
IOV
CC
= 5V, LOGIC VOLTAGE
DECREASING
IOV
CC
= 3V, LOGIC VOLTAGE
INCREASING
IOV
CC
= 3V, LOGIC VOLTAGE
DECREASING
09650-038
Figure 38. IOICC vs. Logic Input Voltage
0.010
0
–0.002
0.002
–0.004
0.004
–0.006
0.006
–0.008
0.008
–0.010
–20 –15 –10 –5 0 5 10 15 20
V
DD
/V
SS
(V)
I
DD
/I
SS
(mA)
09650-039
I
DD
I
SS
Figure 39. Power Supply Currents vs. Power Supply Voltages
–10
–8
–6
–4
–2
0
2
4
6
–1012345
V
OUT
(V)
TIME (µs)
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –10V
ADA4808-1 BUFFERED
LOAD = 10MΩ || 20pF
09650-040
Figure 40. Rising Full-Scale Voltage Step
–10
–8
–6
–4
–2
0
2
4
6
–1012345
V
OUT
(V)
TIME (µs)
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –10V
ADA4808-1 BUFFERED
LOAD = 10MΩ || 20pF
09650-041
Figure 41. Falling Full-Scale Voltage Step
Data Sheet AD5760
Rev. B | Page 17 of 32
TIME (µs)
0
1
2
3
4
5
6
7
8
9
10
–1012345
V
OUT
(mV)
V
REFP
= +10V
V
REFN
= –10V
RC LOW-PASS FILTER
UNITY-GAIN MODE
ADA4898-1
09650-042
Figure 42. 500 Code Step Settling Time
0
5
10
15
20
25
16384
49152
81920
114688
147456
180224
212992
245760
278528
311296
344064
376832
409600
442368
475136
507904
540672
573440
606208
638976
671744
704512
737280
770048
802816
835584
868352
901120
933888
966656
999424
1032192
OUTPUT GLITCH (nV-s)
CODE
NEGATIVE
CODE CHANGE
V
REFP
= +10V
V
REFN
= –10V
UNITY-GAIN MODE
ADA4898-1
RC LOW PASS FILTER POSITIVE
CODE CHANGE
NEGATIVE
POSITIVE
09650-044
Figure 43. 6 MSB Segment Glitch Energy for ±10 V VREF
OUTPUT GLITCH (nV-s)
CODE
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
16384
65536
114688
163840
212992
262144
311296
360448
409600
458752
507904
557056
606208
655360
704512
753664
802816
851968
901120
950272
999424
V
REFP
= 10V
V
REFN
= 0V
UNITY-GAIN MODE
ADA4898-1
RC LOW-PASS FILTER
NEGATIVE
POSITIVE
09650-045
Figure 44. 6 MSB Segment Glitch Energy for 10 V VREF
OUTPUT GLITCH (nV-s)
CODE
16384
65536
114688
163840
212992
262144
311296
360448
409600
458752
507904
557056
606208
655360
704512
753664
802816
851968
901120
950272
999424
0
1
2
3
4
5
6
09650-046
NEGATIVE
POSITIVE
V
REFP
= 5V
V
REFN
= 0V
UNITY-GAIN MODE
ADA4898-1
RC LOW-PASS FILTER
Figure 45. 6 MSB Segment Glitch Energy for 5 V VREF
TIME (µs)
–10123
–25
–15
–5
5
15
25
35
45
55
OUTPUT GLITCH (V)
±10V REF
10V REF
5V REF
09650-047
Figure 46. Midscale Peak-to-Peak Glitch for ±10 V
800
600
400
200
0
–200
–400
–600
012345678 910
TIME (Seconds)
OUTPUT VOLTAGE (nV)
MIDSCALE CODE LOADED
OUTPUT UNBUFFERED
AD8676 REFERENCE BUFFERS
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –10V
09650-048
Figure 47. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth
AD5760 Data Sheet
Rev. B | Page 18 of 32
1
10
100
0.1 1 10 100 1k 10k
NSD (nV/
√
Hz)
FREQUENCY (Hz)
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –10V
09650-056
0.20
OUTPUT VOLTAGE (V)
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
–0.02
0123
TIME (µs)
456
V
DD
= +15V
V
SS
= –15V
V
REFP
= +10V
V
REFN
= –10V
UNITY GAIN
ADA4898-1
09650-049
Figure 48. Noise Spectral Density vs. Frequency Figure 49. Glitch Impulse on Removal of Output Clamp
Data Sheet AD5760
Rev. B | Page 19 of 32
TERMINOLOGY
Relative Accuracy
Relative accuracy, or integral nonlinearity (INL), is a measure of
the maximum deviation, in LSB, from a straight line passing
through the endpoints of the DAC transfer function. A typical
INL error vs. code plot is shown in Figure 6.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic. A
typical DNL error vs. code plot is shown in Figure 10.
Linearity Error Long-Term Stability
Linearity error long-term stability is a measure of the stability of
the linearity of the DAC over a long period of time. It is specified
in LSB for a time period of 500 hours and 1000 hours at an
elevated ambient temperature.
Zero-Scale Error
Zero-scale error is a measure of the output error when zero-scale
code (0x00000) is loaded to the DAC register. Ideally, the output
voltage should be VREFN. Zero-scale error is expressed in LSBs.
Zero-Scale Error Temperature Coefficient
Zero-scale error temperature coefficient is a measure of the
change in zero-scale error with a change in temperature. It is
expressed in ppm FSR/°C.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0x3FFFF) is loaded to the DAC register. Ideally, the
output voltage should be VREFP − 1 LSB. Full-scale error is
expressed in LSBs.
Full-Scale Error Temperature Coefficient
Full-scale error temperature coefficient is a measure of the
change in full-scale error with a change in temperature. It is
expressed in ppm FSR/°C.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed in ppm of the full-scale range.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change in
gain error with a change in temperature. It is expressed in ppm
FSR/°C.
Midscale Error
Midscale error is a measure of the output error when midscale
code (0x20000) is loaded to the DAC register. Ideally, the output
voltage should be (VREFP – VREFN)/2 +VREFN. Midscale error is
expressed in LSBs.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output voltage to settle to a specified level for a specified
change in voltage. For fast settling applications, a high speed
buffer amplifier is required to buffer the load from the 3.4 kΩ
output impedance of the AD5760, in which case, it is the
amplifier that determines the settling time.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is specified as the area of the glitch in nV-sec and is
measured when the digital input code is changed by 1 LSB at
the major carry transition (see Figure 49).
Output Enabled Glitch Impulse
Output enabled glitch impulse is the impulse injected into the
analog output when the clamp to ground on the DAC output is
removed. It is specified as the area of the glitch in nV-sec (see
Figure 49).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s, and vice versa.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of the
harmonics of the DAC output to the fundamental value. Only
the second to fifth harmonics are included.
DC Power Supply Rejection Ratio.
DC power supply rejection ratio is a measure of the rejection of
the output voltage to dc changes in the power supplies applied
to the DAC. It is measured for a given dc change in power
supply voltage and is expressed in μV/V.
AC Power Supply Rejection Ratio (AC PSRR)
AC power supply rejection ratio is a measure of the rejection of
the output voltage to ac changes in the power supplies applied
to the DAC. It is measured for a given amplitude and frequency
change in power supply voltage and is expressed in decibels.
AD5760 Data Sheet
Rev. B | Page 20 of 32
THEORY OF OPERATION
The AD5760 is a high accuracy, fast settling, single, 16-bit,
serial input, voltage output DAC. It operates from a VDD supply
voltage of 7.5 V to 16.5 V and a VSS supply of −16.5 V to −2.5 V.
Data is written to the AD5760 in a 24-bit word format via a 3-wire
serial interface. The AD5760 incorporates a power-on reset
circuit that ensures the DAC output powers up to 0 V with the
VOUT pin clamped to AGND through a ~6 kΩ internal resistor.
DAC ARCHITECTURE
The architecture of the AD5760 consists of two matched DAC
sections. A simplified circuit diagram is shown in Figure 50.
The six MSBs of the 16-bit data-word are decoded to drive
63 switches, E0 to E62. Each of these switches connects one of
63 matched resistors to either the buffered VREFP or buffered
VREFN voltage. The remaining 10 bits of the data-word drive the
S0 to S9 switches of a 10-bit voltage mode R-2R ladder network.
2R
S0
2R
S1
2R
S9
2R
E62
2R
E61
2R
E0
10-BIT R-2R LADDER
...
...
...
...
RR
R
2R
V
OUT
SIX MSBs DECODED INTO
63 EQUAL SEGMENTS
V
REFP
V
REFN
09650-050
Figure 50. DAC Ladder Structure Serial Interface
SERIAL INTERFACE
The AD5760 has a 3-wire serial interface (SYNC, SCLK, and
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs (see for a
timing diagram).
Figure 2
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK, which can operate at up to 35 MHz. The
input register consists of a R/W bit, three address bits, and
20 data bits as shown in . The timing diagram for this
operation is shown in .
Table 6
Figure 2
Table 6. Input Shift Register Format
MSB LSB
DB23 DB22 DB21 DB20 DB19 to DB0
R/W Register address Register data
Table 7. Decoding the Input Shift Register
R/W Register Address Description
X1 0 0 0 No operation (NOP). Used in readback operations.
0 0 0 1 Write to the DAC register.
0 0 1 0 Write to the control register.
0 0 1 1 Write to the clearcode register.
0 1 0 0 Write to the software control register.
1 0 0 1 Read from the DAC register.
1 0 1 0 Read from the control register.
1 0 1 1 Read from the clearcode register.
1 X is don’t care.
Data Sheet AD5760
Rev. B | Page 21 of 32
Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can be used
only if SYNC is held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used, and SYNC must be taken high after
the final clock to latch the data. The first falling edge of SYNC
starts the write cycle. Exactly 24 falling clock edges must be applied
to SCLK before SYNC is brought high again. If SYNC is brought
high before the 24th falling SCLK edge, the data written is invalid.
If more than 24 falling SCLK edges are applied before SYNC is
brought high, the input data is also invalid.
The input shift register is updated on the rising edge of SYNC.
For another serial transfer to take place, SYNC must be brought
low again. After the end of the serial data transfer, data is
automatically transferred from the input shift register to the
addressed register. When the write cycle is complete, the output
can be updated by taking LDAC low while SYNC is high.
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy chain several devices together. Daisy-chain mode
can be useful in system diagnostics and in reducing the number
of serial interface lines. The first falling edge of SYNC starts
the write cycle. SCLK is continuously applied to the input shift
register when SYNC is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO
of the first device to the SDIN input of the next device in the
chain, a multidevice interface is constructed. Each device in the
system requires 24 clock pulses. Therefore, the total number of
clock cycles must equal 24 × N, where N is the total number of
devices in the chain. When the serial transfer to all
devices is complete,
AD5760
SYNC is taken high. This latches the input
data in each device in the daisy chain and prevents any further
data from being clocked into the input shift register. The serial
clock can be a continuous or a gated clock.
A continuous SCLK source can be used only if SYNC is held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used, and SYNC must be taken high after the final clock to
latch the data.
In any one daisy-chain sequence, do not mix writes to the DAC
register with writes to any of the other registers. All writes to the
daisy-chained parts must be either writes to the DAC registers
or writes to the control, clearcode, or software control register.
CONTROLLER
DATA IN
SYNC
SDIN
SCLK
DATA OUT
SERIAL CLOCK
CONTROL OUT
SDO
SYNC
SCLK
SDO
SYNC
SCLK
SDO
SDIN
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5760*
AD5760*
AD5760*
09650-051
Figure 51. Daisy-Chain Block Diagram
Readback
The contents of all the on-chip registers can be read back via
the SDO pin. Table 7 outlines how the registers are decoded.
After a register has been addressed for a read, the next 24 clock
cycles clock the data out on the SDO pin. The clocks must be
applied while SYNC is low. When SYNC is returned high, the
SDO pin is placed in tristate. For a read of a single register, the
NOP function can be used to clock out the data. Alternatively,
if more than one register is to be read, the data of the first
register to be addressed can be clocked out at the same time
that the second register to be read is being addressed. The SDO
pin must be enabled to complete a readback operation. The
SDO pin is enabled by default.
HARDWARE CONTROL PINS
Load DAC Function (LDAC)
After data has been transferred into the input register of the
DAC, there are two ways to update the DAC register and DAC
output. Depending on the status of both SYNC and LDAC, one
of two update modes is selected: synchronous DAC update or
asynchronous DAC update.
Synchronous DAC Update
In this mode, LDAC is held low while data is being clocked into
the input shift register. The DAC output is updated on the rising
edge of SYNC.
AD5760 Data Sheet
Rev. B | Page 22 of 32
Asynchronous DAC Update
In this mode, LDAC is held high while data is being clocked
into the input shift register. The DAC output is asynchronously
updated by taking LDAC low after SYNC has been taken high.
The update now occurs on the falling edge of LDAC.
Reset Function (RESET)
The AD5760 can be reset to its power-on state by two means:
either by asserting the RESET pin or by using the reset function
in the software control register (see ). If the Table 13 RESET pin
is not used, hardwire it to IOVCC.
Asynchronous Clear Function (CLR)
The CLR pin is an active low clear that allows the output to be
cleared to a user defined value. The 16-bit clearcode value is
programmed to the clearcode register (see ). It is
necessary to maintain
Table 12
CLR low for a minimum amount of time
to complete the operation (see ). When the Figure 2 CLR signal
is returned high, the output remains at the clear value (if LDAC
is high) until a new value is loaded to the DAC register. The
output cannot be updated with a new value while the CLR pin is
low. A clear operation can also be performed by setting the CLR
bit in the software control register (see ). Table 13
ON-CHIP REGISTERS
DAC Register
Table 9 outlines how data is written to and read from the DAC
register.
The following equation describes the ideal transfer function of
the DAC:
(
)
REFN
REFNREFP
OUT V
DVV
V+
×
−
=16
2
where:
VREFN is the negative voltage applied at the VREFN input pin.
VREFP is the positive voltage applied at the VREFP input pin.
D is the 16-bit code programmed to the DAC.
Table 8. Hardware Control Pins Truth Table
LDAC CLR RESET Function
X1 XX
1 0 The AD5760 is in reset mode. The device cannot be programmed.
X1 XX
1 The AD5760 is returned to its power-on state. All registers are set to their default values.
0 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly.
0 1 1 The output is set according to the DAC register value.
1 0 1 The DAC register is loaded with the clearcode register value, and the output is set accordingly.
1 1 The output is set according to the DAC register value.
0 1 The output remains at the clearcode register value.
1 1 The output remains set according to the DAC register value.
0 1 The output remains at the clearcode register value.
1 1 The DAC register is loaded with the clearcode register value and the output is set accordingly.
0 1 The DAC register is loaded with the clearcode register value and the output is set accordingly.
1 1 The output remains at the clearcode register value.
0 1 The output is set according to the DAC register value.
1 X is don’t care.
Table 9. DAC Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 to DB4 DB3 DB2 DB1 DB0
R/W Register address DAC register data
R/W 0 0 1 16 bits of data X1 X1 X
1 X1
1 X is don’t care.
Data Sheet AD5760
Rev. B | Page 23 of 32
Control Register
The control register controls the mode of operation of the
AD5760.
Clearcode Register
The clearcode register sets the value to which the DAC output is
set when the CLR pin or CLR bit in the software control register
is asserted. The output value depends on the DAC coding that is
being used, either binary or twos complement. The default
register value is 0.
Table 10. Control Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 to DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R/W Register address Control register data
R/W 0 1 0 Reserved Reserved 0000 SDODIS BIN/2sC DACTRI OPGND RBUF Reserved
Table 11. Control Register Functions
Bit Name Description
Reserved These bits are reserved and should be programmed to zero.
RBUF Output amplifier configuration control.
0: the internal amplifier, A1, is powered up and Resistors RFB and R1 are connected in series, as shown in Figure 54. This allows
an external amplifier to be connected in a gain of two configuration. See the AD5760 Features section for further details.
1: (default) the internal amplifier, A1, is powered down and Resistors RFB and R1 are connected in parallel, as shown in
Figure 53, so that the resistance between the RFB and INV pins is 3.4 kΩ, equal to the resistance of the DAC. This allows the RFB
and INV pins to be used for input bias current compensation for an external unity-gain amplifier. See the AD5760 Features
section for further details.
OPGND Output ground clamp control.
0: the DAC output clamp to ground is removed, and the DAC is placed in normal mode.
1: (default) the DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate mode.
Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated.
Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit.
DACTRI DAC tristate control.
0: the DAC is in normal operating mode.
1: (default) the DAC is in tristate mode.
BIN/2sC DAC register coding selection.
0: (default) the DAC register uses twos complement coding.
1: the DAC register uses offset binary coding.
SDODIS SDO pin enable/disable control.
0: (default) the SDO pin is enabled.
1: the SDO pin is disabled (tristate).
R/W Read/write select bit.
0: AD5760 is addressed for a write operation.
1: AD5760 is addressed for a read operation.
Table 12. Clearcode Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 to DB4 DB3 DB2 DB1 DB0
R/W Register address Clearcode register data
R/W 0 1 1 16 bits of data X1 XX
1 XX
1 XX
1
1 X is don’t care.
AD5760 Data Sheet
Rev. B | Page 24 of 32
Software Control Register
This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low.
Table 13. Software Control Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 to DB3 DB2 DB1 DB0
R/W Register address Software control register data
0 1 0 0 Reserved Reset CLR1 LDAC2
1 The CLR function has no effect when the LDAC pin is low.
2 The LDAC function has no effect when the CLR pin is low.
Table 14. Software Control Register Functions
Bit Name Description
LDAC Setting this bit to 1 updates the DAC register and, consequently, the DAC output.
CLR Setting this bit to 1 sets the DAC register to a user defined value (see Table 12) and updates the DAC output. The output
value depends on the DAC register coding that is being used, either binary or twos complement.
Reset Setting this bit to 1 returns the AD5760 to its power-on state.
Data Sheet AD5760
Rev. B | Page 25 of 32
AD5760 FEATURES
POWER-ON TO 0 V
The AD5760 contains a power-on reset circuit that, as well as
resetting all registers to their default values, controls the output
voltage during power-up. Upon power-on, the DAC is placed in
tristate (its reference inputs are disconnected), and its output is
clamped to AGND through a ~6 kΩ resistor. The DAC remains
in this state until programmed otherwise via the control register.
This is a useful feature in applications where it is important to
know the state of the DAC output while it is in the process of
powering up.
CONFIGURING THE AD5760
After power-on, the AD5760 must be configured to put it into
normal operating mode before programming the output. To
do this, the control register must be programmed. The DAC
is removed from tristate by clearing the DACTRI bit, and the
output clamp is removed by clearing the OPGND bit. At this
point, the output goes to VREFN unless an alternative value is
first programmed to the DAC register.
DAC OUTPUT STATE
The DAC output can be placed in one of three states, controlled
by the DACTRI and OPGND bits of the control register, as
shown in Table 15.
Table 15. Output State Truth Table
DACTRI OPGND Output State
0 0 Normal operating mode.
0 1 Output is clamped via ~6 kΩ to AGND.
1 0 Output is in tristate.
1 1 Output is clamped via ~6 kΩ to AGND.
OUTPUT AMPLIFIER CONFIGURATION
There are a number of different ways that an output amplifier
can be connected to the AD5760, depending on the voltage
references applied and the desired output voltage span.
Unity-Gain Configuration
Figure 52 shows an output amplifier configured for unity gain.
In this configuration, the output spans from VREFN to VREFP.
A1
6.8kΩ6.8kΩ
R1 RFB
V
REFP
RFB
INV
VOUT
VOUT
16-BIT
DAC
VREFN
AD5760
AD8675
ADA4898-1
ADA4004-1
09650-052
Figure 52. Output Amplifier in Unity-Gain Configuration
A second unity-gain configuration for the output amplifier is
one that removes an offset from the input bias currents of the
amplifier. It does this by inserting a resistance in the feedback
path of the amplifier that is equal to the output resistance of the
DAC. The DAC output resistance is 3.4 kΩ. By connecting R1
and RFB in parallel, a resistance equal to the DAC resistance is
available on chip. Because the resistors are all on one piece of
silicon, they are temperature coefficient matched. To enable this
mode of operation, the RBUF bit of the control register must be
set to Logic 1. Figure 53 shows how the output amplifier is
connected to the AD5760. In this configuration, the output
amplifier is in unity gain, and the output spans from VREFN to
VREFP. This unity-gain configuration allows a capacitor to be
placed in the amplifier feedback path to improve dynamic
performance.
V
REFP
RFB
INV
VOUT VOUT
10pF
16-BIT
DAC
VREFN = 0V
AD5760
AD8675
ADA4898-1
ADA4004-1
RFB
6.8kΩ
R1
6.8kΩ
09650-053
Figure 53. Output Amplifier in Unity-Gain with Amplifier Input Bias Current
Compensation
AD5760 Data Sheet
Rev. B | Page 26 of 32
Gain of Two Configuration (×2 Gain Mode)
Figure 54 shows an output amplifier configured for a gain of
two. The gain is set by the internal matched 6.8 kΩ resistors,
which are exactly twice the DAC resistance, having the effect
of removing an offset from the input bias current of the external
amplifier. In this configuration, the output spans from 2 × VREFN −
VREFP to VREFP. This configuration is used to generate a bipolar
output span from a single-ended reference input, with VREFN =
0 V. For this mode of operation, the RBUF bit of the control
register must be cleared to Logic 0.
A1
6.8kΩ6.8kΩ
R1 R
FB
V
REFP
R
FB
INV
V
OUT
V
OUT
10pF
16-BIT
DAC
V
REFN
AD5760
AD8675
ADA4898-1
ADA4004-1
09650-054
Figure 54. Output Amplifier in Gain of Two Configuration
Data Sheet AD5760
Rev. B | Page 27 of 32
APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
09650-055
Figure 55. Typical Operating Circuit
AD5760 Data Sheet
Rev. B | Page 28 of 32
Figure 55 shows a typical operating circuit for the AD5760
using an AD8675 as an output buffer. Because the output
impedance of the AD5760 is 3.4 kΩ, an output buffer is
required for driving low resistive, high capacitive loads.
EVALUATION BOARD
Refer to the evaluation board available for the AD5780 or
AD5790 to evaluate a 18-bit version or 20-bit version of the
AD5760. An evaluation board is available for the AD5780
to aid designers in evaluating the high performance of the part
with minimum effort. The evaluation kit includes a populated
and tested AD5780 printed circuit board (PCB). The evaluation
board interfaces to the USB port of a PC. Software is available
with the evaluation board to allow the user to easily program
the AD5780. The software runs on any PC that has Microsoft®
Windows® XP (SP2), Vista (32-bit or 64-bit), or Windows 7
installed. The UG-256 is available, which gives full details on
the operation of the evaluation board
Data Sheet AD5760
Rev. B | Page 29 of 32
OUTLINE DIMENSIONS
122409-B
BOTTOM VIEWTOP VIEW
0.30
0.25
0.20
1.00
0.90
0.80
1
7
8
12
13
19
20 24
5.00 BSC
4.00 BSC
PIN 1
INDICATOR
(Chamfer 0.225)
3.75
3.65
3.50
2.75
2.65
2.50
EXPOSED
PAD
SEATING
PLANE
PIN 1
INDICATOR
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
0.50
BSC
0.50
0.40
0.30
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 5 mm, Very Thin Quad
(CP-24-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range INL Package Description Package Option
AD5760BCPZ −40°C to +125°C ±0.5 LSB 24-Lead LFCSP_VQ CP-24-5
AD5760BCPZ-REEL7 −40°C to +125°C ±0.5 LSB 24-Lead LFCSP_VQ CP-24-5
AD5760ACPZ −40°C to +125°C ±2 LSB 24-Lead LFCSP_VQ CP-24-5
AD5760ACPZ-REEL7 −40°C to +125°C ±2 LSB 24-Lead LFCSP_VQ CP-24-5
1 Z = RoHS Compliant Part.
AD5760 Data Sheet
Rev. B | Page 30 of 32
NOTES
Data Sheet AD5760
Rev. B | Page 31 of 32
NOTES
