General Description
The MAX15003 is a triple-output, pulse-width-modulat-
ed (PWM), step-down DC-DC controller with tracking
and sequencing capability. The device operates over
the input voltage range of 5.5V to 23V or 5V ±10%.
Each PWM controller provides an adjustable output
down to 0.6V and delivers up to 15A for each output
with excellent load and line regulation. The MAX15003
is optimized for high-performance, small-size power
management solutions.
The options of coincident tracking, ratiometric tracking,
and output sequencing allow the tailoring of the power-
up/power-down sequence depending on the system
requirements. Each of the MAX15003 PWM sections uti-
lizes a voltage-mode control scheme with external com-
pensation allowing for good noise immunity and
maximum flexibility with a wide selection of inductor val-
ues and capacitor types. Each PWM section operates
at the same, fixed switching frequency that is program-
mable from 200kHz to 2.2MHz and can be synchro-
nized to an external clock signal using the SYNC input.
Each converter operating at up to 2.2MHz with 120°
out-of-phase, increases the input capacitor ripple fre-
quency up to 6.6MHz, thereby reducing the RMS input
ripple current and the size of the input bypass capaci-
tor requirement significantly.
The MAX15003 includes internal input undervoltage
lockout with hysteresis, digital soft-start/soft-stop for
glitch-free power-up and power-down of each convert-
er. The power-on reset (RESET) with an adjustable
timeout period monitors all three outputs and provides
a RESET signal to the processor when all outputs are
within regulation. Protection features include lossless
valley-mode current limit and hiccup mode output
short-circuit protection.
The MAX15003 is available in a space-saving, 7mm x
7mm, 48-pin TQFN-EP package and is specified for
operation over the -40°C to +125°C automotive temper-
ature range. See the MAX15002 data sheet for a dual
version of the MAX15003.
Applications
PCI Express®Host Bus Adapter Power Supplies
Networking/Server Power Supplies
Point-of-Load DC-DC Converters
Features
o5.5V to 23V or 5V ±10% Input Voltage Range
oTriple-Output Synchronous Buck Controller
oSelectable In-Phase or 120° Out-of-Phase
Operation
oOutput Voltages Adjustable from 0.6V to 0.85VIN
oLossless Valley-Mode Current Sensing or
Accurate Valley Current Sensing Using RSENSE
oExternal Compensation for Maximum Flexibility
oDigital Soft-Start and Soft-Stop
oSequencing or Coincident/Ratiometric VOUT
Tracking
oIndividual PGOOD Outputs
oRESET Output with a Programmable Timeout
Period
o200kHz to 2.2MHz Programmable Switching
Frequency
oExternal Frequency Synchronization
oHiccup Mode Short-Circuit Protection
oSpace-Saving (7mm x 7mm) 48-Pin TQFN
Package
Ordering Information
19-1048; Rev 1; 8/12
PCI Express is a registered trademark of PCI-SIG Corporation.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
EVALUATION KIT AVAILABLE
Pin Configuration appears at end of data sheet.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
Note: Devices are also available in a tape-and-reel packaging.
Specify tape and reel by adding “T” to the part number when
ordering. Tape-and-reel orders are available in 2.5k incre-
ments.
PART TEMP RANGE PIN-PACKAGE
MAX15003ATM+ -40°C to +125°C 48 TQFN-EP*
(7mm x 7mm)
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
2Maxim Integrated
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2µF, RRT =
100kΩ, CCT = 0.1µF, RILIM_ = 60kΩ, TA= TJ= -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V and TA= TJ
= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, LX_, CSN_ to SGND..........................................-0.3V to +30V
BST_ to SGND ........................................................-0.3V to +30V
BST_ to LX_ ..............................................................-0.3V to +6V
REG, DREG_, SYNC, EN_, RT, CT,
RESET, PHASE, SEL to SGND ...............................-0.3V to +6V
ILIM_, PGOOD_, FB_, COMP_, CSP_ to SGND .......-0.3V to +6V
DL_ to PGND_.......................................-0.3V to (VDREG_ + 0.3V)
DH_ to LX_...............................................-0.3V to (VBST_ + 0.3V)
PGND_ to SGND, PGND_ to Any Other PGND_.......-0.3V to +0.3V
Continuous Power Dissipation (TA= +70°C)
48-Pin TQFN (derate 38.5mW/°C above +70°C) .......3076.9mW*
Operating Junction Temperature Range...........-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SYSTEM SPECIFICATIONS
5.5 23.0 V
Input Voltage Range VIN VIN = VREG = VDREG_ (Note 2) 4.5 5.5 V
Input Undervoltage Lockout
Threshold VUVLO VIN rising 3.95 4.05 4.15 V
Input Undervoltage Lockout
Hysteresis 0.35 V
Operating Supply Current VIN = 12V, VFB_ = 0.8V, no switching 5 8 mA
Shutdown Supply Current VIN = 12V, EN_ = 0V, PGOOD_ unconnected 150 300 µA
REG VOLTAGE REGULATOR
Output-Voltage Setpoint VREG VIN = 5.5V to 23V 4.9 5.2 V
Load Regulation IREG = 0 to 120mA, VIN = 12V 0.2 V
DIGITAL SOFT-START/SOFT-STOP
Soft-Start/Soft-Stop Duration 2048 Clocks
Reference Voltage Steps 64 Steps
ERROR TRANSCONDUCTANCE AMPLIFIER
FB_, TRACK_ Input Bias Current -250 +250 nA
TA = TJ = 0°C to +85°C 0.5945 0.6 0.6065 V
FB_ Voltage Setpoint VFB TA = TJ = -40°C to +125°C 0.590 0.6 0.608 V
PACKAGE THERMAL CHARACTERISTICS (Note 1)
48 TQFN
Junction-to-Ambient Thermal Resistance (θJA)...............26°C/W
Junction-to-Case Thermal Resistance (θJC)......................1.3°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
*
As per JEDEC51 standard (multilayer board).
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
3
Maxim Integrated
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FB_ to COMP_
Transconductance 2.1 mS
COMP_ Output Swing 0.75 3.50 V
Open-Loop Gain 80 dB
Unity-Gain Bandwidth 10 MHz
DRIVERS
DL_, DH_ Break-Before-Make
Time CLOAD = 5nF 20 ns
Low, sinking 100mA 0.9
DH1 On-Resistance High, sourcing 100mA 1.3
Ω
Low, sinking 100mA 0.9
DH2 On-Resistance
High, sourcing 100mA 0.3
Ω
Low, sinking 100mA 0.9
DH3 On-Resistance
High, sourcing 100mA 1.3
Ω
Low, sinking 100mA 0.9
DL1 On-Resistance High, sourcing 100mA 1.3
Ω
Low, sinking 100mA 0.9
DL2 On-Resistance
High, sourcing 100mA 1.3 Ω
Low, sinking 100mA 0.9
DL3 On Resistance
High, sourcing 100mA 1.3 Ω
LX_ to PGND_ On-Resistance Sinking 10mA 8 Ω
CURRENT-LIMIT AND HICCUP MODE
Cycle-By-Cycle Valley Current-
Limit Adjustment Range VCL VCL_ = VILIM_ / 10 50 300 mV
VILIM_ = 0.5V 44 54
Cycle-By-Cycle Valley Current-
Limit Threshold Tolerance VILIM_ = 3V 290 310 mV
ILIM_ Reference Current VILIM_ = 0 to 3V, TA = TJ = +25°C 20 µA
ILIM_ Reference Current
Temperature Coefficient 3333 ppm/°C
CSP_, CSN_ Input Bias Current VCSP_ = 0V, VCSN_ = -0.3V -20 +20 µA
Number of Cumulative Current-
Limit Events to Hiccup NCL 8
Number of Consecutive Non-
Current-Limit Cycles to Clear NCL NCLR 3
Hiccup Timeout 4096 Clock
periods
ENABLE/PHASE/SEL
EN_ Threshold VEN–TH EN_ rising 1.19 1.215 1.24 V
EN_ Threshold Hysteresis 0.12 V
EN_ Input Bias Current -1 +1 µA
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2µF, RRT =
100kΩ, CCT = 0.1µF, RILIM_ = 60kΩ, TA= TJ= -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V and TA= TJ
= +25°C, unless otherwise noted.) (Note 1)
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
4Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 5.5V to 23V or VIN = VREG = 4.5V to 5.5V, VDREG_ = VREG, VPGND_ = VSYNC = VPHASE = VSEL = 0V, CREG = 2.2µF, RRT =
100kΩ, CCT = 0.1µF, RILIM_ = 60kΩ, TA= TJ= -40°C to +125°C, unless otherwise noted. Typical values are at VIN = 12V and TA= TJ
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PHASE Input Logic High 2V
PHASE Input Logic Low 0.8 V
PHASE Input Bias Current -1 +1 µA
SEL High Threshold 80 %VREG
SEL Low Threshold 20 %VREG
SEL Input Bias Current Present only during startup -100 +100 µA
PGOOD, RESET OUTPUTS
FB_ For Threshold PGOOD_ FB_ falling 0.540 0.555 0.570 V
RESET, PGOOD_ Output Low
Level Sinking 3mA 0.1 V
RESET, PGOOD_ Leakage -1 +1 µA
CT Charging Current 1.8 2.0 2.2 µA
CT Pulldown Resistance Sinking 3mA 33 Ω
CT rising 1.8 2.6
CT Threshold for RESET Delay CT failling 1.2 V
OSCILLATOR
Switching Frequency Range
(Each Converter) fSW VSYNC = 0V, fCLK = 1011 / (RRT + 1.75kΩ) 200 2200 kHz
fSW ≤ 1500kHz -5 +5
Switching Frequency Accuracy
(Each Converter) fSW ≥ 1500kHz -7 +7 %
VPHASE = 0V (DH1 rising to DH2 rising and
DH2 rising to DH3 rising) 120 degrees
Phase Delay VPHASE = VREG (DH1 rising to DH2 rising
and DH2 rising to DH3 rising) 0 degrees
RT Voltage VRT 40kΩ < RRT < 500kΩ2V
Minimum Controllable On-Time tON
(
MIN
)
75 ns
Minimum Off-Time tOFF
(
MIN
)
150 ns
SYNC High-Level Voltage 2V
SYNC Low-Level Voltage 0.8 V
SYNC Internal Pulldown Resistor 50 100 200 kΩ
SYNC Frequency Range (Note 3) 0.6 6.9 MHz
SYNC Minimum On-Time 30 ns
SYNC Minimum Off-Time 30 ns
PWM Ramp Amplitude
(Peak-to-Peak) 2V
PWM Ramp Valley 1V
Note 1: 100% production tested at TA= TJ= +25°C and TA= TJ= +125°C. Limits at other temperature are guaranteed by design.
Note 2: For 5V applications, connect REG directly to IN.
Note 3: The switching frequency is 1/3 of the SYNC frequency.
CONVERTER 1 EFFICIENCY
vs. LOAD CURRENT
MAX15003 toc01
LOAD CURRENT (A)
EFFICIENCY (%)
1
50
60
70
80
90
100
40
0.1 10
VIN = 6V
VIN = 12V
VIN = 16V
VOUT1 = 3.3V
fSW = 600kHz
CONVERTER 2 EFFICIENCY
vs. LOAD CURRENT
MAX15003 toc02
LOAD CURRENT (A)
EFFICIENCY (%)
1
50
60
70
80
90
100
40
20
30
10
0
0.1 10
VIN = 6V
VIN = 12V
VIN = 16V
VOUT2 = 2.5V
fSW = 600kHz
CONVERTER 3 EFFICIENCY
vs. LOAD CURRENT
MAX15003 toc03
LOAD CURRENT (mA)
EFFICIENCY (%)
1
50
60
70
80
90
100
40
20
30
10
0
0.1 10
VIN = 6V
VIN = 12V
VIN = 16V
VOUT3 = 1.2V
fSW = 600kHz
CONVERTER 1 LOAD REGULATION
MAX15003 toc04
LOAD CURRENT (mA)
OUTPUT VOLTAGE ACCURACY (%)
1500
0
0.25
0.50
0.75
1.00
-0.25
-0.50
-0.75
-1.00
0 2000500 25001000 3000
VOUT1 = 3.3V
CONVERTER 2 LOAD REGULATION
MAX15003 toc05
LOAD CURRENT (mA)
OUTPUT VOLTAGE ACCURACY (%)
3000
0
0.25
0.50
0.75
1.00
-0.25
-0.50
-0.75
-1.00
0 40001000 50002000 6000
VOUT2 = 2.5V
CONVERTER 3 LOAD REGULATION
MAX15003 toc06
LOAD CURRENT (mA)
OUTPUT VOLTAGE ACCURACY (%)
6000
0
0.25
0.50
0.75
1.00
-0.25
-0.50
-0.75
-1.00
0 80002000 4000 10,000
VOUT3 = 1.2V
Typical Operating Characteristics
(Figure 8, VIN = 12V, CREG = 2.2µF, TA= +25°C, unless otherwise noted.)
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
5
Maxim Integrated
INTERNAL VOLTAGE REGULATION (REG)
MAX15003 toc07
IREG (mA)
VREG (V)
60
4.95
4.97
4.96
4.98
4.99
5.00
4.94
4.93
4.92
4.91
4.90
08020 40 100
VIN = 12V
CREG = 2.2µF
CONVERTER_ SWITCHING FREQUENCY
vs. RRT
MAX15003 toc08
RRT (kΩ)
SWITCHING FREQUENCY (kHz)
300 400
1000
10,000
100
0
0 500100 200 600
Typical Operating Characteristics (continued)
(Figure 8, VIN = 12V, CREG = 2.2µF, TA= +25°C, unless otherwise noted.)
SWITCHING FREQUENCY ACCURACY
vs. TEMPERATURE
MAX15003 toc09
TEMPERATURE (°C)
SWITCHING FREQUENCY ACCURACY (kHz)
50 10075
10
8
6
4
2
0
-2
-4
-6
-8
-10
-50 125-25 0 25 150
fSW = 600kHz
VALLEY CURRENT-LIMIT THRESHOLD
vs. VILIM
MAX15003 toc10
VILIM (mV)
VALLEY CURRENT-LIMIT THRESHOLD (mV)
2000 2500
350
300
250
200
150
100
50
500 30001000 1500 3500
VALLEY CURRENT-LIMIT THRESHOLD
vs. TEMPERATURE
MAX15003 toc11
TEMPERATURE (°C)
VALLEY CURRENT-LIMIT THRESHOLD (mV)
5025 75
100
90
80
70
60
50
40
30
20
-50 100 125-25 0 150
RILIM = 25.5kΩ
TEMPERATURE COEFFICIENT
(NOM.) = 3,333ppm/°C
SWITCHING CURRENT
vs. FREQUENCY
MAX15003 toc12
FREQUENCY (kHz)
SWITCHING CURRENT (mA)
1200
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
200 1700700 2200
RATIOMETRIC STARTUP
MAX15003 toc13
1ms/div
10V/div
1V/div
1V/div
1V/div
0V
VOUT1, 2, 3
VIN
VEN2 = VEN3 = 0V, SEL = REG
RATIOMETRIC SHUTDOWN
MAX15003 toc14
400
µ
s/div
500mV/div
500mV/div
0V
VOUT1, 2, 3
VOUT2
VOUT3
VOUT1
VEN2 = VEN3 = 0V, SEL = REG
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
6Maxim Integrated
CHANNEL 2 SHORT CIRCUIT
(RATIOMETRIC MODE)
MAX15003 toc15
400
µ
s/div
1V/div
1V/div
0V
VOUT2
VOUT3
VOUT1
VEN2 = VEN3 = 0V, SEL = REG
CHANNEL 1 SHORT CIRCUIT
(RATIOMETRIC MODE)
MAX15003 toc16
400
µ
s/div
1V/div
1V/div
1V/div
0V
0V
VOUT2
VOUT3
VOUT1
VEN2 = VEN3 = 0V, SEL = REG
Typical Operating Characteristics (continued)
(Figure 8, VIN = 12V, CREG = 2.2µF, TA= +25°C, unless otherwise noted.)
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
7
Maxim Integrated
CHANNEL 2 SHORT CIRCUIT
(COINCIDENT MODE)
MAX15003 toc19
400
µ
s/div
1V/div
1V/div
1V/div
10V/div
0V
0V
VOUT1
VOUT2
VIN
VOUT3
CHANNEL 1 SHORT CIRCUIT
(COINCIDENT MODE)
MAX15003 toc20
400
µ
s/div
1V/div
1V/div
1V/div
10V/div
0V
0V
VOUT1
VOUT2
VIN
VOUT3
SEQUENCING STARTUP
MAX15003 toc21
1ms/div
1V/div
0V
1V/div
1V/div
10V/div
0V
VIN
VOUT1, 2, 3
SEL = REG
SEQUENCING SHUTDOWN
MAX15003 toc22
400
µ
s/div
500mV/div
500mV/div
500mV/div
0V
VOUT3
VOUT1
VOUT2
SEL = REG
COINCIDENT STARTUP
MAX15003 toc17
1ms/div
1V/div
10V/div
1V/div
1V/div
0V
0V
VOUT1, 2, 3
VIN
CIRCUIT OF FIGURE 8, SEL = REG
COINCIDENT SHUTDOWN
MAX15003 toc18
400
µ
s/div
500mV/div
500mV/div
500mV/div
0V
VOUT1
VOUT2
VOUT3
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
8Maxim Integrated
Typical Operating Characteristics (continued)
(Figure 8, VIN = 12V, CREG = 2.2µF, TA= +25°C, unless otherwise noted.)
RESET AT SHUTDOWN
(SEQUENCING MODE)
MAX15003 toc25
400µs/div
1V/div
1V/div
1V/div
5V/div
0V
0V
VOUT1
VOUT2
VOUT3
VRESET
EN/TRACK2 = PGOOD1
EN/TRACK3 = PGOOD2
SEL = GND
CONVERTER 1 SHORT-CIRCUIT CONDITION
(HICCUP MODE)
MAX15003 toc26
1ms/div
10V/div
10A/div
1V/div
500mV/div
5V/div
VOUT1
IOUT1
VLX1
VDL1
VPGOOD1
CONVERTER 1 OUTPUT SHORT-CIRCUIT
(SEQUENCING MODE)
MAX15003 toc27
400µs/div
1V/div
1V/div
10V/div
2V/div
0V
0V
0V
VOUT1
VOUT2
VOUT3
VIN
EN/TRACK2 = PGOOD1
EN/TRACK3 = PGOOD2
SEL = GND
CONVERTER 2 OUTPUT SHORT-CIRCUIT
(SEQUENCING MODE)
MAX15003 toc28
400µs/div
2V/div
1V/div
10V/div
2V/div
0V
0V
0V
VOUT1
VOUT2
VOUT3
VIN
EN/TRACK2 = PGOOD1
EN/TRACK3 = PGOOD2
SEL = GND
CHANNEL 1 OUTPUT SHORT CIRCUIT
(SEQUENCING MODE)
MAX15003 toc23
400µs/div
1V/div
1V/div
10V/div
2V/div
0V
0V
0V
0V
VOUT3
VOUT1
VIN
VOUT2
SEL = GND EN/TRACK2 = PGOOD1
EN/TRACK3 = PGOOD2
RESET AT STARTUP
(SEQUENCING MODE)
MAX15003 toc24
20ms/div
1V/div
1V/div
1V/div
5V/div
0V
0V
VOUT1, 2, 3
EN/TRACK2 = PGOOD1
EN/TRACK3 = PGOOD2
VRESET
SEL = GND
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
9
Maxim Integrated
Typical Operating Characteristics (continued)
(Figure 8, VIN = 12V, CREG = 2.2µF, TA= +25°C, unless otherwise noted.)
CONVERTER 3 OUTPUT SHORT-CIRCUIT
(SEQUENCING MODE)
MAX15003 toc29
400µs/div
2V/div
1V/div
10V/div
1V/div
0V
0V
0V
VOUT1
VOUT2
VOUT3
VIN
EN/TRACK2 = PGOOD1
EN/TRACK3 = PGOOD2
SEL = GND
120° OUT-OF-PHASE OPERATION
MAX15003 toc30
400ns/div
10V/div
10V/div
5V/div
10V/div
0V
0V
0V
0V
VLX2
VLX3
VLX1
VSYNC
SEL = GND
IN-PHASE OPERATION
MAX15003 toc31
400ns/div
10V/div
10V/div
5V/div
10V/div
0V
0V
0V
0V
VLX2
VLX3
VLX1
VSYNC
SEL = GND
BREAK-BEFORE-MAKE TIMING
MAX15003 toc32
20ns/div
2V/div
5V/div
0V
0V
VDL1
VLX1
LOAD-TRANSIENT RESPONSE
(IOUT3 = 100mA TO 10A)
MAX15003 toc33
200
µ
s/div
100mV/div
(AC-COUPLED)
5A/div
0A
VOUT3
IOUT3
LOAD-TRANSIENT RESPONSE
(IOUT3 = 5A TO 10A)
MAX15003 toc34
200
µ
s/div
100mV/div
(AC-COUPLED)
5A/div
0A
VOUT3
IOUT3
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
10 Maxim Integrated
Pin Description
PIN NAME FUNCTION
1CT
RESET Timeout Capacitor Connection. Connect a timing capacitor from CT to SGND to set the RESET
delay. CT sources 2µA into the timing capacitor. When the voltage at CT passes 2V, open-drain RESET
goes high impedance.
2IN
Supply Input Connection. Connect to an external voltage source from 5.5V to 23V. For 4.5V to 5.5V input
application, connect IN and REG together.
3 REG 5V Regulator Output. Bypass with a 2.2µF ceramic capacitor to SGND.
4 SEL
Track/Sequence Select Input. Connect SEL to REG to configure as a triple tracker at startup or connect SEL
to SGND to configure as a triple sequencer or leave SEL unconnected to configure as a dual tracker and
independent sequencer. Note: When configured as a triple sequencer, each rail is independently enabled
using the EN_.
5 PGND1
Controller 1 Power-Ground Connection. Connect the input filter capacitor’s negative terminal, the source of
the synchronous MOSFET, and the output filter capacitor’s return to PGND1. Connect externally to SGND at
a single point near the input capacitor return terminal.
6 DL1 Controller 1 Low-Side Gate Driver Output. DL1 is the gate driver output for the synchronous MOSFET.
7 DREG1 Controller 1 Low-Side Gate Driver Supply. Connect externally to REG and the anode of the boost diode.
Connect a minimum of 0.1µF ceramic capacitor from DREG1 to PGND1.
8 LX1 Controller 1 High-Side MOSFET Source Connection/Synchronous MOSFET Drain Connection. Connect the
inductor and the negative side of the boost capacitor to LX1.
9 DH1 Controller 1 High-Side Gate Driver Output. DH1 drives the gate of the high-side MOSFET.
10 BST1 Controller 1 High-Side Gate Driver Supply. Connect BST1 to the cathode of the boost diode and to the
positive terminal of the boost capacitor.
11 CSN1
Controller 1 Negative Current-Sense Input. Connect CSN1 to the synchronous MOSFET drain (connected to
LX1). When using a current-sense resistor, connect CSN1 to the junction of a low-side MOSFET’s source
and the current-sense resistor. See Figure 11.
12 CSP1
Controller 1 Positive Current-Sense Input. Connect CSP1 to the synchronous MOSFET source (connected to
PGND1). When using a current-sense resistor, connect CSP1 to the PGND1 end of the current-sense
resistor.
13 ILIM1
Controller 1 Valley Current-Limit Set Output. Connect a 25kΩ to 150kΩ resistor, RILIM1, from ILIM1 to SGND
to program the valley current-limit threshold from 50mV to 300mV. ILIM1 sources 20µA out to RILIM1. The
resulting voltage divided by 10 is the valley current-limit threshold. When using a precision current-sense
resistor, connect a resistive divider from REG to ILIM1 to SGND to set the valley current limit. See Figure 11.
14 COMP1 Controller1 Error Transconductance Amplifier Output. Connect COMP1 to the compensation feedback
network.
15 EN1
Controller 1 Enable Input. EN1 must be above 1.24V, VEN-TH, for the PWM controller to start Output 1.
Controller 1 is the master. Use the master as the highest output voltage in a coincident tracking
configuration.
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
11
Maxim Integrated
Pin Description (continued)
PIN NAME FUNCTION
16 FB1 Controller 1 Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter
output to SGND to set the output voltage. The FB1 voltage regulates to VFB (0.6V).
17 PGOOD1 Controller 1 Power-Good Output. Open-drain PGOOD1 output goes high impedance (releases) when FB1 is
above 0.925 x VFB = 0.555V.
18 PGND2
Controller 2 Power Ground Connection. Connect the input filter capacitor’s negative terminal, the source of
the synchronous MOSFET, and the output filter capacitor’s return to PGND2. Connect externally to SGND at
a single point near the input capacitor return terminal.
19 DL2 Controller 2 Low-Side Gate Driver Output. DL2 is the gate driver output for the synchronous MOSFET.
20 DREG2 Controller 2 Low-Side Gate Driver Supply. Connect externally to REG and the anode of the boost diode.
Connect at minimum, a 0.1µF ceramic capacitor from DREG2 to PGND2.
21 LX2 Controller 2 High-Side MOSFET Source Connection/Synchronous MOSFET Drain Connection. Connect the
inductor and the negative side of the boost capacitor to LX2.
22 DH2 Controller 2 High-Side Gate Driver Output. DH2 drives the gate of the high-side MOSFET.
23 BST2 Controller 2 High-Side Gate Driver Supply. Connect BST2 to the cathode of the boost diode and to the
positive terminal of the boost capacitor.
24 CSN2
Controller 2 Negative Current-Sense Input. Connect CSN2 to the synchronous MOSFET drain (connected to
LX2). When using a current-sense resistor, connect CSN2 to the junction of the low-side MOSFET’s source
and the current-sense resistor. See Figure 11.
25 CSP2
Controller 2 Positive Current-Sense Input. Connect CSP2 to the synchronous MOSFET source (connected to
PGND2). When using a current-sense resistor, connect CSP2 to the PGND2 end of the current-sense
resistor.
26 ILIM2
Controller 2 Valley Current-Limit Set Output. Connect a 25kΩ to 150kΩ resistor, RILIM2, from ILIM2 to SGND
to program the valley current-limit threshold from 50mV to 300mV. ILIM2 sources 20µA out to RILIM2. The
resulting voltage divided by 10 is the valley current-limit threshold. When using a precision current-sense
resistor, connect a resistive divider from REG to ILIM2 to SGND to set the valley current limit. See Figure 11.
27 COMP2 Controller 2 Error Transconductance Amplifier Output. Connect COMP2 to the compensation feedback
network.
28 EN/TRACK2
Controller 2 Enable/Tracking Input. See Figure 2.
When sequencing, EN/TRACK2 must be above 1.24V for the PWM controller 2 to start.
Coincident tracking—connect the same resistive divider used for FB2, from Output 1 to EN/TRACK2 to
SGND.
Ratiometric tracking—connect EN/TRACK2 to analog ground.
29 FB2 Controller 2 Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter
output to SGND to set the output voltage. The FB2 voltage regulates to VFB (0.6V).
30 PGOOD2 Controller 2 Power-Good Output. Open-drain PGOOD2 output goes high impedance (releases) when FB2 is
above 0.925 x VFB = 0.555V.
31 PGOOD3 Controller 3 Power-Good Output. Open-drain PGOOD3 output goes high impedance (releases) when FB3 is
above 0.925 x VFB = 0.555V.
32 FB3 Controller 3 Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter
output to SGND to set the output voltage. The FB3 voltage regulates to VFB (0.6V).
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
12 Maxim Integrated
Pin Description (continued)
PIN NAME FUNCTION
33 EN/TRACK3
Controller 3 Enable/Tracking Input. See Figure 2.
When sequencing, EN/TRACK3 must be above 1.24V for the PWM controller 3 to start.
Coincident tracking—connect the same resistive divider used for FB3, from Output 1 to EN/TRACK3 to
SGND.
Ratiometric tracking—connect EN/TRACK3 to analog ground.
34 COMP3 Controller 3 Error Transconductance Amplifier Output. Connect COMP3 to the compensation feedback
network.
35 ILIM3
Controller 3 Valley Current-Limit Set Output. Connect a 25kΩ to 150kΩ resistor, RILIM3, from ILIM3 to SGND
to program the valley current-limit threshold from 50mV to 300mV. ILIM3 sources 20µA out to RILIM3. The
resulting voltage divided by 10 is the valley current-limit threshold. When using a precision current-sense
resistor, connect a resistive divider from REG to ILIM3 to SGND to set the valley current limit. See Figure 11.
36 CSP3
Controller 3 Positive Current-Sense Input. Connect CSP3 to the synchronous MOSFET source (connected to
PGND3). When using a current-sense resistor, connect CSP3 to the PGND3 end of the current-sense
resistor.
37 CSN3
Controller 3 Negative Current-Sense Input. Connect CSN3 to the synchronous MOSFET drain (connected to
LX3). When using a current-sense resistor, connect CSN3 to the junction of low-side MOSFET’s source and
the current-sense resistor. See Figure 11.
38 BST3 Controller 3 High-Side Gate Driver Supply. Connect BST3 to the cathode of the boost diode and to the
positive terminal of the boost capacitor.
39 DH3 Controller 3 High-Side Gate Driver Output. DH3 drives the gate of the high-side MOSFET.
40 LX3 Controller 3 High-Side MOSFET Source Connection/Synchronous MOSFET Drain Connection. Connect the
inductor and the negative side of the boost capacitor to LX3.
41 DREG3 Controller 3 Low-Side Gate Driver Supply. Connect externally to REG and anode of the boost diode.
Connect a minimum of 0.1µF ceramic capacitor from DREG3 to PGND3.
42 DL3 Controller 3 Low-Side Gate Driver Output. DL3 is the gate driver output for the synchronous MOSFET.
43 PGND3
Controller 3 Power-Ground Connection. Connect the input filter capacitor’s negative terminal, the source of
the synchronous MOSFET, and the output filter capacitor’s return to PGND3. Connect externally to SGND at
a single point near the input capacitor return terminal.
44 SYNC
Synchronization Input. Drive with a frequency at least 20% higher than three times the frequency
programmed using the RT pin. The switching frequency is 1/3 the SYNC frequency. Connect SYNC to
SGND when not used.
45 SGND Analog Ground Connection. Connect SGND and PGND_ together at one point near the input bypass
capacitor return terminal.
46 RT Oscillator Timing Resistor Connection. Connect a 500kΩ to 45kΩ resistor from RT to SGND to program the
switching frequency from 200kHz to 2.2MHz.
47 PHASE Phase Select Input. Connect PHASE to SGND for 120° out-of-phase operation between the controllers.
Connect to REG for in phase operation.
48 RESET RESET Output. Open-drain RESET output releases after all PGOODs are released and timeout programmed
by CT finishes.
— EP Exposed Pad. Solder the exposed pad to a large SGND plane.
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
13
Maxim Integrated
Functional Diagrams
REG
VREF
VR1
DOWN1
CLK1
FB1
COMP1
LDO
1.24V
SHDN SHDN
RES
OVERLOAD
MANAGEMENT
VREGOK
IN SEL
PWM CONTROLLER 1
EN1 CT RESET
1.24VON
1.12VOFF
SEQ_
EN
EN
OSC
OVL
CONFIG
CSP1
SGND
CSN1
ILIM1
BST1
DH1
LX1
DREG1
DL1
PGND1
OVL_
RQ
SET
DOMINANT
S
0.925
x
VREF
FB1
PGPD1
PGPD_
DIGITAL
SOFT-START
AND
SOFT-STOP
0.6V
REF
CONFIG
SELECTOR
E/A
CPWM
CLK1
LEVEL
SHIFT
RESET
TIMEOUT
RAMP
CLK2 CLK3
CURRENT-
LIMIT
SET
SYNC
RT
PHASE
EN1
OVL1
IMAX1 CLK1
SEQ_
PGOOD1
MAX15003
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
14 Maxim Integrated
Detailed Description
The MAX15003 is a triple-output, pulse-width-modulat-
ed (PWM), step-down, DC-DC controller with tracking
and sequencing options. The device operates over the
input voltage range of 5.5V to 23V or 5V ±10%. Each
PWM controller provides an adjustable output down to
0.6V and delivers up to 15A load current with excellent
load and line regulation.
Each of the MAX15003 PWM sections utilizes a volt-
age-mode control scheme for good noise immunity and
offers external compensation allowing for maximum
flexibility with a wide selection of inductor values and
capacitor types. The device operates at a fixed switch-
ing frequency that is programmable from 200kHz to
2.2MHz and can be synchronized to an external clock
signal using the SYNC input. Each converter, operating
at up to 2.2MHz with 120° out-of-phase, increases the
input capacitor ripple frequency up to 6.6MHz, reduc-
ing the RMS input ripple current and the size of the
input bypass capacitor requirement significantly.
The MAX15003 provides either coincident tracking,
ratiometric tracking, or sequencing. This allows tailor-
ing of the power-up/power-down sequence depending
on the system requirements.
The MAX15003 features lossless valley-mode current-
limit protection by monitoring the voltage drop across
the synchronous MOSFET’s on-resistance to sense the
inductor current. The MAX15003’s internal current
source exhibits a positive temperature coefficient to help
compensate for the MOSFET’s temperature coefficient.
Use an external voltage-divider when a more precise
current limit is desired. This divider along with a preci-
sion shunt resistor allows for more accurate current limit.
The MAX15003 includes internal undervoltage lockout
with hysteresis, digital soft-start/soft-stop for glitch-free
power-up and power-down of the converters. The
power-on reset (RESET) with adjustable timeout period
monitors all three outputs and provides a RESET signal
to a system controller/processor indicating when all
outputs are within regulation. Protection features
include lossless valley-mode current limit and hiccup
mode output short-circuit protection.
Functional Diagrams (continued)
VREF
VREF
VR2/3
DOWN2/3
CLK2/3
EN/
TRACK2/3
FB2/3
COMP2/3
EN2/3
RES
OVERLOAD
MANAGEMENT
PWM CONTROLLERS 2 AND 3 EN1
1.24VON
1.12VOFF
OVL
CONFIG
CSP2/3
CSN2/3
ILIM2/3
BST2/3
DH2/3
LX2/3
DREG2/3
DL2/3
PGND2/3
OVL_
EN
CONFIG
RQ
SET
DOMINANT
S
0.925
x
VREF
FB2/3
PGPD2/3
DIGITAL
SOFT-START
AND
SOFT-STOP
E/A
CPWM
CLK2/3
LEVEL
SHIFT
RAMP
CURRENT-
LIMIT
SET
CLK2/3
SHDNEN_
OVL2/3
IMAX2/3 CLK2/3
SEQ_
SEQ_
PGOOD2/3
MAX15003
SEL_
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
15
Maxim Integrated
Internal Undervoltage Lockout (UVLO)
VIN must exceed the default UVLO threshold before any
operation can commence. The UVLO circuitry keeps the
MOSFET drivers, oscillator, and all the internal circuitry
shut down to reduce current consumption. The UVLO
rising threshold is 4.05V with 350mV hysteresis.
Digital Soft-Start/Soft-Stop
The MAX15003 soft-start feature allows the load voltage
to ramp up in a controlled manner, eliminating output-
voltage overshoot. Soft-start begins after VIN exceeds
the undervoltage lockout threshold and the enable
input is above 1.24V. The soft-start circuitry gradually
ramps up the reference voltage. This controls the rate
of rise of the output voltage and reduces input surge
currents during startup. The soft-start duration is 2048
clock cycles. The output voltage is incremented
through 64 equal steps. The output reaches regulation
when soft-start is completed, regardless of output
capacitance and load.
Soft-stop commences when the enable input falls
below 1.12V. The soft-stop circuitry ramps down the
reference voltage controlling the output voltage rate of
fall. The output voltage is decremented through 64
equal steps in 2048 clock cycles.
Internal Linear Regulator (REG)
REG is the output terminal of a 5V LDO powered from IN
that provides power to the IC. Connect REG externally to
DREG to provide power for the low-side MOSFET gate
driver. Bypass REG to SGND with a minimum 2.2µF
ceramic capacitor. Place the capacitor physically close
to the MAX15003 to provide good bypassing. REG is
intended for powering only the internal circuitry and
should not be used to supply power to external loads.
REG can source up to 120mA. This current, IREG,
includes quiescent current (IQ) and gate drive current
(IDREG):
IREG = IQ+ [fSW x Σ(QGHS_ + QGLS_)]
where QGHS_ to QGLS_ are the total gate charge of
each of the respective high- and low-side external
MOSFETs at VGATE = 5V. fSW is the switching frequen-
cy of the converter and IQis the quiescent current of
the device at the switching frequency.
MOSFET Gate Drivers
DREG_ is the supply input for the low-side MOSFET dri-
ver. Connect DREG_ to REG externally. Everytime the
low-side MOSFET switches on, high peak current is
drawn from DREG for a short amount of time. Adding
an RC filter (1Ωto 3.3Ωand 2.2µF in parallel to 0.1µF
ceramic capacitors are typical) from REG to DREG_ fil-
ters out high-peak currents.
BST_ supplies the power for the high-side MOSFET dri-
vers. Connect the bootstrap diode from BST_ to DREG_
(anode at DREG_ and cathode at BST_). Connect a
bootstrap 0.1µF or higher ceramic capacitor between
BST_ and LX_. Though not always necessary, it may be
useful to insert a small resistor (4.7Ωto 22Ω) in series
with the BST_ pin and the cathode of the bootstrap
diode for additional noise immunity.
The high-side (DH_) and low-side (DL_) drivers drive
the gates of the external n-channel MOSFETs. The dri-
vers’ 2A peak source- and sink-current capability pro-
vides ample drive for the fast rise and fall times of the
switching MOSFETs. Faster rise and fall times result in
reduced switching losses.
The gate driver circuitry also provides a break-before-
make time (20ns typ) to prevent shoot-through currents
during transition.
Oscillator/Synchronization Input/Phase
Staggering (RT, SYNC, PHASE)
Use an external resistor at RT to program the
MAX15003 switching frequency from 200kHz to
2.2MHz. Choose the appropriate resistor at RT to cal-
culate the desired output switching frequency (fSW):
fSW (Hz) = 1011/(RRT + 1750) (Ω)
Connect an external clock at SYNC for external clock
synchronization. A rising clock edge on SYNC is inter-
preted as a synchronization input. If the SYNC signal is
lost, the internal oscillator takes control of the switching
rate, returning the switching frequency to that set by
RRT. This maintains output regulation even with intermit-
tent SYNC signals. For proper synchronization, the
external frequency must be at least 20% higher than
three times the frequency programmed through the RT
input. The switching frequency is 1/3 the SYNC fre-
quency. Connect SYNC to SGND when not used.
Connect PHASE to SGND for 120° out-of-phase opera-
tion between the controllers. Connect PHASE to REG
for in-phase operation.
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
16 Maxim Integrated
Coincident/Ratiometric
Tracking (SEL, EN/TRACK_)
The enable/tracking input in conjunction with digital soft-
start and soft-stop provides coincident/ratiometric track-
ing (see Figure 1). Track an output voltage by
connecting a resistive divider from the output being
tracked to the enable/tracking input. For example, for
VOUT2 to coincidentally track VOUT1, connect the same
resistive divider used for FB2, from OUT1 to
EN/TRACK2 to SGND. See Figure 2 and the Coincident
Startup and Coincident Shutdown graphs in the
Typical
Operating Characteristics
.
Track ratiometrically by connecting EN/TRACK_ to
SGND. This synchonizes the soft-start and soft-stop of
all the controllers’ references, and hence their respec-
tive output voltages track ratiometrically. See Figure 2
and the
Typical Operating Characteristics
(Ratiometric
Startup and Ratiometric Shutdown graphs).
Connect SEL to REG to configure as a triple tracker.
When the MAX15003 converter is configured as a
tracker, the output short-circuit fault situations at master
or slave outputs are handled carefully so that either the
master or slave output does not stay on when the other
outputs are shorted to the ground. When the slave is
shorted and enters in hiccup mode, both the master
and the other slave soft-stop. When the master is short-
ed and the part enters in hiccup mode, the slaves ratio-
metrically soft-stop. Coming out of the hiccup, all
outputs soft-start coincidently or ratiometrically
depending on their initial configuration. See the
Typical
Operating Characteristics
for the output behaviour dur-
ing the fault conditions. During power-off, when the
input falls below its UVLO, the output voltages fall down
at the rate depending on the respective output capaci-
tor and load.
Output-Voltage Sequencing
(SEL, EN/TRACK_, PGOOD)
Referring to Figure 1c, when sequencing, the
enable/tracking input must be above 1.24V for each PWM
controller to start. The PGOOD_ outputs and EN/TRACK_
inputs can be daisy-chained to generate power sequenc-
ing. Open-drain PGOOD_ outputs go high impedance
when FB_ is above the PGOOD_ threshold (555mV typ).
Connect a resistive divider from the power-good output to
the enable/tracking input to SGND to set when each con-
troller will start. See Figure 2. Connect SEL to SGND to
configure as a triple sequencer.
VOUT1
VOUT2
VOUT3
VOUT1
VOUT2
VOUT3
VOUT1
VOUT2
VOUT3
SOFT-START SOFT-STOP
SOFT-START SOFT-STOP
A) COINCIDENT TRACKING OUTPUTS
B) RATIOMETRIC TRACKING OUTPUTS
SOFT-
START SOFT-STOP
C) SEQUENCED OUTPUTS
Figure 1. Graphical Representation of Coincident Tracking,
Ratiometric Tracking, or PGOOD Sequencing
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
17
Maxim Integrated
Error Amplifier
The output of the internal error transconductance
amplifier (COMP_) is provided for frequency compen-
sation (see the
Compensation Design Guidelines
sec-
tion). The inverting input is FB_ and the output COMP_.
The error transamplifier has an 80dB open-loop gain
and a 10MHz GBW product.
Output Short-Circuit Protection
(Hiccup Mode)
The current-limit circuit employs a valley current-limiting
algorithm that either uses a shunt or the synchronous
MOSFET’s on-resistance as the current-sensing ele-
ment. Once the high-side MOSFET turns off, the volt-
age across the current-sensing element is monitored. If
this voltage does not exceed the current-limit threshold,
the high-side MOSFET turns on normally at the start of
the next cycle. If the voltage exceeds the current-limit
threshold just before the beginning of a new PWM
cycle, the controller skips that cycle. During severe
overload or short-circuit conditions, the switching fre-
quency of the device appears to decrease because the
on-time of the low-side MOSFET extends beyond a
clock cycle.
If the current-limit threshold is exceeded for more than
eight cumulative clock cycles (NCL), the device shuts
down (both DH and DL are pulled low) for 4096 clock
cycles (hiccup timeout) and then restarts with a soft-
start sequence. If three consecutive cycles pass with-
out a current-limit event, the count of NCL is cleared
(see Figure 3). Hiccup mode protects against a contin-
uous output short circuit.
COINCIDENT TRACKING PGOOD SEQUENCING
EN/TRACK2
SEL REG
VIN
EN1
RATIOMETRIC TRACKING
RA
RB
RA
RB
RC
RD
VIN
EN1
PGOOD1
EN/TRACK2
REG
VIN
EN1
VOUT2
FB2
VOUT3
FB3
VOUT1
EN/TRACK2
EN/TRACK3
RC
RD
EN/TRACK3
SEL
SEL REG
PGOOD2
EN/TRACK3
REG
Figure 2. Ratiometric Tracking, Coincident Tracking, PGOOD Sequencing Configurations
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
18 Maxim Integrated
PWM Controller
Design Procedures
Setting the Switching Frequency
Connect a 500kΩto 45kΩresistor from RT to SGND to
program the switching frequency from 200kHz to
2.2MHz. Calculate the switching frequency using the
following equation:
fSW = 1011/(RRT + 1750)
Higher frequencies allow designs with lower inductor
values and less output capacitance. Consequently,
peak currents and I2R losses are lower at higher
switching frequencies, but core losses, gate-charge
currents, and switching losses increase.
Effective Input Voltage Range
Although the MAX15003 converters can operate from
input supplies ranging from 5.5V to 23V, the input volt-
age range can be effectively limited by the MAX15003
duty-cycle limitations for a given output voltage. The
maximum input voltage is limited by the minimum on-
time (tON(MIN)):
where tON(MIN) is 75ns.
The minimum input voltage is limited by the maximum
duty cycle and is calculated using the following equa-
tion:
where tOFF(MIN) typically is equal to 150ns.
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX15003: inductance value (L),
peak inductor current (IPEAK), and inductor saturation
current (ISAT). The minimum required inductance is a
function of operating frequency, input-to-output voltage
differential, and the peak-to-peak inductor current
(∆IP-P). Higher ∆IP-P allows for a lower inductor value. A
lower inductance value minimizes size and cost and
improves large-signal and transient response.
However, efficiency is reduced due to higher peak cur-
rents and higher peak-to-peak output voltage ripple for
the same output capacitor. A higher inductance
increases efficiency by reducing the ripple current,
however resistive losses due to extra wire turns can
exceed the benefit gained from lower ripple current lev-
els especially when the inductance is increased without
also allowing for larger inductor dimensions. A good
rule of thumb is to choose ∆IP-P equal to 30% of the full
load current. Calculate the inductance using the follow-
ing equation:
VIN and VOUT are typical values so that efficiency is
optimum for typical conditions. The switching frequen-
cy is programmable between 200kHz and 2.2MHz (see
Oscillator/Synchronization Input/Phase Staggering (RT,
SYNC, PHASE)
section). The peak-to-peak inductor
current, which reflects the peak-to-peak output ripple,
is worst at the maximum input voltage. See the
Output
Capacitor Selection
section to verify that the worst-case
output current ripple is acceptable. The inductor satu-
ration current (ISAT) is also important to avoid runaway
current during continuous output short-circuit condi-
tions. Select an inductor with an ISAT specification high-
er than the maximum peak current.
LOUT IN OUT
IN SW P P
VVV
Vf I
= −
()
××
−
∆
VV
tf
IN MIN OUT
OFF MIN SW
()
()
≥−×
()
1
VV
tf
IN MAX OUT
ON MIN SW
() ()
≤×
CURRENT LIMIT COUNT OF 8
NCL
IN
CLR
INITIATE HICCUP
TIMEOUT
NHT
COUNT OF 3
NCLR
IN
CLR
Figure 3. Hiccup-Mode Block Diagram
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
19
Maxim Integrated
Input Capacitor Selection
The discontinuous input current of the buck converter
causes large input ripple currents, and therefore, the
input capacitor must be carefully chosen to withstand
the input ripple current and keep the input voltage rip-
ple within design requirements. The 120° ripple phase
operation increases the frequency of the input capaci-
tor ripple current to thrice the individual converter
switching frequency. When using ripple phasing, the
worst-case input capacitor ripple current is when the
one converter with the highest output current is on.
The input voltage ripple comprises ∆VQ(caused by the
capacitor discharge) and ∆VESR (caused by the ESR of
the input capacitor). The total voltage ripple is the sum of
∆VQand ∆VESR which peaks at the end of the on-cycle.
Calculate the input capacitance and ESR required for a
specified ripple using the following equations:
where:
ILOAD(MAX) is the maximum output current, ∆IP-P is the
peak-to-peak inductor current, and fSW is the switching
frequency.
For the condition with only one converter is on, calculate
the input ripple current using the following equation:
The MAX15003 includes UVLO hysteresis to avoid pos-
sible unintentional chattering during turn-on. Use addi-
tional bulk capacitance if the input source impedance is
high. At lower input voltage, additional input capaci-
tance helps avoid possible undershoot below the under-
voltage lockout threshold during transient loading.
Output Capacitor Selection
The allowed output voltage ripple and the maximum devi-
ation of the output voltage during load steps determine
the required output capacitance and its ESR. The output
ripple is mainly composed of ∆VQ(caused by the capaci-
tor discharge) and ∆VESR (caused by the voltage drop
across the equivalent series resistance of the output
capacitor). The equations for calculating the output
capacitance and its ESR are:
∆VESR and ∆VQare not directly additive because they
are out of phase from each other. If using ceramic
capacitors, which generally have low ESR, ∆VQ domi-
nates. If using electrolytic capacitors, ∆VESR domi-
nates.
The allowable deviation of the output voltage during
fast load transients also affects the output capacitance,
its ESR, and its equivalent series inductance (ESL). The
output capacitor supplies the load current during a
load step until the controller responds with a greater
duty cycle. The response time (tRESPONSE) depends on
the gain bandwidth of the converter (see the
Compensation Design Guidelines
section). The resis-
tive drop across the output capacitor’s ESR, the drop
across the capacitor’s ESL, and the capacitor dis-
charge cause a voltage droop during the load-step
(ISTEP). Use a combination of low-ESR tantalum/alu-
minum electrolytic and ceramic capacitors for better
load-transient and voltage-ripple performance. Surface-
mount capacitors and capacitors in parallel help
reduce the ESL. Keep the maximum output voltage
deviation below the tolerable limits of the electronics
being powered.
Use the following equations to calculate the required
ESR, ESL, and capacitance value during a load step:
where ISTEP is the load step, tSTEP is the rise time of the
load step, and tRESPONSE is the response time of the
controller.
EESR
STEP
OUT STEP RESPONSE
Q
EESL STEP
STEP
V
I
CIt
V
Vt
I
SR =
=
SL =
∆
∆
∆
×
×
CI
Vf
V
I
OUT PP
QSW
EESR
PP
=
SR =
∆
∆
∆
∆
−
−
××
×
8
2
IVVV
V
CIN RMS ILOAD MAX
OUT IN OUT
IN
() ()
=××
()
−
∆IVV V
Vf L
PP IN OUT OUT
IN SW
−−
()
×
××
=
EESR
LOAD MAX PP
CIN
LOAD MAX OUT
IN
QSW
V
II
IV
V
Vf
SR =
=
∆
∆
∆
()
()
+
⎛
⎝
⎜⎞
⎠
⎟
×⎛
⎝
⎜⎞
⎠
⎟
×
−
2
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
20 Maxim Integrated
Setting the Current Limit
Connect a 25kΩto 150kΩresistor, RILIM, from ILIM to
SGND to program the valley current-limit threshold
(VCL) from 50mV to 300mV. ILIM sources 20µA out to
RILIM. The resulting voltage divided by 10 is the valley
current-limit threshold.
The MAX15003 uses a valley current-sense method for
current limiting. The voltage drop across the low-side
MOSFET due to its on-resistance is used to sense the
inductor current. The voltage drop (VVALLEY) across the
low-side MOSFET at the valley point and at ILOAD is:
RDS(ON) is the on-resistance of the low-side MOSFET,
ILOAD is the rated load current, and ∆IP-P is the peak-
to-peak inductor current.
The RDS(ON) of the MOSFET varies with temperature.
Calculate the RDS(ON) of the MOSFET at its operating
junction temperature at full load using the MOSFET
datasheet. To compensate for this temperature varia-
tion, the 20µA ILIM reference current has a temperature
coefficient of 3333ppm/°C. This allows the valley cur-
rent-limit threshold (VCL) to track and partially compen-
sate for the increase in the synchronous MOSFET’s
RDS(ON) with increasing temperature. Use the following
equation to calculate RILIM:
Figure 4 illustrates the effect of the MAX15003 ILIM ref-
erence current temperature coefficient to compensate
for the variation of the MOSFET RDS(ON) over the oper-
ating junction temperature range.
Power MOSFET Selection
When choosing the MOSFETs, consider the total gate
charge, RDS(ON), power dissipation, the maximum drain-
to-source voltage and package thermal impedance. The
product of the MOSFET gate charge and on-resistance is
a figure of merit, with a lower number signifying better
performance. Choose MOSFETs that are optimized for
high-frequency switching applications. The average gate-
drive current from the MAX15003’s output is proportional
to the frequency and gate charge required to drive the
MOSFET. The power dissipated in the MAX15003 is pro-
portional to the input voltage and the average drive cur-
rent (see the
Power Dissipation
section).
Compensation Design Guidelines
The MAX15003 uses a fixed-frequency, voltage-mode
control scheme that regulates the output voltage by dif-
ferentially comparing the “sampled” output voltage
against a fixed reference. The subsequent error voltage
that appears at the error amplifier output (COMP) is
compared against an internal ramp voltage to generate
the required duty cycle of the pulse-width modulator. A
second order lowpass LC filter removes the switching
harmonics and passes the DC component of the pulse-
width-modulated signal to the output. The LC filter,
which has an attenuation slope of -40dB/decade, intro-
duces 180° of phase shift at frequencies above the LC
resonant frequency. This phase shift, in addition to the
inherent 180° of phase shift of the regulator’s self-gov-
erning (negative) feedback system, poses the potential
for positive feedback. The error amplifier and its associ-
ated circuitry are designed to compensate for this insta-
bility to achieve a stable closed-loop system.
The basic regulator loop consists of a power modulator
(comprises the regulator’s pulse-width modulator, asso-
ciated circuitry, and LC filter), an output feedback
divider, and an error amplifier. The power modulator
has a DC gain set by VIN / VRAMP, with a double pole
and a single zero set by the output inductance (L), the
output capacitance (COUT), and its equivalent series
resistance (ESR). A second, higher frequency zero also
exists, which is a function of the output capacitor’s ESR
and ESL); though only taken into account when using
very high-quality filter components and/or frequencies
of operation.
RILIM
RDS ON ICL MAX IPP
TC
=
() ( )
.
×⎛
⎝
⎜⎞
⎠
⎟×
×+× −°
()
⎡
⎣
⎢⎤
⎦
⎥
−−
−−
∆
210
20 10 61 3 333 10 325
VR I
I
VALLEY DS ON LOAD PP
=()
×⎛
⎝
⎜⎞
⎠
⎟
−−
∆
2
VALLEY CURRENT-LIMIT THRESHOLD
AND RDS(ON) vs. TEMPERATURE
MAX15003 fig04
TEMPERATURE (°C)
VILIM AND RDS(ON) (NORMALIZED)
13011070 90-10 10 30 50-30
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
0.5
-50 150
RDS(ON)
VILIM
RILIM = 25.5kΩ
Figure 4. Current-Limit Trip Point and VRDS(ON) vs.
Temperature
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
21
Maxim Integrated
Below are equations that define the power modulator:
The switching frequency is programmable between
200kHz and 2.2MHz using an external resistor at RT.
Typically, the crossover frequency (fCO), which is the
frequency when the system’s closed-loop gain is equal
to unity crosses the 0dB axis—should be set at or
below one-tenth the switching frequency (fSW/10) for
stable, closed-loop response.
The MAX15003 provides an internal transconductance
amplifier with its inverting input and its output available
to the user for external frequency compensation. The
flexibility of external compensation for each converter
offers wide selection of output filtering components,
especially the output capacitor. For cost-sensitive appli-
cations, use aluminum electrolytic capacitors and for
space-sensitive applications, use low-ESR tantalum or
multilayer ceramic chip (MLCC) capacitors at the out-
put. The higher switching frequencies of the MAX15003
allow the use of MLCC as the primary filter capacitor(s).
First, select the passive and active power components
that meet the application’s output ripple, component
size, and component cost requirements. Second,
choose the small-signal compensation components to
achieve the desired closed-loop frequency response
and phase margin as outlined below.
Closed-Loop Response and Compensation
of Voltage-Mode Regulators
The power modulator’s LC lowpass filter exhibits a vari-
ety of responses, depending on the value of the L and
C (and their parasitics).
One such response is shown in Figure 5a. In this example
the power modulator’s uncompensated crossover is
approximately 1/6th the desired crossover frequency,
fCO. Note also, the uncompensated roll-off through the
0dB plane follows the double-pole, -40dB/decade
slope and approaches 180° of phase shift, indicative of
a potentially unstable system. Together with the inher-
ent 180° of phase delay in the negative feedback
system, this may lead to near 360° or positive feed-
back—an unstable system.
The desired (compensated) roll-off follows a
-20dB/decade slope (and commensurate 90° of phase
shift), and, in this example, occurs at approximately 6x
the uncompensated crossover frequency, fCO. In this
example, a Type II compensator provides for stable
closed-loop operation, leveraging the +20dB/decade
slope of the capacitor’s ESR zero (see Figure 5b).
G
f
f
f
MOD DC
V
IN
VRAMP
LC LC
OUT
ZERO ESR ESR COUT
ZERO ESL ESR
ESL
()
,
,
=
=
=
=
1
2
1
2
2
π
π
π
××
××
×
POWER MODULATOR (LARGE, BULK OUTPUT
CAPACITOR(S)) GAIN (REAL, ASYMPTOTIC/
PHASE RESPONSE vs. FREQUENCY
MAX15003 fig05a
MAGNITUDE (dB)
PHASE (DEGREES)
-60
-40
-20
0
20
40
-80
100 1k 10k
FREQUENCY (Hz)
100k 1M 10M
10
-135
-90
-45
0
45
90
-180
|GMOD|
|GMOD|
fLC
fZERO,ESL
fZERO,ESR
< GMOD
Figure 5a. Power Modulator Gain and Phase Response (Large,
Bulk COUT)
MAX15003 fig05b
MAGNITUDE (dB)
PHASE (DEGREES)
FREQUENCY (Hz)
-60
-40
-20
0
20
40
60
80
-80
-135
-90
-45
0
45
90
135
180
-180
POWER MODULATOR (LARGE, BULK OUTPUT
CAPACITOR(S)) AND TYPE II COMPENSATION GAIN
(ASYMPTOTIC)/PHASE RESPONSE vs. FREQUENCY
100 1k 10k 100k 1M 10M
10
<GEA
|GEA|
fLC
fZERO,ESR
fZERO,ESL
fCO
< GMOD
Figure 5b. Power Modulator (Large, Bulk COUT) and Type II
Compensator Responses
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
22 Maxim Integrated
The Type II compensator’s mid-frequency gain
(approximately 18dB shown here) is designed to com-
pensate for the power modulator’s attenuation at the
desired crossover frequency, fCO (GE/A + GMOD = 0dB
at fCO). In this example, the power modulator’s inherent
-20dB/decade roll-off above the ESR zero (fZERO, ESR)
is leveraged to extend the active regulation gain-band-
width of the voltage regulator. As shown in Figure 5b,
the net result is a 6x increase in the regulator’s gain
bandwidth while providing greater than 75° of phase
margin (the difference between GE/A and GMOD
respective phases at crossover, fCO).
Other filter schemes pose their own problems. For
instance, when choosing high-quality filter capacitor(s),
e.g., MLCCs, and an inductor with minimal parasitics,
the inherent ESR zero may occur at a much higher fre-
quency, as shown in Figure 5c.
As with the previous example, the actual gain and
phase response is overlaid on the power modulator’s
asymptotic gain response. One readily observes the
more dramatic gain and phase transition at or near the
power modulator’s resonant frequency, fLC, versus the
gentler response of the previous example. This is due
to the component’s lower parasitics leading to the high-
er frequency of the inherent ESR zero of the output
capacitor. In this example, the desired crossover fre-
quency occurs
below
the ESR zero frequency.
In this example, a compensator with an inherent mid-
frequency double-zero response is required to mitigate
the effects of the filter’s double-pole. Such is available
with the Type III topology.
As demonstrated in Figure 5d, the Type III’s mid-
frequency double-zero gain (exhibiting a +20dB/
decade slope, noting the compensator’s pole at the ori-
gin) is designed to compensate for the power modula-
tor’s double-pole -40dB/decade attenuation at the
desired crossover frequency, fCO (again, GE/A + GMOD
= 0dB at fCO). (See Figure 5d).
In the above example, the power modulator’s inherent
(mid-frequency) -40dB/decade roll-off is mitigated by
the mid-frequency double zero’s +20dB/decade gain to
extend the active regulation gain-bandwidth of the volt-
age regulator. As shown in Figure 5d, the net result is
an approximate doubling in the regulator’s gain band-
width while providing greater than 60° of phase margin
(the difference between GE/A and GMOD respective
phases at crossover, fCO).
Design procedures for both Type II and Type III com-
pensators are shown below.
MAGNITUDE (dB)
PHASE (DEGREES)
FREQUENCY (Hz)
-60
-40
-20
0
20
40
-80
-135
-90
-45
0
45
90
-180
POWER MODULATOR (HIGH-QUALITY OUTPUT
CAPACITORS (S)) GAIN (REAL, ASYMPTOTIC)/
PHASE RESPONSE vs. FREQUENCY
MAX15003 fig05c
100 1k 10k 100k 1M 10M
10
|GMOD|
|GMOD|
|GMOD|
fLC
fZEROES
fZEROES
Figure 5c. Power Modulator Gain and Phase Response (High-
Quality COUT)
POWER MODULATOR (HIGH-QUALITY OUTPUT CAPACITOR(S))
AND TYPE III COMPENSATOR GAIN (ASYMPTOTIC)/
PHASE RESPONSE vs. FREQUENCY
MAX15003 fig05d
MAGNITUDE (dB)
PHASE (DEGREES)
FREQUENCY (Hz)
-60
-40
-20
0
20
40
60
80
-80
-203
-135
-68
0
68
135
203
270
-270
100 1k 10k 100k 1M 10M
10
< GEA
|GEA|
|GMOD|
fLC
fZEROES
fZEROES
fCO
< GMOD
Figure 5d. Power Modulator (High-Quality COUT) and Type III
Compensator Responses
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
23
Maxim Integrated
Type II: Compensation When f
CO
> f
ZERO, ESR
When the fZERO,ESR is lower than fCO and close to fLC,
a Type II compensation network provides the neces-
sary closed-loop response. The Type II compensation
network provides a mid-band compensating zero and
high-frequency pole (see Figures 6a and 6b).
RFCF provides the mid-band zero fMID,ZERO, and
RFCCF provides the high-frequency pole. Use the fol-
lowing procedure to calculate the compensation net-
work components.
1) Calculate the fZERO,ESR and LC double pole, fLC:
2) Calculate the unity-gain crossover frequency as:
3) Determine RFfrom the following:
Note: RFis derived by setting the total loop gain at
crossover frequency to unity, e.g., GEA(fCO) x GM(fCO)
= 1V/V. The transconductance error amplifier gain is
GEA(fCO) = gMx RFwhile the modulator gain is:
The total loop gain can be expressed logarithmically as
follows:
where VRAMP is the peak-to-peak ramp amplitude
equal to 2V.
4) Place a zero at or below the LC double pole, fLC:
5) Place a high-frequency pole at or below fP= 0.5 x
fSW:
6) Choose an appropriately sized R1 (connected from
OUT_ to FB_, start with a 10kΩ). Once R1 is select-
ed, calculate R2 using the following equation:
where VFB = 0.6V.
RRVFB
VOUT VFB
21
=× −
CCF RFfSW
=××
1
π
CFRFfLC
=××
1
2π
2
220
0log10 gmRF+
0log10
[]
××
××
()
××
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥=
ESR V
IN VFB
fCO LV
OUT VRAMP
dB
π
Gf
MOD CO
V
IN
VRAMP
ESR
fCO L
VFB
VOUT
()
=×
××
× 2π
RF
VRAMP fCO LV
OUT
VFB V
IN gmESR
=××
()
×××
2π
fCO
fSW
≤10
f
f
ZERO ESR ESR COUT
LC LC
OUT
, =
=
1
2
1
2
π
π
××
××
R1
RF
COMP
VOUT
VREF
CCF
CF
R2
-
+
gM
Figure 6a. Type II Compensation Network
GAIN
(dB)
1ST ASYMPTOTE
GMODVREFVOUT-1(ωCF)-1
ω(rad/s)
3RD ASYMPTOTE
GMODVREFVOUT-1(ωCCF)-1
2ND ASYMPTOTE
GMODVREFVOUT-1RF
1ST POLE
(AT ORIGIN)
2ND POLE
(RFCCF)-1
1ST ZERO
(RFCF)-1
Figure 6b. Type II Compensation Network Response
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
24 Maxim Integrated
Type III: Compensation When f
CO
< f
ZERO, ESR
As indicated above, the position of the output capaci-
tor’s inherent ESR zero is critical in designing an appro-
priate compensation network. When low-ESR ceramic
output capacitors are used, the ESR zero frequency
(fZERO, ESR) is usually much higher than unity
crossover frequency (fCO). In this case, a Type III com-
pensation network is recommended (see Figure 7a).
As shown in Figure 7b, a Type III compensation net-
work introduces two zeros and three poles into the con-
trol loop. The error amplifier has a low-frequency pole
at the origin, two zeros, and higher frequency poles.
The locations of the zeros and poles should be such
that the phase margin peaks at fCO.
Set the ratios of fCO-to-fZand fP-to-fCO equal to one
another, e.g., fCO = fP=5is a good number to get about
fZfCO
60° of phase margin at fCO. Whichever technique, it is
important to place the two zeros at or below the double
pole to avoid the conditional stability issue.
Use the following procedure to calculate the compen-
sation network components.
1) Select a crossover frequency, fCO:
2) Calculate the LC double-pole frequency, fLC :
3) Select RF≥10kΩ.
4) Place a zero fZ1 = 1at 0.75 x fLC where
2πx RFx CF
5) Calculate CIfor a target unity-gain crossover fre-
quency, fC:
Note: CIis derived by setting the total loop gain at
crossover frequency to unity, e.g., GEA(fCO) x
GMOD(fCO) = 1V/V. The total loop gain can be
expressed logarithmically as follows:
6) Place a second zero, fZ2, at or below fLC thereby
determining R1.
7) Place a pole (fP1 =1), at or below fZERO,ESR.
(2πx R1x CI)
8) Place a second pole (fP2 = 1 ) at or below
2πx RFx CCF
one-half the switching frequency.
9) Calculate R2 using the following equation:
where VFB = 0.6V.
RR VFB
VOUT VFB
21
=×−
CCF fSW RF
=××
1
π
RfZERO ESR CI
11
2
=××π
,
RfZCI
11
22
=××π
20 2
20
2
0
10
10 2
××××
[]
+
××
()
××
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥=
log
log ()
π
π
fRC
G
fLC
dB
CO F I
MOD DC
CO OUT
CI
fCO LC
OUT VRAMP
V
IN RF
=××× ×
×
2π
CFRFfLC
=×× ×
1
2075π.
f
LC LC
OUT
= 1
2π× ×
fCO
fSW
≤10
R1 RF
COMP
VOUT
VREF
R2
RI
CI
CF
CCF
-
+
gM
Figure 7a. Type III Compensation Network
Figure 7b. Type III Compensation Network Response
GAIN
(dB)
1ST ASYMPTOTE
(ωRICF)-1
3RD ASYMPTOTE
ωRFCI
5TH ASYMPTOTE
(ωRICCF)-1
4TH ASYMPTOTE
RFRI-1
ω(rad/sec)
2ND ASYMPTOTE
(RFRI)-1
1ST POLE
(AT ORIGIN)
2ND POLE
(RICI)-1
3RD POLE
(RFCCF)-1
1ST ZERO
(RFCF)-1
2ND ZERO
(RICI)-1
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
25
Maxim Integrated
Typical Operating Circuits
MAX15003
DREG3
VOUT2
150µF/16V
19.1kΩ6.04kΩ
750Ω
10kΩ
100µF
0.1µF
3.3µF
22µF
0.1µF
25.5kΩ
1.8µF
11kΩ
2.2µF
470nF
11kΩ
25.5kΩ
165kΩ10kΩ
2.2µF0.022µF
470pF
1.2nF
47pF
13kΩ
25.5kΩ
4.22kΩ
19.1kΩ
10kΩ750kΩ
1800pF
47pF
1200nF
100µF
34kΩ
34kΩ
1.15kΩ10kΩ
0.1µF
22µF
1nF
47pF
100nF
2.2Ω
2.2Ω
(1/2) IRF7904
(1/2) FDS6982A5
(1/2) FDS6982A5
IRF7807Z
NTMFS4835N
IN
CIN
PGND SGND
BST3
DH3
LX3
CSN3
COUT
120µF
(2)
DL3
VOUT3
CSP3
PGND3
EP
EN/TRACK3
FB3
COMP3
ILIM3
PGOOD3
IN
DREG2
BST2
DH2
LX2
CSN2
DL2
CSP2
EN/TRACK2
FB2
COMP2
ILIM2
PGND2
PGOOD2
SEL
PHASE
SYNC
RT
REG
SGND
CT
RESET
DREG1
BST1
DH1
LX1
CSN1
DL1
VOUT1
CSP1
PGND1
EN1
FB1
COMP1
ILIM1
PGOOD1
Figure 8. Coincident Triple Tracker with Lossless Current Sense
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
26 Maxim Integrated
Typical Operating Circuits (continued)
MAX15003
DREG3
VOUT2
IN
CIN
PGND SGND
BST3
DH3
LX3
CSN3
COUT DL3
VOUT3
CSP3
PGND3
EP
EN/TRACK3
FB3
COMP3
ILIM3
PGOOD3
IN
DREG2
BST2
DH2
LX2
CSN2
DL2
CSP2
EN/TRACK2
FB2
COMP2
ILIM2
PGND2
PGOOD2
SEL
PHASE
SYNC
RT
REG
SGND
CT
RESET
DREG1
BST1
DH1
LX1
CSN1
DL1
VOUT1
CSP1
PGND1
EN1
FB1
COMP1
ILIM1
PGOOD1
Figure 9. Triple Sequencer with Lossless Current Sense
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
27
Maxim Integrated
Typical Operating Circuits (continued)
MAX15003
DREG3
VOUT2
IN
CIN
PGND SGND
BST3
DH3
LX3
CSN3
COUT DL3
VOUT3
CSP3
PGND3
EP
EN/TRACK3
FB3
COMP3
ILIM3
PGOOD3
IN
DREG2
BST2
DH2
LX2
CSN2
DL2
CSP2
EN/TRACK2
FB2
COMP2
ILIM2
PGND2
PGOOD2
SEL
PHASE
SYNC
RT
REG
SGND
CT
RESET
DREG1
BST1
DH1
LX1
CSN1
DL1
VOUT1
CSP1
PGND1
EN1
FB1
COMP1
ILIM1
PGOOD1
Figure 10. Coincident Dual Tracker and a Sequencer with Lossless Current Sense
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
28 Maxim Integrated
Typical Operating Circuits (continued)
MAX15003
DREG3
VOUT2
IN
CIN
PGND SGND
BST3
DH3
LX3
DL3
COUT CSN3
VOUT3
CSP3
PGND3
EP
EN/TRACK3
FB3
COMP3
ILIM3
PGOOD3
IN
DREG2
BST2
DH2
LX2
CSN2
DL2
CSP2
EN/TRACK2
FB2
COMP2
ILIM2
PGND2
PGOOD2
SEL
PHASE
SYNC
RT
REG
SGND
CT
RESET
DREG1
BST1
DH1
LX1
CSN1
DL1
VOUT1
CSP1
PGND1
EN1
FB1
COMP1
ILIM1
PGOOD1
Figure 11. Ratiometric Triple Tracker with Accurate Valley-Mode Current Sense
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
29
Maxim Integrated
PWM Controller
Applications Information
Power Dissipation
The 48-pin TQFN thermally enhanced package can dis-
sipate up to 3.08W. Calculate power dissipation in the
MAX15003 as a product of the input voltage and the
total REG output current (IREG). IREG includes quies-
cent current (IQ) and the total gate drive current
(IDREG):
PD= VIN x IREG
IREG = IQ+ [fSW x (QG1 + QG2 + QG3 + QG4 + QG5 +
QG6)]
where QG1 to QG6 are the total gate charge of the low-
side and high-side external MOSFETs. fSW is the
switching frequency of the converter and IQis the qui-
escent current of the device at the switching frequency.
Use the following equation to calculate the maximum
power dissipation (PDMAX) in the chip at a given ambi-
ent temperature (TA):
PDMAX = 38.5 x (150 - TA)……….mW
PCB Layout Guidelines
Use the following guidelines to layout the switching
voltage regulator.
1) Place the IN, REG, and DREG_ bypass capacitors
close to the MAX15003.
2) Minimize the area and length of the high-current
loops from the input capacitor, upper switching
MOSFET, inductor, and output capacitor back to
the input capacitor negative terminal.
3) Keep the current loop formed by the lower switch-
ing MOSFET, inductor, and output capacitor short.
4) Keep SGND and PGND isolated and connect them
at one single point close to the negative terminal of
the input filter capacitor.
5) Run the current-sense lines CSP_ and CSN_ close
to each other to minimize the loop area.
6) Avoid long traces between the DREG_ bypass
capacitor, low-side driver outputs of the
MAX15003, MOSFET gate, and PGND. Minimize
the loop formed by the DREG_ bypass capacitor,
bootstrap diode, bootstrap capacitor, high-side dri-
ver output of the MAX15003, and upper MOSFET
gates.
7) Place the bank of output capacitors close to the
load.
8) Distribute the power components evenly across the
board for proper heat dissipation.
9) Provide enough copper area at and around the
switching MOSFETs, and inductor to aid in thermal
dissipation.
10) Connect the MAX15003 exposed paddle to a large
copper plane to maximize its power dissipation
capability. Connect the exposed paddle to SGND.
Do not connect the exposed paddle to the SGND
pin (pin 45) directly underneath the IC.
11) Use 2oz copper to keep the trace inductance and
resistance to a minimum. Thin copper PCBs com-
promise efficiency because high currents are
involved in the application. Also, thicker copper
conducts heat more effectively, thereby reducing
thermal impedance.
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
30 Maxim Integrated
Chip Information
PROCESS: BiCMOS
TOP VIEW
MAX15003
THIN QFN
(7mm x 7mm)
13
14
15
16
17
18
19
20
21
22
23
24
ILIM1
COMP1
EN1
FB1
PGOOD1
PGND2
DL2
DREG2
LX2
DH2
BST2
CSN2
48
47
46
45
44
43
42
41
40
39
38
37
1
+
2345678910
11 12
RESET
PHASE
RT
SGND
SYNC
PGND3
DL3
DREG3
LX3
DH3
BST3
CSN3
CSP1
CSN1
BST1
DH1
LX1
DREG1
DL1
PGND1
SEL
REG
IN
CT
36 35 34 33 32 31 30 29 28 27 26 25
CSP2
ILIM2
COMP2
EN/TRACK2
FB2
PGOOD2
PGOOD3
FB3
EN/TRACK3
COMP3
ILIM3
CSP3
Pin Configuration
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE OUTLINE NO. LAND
PATTERN NO.
48 TQFN-EP T4877+3 21-0144 90-0129
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________
31
© 2012 Maxim Integrated Products, Inc. The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
MAX15003
Triple-Output Buck Controller with
Tracking/Sequencing
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 10/07 Initial release —
1 8/12 Updated MOSFET Gate Drivers section 15
