ANALOG DEVICES 12-Bit Serial Input Multiplying CMOS D/A Converter PM-7943 FEATURES e Fast, Flexible Microprocessor Interface with Serial Data Input e Superior Accuracy +1/2 LSB INL Max +1 LSB Gain Error Max Low Sppm/C Max Tempco Improved ESD Resistance Auto-Insertable DIP Package Surface Mount SOL Package Superior Direct Replacement for AD7543 40C to +85C for the Extended Industrial Temperature Range e Available in Die Form APPLICATIONS e Process Contro! and Industrial Automation e Programmable Amplifiers e Digitally-Controlied Power Supplies, Attenuators, Fliters e Instrumentation e Avionics e Auto-Calibration Systems ORDERING INFORMATIONt TEMPERATURE RANGE GAIN NON- EXTENDED ERROR LINEARITY MILITARY* INDUSTRIAL COMMERCIAL +LSB = +1LSB ss PM7543AQ PM7543EQ - +2tSB s+ 1/2LSB - - PM7543GP 22LSB #1LSB s PM7543BQ PM7543FQ - +2LSB 41LSB = PM7543BRC/883_ PM7543FP ~ +2LSB +1LSB - PM7543FS - +2LSB +1LSB - PM7543FPC - For devices processed in total compliance to MIL-STD-883, add /883 after part number. Consult factory for /883 data sheet. Burn-in is available on commercial and industrial temperature range parts in CerDIP, plastic DIP, and TO-can packages. 'T For availability and burn-in information on SO and PLCC packages, contact your local sales office. ttt CerDIP and epoxy devices are available in the extended industrial tempera- ture range of -40C to +85C. tT CROSS REFERENCE TEMPERATURE PMI ADI RANGE PM7543AQ AD7543GTD PM7543AQ AD7543TD MIL PM7543BQ AD7543SD PM7543EQ AD7543GBD PM7543EQ AD7543BD IND PM7543FQ AD7543AD PM7543GP AD7543GKN PM7543GP AD7543KN COM PM7543FP AD7543JN PM7543FPC AD7543JP REV. D GENERAL DESCRIPTION The PM-7543 isa 12-bitresolution, multiplying, CMOS D/Aconverter, which features serial data input and current output. Serial data input reduces pin count and allows the PM-7543 to be placed in a smaller package, saving PC board space. Improved analog parameters such as digital charge injection, power supply rejection, outputcapacitance, feedthrough error, fast microprocessor interface, andimproved ESD protective circuitry make the PM-7543 a superior pin-compatible second-source to the industry standard AD7543. The rising or falling edge (user selected) of the strobe inputs are used to clock serial data (present at the SRI pin) into the input shift regis- ter. When the shift register's data has been updated, the new data word is transferred to the DAC register with use of the LOAD inputs. Continued PIN CONNECTIONS AGND STI 16-PIN EPOXY DIP (P-Suffix) 16-PIN CERDIP 20-PIN LCC (Q-Suftix) (RC-Suffix) 16-PIN SOL 20-PIN PLCC (S-Suftix) (PC-Suffix) FUNCTIONAL BLOCK DIAGRAM PM-7543 LS OF ra 1 Veer 0-8 12-BIT DA CONVERTER rr ours rO lour 2 4 3.9 aGno cLRO DAC REGISTER imo+] LOAD ot sTBIO stBs0-tt (err: SHIFT REGISTER) osai wn O00 sTe20-2 2 open DIGITAL-TO-ANALOG CONVERTERS 2-553PM-7943 GENERAL DESCRIPTION Continued Separate LOAD control inputs allow simultaneous output updating of multiple DACs. An asynchronous CLEAR input resets the DAC register without altering the data in the input register. Improved linearity and gain error performance may permit reduced circuit parts count through the elimination of trimming components. Fast interface timing may reduce timing designconsiderations while minimizing microprocessor wait states. The PM-7543is available in standard plasticand CerDIP packages that arecompatible with auto- insertion equipment. Foran even smaller package, considerthe DAC- 8043, available in an 8-pin mini-DIP. CerDIP and epoxy devices are available in the extended industrial temperature range of 40C to +85C. ABSOLUTE MAXIMUM RATINGS (T, = +25C, unless otherwide noted.) Voy 10 DGND.sesssssessssssstsststesseeneeestestsnseeeetneeeees Vagr 10 DGND..... Var to DGND......... DGND to AGND AGND to DGND ....ssncsssesseretsteresttentseetnteneeetes Vop + 0.3V Digital input Voltage Range Output Voltage (Pin 1, Pin 2) ............... euvsaeseenes -0.3V to V, seeseeaseee O.3V tO Vop Operating Temperature Range AQ/BQ VeEISIONS ..........ccccscsscsesceseseserssceraee 55C to +125C EQ/FOQ/FP/FPC/FS Versions ............:0 ~40C to +85C GP VOrSiON 0.0... ccccsccseseecesstsseecerencansseseeresesee 0C to +70C JUNCTION TOMPOratUre 0.0... secre sseesesecesceersssessneoes +150C Storage Temperature ...........sseseseccscseeseesees 65C to +150C Lead Temperature (Soldering, 60 Sec) ...........sccceesees +300C PACKAGE TYPE @,, (Note 1) G- UNITS 16-Pin Hermetic DIP (Q) 94 12 C/W 18-Pin Plastic DIP (P) 76 33 C 20-Contact LCC (RC) 88 33 C 20-Pin SOL (S) 88 25 C 20-Contact PLCC (PC) 73 33 C/W NOTE: 1. 8 8 specified for worst case mounting conditions, i.e., 8, . |S specified for device in socket for CerDIP, P-DIP, and LCC packages; @., is specified for device soldered to printed circuit board for SOL and PLCC packages. CAUTION: 1. Do not apply voltage higher than Vp p Of fess than DGND potential on any terminal except V___ (Pin 15) and R_ , (Pin 16). 2. The digital control input are zener-protected; however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all times until ready to use. 3. Use proper antistatic handling procedures. 4. Absolute Maximum Ratings apply to both packaged devices and DICE. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. ELECTRICAL CHARACTERISTICS at V,, = +5V; Vee = +10V5 Vous, Vouts = Vagnp = Vognp @ OV; Ty = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted. PM-7543 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY Resolution N 12 - - Bits Nonlinearity PM-7543A/E/G - - +1/2 (Note 1) INL PM-7543B/F - - +1 LSB Differential Nonlinearity PM-7543A/E - - 1/2 (Note 2) ONL PM-7543B/F/G - - #1 LSB T, = 425C . PM-7543A/E - - +1 Gain Error G PM-7543B/F/G - - +2 LSB (Note 3) FSE T, = Full Temp. Range All Grades - - +2 Gain Tempco (AGair/A Temp) Tors - - +5 ppm/C {Note 6) Power Supply Rejection Ratio PSRR AVyp #25% - +0.0006 0.002 %l% (4 Gain/A Vpp) Ty = +25C - - i Output Leakage Current | T, = Full Temp. Range A (Notes 4.5) LKa PM.-7543A/B - - 100 n PM-7543E/F/G - - +10 Ty = +25C - +0.002 +0.006 Zero Scale Error I T, = Full Temp. Range ise (Notes 8, 13) 2se PM-7543A/B - 40.05 +0.61 PM-7549E/F/G - +0.01 0.06 Input Resistance : (Note 9) Rw Vrer Pin 7 11 15 kQ 2-554 DIGITAL-TO-ANALOG CONVERTERS REV. DPM-7543 = OV; T, = Full Temperature V, AGND Voeno ELECTRICAL CHARACTERISTICS at V,, = +5V; Vaep = +10V; V f . I ~) Fouts Voura = Range specified under Absolute Maximum Ratings, unless otherwise noted. Continued PM-7543 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AC PERFORMANCE Output Current Setting Time t, - 0.380 1 ys (Notes 6,7) AC Feedthrough Error VacF =20Vp-p @ f= 10kHz Vrer ' lout) FT Ty = 425C ~ - 2.0 map (Note 6, 12) Veer = OV Digital to Analog Inyr Load = 1008 Glitch Energy Q Coyy = 13pF - - 20 avs (Note 6, 11) DAC register loaded alternately with all Os and all 1s Total Harmonic Vic. = 6V RMS @ 1kHz REF _ - i di Distortion (Note 6) THD DAC register loaded with all 1s 92 8 Output Noise Voltage Density e, Lorena nn a - - 18 nvWHz (Notes 6, 14) FB our DIGITAL INPUTS Digital Input HIGH Vin 24 - - Vv Digital Input LOW Vi - - 08 V Input Leakage Current (Note 10) ln Vip = OV to +5V - - +H yA Input Capacitance (Note 6) Cin Vin= OV - - 8 pF ANALOG OUTPUTS Output Capacitance Cours Digital Inputs = all 1s - - 90 F {Note 6) Courte Digital Inputs = all Os - - 30 P Quiput Capacitance Cours Digital Inputs = all Os ~ ~- 60 F (Note 6) Cours Digital inputs = all 1s - - 60 p TIMING CHARACTERISTICS STB used = T, = +25C 50 - - losy asthe strobe 1, =Full Temp. Range 50 - - STB2used = T, = +25C 20 ~ - Serial Input t t th ib = Full Temp. - - enn noe rime Ds2 asthe strobe T, =Full Temp Range 20 ns eB ons) STB3used T, = +25C 10 ~ - STB toss as the strobe T, = Fuil Temp. Range 20 - - STB4 used Ty = +25C 20 - - losa asthe strobe 1, =Full Temp. Range 20 - - STB1 used Ty, = +25C 40 - - Tous asthe strobe 7, = Full Temp. Range 50 - - STB2 used T, = +25C 50 - - Serial Input to tone as the strobe = T, = Full Temp. Range 60 - - Strobe Hold Times ns (tera = 808) STB3 used T, = +26C 80 - - STB tous asthe strobe = T, = Full Temp. Range 80 - - STB4 used T, = 426C 80 - - loa asthestrobe 1, =Full Temp. Range 80 ~ - REV. D DIGITAL-TO-ANALOG CONVERTERS 2-555PM-7943 ELECTRICAL CHARACTERISTICS at Vop =+5V; Veep = +10V; Vourt = Vourz = Vicnp = Vognp = OV; T, = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted. Continued PM-7543 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SRI Data Pulse Width tgp) Th = Full Temp. Range 100 - - ns STBi Pulse Width (STB1 = 80ns) tstat T, = Full Temp. Range 80 - - ns (Note 15) STB2 Pulse Width (STB2 = 10ns) lgype T, =Full Temp. Range 80 - - ns (Note 15) STB3 Pulse Width (STB3 = 80ns) tot Ty = Full Temp. Range 80 - - ns (Note 15) STB4 Pulse Width (STB4 = 80ns) lore4 T, = Full Temp. Range 80 - - ns (Note 15) T, = 425C 140 - - Load Pulse Width A oad Pulse Wi or ioe T,, = Full Temp. Range 180 - - ns LSB Strobe into Input Register T, =Full. Temp. - - to Load DAC Register Time ASB a= Full. Temp. Range ns CLR Pulse Width toLa T, = Full Temp. Range 80 - - ns POWER SUPPLY Supply Voltage Vop 4.75 5 .25 v Alt Digital Inputs = V,_, or V, - - 2 Cc tHE Supply Current bo All Digital Inputs = OV or V,, - - 0.4 mA NOTES: 41. 1/2 LSB = +0.012% of Full Scale. 9. Absolute temperature coefficient is less than +300ppm/C. 2. All grades are monotonic to 12-bits over temperature. 10. Digital inputs are CMOS gates; |, is typically 1nA at +25C. 3. Using more feedback resistor. V 11. Veg = OV, all digital inputs = OV to Vp 5 Of Vpp to OV. 4. _ 0 out all nie =Vip ner = ee y 12. Alldigital inputs = OV. . speci eae ., app es i, loute men Gigital inputs = V),,. 13. Calculated from worst case Ra. 7 oe oad 1000.6 ee pF ital input = OV 10 Vp oF V_,. 10 0V lage (iN LSB8) = Rarer | xg % 4098) Veep: * OUTt - ext = TSPhs 3! pul= DDT "BD . 14, Calculations from e_ = 4K TRB where: Extrapolated to 1/2 LSB: t, = propagation delay (t, p) +9t. where t = meas- K =Boluzmann constant JK Reresistance a ured time constant of the final RC decay. T =resistor temperature,K 8 = bandwidth, Hz 8. Veep = +10V, all digital inputs = OV. 15. Minimum low time pulse width for STB1, STB2, and STB4, and minimum 2-556 DIGITAL-TO-ANALOG CONVERTERS high time pulse width for STB3. REV. DPM-7543 DICE CHARACTERISTICS iri TTT ee TM 1. ours 9. [D2 2. ouT2 10. STB3 3. AGND 11. STB4 4. STB1 412. DGND 5. LDi 13. CLA 6. N.C. 14. V,,, (Substrate) 8. STB2 16. Ree Substrate (die backside) is internally connected to Vip- DIE SIZE 0.099 x 0.107 inch, 10,543 sq. mils (2.51 x 2.72 mm, 6.83 sq. mm) WAFER TEST LIMITS at V,,,, = +5V; Voie, = +10V; Vout: = Youre = Yaenn = Moanp = OV: Ta = 425C. PM-7543G PARAMETER SYMBOL CONDITIONS LIMITS UNITS STATIC ACCURACY Resolution N 12 Bits MIN Integral Nonlinearity INL +1 LSB MAX Differential Nonlinearity DNL +1 LSB MAX Gain Error Geog Using internal feedback resistor +2 LSB MAX Power Supply PSRR AV yp = 45% 0.002 lo MAX Rejection Ratio DD ona mth) hk Digital Inputs = V,, + nA MAX REFERENCE INPUT Input Resistance Ry Veer pad 715 kQ MIN/MAX DIGITAL INPUTS Digital Input HIGH Vig 2.4 V MIN Digital Input LOW Vi 0.8 V MAX Input Leakage Current I Vin = OV toV) 5 +1 pA MAX POWER SUPPLY Supply Current loo Disa hats - ovary as mA MAX NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. REV. D DIGITAL-TO-ANALOG CONVERTERS 2-557PM-7543 TYPICAL PERFORMANCE CHARACTERISTICS MULTIPLYING MODE MULTIPLYING MODE FREQUENCY RESPONSE TOTAL HARMONIC vs DIGITAL CODE DISTORTION vs FREQUENCY ALL BITS ON 0 0.032 ~ (MSB) B1y Vin = 6Vans a Bio W2 OUTPUT OP AMP: OP-42 9 Bg a Bs 94 0.018 on B; ee g ag Bs 2 _ 0.010 a: 5 g By z z FE z By E 0.0056 (LSB) Bg 2 < a 0.0032 96 108 0.0018 100 1k {ck 100k 1M 10M 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) SUPPLY CURRENT vs LINEARITY ERROR vs LINEARITY ERROR vs LOGIC INPUT VOLTAGE DIGITAL CODE REFERENCE VOLTAGE i Ipp (mA) aa INL (LSB) LINEARITY ERROR (LSB) J 9 1 2 3 4 5 9 512 1024 1536 2048 2560 3072 3584 4095 2 4 6 8 10 Vy (VOLTS) DIGITAL INPUT CODE (DECIMAL) Veer (VOLTS) LOGIC THRESHOLD VOLTAGE DNL ERROR vs vs SUPPLY VOLTAGE REFERENCE VOLTAGE THRESHOLD VOLTAGE (VOLTS) DNL (LSB) 1 3 5 7 9 11 13 15 2 4 6 8 10 Vpp (VOLTS) Vrer (VOLTS) 2-558 DIGITAL-TO-ANALOG CONVERTERS REV. DPM-7543 SPECIFICATION DEFINITIONS RESOLUTION The resolution of a DAC is the number of states (2") that the full- scale range (FSR) is divided (or resolved) into, where "n is equal to the number of bits. SETTLING TIME Time required for the analog output of the DAC to settle to within 1/2 LSB of its final value for a given digital input stimulus; i.e. zero to full scale. GAIN Ratio of the DAC's external operational amplifier output voltage to the V,_, input voltage when all digital inputs are HIGH. FEEDTHROUGH ERROR Error caused by capacitive coupling from V,-, to output. Feedthrough error limits are specified with all switches OFF. OUTPUT CAPACITANCE Capacitance from |,,,,, to ground. OUTPUT LEAKAGE CURRENT Current appearing at ly, when all digital inputs are LOW, or at lout2 terminal when all inputs are HIGH. GENERAL CIRCUIT INFORMATION The PM-7543 is a 12-bit multiplying D/A converter with a very low temperature coefficient, R-2R resistor ladder network, data input and control logic, and two data registers. The digital cir- cuitry forms an interface in which serial data can be loaded, under microprocessor control, into a 12-bit shift register and then transferred, in parallel, to the 12-bit DAC register. An asynchronous CLEAR function allows resetting the DAC register to a zero code (0000 0000 0000) without altering data stored in the registers. Asimplified circuit of the PM-7543 DAC is shown in Figure 1. An inverted R-2R ladder network consisting of silicon-chrome, thin- film resistors, and twelve pairs of NMOS current-steering switches. These switches steer binarily weighted currents into either |oyry OF Ioyza Switching current to |,,,,, OF lou7, yields a constant current in each ladder leg, regardless of digital input code. This constant current results in a constant input resis- tance at V,., equal to R (typically 11kQ). The V,,., input may be driven by any reference voltage or current, AC or OC, that is within the limits stated in the Absolute Maximum Ratings chart. The twelve output current-steering switches are in series with the R-2R resistor ladder, and therefore, can introduce bit errors. It was essential to design these switches such that the switch "ON" resistance be binarily scaled so that the voltage drop across each switch remains constant. If, for example, switch 1 of Figure 1 was designed with an "ON" resistance of 10 ohms, switch 2 for 20 ohms, etc., a constant 5mV drop would then be maintained across each switch. To further insure accuracy across the full temperature range, permanently "ON" MOS switches were included in series with REV. D Veer 10k2 10kn. 10k2 loutz | } I | 1 \ t | et i 10k0. 6 I 1 | | 1 { i lourt L-w-- ' ' t | 1 \ ' I ' | \ Rreepeack 2 a = a 2 2 a SS g T3 BIT 12 (LSB) DIGITAL INPUTS (SWITCHES SHOWN FOR DIGITAL INPUTS HIGH) * THESE SWITCHES PERMANENTLY ON FIGURE 1: Simplified DAC Circuit the feedback resistor and the R-2R ladder's terminating resis- tor. The "Simplified DAC Circuit," Figure 1, shows the location of these switches. These series switches are equivalently scaled to two times switch 1 (MSB) and to switch 12 (LSB) to maintain constant relative voltage drops with varying temperature. Dur- ing any testing of the resistor ladder or Ree e pp ac, (such as in- coming inspection), V,,) must be present to turn "ON" these series switches. ESD PROTECTION The PM-7543 data inputs have been designed with ESD resis- tance incorporated through careful layout and the inclusion of input protection circuitry. Figure 2 shows the input protection diodes. High voltage siatic charges applied to the digital inputs are shunted to the supply and ground rails through forward biased diodes. These protection diodes were designed to clamp the inputs well below dangerous levels during static discharge conditions. DTL/TTLICMOS INPUTS FIGURE 2: Digital Input Protection DIGITAL-TO-ANALOG CONVERTERS 2-559PM-7543 RFEEDBACK R= 10kn lours LeaKace laer e R= 10k ow + Vac I { 1/4096 A e LEAKAGE 90pF 0 four2 FIGURE 3: PM-7543 Equivalent Circuit (All Inputs LOW) Rreeopack Inge R= 10k em R= 10kN OWw\-# + VaeF | lout: 1/4096 4 WEAKAGE | 90pF lour2 A |LEAKAGE | 60pF FIGURE 4: PM-7543 Equivalent Circuit (All Digital Inputs HIGH) EQUIVALENT CIRCUIT ANALYSIS Figures 3 and 4 show equivalent circuits for the PM-7543's inter- nal DAC with all bits LOW and HIGH, respectively. The reter- ence current is switched to lo T2 when all data bits are LOW, and to |,,,;, when all bits are HIGH. The | -axage current source is the combination of surface and junction leakages to the substrate. The 1/4096 current source represents the con- stant 1-bit current drain through the ladder's terminating resis- tor. Output capacitance is dependent upon the digital input code. This is because the gate capacitance of MOS transistors in- creases with applied gate voltage. This output capacitance var- ies between the low and high values. DYNAMIC PERFORMANCE OUTPUT IMPEDANCE The output resistance, as in the case of the output capacitance, varies with the digital input code. This resistance, looking back into the |,.,,, terminal, may be between 11kQ (the feedback resistor alone when all digital inputs are LOW) and 7.5kQ (the feedback resistor in parallel with approximately 30kQ of the R- 2R ladder network resistance when any single bit logic is HIGH). Static accuracy and dynamic performance will be affected by these variations. 2-560 DIGITAL-TO-ANALOG CONVERTERS The gain and phase stability of the output amplifier, board lay- out, and power supply decoupling will all affect the dynamic performance of the PM-7543. The use of a small compensation capacitor may be required when high-speed operational ampli- fiers are used. It may be connected across the amplifiers feed- back resistor to provide the necessary phase compensation to critically damp the output. The considerations when using high-speed amplifiers are: 1. Phase compensation (see Figures 7 and 8). 2. Power supply decoupling at the device socket and use of proper grounding techniques. APPLICATIONS INFORMATION APPLICATION TIPS In most applications, linearity depends upon the potential of lout: toute: and AGND (pins 1, 2, and 3) being exactly equal to each other. In most applications, the DAC is connected to an external op amp with its noninverting input tied to ground (see Figures 7 and 8). The amplifier selected should have a low input bias current and low drift over temperature. The amplifier's input offset voltage should be fulled to less than +200uV (less than 10% of 1 LSB). The operational amplifiers noninverting input should have a minimum resistance connection to ground; the usual bias cur- rent compensation resistor should not be used. This resistor can cause a variable offset voltage appearing as a varying output error. All grounded pins should tie to a single common ground point, avoiding ground loops. The V,,. power supply should have a low noise level with no transients greater than +17V. It is recommended that the digital inputs be taken to ground or Vin Via a high value (1MQ) resistor; this will prevent the accu- mulation of static charge if the PC card is disconnected from the system. Peak supply current flows as the digital inputs pass through the transition region (see the Supply Current vs Logic Input Voltage graph under the Typical Performance Characteristics). The supply current decreases as the input voltage approaches the supply rails (V,,, or DGND), i.e. rapidly slewing logic signals that settle very near the supply rails will minimize supply current. OUTPUT AMPLIFIER CONSIDERATIONS When using high speed op amps, a small feedback capacitor (typically 5-30pF) should be used across the amplifier to mini- mize overshoot and ringing. For low speed or static applications, AC specifications of the amplifier are not very critical. In high- speed applications, slew rate, settling time, open-loop gain, and gain/ohase margin specifications of the amplifier should be se- lected for the desired performance. It has already been noted that an offset can be caused by including the usual bias current compensation resistor in the amplifier's noninverting input ter- minal. This resistor should not be used. instead, the amplifier should have a bias current which is low over the temperature range of interest. REV. OPM-7543 FIGURE 5: Simplified Circuit Static accuracy is affected by the variation in the DAC's output resistance. This variation is best illustrated by using the circuit of Figure 5 and the equation: VeRROR = Vos (1 + Ri} Ro where R.. is a function of the digital code, and: Ro = 10k for more than four bits of logic 1, R, = 80kQ for any single bit of logic 1. Therefore, the offset gain varies as follows: atcode 001111111111, VERROR; = Vos(1 + rie =2 Vos 10kQ at code 0100 0000 0000, 10kQ VERROR? = Vi [1 }=43 Vos Re ST 30KQ The error difference is 2/3 Vos: Since one LSB has a weight (for V,-, =+10V) of 2.4mV for the PM- 7543, itis clearly important that V,, be minimized, either using the amplifier's nulling pins, an external nulling network, or by selection of an amplifier with inherently low V,.. Amplifiers with sufficiently low V,, include PMI's OP-77, OP-97, OP-07, OP-27 and OP-42. INTERFACE LOGIC OPERATION The microprocessor interface of the PM-7543 has been de- signed with multiple STROBE and LOAD inputs to maximize interfacing options. Control signals decoding may be done on- chip or with the use of external decoding circuitry (see Fig- ure-11). Serial data can be clocked into the input register with STB1, STB2, or STB4. The strobe inputs are active on the rising edge. STB3 may be used with a falling edge to clock-in data. Holding any STROBE input at its selected state (i.e. STB1, STB2 or STB4 at logic HIGH or STB3 at logic LOW) will act to prevent any further data input. When a new data word has been entered into the input register, it is transferred to the DAC register by asserting both LOAD inputs. The CLR input allows asynchronous resetting of the DAC regis- ter to 0000 0000 0000. This reset does not affect data held in the input registers. While in unipolar mode, a CLEAR will result in the analog output going to OV. In bipolar mode, the output will go to Vier INTERFACE INPUT DESCRIPTION STB1 (Pin 4), STB2 (Pin 8), STB4 (Pin 11) Input Register Strobe. Inputs Active on Rising Edge. Selected to load serial data into input register. See Table 1 for details. STB3 (Pin 10) Input Register Strobe Input. Active on Fall- ing Edge. Selected to load serial data into input register. See Table 1 for details. LD1 (Pin 5), LD2 (Pin 9) - Load DAC Register Inputs. Active Low. Selected together to load contents of Input Register into DAC register. CLR (Pin 13) - Clear Input. Active Low. Asynchronous. When LOW, 12-bit DAC register is forced to a zero code (0000 0000 0000) regardless of other interface inputs. tev =t BITT tost tpsa toss: toss | | zx , font tora: tox tone menses) BIT 12 STROBE INPUT 1 2 (STB1, STB2, STB4) t S781 " *STROBE WAVEFORM IS INVERTED IF STB3 IS USED TO STROBE SERIAL DATA BITS INTO REGISTER. *DATA LOADED MSB FIRST. terea torn teres Sate teres STBS LOAD SERIAL DATA t je INPUT REGISTER eo} | of .)> Ms tos TDi AND (02 toe NOTES: LOAD INPUT REGISTER'S DATA INTO DAC REGISTER FIGURE 6: Timing Diagram REV. D DIGITAL-TO-ANALOG CONVERTERS 2-561PM-7543 TABLE 1: PM-7543 Truth Table PM-7543 Logic Inputs inputRegister Controllnputs DAC Register Control Inputs PM-7543 Operation Notes STB4 STB3 STB2 STB CLR LD2 LDi 0 1 0 Ff X X X 0 1 Ff ) X xX xX Serial Data Bit Loaded from SRI 23 0 7 0 0 X X X into Input Register . I 1 0 0 X X X ae 4 % XK X% x 0 xX x No Operation (Input Register) 3 x x 1 4 X X X 1 Reset DAC Register to Zero Code 0 Xx x (Code: 0000 0000 0000) 1,3 (Asynchronous Operation) a * No Operation (DAC Register) 3 Load DAC Register with the Contents 3 1 0 0 of Input Register NOTES: 1. CLR =0 Asynchronously resets DAC Register to 0000 0000 0000, but has no efieci on input Regisier. UNIPOLAR OPERATION (2-QUADRANT) The circuit shown in Figures 7 and 8 may be used with an AC or DC reference voltage. The circuit's output will range between OV and approximately V,,.. (4095/4096) depending upon the digital input code. The relationship between the digital input and the analog out- put is shown in Table 2. The V,,- voltage range is the maximum input voltage range of the op amp or +25V, whichever is lowest. In many applications the PM-7543's negligible zero scale error and very low gain error permit the elimination of the trimming of the com- ponents (R, and the external R--engack) Without adverse effects on circuit performance. +5V Veer iy |aer Yoo SERIAL R , aATAO 7% 4 yp Preeosac INPUT 1 PM-7543 9 CLR O4 13 3 45 CONTROL INPUTS ef a 12 | DGND FIGURE 7: Quadrant) Unipolar Operation with High Accuracy Op Amp (2- 2-562 DIGITAL-TO-ANALOG CONVERTERS 2. Serial datais loaded into Input Register MSB first, on edges shown is posilive edge, . is negalive edge. 3. 0=Logic LOW, 1 = Logic HIGH, X = Don't Care. TABLE 2: Unipolar Code Table DIGITAL INPUT NOMINAL ANALOG OUTPUT (Voy7 28 shown MSB LSB in Figures 7 and 8) Vv 4096) 1444 4494 1991 A (4088 Vaer (2042) 1000 0000 0001 aaa 1000 0000 0000 ~Vner (2048) - Wage 4096 2 O1i4 4444 49491 ~Vner {2047} 4096 0000 0000 0001 ~Vaer (1_} 4096 0000 0000 0000 ~Vner (| = 0 4096 NOTES: 1. Nominal full scale for the circuits of Figures 7 and 8 is given by FS =Vper (4095). REF (ie3a) 2. Nominal LSB magnitude for the circuits of Figures 7 and 8 is given by LS8 =Vrer {1_} or Veer (27) . REF (roa) or Var (2-7) For applications requiring a tighter gain error than 0.024% at 25C for the top grade part, or 0.048% for the lower grade part, the circuit in Figure 8 may be used. Gain error may be trimmed by adjusting R, . REV. DPM-7543 Rreenpack LR O] 13 O45 I 1 1 olen 12 _[esno TABLE 3: Bipolar (Offset Binary) Code Table FIGURE 8: Unipolar Operation with Fast Op Amp and Gain Error Trimming (2-Quadrant) The DAC register must first be loaded with all 1s. R, is then adjusted until Voy7=Veger (4095/4096). In the case of an adjustable V..-., R, and Reeeppack May be omitted, with V,_, adjusted to yield the desired full-scale output. BIPOLAR OPERATION (4-QUADRANT) Figure 9 details a suggested circuit for bipolar, or offset binary opera- tion. Table 3 shows the digital input to analog output relationship. The circuit uses offset binary coding. Two's complement code can be converted to offset binary by software inversion of the MSB or by the addition of an external inverter to the MSB input. Resistors R,, R,, and R, must be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coefficient match. Mismatching between R, andR, causes offset and full-scale errors while an R, to R, and R, mismatch will result in full-scale error. Calibration is performed by loading the DAC register with 1000 0000 0000 and adjusting R, until V,,,, =0V.R, and R, may be omitted by DIGITAL INPUT NOMINAL ANALOG OUTPUT MSB LSB (Vy, a8 shown in Figure 9) 14410 4491 4111 Vaer (2047) 2048 1000 0000 0001 + Veer (| 2048 1000 0000 0000 0 014d 4494 41941 Veer (\_} 2048 0000 0000 0001 Veer (2047) 2048 0000 0000 0000 -Vner (2048) 2048 NOTES: 1. Nominal full scale for the circuits of Figure 9 is given by FS =Vper (2047). AEF Gael 2. Norninal LSB magnitude for the circuits of Figure 9 is given by LSB =Vrer{_t_}. REF (soaal adjusting the ratio of R, to R, to yield V,,, , = OV. Full scale can be adjusted by loading the DAC register with 1114 1111 1111 and ei- ther adjusting the amplitude of V....- orthe value of R,, until the desired Vout is achieved. ANALOG/DIGITAL DIVISION The transfer function for the PM-7543 connected in the multiplying mode as shown in Figures 7 and 8 is: Vo =Vin Ar, A2 Ag, Ai2 where Ay assumes a value of 1 foran "ON" bit and 0 for an "OFF" bit. 12 _Lfoeno Yoo Fre Vin O-4 Vrer PM-7543 100Q CONTROL a1 SERIAL CONTROL DATA INPUTS INPUT FIGURE 9: Bipolar Operation (4-Quadrant, Offset Binary) REV. D DIGITAL-TO-ANALOG CONVERTERS 2-563PM-7943 DIGITAL FIGURE 10: Analog/Digital Divider The transfer function is modified when the DAC is connected in the feedback of an operational amplifier as shown in Figure 10 andis: Vo = fags | Ar Az Aa, Ata a! 52 93 912 The above transfer function is the division of an analog voltage (V,,_-) by a digital word. The amplifier goes to the rails with all bits "OFF" since division by zero is infinity. With all bits "ON," the gain is 1 (+1 LSB). The gain becomes 4096 with the LSB, bit 12, "ON." INTERFACING TO THE MC6800 As shown in Figure 11, the PM-7543 may be interfaced to the 6800 by successively executing memory WRITE instructions while ma- nipulating the data between WRITEs, so that each WRITE presents the next bit. In this example, the most significant bits are found in memory loca- tions 0000 and 0001. The four MSBs are found in the lower half of 0000, the eight LSBs in 0001. The data is taken from the DB. line. The serial data loading is triggered by STB1 which is asserted by a decoded memory WRITE toamemory location, RW, ando2. AWRITE to another address locationtransfers datafrom input register to DAC register. PM-7543 INTERFACE TO THE 8085 The PM-7543's interface to the 8085 microprocessoris shownin Figure 12. Note that the microprocessor's SOD line is used to present data serially to the DAC. 2-564 DIGITAL-TO-ANALOG CONVERTERS Ao 16-BIT ADDRESS BUS Aus RW}-_dlE, Ao Az MC6800 7ALS138 62 E; ADDRESS E DECODER 2 FROM SYSTEM RESET * ANALOG CIRCUITRY OMITTED FOR SIMPLICITY FIGURE 11: PM-7543 MC6800 Interface 8) ADDRESS BUS (16) 1s E, Ao Az ALE 212 s 74.5138 > +5VOJEs ADDRESS DECODER (8) AD, , sop STB2 sri LD2 S763 FROM SYSTEM RESET * ANALOG CIRCUITRY OMITTED FOR SIMPLICTY FIGURE 12: PM-7543 - 8085 Interface Data is strobed into the PM-7543 by executing memory write instruc- tions. The strobe 2 input is generated by decoding an address loca- tion and WR. Data is loaded into the DAC register with a memory write instruction to another address location. Serial data supplied to the PM-7543 must be present in the right- justified format in registers H and L of the microprocessor. REV. D