TECHNICAL NOTE Serial-in / Parallel-out Driver Series Serial / Parallel 4-input Drivers BU2050F, BU2092F/FV, BU2099FV, BD7851FP, BU2152FS Description Serial-in-parallel-out driver incorporates a built-in shift register and a latch circuit to control a maximum of 24 LED by a 4-line interface, linked to a microcontroller. A single external resistor can set the output current value of the constant current up to a maximum of 50mA. (BD7851FP only) CMOS open drain output type products can drive the maximum current of 25mA. Features 1) LED can be driven directly. 2) Parallel output of a maximum of 24 bit 3) Operational on low voltage (2.7V5.5V) 4) Cascade connection is possible (BU2050F and BU2092F/FV are not acceptable) Application For AV equipment such as, audio stereo sets, videos and TV sets, PCs, control microcontroller mounted equipment. Product line-up Parameter BU2050F BU2092F BU2092FV BU2099FV BD7851FP BU2152FS Unit Output current 25 25 25 25 50 25 mA Output line 8 12 12 12 16 24 line Output type CMOS CMOS - SSOP-A32 - Constant Open drain current Package SOP14 SOP18 SSOP-B20 SSOP-B20 HSOP25 Mar. 2008 Thermal derating curve 700 Pd [mW] Pd [mW] 700 600 BU2050F Power dissipation Power dissipation 500 400 BU2099FV 300 200 100 600 BU2092F 500 400 BU2092FV 300 200 100 85 0 25 50 75 100 125 150 0 175 Ambient temperature Ta [] 25 50 75 100 125 150 175 Ambient temperature Ta [] Pd [mW] 1600 1400 BD7851FP 1200 Power dissipation 1000 BU2152FS 800 600 400 200 85 0 25 50 75 100 125 150 175 Ambient temperature Ta [] Absolute maximum ratings (Ta=25) Parameter Symbol Power Supply Voltage Power dissipation 1 Power dissipation 2 Input Voltage Output Voltage Operating Temperature Storage Temperature VDD Pd1 Pd2 VIN Vo Topr Tstg *1 Reduced by 4.5mW/ *2 Reduced by 4.5mW/ *3 Reduced by 4.0mW/ *4 Reduced by 5.5mW/ *5 Reduced by 6.5mW/ BU2050F -0.3+7.0 450 *1 VSS-0.3VDD+0.5 VSS-0.3VDD+0.5 -40+85 -55+125 Limits BU2092F BU2092FV -0.3+7.0 450 (SOP) * 400 (SSOPB) *3 550 (SOP) *4 650 (SSOPB) *5 VSS-0.3VDD+0.3 VSS+25.0 -25+75 -55+125 2 Unit V mW mW V V over 25 over 25 over 25 for each increase in Ta of 1 over 25 (When mounted on a board 50mmx50mmx1.6mm Glass-epoxy PCB). for each increase in Ta of 1 over 25 (When mounted on a board 70mmx70mmx1.6mm Glass-epoxy PCB). Parameter Symbol Power Supply Voltage Power dissipation 1 Power dissipation 2 Input Voltage Output Voltage Operating Temperature Storage Temperature VDD Pd1 Pd2 VIN Vo Topr Tstg BU2099FV -0.3+7.0 400 (SSOPB) *6 650 (SSOPB) *9 VSS-0.3VDD+0.3 VSS+25.0 -40+85 -55+125 Limits BD7851FP 0+7.0 1450 *7 -0.3VCC+0.3 0+10 -30+85 -55+150 BU2152FS -0.3+7.0 800 *8 VSS-0.3VDD+0.3 VSS-0.3VDD+0.3 -25+85 -55+125 *6 Reduced by 4.5mW/ over 25 *7 Reduced by 11.6mW/ over 25 *8 Reduced by 8.0mW/ over 25 *9 Reduced by 6.5mW/ for each increase in Ta of 1 over 25 (When mounted on a board 70mmx70mmx1.6mm Glass-epoxy PCB). 2/24 Unit V mW mW V V Electrical characteristics BU2050F (Unless otherwise noted, Ta=25, VDD=4.55.5V) Parameter Symbol Min. Power Supply Voltage VDD 4.5 Input high-level Voltage VIH 0.7VDD Input low-level Voltage VIL VSS Input Hysteresis VHYS VDD-1.5 Output high-level Voltage VOHD VDD-1.0 VDD-0.5 VSS Output low-level Voltage VOLD VSS VSS Quiescent Current IDD - Typ. 0.5 - Max. 5.5 VDD 0.3VDD VDD VDD VDD 1.5 0.8 0.4 0.1 Unit V V V V BU2092F/FV (Unless otherwise noted, Ta=25, VSS=0V, VDD=5.0V/3.0V) Parameter Symbol Min. Typ. Power Supply Voltage VDD 2.7 Input high-level Voltage VIH 3.5 / 2.5 Input low-level Voltage VIL - Max. 5.5 1.5 / 0.4 Unit V V V Output low-level Voltage VOL - - 2.0 / 1.0 V Output high-level disable Current Output low-level disable Current IOZH IOZL - - 10.0 -5.0 A A Quiescent Current IDD - - 5.0 / 3.0 A Max. 5.5 1.5 / 0.9 Unit V V V - V BU2099FV (Unless otherwise noted, Ta=25, VSS=0V, VDD=5.0V/3.0V) Parameter Symbol Min. Typ. Power Supply Voltage VDD 2.7 Input high-level Voltage VIH 3.5 / 2.1 Input low-level Voltage VIL VDD-0.5 Output high-level Voltage (SO) VOH / VDD-0.3 - - 1.0 - - 1.5 2.0 V V mA IOH=-25mA IOH=-15mA IOH=-10mA IOL=25mA IOL=15mA IOL=10mA VIH=VDD, VIL=VSS Condition VDD=5V/3V VDD=5V/3V VDD=5V/3V, IOL=20mA/5mA VO=25.0V VO=0V VIN=VSS or VDD (VDD=5V/3V) OUTPUT:OPEN Condition VDD=5V/3V VDD=5V/3V VDD=5V/3V, IOH=-400A/-100A VDD=5V/3V, IOL1=10mA/5mA VDD=5V, IOL1=15mA VDD=5V, IOL1=20mA VDD=5V/3V, IOL2=1.5mA/0.5mA Output low-level Voltage 1 (Qx) VOL1 Output low-level Voltage 2 (SO) VOL2 - - 0.4 / 0.3 V IOZH - - 10 A VO=25.0V IOZL - - -5.0 A VO=0V IPD VCLR 1.1 - 150 / 60 2.4 A V OE= VDD, VDD=5V/3V IDD - - 200 A Output high-level disable Current (Qx) Output low-level disable Current (Qx) IPULLDOWN (OE) Low Voltage Reset Quiescent Current 3/24 V Condition VIN=VSS or VDD, VDD=5V OUTPUT:OPEN Electrical characteristics BD7851FP (Unless otherwise noted, Ta=25, VCC=5.0V) Parameter Symbol Min. Power Supply Voltage VDD 4.5 Input high-level Voltage VIH 0.8xVCC Input low-level Voltage VIL Output high-level Voltage VOH VCC-0.5 Output low-level Voltage VOL - Quiescent Current Reference Current Output Current (including the equation between each bit) Equation between each bit of Reference Current Output Current Change rate of reference current output current for output voltage Output Leak Current Typ. - Max. 5.5 0.2xVCC 0.5 Unit V V V V V - 0.7 1.0 mA - 1.8 3.0 mA - 4.0 6.5 mA - 30 40 mA Iolc1 48 55 62 mA IOH=-1mA IOL=1mA R=13k OUT1OUT16:OFF R=1.3k OUT1OUT16:OFF R=13k OUT1OUT16:ON R=1.3k OUT1OUT16:ON VOUT=2.0V, R=1.3k Iolc2 5.0 5.9 6.8 mA VOUT=2.0V, R=13k iolc - 1 6 % IVCC - 1 6 %/V IOH - 0.01 0.8 A Max. 5.5 0.6 1.5 1.0 0.8 5 1 1 Unit V V V ICC BU2152FS (Unless otherwise noted, Ta=25, VDD=2.75.5V) Parameter Symbol Min. Typ. Power Supply Voltage VDD 2.7 Input high-level Voltage VIH 2.0 Input low-level Voltage VIL -1.5 VDD Output high-level Voltage VOH VDD-1.0 VDD-0.5 Output low-level Voltage VOL Quiescent Current IDDST Input high-level Current IIH Input low-level Current IIL - 4/24 V V A A A Condition VOUTn=2.0V, R=1.3k (1bit : ON) VOUT=2.03.0V, R=1.3k VOUT=10V Condition VDD=5V VDD=5V IOH=-25mA IOH=-15mA IOH=-10mA IOL=25mA IOL=15mA IOL=10mA VIL=VSS, VIH=VDD Block diagram BU2050F STB Controller 8bit CLR Shift CLOCK Register L a t c h Write Buffer P1P8 DATA BU2092F/FV LCK Controller CLOCK DATA 12bit Shift Register L a t c h Write Buffer Q0Q11 OE BU2099FV LCK CLOCK LPF Controller DATA 12bit Shift Register L a t c h Write Buffer Q0Q11 OE BD7851FP S_IN 16bit Shift CLOCK Register L a t c h Write Buffer OUT1OUT16 SOUT LATCH ENABLE R_Iref Current Adjustment BU2152FS STB Controller 24bit CLB Shift CLOCK Register L a t c h Write Buffer P1P24 DATA SO 5/24 Operating description (1) Data clear When the reset terminal (CLR, CLB) is set to "L", the content of all latch circuits are set to "H", and all parallel outputs are initialised. (For model with reset terminal only) (2) Data transfer Serial data is sequentially input to the shift register during the rise of the clock time (strobe signal is not active). When the strobe signal is active, the content of the shift register are transferred to the latch circuit. (3) Cascade connection Serial input data is output from the serial output through the shift register, regardless of the strobe signal. (except for BU2050F, BU2092F/FV) Application circuit C1 (*) VDD P1 P2 Pn-2 Pn-1 Pn VDD Serial data input Clock input MPU VSS Strobe input Latch input Serial data output VSS P1 P2 Pn-2 Pn-1 Pn VDD Serial data input Clock input VSS Strobe input Latch input Serial data output (*C1 must be placed as close to the terminal as possible.) Fig. 1 BU2092F/FV DATA, CLOCK, LCK, OE BU2092F/FV Q0Q11 Interfaces BU2050F DATA, CLOCK, STB, CLR BU2050F P1P8 VDD VDD VDD VDD OUT INPUT OUTPUT IN GND(VSS) GND(VSS) GND(VSS) GND(VSS) BU2099FV DATA, CLOCK, LCK, OE VDD VDD GND(VSS) GND(VSS) GND(VSS) BU2099FV Q0Q11 BU2099FV SO VDD BU2152FS CLOCK, DATA, STB, CLB VDD VDD VDD VDD GND(VSS) GND(VSS) OUT IN OUT GND(VSS) (only OE pin) GND(VSS) GND(VSS) GND(VSS) GND(VSS) BU2152FS P1P28 VDD VDD VSS VSS BU2152FS SO VDD VSS GND(VSS) VDD VDD GND(VSS) GND(VSS) 6/24 GND(VSS) BU2050F Pin descriptions Pin No. 1 2 3 4 5 6 7 8 9 Pin Name P3 P4 P5 VSS P6 P7 P8 DATA CLK 10 STB 11 CLR 12 13 14 P1 P2 VDD Function Parallel Data Output GND Parallel Data Output Serial Data Input Clock Signal Input Strobe Signal Input In case of "L", the data of shift register outputs. In case of "H", all parallel outputs and data of latch circuit do not change. Reset Signal Input In case of "L", the data of latch circuit reset, and all parallel output (P1P8) can be L. Normally CLR=H Parallel Data output Power Supply Timing chart CLK DATA DATA8 DATA7 DATA6 DATA2 DATA1 CLR STB Pn Previous DATA DATA "L" Fig. 2 1. 2. 3. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 8 data bits into the DATA pin. th Pn parallel output data of the shift register is set after the 8 clock by the STB. Since the STB is level latch, data is retained in the "L" section and renewed in the "H" section of the STB. Function explanation A latch circuit has the reset function, which is common in all bits. In case of CLR terminal is "L", the latch circuit is reset non-synchronously without the other input condition, and all parallel output can be "L". A serial data inputted from DATA terminal is read in shift register with synchronized rising of clock. In case of STB is "L" (CLR is "H"), transmit the data which read in the shift register to latch circuit, and outputs from the parallel data output terminal (P1P8). In case of STB is "H", all parallel outputs and the data of latch do not change. 7/24 Switching characteristics (Unless otherwise specified, VDD=4.55.5V, Ta=25) Limit Parameter Symbol Min. Typ. Max. Unit Condition Set up time (DATA-CLK) tSD 20 - - ns - Hold time (DATA-CLK) tHD 20 - - ns - Set up time ( STB - CLK) tSSTB 30 - - ns - Hold time ( STB - CLK) tHSTB 30 - - ns - Propagation ( CLR - P1P8) tPDPCK - - 100 ns P1P8 terminal load 20pF or less Propagation ( STB - P1P8) tPDPSTB - - 80 ns P1P8 terminal load 20pF or less Propagation ( CLR - P1P8) tPDPCLR - - 80 ns P1P8 terminal load 20pF or less fMAX 5 - - MHz - Maximum clock frequency Switching Time Test Waveform fMAX 1 2 8 9 10 11 CLK tSD DATA tHD STB tHSTB tSSTB CLR P8 P1 tPDPSTB Fig. 3 8/24 tPDPCLR tPDPCK 12 BU2092F/FV Pin descriptions Pin No. Pin Name I/O Function 1 2 3 4 VSS DATA CLOCK LCK I I I GND Serial Data Input Shift clock of DATA (Rising Edge Trigger) Latch clock of DATA (Rising Edge Trigger) 511, 1418 Q0Q11 O Parallel Data Output (Nch Open Drain FET) Latch Data L H Output FET ON OFF 12, 13 17 18 N.C. OE VDD I - Non connected Output Enable ("H" level : output FET is OFF) Power Supply Timing chart CLOCK DATA DATA11 DATA10 DATA9 DATA1 DATA0 LCK OE "H" Qx Previous DATA DATA110 Note) Diagram shows a status where a pull-up resistor is connected to output. Fig. 4 1. 2. 3. 4. After the power is turned on and the voltage is stabilized, LCK should be activated, after clocking 12 data bits into the DATA terminal. th Qx parallel output data of the shift register is set after the 12 clock by the LCK. Since the LCK is a label latch, data is retained in the "L" section and renewed in the "H" section of the LCK. Data retained in the internal latch circuit is output when the OE is in the "L" section. Truth Table Input CLOCK x x x x DATA x x LCK x x OE H L L x x H x x x x x x x x x Function Output (Q0Q11) Disable Output (Q0Q11) Enable Store "L" in the first stage data of shift register, the previous stage data in the others. (The conditions of storage register and output have no change.) Store "H" in the first stage data of shift register, the previous stage data in the others. (The conditions of storage register and output have no change.) The data of shift register has no change. The data of shift register is transferred to the storage register. The data of storage register has no change. 9/24 Switching characteristics (Unless otherwise specified, VDD=5V, VSS=0V, Ta=25) Limit Parameter Minimum Clock Pulse Width Minimum Latch Pulse Width Symbol Unit Condition Min. Typ. Max. VDD(V) 1000 - - ns 3 500 - - ns 5 tw 1000 - - ns 3 (LCK) 500 - - ns 5 400 - - ns 3 200 - - ns 5 400 - - ns 3 200 - - ns 5 400 - - ns 3 200 - - ns 5 tPLZ - 90 - ns 3 RL=5k (LCK) - 55 - ns 5 CL=10pF tPZL - 115 - ns 3 RL=5k (LCK) - 50 - ns 5 CL=10pF - 70 - ns 3 RL=5k - 45 - ns 5 CL=10pF - 80 - ns 3 RL=5k - 35 - ns 5 CL=10pF tw - (LCK) Setup Time ts - (LCKCLOCK) Setup Time tsu - (DATACLOCK) Hold Time tH - (CLOCKDATA) Propagation (LCKOUTPUT QX) tPLZ Propagation ( OE OUTPUT QX) tPZL Switching Time Test Circuit 25V VDD Pulse Gen. RL Q0 CL CLOCK Pulse Gen. LCK Pulse Gen. DATA GND (Vss) 25V RL OE Q11 CL Pulse Gen. GND (Vss) Fig. 5 10/24 GND (Vss) BU2092F/FV Switching Time Test Waveforms tW 90% CLOCK 90% 10% tSU 90% tW 90% VDD 90% 10% 10% GND (VSS) tH VDD 90% tS DATA GND (VSS) tW(CLK) 90% 50% LCK VDD 90% 50% 10% tPLZ(LCK) GND (VSS) tPZL(LCK) VDD 50% 50% OE GND (VSS) tPZL tPLZ VDD 50% Qx 10% 50% 10% GND (VSS) Fig. 6 11/24 BU2099FV Pin descriptions Pin No. Pin Name I/O Function 1 2 3 4 5 VSS N.C. DATA CLOCK LCK I I I GND Non connected Serial Data Input Shift clock of Shift register (Rising Edge Trigger) Latch clock of Storage register (Rising Edge Trigger) 617 Q0Q11 (Qx) O Parallel Data Output (Nch Open Drain FET) Latch Data L H Output FET ON OFF 18 19 20 SO OE VDD O I - Serial Data Output Output Enable Control Input Power Supply OE pin is pulled down to Vss. Timing chart CLOCK DATA DATA12 DATA11 DATA10 DATA2 DATA1 LCK OE Qx SO Previous DATA "H" Previous DATA 11 DATA Previous DATA 11 DATA12 DATA11 Fig. 7 1. 2. 3. 4. 5. After the power is turned on and the voltage is stabilized, LCK should be activates, after clocking 12 data bits into the DATA terminal. Qx parallel output data of the shift register is set after the 12th clock by the LCK. Since the LCK is a label latch, data is retained in the "L" section and renewed in the "H" section of the LCK. Data retained in the internal latch circuit is output when the OE is in the "L" section. The final stage data of the shift register is output to the SO by synchronizing with the rise time of the CLOCK. Truth Table Input CLOCK x x x x DATA x x LCK x x OE H L L x x H x x x x x x x x x Function All the output data output "H" with pull-up. The Q0Q11 output can be enable and output the data of storage register. Store "L" in the first stage data of shift register, the previous stage data in the others. (The conditions of storage register and output have no change.) Store "H" in the first stage data of shift register, the previous stage data in the others. (The conditions of storage register and output have no change.) The data of shift register has no change. SO outputs the final stage data of shift register with synchronized falling edge of CLOCK, not controlled by OE. The data of shift register is transferred to the storage register. The data of storage register has no change. The Q0Q11 output have a Nch open drain Tr. The Tr is ON when data from shift register is "L", and Tr is OFF when data is "H". 12/24 BU2099FV Switching characteristics (Unless otherwise specified, VDD=5V, VSS=0V, Ta=25) Parameter Symbol Minimum Clock Pulse Width (CLOCK) tW Minimum Latch Pulse Width (LCK) tW (LCK) Setup Time (LCKCLOCK) tS Setup Time (DATACLOCK) tsu Hole Time (CLOCKDATA) tH Propagation (SO) tPLH tPHL tPLZ (LCK) Propagation (LCKQX) * tPZL (LCK) tPLZ Propagation ( QE QX) * tPZL Noise Pulse Suppression Time (LCK) * tI Min. Limit Typ. 1000 500 1000 500 400 200 400 200 400 200 - 360 170 260 175 115 85 175 65 30 20 Max. 500 250 - *Reference value Input Voltage Test Circuit RL =10k GND (Vss) P.G. VIH VIL GND Fig. 8 Switching Time Test Circuit +25V VDD RL =5k CL =10pF GND (Vss) GND (Vss) +25V P.G. RL =5k CL =10pF GND (Vss) Fig. 9 13/24 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD(V) 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 - Condition RL=5k CL=10pF RL=5k CL=10pF RL=5k CL=10pF RL=5k CL=10pF - BU2099FV Output Voltage Test Circuit VDD 25V 12 SW4 1 SW3 SW2 2 1 3 2 SW1 1 GND (Vss) IOL1 P.G. GND (Vss) GND (Vss) GND (Vss) IOH GND (Vss) GND (Vss) IOL2 GND (Vss) Test condition VOL1 Set all data "L". SW1="ON", SW2="3", SW3="1""12". VOL2 Set output data "L" to SO and SW4 is positioned to "2", then voltage is measured at IOL2. VOH Set output data "H" to SO and SW4 is positioned to "1", then voltage is measured at IOH. Fig. 10 Switching Time Test Waveforms tW 90% tW 90% 90% CLOCK VDD 90% 50% 50% 10% 50% 10% 10% GND (VSS) tH tSU 90% VDD 90% tS DATA GND (VSS) tW (CLK) 90% 50% VDD 90% 50% LCK tS 2 10% GND (VSS) tPLZ tPLZ(LCK) VDD 50% 50% OE GND (VSS) tPZL tPZL(LCK) VEXT 50% Qx 10% 50% 10% GND (VSS) tPLH tPHL VDD 50% 50% SO GND (VSS) Fig. 11 14/24 BD7851FP Pin descriptions Pin No. Pin Name Function 1 2 3 4 GND R_Iref LATCH S_IN OUT16 OUT6 P_GND OUT5 OUT1 SOUT CLOCK ENABLE VCC Ground Reference Current Output Current setting Latch Signal Input Serial Data Input 515 16 1721 22 23 24 25 Reference Current Output Ground for Driver Reference Current Output Serial Data Output Clock Input ENABLE VCC Timing chart CLOCK S_IN DATA16 DATA15 DATA14 DATA2 DATA1 LATCH ENABLE OUTn SOUT Previous DATA Previous DATA15 DATA Previous DATA2 Previous DATA14 Previous DATA1 DATA16 DATA15 DATA14 Fig. 12 1. 2. 3. 4. 5. After the power is turned on and the voltage is stabilized, LATCH should be activated, after clocking 16 data bits into the S_IN terminal. OUTn parallel output data of the shift register is set after the 16th clock by the LATCH. The final stage data of the shift register is outputted to the SOUT by synchronizing with the rise time of the CLOCK. Since the LATCH is a label latch, data is retained in the "L" section and renewed in the "H" section of the LATCH. Data retained in the internal latch circuit is outputted when the ENABLE is in the "L" section. When the ENABLE is in the "H" section, data is fixed in the "H" section. 15/24 BD7851FP Timing characteristics (Unless otherwise specified, VCC=5V, Ta=25) Parameter Min. Limit Typ. Max. 20 40 30 30 30 30 30 - 50 50 30 50 50 50 50 300 300 - 10 100 50 50 tpLH - 400 650 tpHL - 300 400 Symbol Frequency CLOCK Pulse Width CLOCK Pulse Width LATCH Pulse Width ENABLE Rise Time / Fall Time fclk twh twh tw tr / tf Setup Time tSU Hold Time th Rise Time tr Fall Time tf Unit MHz ns ns ns ns ns ns ns ns ns Propagation Condition CLOCK LATCH ENABLE CLOCK S_IN-CLOCK LATCH-CLOCK S_IN-CLOCK LATCH-CLOCK OUTn SOUT OUTn SOUT CLK-SOUT, LATCH ENABLE-OUTn CLK-SOUT, LATCH ENABLE-OUTn Reference Current of Output Current 250 [Condition] Vcc=5.0V, Vo=5.0V, Ta=25 IOUT [mA] 200 The reference current of output current is determined by the external resistor. (between 2pin and GND ) 150 100 50 0 0.1 1 10 100 R_Iref [k] This is a data for the standard sample, not guaranteed the characteristic. Fig. 13 R_Iref-VOUT 1.6 [Condition] Vcc=5.0V, Ta=27, all bit : ON 1.4 1.2 VOUT [V] 1.0 0.8 0.6 0.4 0.2 0.0 1 10 100 R_Iref [k] Notes the increase of consumption current Icc, in case sets the voltage of VOUT lower. See the graph above. Fig. 14 16/24 BD7851FP Test Circuit 1 Vcc Vcc 25 1 GND R LATCH S_IN 2 R_Iref ENABLE 24 3 LATCH CLOCK 23 4 S_IN SOUT 22 5 OUT16 OUT1 21 6 OUT15 OUT2 20 ENABLE CLOCK SOUT VE BD7851FP 7 OUT14 8 OUT13 OUT3 19 9 OUT12 OUT4 18 10 OUT11 OUT5 17 11 OUT10 P_GND 16 12 OUT9 OUT6 15 13 OUT8 OUT7 14 P_GND Fig. 15 Test Circuit 2 Vcc Vcc 25 1 GND R 2 R_Iref LATCH S_IN ENABLE 24 CLOCK 23 3 LATCH 4 S_IN SOUT 22 5 OUT16 OUT1 21 6 OUT15 OUT2 20 ENABLE CLOCK SOUT VE BD7851FP 7 OUT14 8 OUT13 OUT3 19 9 OUT12 OUT4 18 10 OUT11 OUT5 17 11 OUT10 P_GND 16 12 OUT9 OUT6 15 13 OUT8 OUT7 14 P_GND R=51 (note : R_Iref=1.3k) , C=15pF Fig. 16 17/24 BD7851FP Switching Time Test Waveforms tWh tr tf 0.8xVCC 0.8xVCC CLOCK 0.8xVCC 0.2xVCC 0.2xVCC tSU th 0.8xVCC 0.8xVCC S_IN twh 0.8xVCC LATCH 0.2xVCC tSU tpHL th 90% OUTn tpHL 90% 90% 10% 10% 10% tf tr tpHLtpLH 0.8xVCC 0.2xVCC ENABLE tw 0.8xVCC SOUT 0.2xVCC tpHLtpLH tftr Fig. 17 18/24 BU2152FS Pin descriptions Pin Pin Name No. 1 VSS 2 CLK 3 VSS 4 DATA 528 P1P24 29 SO 30 STB 31 CLB 32 VDD I/O Function I I O O I I - Ground Clock Input Ground Serial Data Input Parallel Data Output Cascade Output Strobe Signal Input active "L" Clear Signal Input active "L" Power Supply Timing chart CLK DATA DATA24 DATA23 DATA22 DATA2 DATA1 STB Pn Previous DATA Previous DATA24 SO DATA Previous DATA23 Previous DATA2 Previous DATA1 DATA24 DATA23 DATA22 Fig. 18 1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 24 data bits into the DATA terminal. Pn parallel output data of the shift register is set after the 24th clock by the LCK. Since the STB is a label latch, data is retained in the "H" section and renewed in the "L" section of the STB. The final stage data of the shift register is outputted to the SO by synchronizing with the rise time of the CLOCK. 2. 3. 4. Truth Table CLK Input STB CLB x x L H H L H L H Function All the data of the latch circuit are set to "H" (data of shift register does not change), all the parallel outputs are "H". Serial data of DATA pin are latched to the shift register. At this time, the data of the latch circuit does not change. The data of the shift register are transferred to the latch circuit, and the data of the latch circuit are outputted from the parallel output pin. The data of the shift register shifts 1bit, and the data of the latch circuit and parallel output also change. 19/24 BU2152FS Switching characteristics (Unless otherwise specified, VDD=2.75.5V, VSS=0V, Ta=25) Limit Parameter Symbol Unit Min. Typ. Max. Condition Maximum Clock Frequency fMAX 5 - - MHz Setup Time 1 tSU1 20 - - ns DATA-CLK Hold Time 1 tHD1 20 - - ns CLK-DATA Setup Time 2 tSU2 30 - - ns STB-CLK Hold Time 2 tHD2 30 - - ns CLK-STB Setup Time 3 tSU3 30 - - ns CLB-CLK Hold Time 3 tHD3 30 - - ns CLK-CLB Setup Time 4 tSU4 30 - - ns STB-CLB Hold Time 4 tHD4 30 - - ns CLB-STB Output Delay Time 1* tPD1 - - 100 ns CLK-P1P24 Output Delay Time 2* tPD2 - - 80 ns STB-P1P24 Output Delay Time 3* tPD3. - - 80 ns CLB-P1P24 *50pF of load is attached. 20/24 Switching characteristic conditions Setup/Hold Time (DATA-CLOCK, STB-CLOCK, CLB-CLOCK) tr tr 90% 90% 50% 50% CLOCK 10% 10% tSU1 DATA tHD1 STB 50% 50% tSU2 tHD2 CLB 50% 50% tSU3 tHD3 Setup/Hold Time (STB-CLB) CLB 50% STB tSU4 tHD4 Fig. 19 Switching characteristic conditions 1 Output Delay Time (CLOCK-P1P24) CLOCK 50% tPD1 P1P24 Output Delay Time (STB-P1P24) STB 50% tPD2 P1P24 Output Delay Time (CLB-P1P24) CLB 50% tPD3 50% Fig. 20 Switching characteristic conditions 2 21/24 Operation Notes 1. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. Connecting the power supply connector backward Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply lines. An external direction diode can be added. 3. Power supply lines Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit, not that capacitance characteristic values are reduced at low temperatures. 4. GND voltage The potential of GND pin must be minimum potential in all operating conditions. 5. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 6. Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if pins are shorted together. 7. Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 8. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting or storing the IC. 9. Ground Wiring Pattern When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. 10. Unused input terminals Connect all unused input terminals to VDD or VSS in order to prevent excessive current or oscillation. Insertion of a resistor (100k approx.) is also recommended. 22/24 Order Type Selections B U 2 0 5 0 F Package type F : SOP14, SOP18 FV : SSOP-B20 FP : HSOP25 FS : SSOP-A32 Product number 2050 2092 2099 7851 2152 ROHM model name BU BD E External Dimensions 2 E1 : Emboss tape reel Pin 1 on draw-out side E2 : Emboss tape reel Pin 1 opposite draw-out side TL : Emboss tape reel Pin 1 on draw-out side TR : Emboss tape reel Pin 1 opposite draw-out side SOP14 <Dimension> <Tape and Reel information> Tape Embossed carrier tape Quantity 2500pcs 8.70.2 0.3Min. 4.40.2 6.20.3 1.50.1 1 7 E2 (The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) 0.150.1 0.1 1234 1Pin Direction of feed Reel (Unit:mm) 1234 1234 1234 1234 1234 1234 1.27 0.40.1 1234 0.11 Direction of feed 8 14 When you order , please order in times the amount of package quantity. SOP18 <Dimension> <Tape and Reel information> Embossed carrier tape Tape 10 1 9 5.40.2 0.3Min. 18 2000pcs Direction of feed E2 (The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) 0.150.1 Direction of feed Reel (Unit:mm) 1234 1Pin 1234 1234 1234 1234 1234 0.1 0.40.1 1234 1.27 Quantity 1234 1.80.1 0.11 7.80.3 11.20.2 When you order , please order in times the amount of package quantity. SSOP-B20 <Dimension> <Tape and Reel information> Embossed carrier tape Tape 20 11 0.3Min. 1 10 0.15 0.1 E2 (The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) 0.1 1234 1234 1234 1pin 1234 Unit:mm) 1234 Reel 1234 1234 0.65 0.22 0.1 2500pcs Direction of feed 1234 6.4 0.3 1.15 0.1 4.4 0.2 0.1 6.5 0.2 Quantity Direction of feed When you order , please order in times the amount of package quantity. 23/24 HSOP25 <Dimension> <Tape and Reel information> 13.6 0.2 7.8 0.3 0.3Min. 0.25 0.1 1234 1234 Direction of feed 1pin Reel (Unit:mm) 1234 1234 0.1 0.36 0.1 1234 0.8 E2 (The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) 1234 0.11 13 1.95 0.1 2000pcs 1234 1.9 0.1 1 Embossed carrier tape Direction of feed 14 5.4 0.2 25 2.75 0.1 Tape Quantity When you order , please order in times the amount of package quantity. SSOP-A32 <Dimension> <Tape and Reel information> 1 16 2000pcs Direction of feed E2 0.3Min. 17 Quantity 1234 1234 1234 (Unit:mm) 1pin 1234 Reel 1234 0.36 0.1 0.15 0.1 0.1 1234 0.8 (The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) 1234 0.11 32 Embossed carrier tape 1234 1.8 0.1 7.8 0.3 5.4 0.2 13.6 0.2 Tape Direction of feed When you order , please order in times the amount of package quantity. 24/24 Catalog No.08T004A '08.3 ROHM (c) 1000 NZ Appendix Notes No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. Products listed in this document are no antiradiation design. The products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). Should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the NOTES specified in this catalog. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright (c) 2008 ROHM CO.,LTD. THE AMERICAS / EUROPE / ASIA / JAPAN Contact us : webmaster@ rohm.co. jp 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix1-Rev2.0