PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
1PS2033A 03/11/96
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Logic Block Diagram
Product Features:
Common Features:
• PI74FCT16373T, PI74FCT162373T, and PI74FCT162H373T are
high-speed,
low power devices with high current drive.
• Vcc = 5V ±10%
• Hysteresis on all inputs
• Packages available:
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 300 mil wide plastic SSOP (V)
PI74FCT16373T Features:
• High output drive: IOH = –32 mA; IOL = 64 mA
• Power off disable outputs permit "live insertion"
• Typical VOLP (Output Ground Bounce) < 1.0V
at VCC = 5V, TA = 25°C
PI74FCT162373T Features:
• Balanced output drivers: ±24 mA
• Reduced system switching noise
• Typical VOLP (Output Ground Bounce) < 0.6V
at VCC = 5V, TA = 25°C
PI74FCT162H373T Features:
• Bus Hold retains last active bus state during 3-state
• Eliminates the need for external pull-up resistors
Product Description:
Pericom Semiconductor’s PI74FCT series of logic circuits are pro-
duced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16373T, PI74FCT162373T, and PI74FCT162H373T
are 16-bit transparent latches designed with 3-state outputs and are
intended for bus oriented applications. The Output Enable and
Latch Enable controls are organized to operate as two 8-bit latches
or one 16-bit latch. When Latch Enable (LE) is HIGH, the flip-flops
appear transparent to the data. The data that meets the set-up time
when LE is LOW is latched. When OE is HIGH, the bus output is
in the high impedance state.
The PI74FCT16373T output buffers are designed with a Power-
Off disable allowing “live insertion” of boards when used as
backplane drivers.
The PI74FCT162373T has ±24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H373T has “Bus Hold” which retains the input’s
last state whenever the input goes to high-impedance preventing
“floating” inputs and eliminating the need for pull-up/down resistors.
PI74FCT16373T
PI74FCT162373T
PI74FCT162H373T
Fast CMOS 16-Bit
Transparent Latches
1OE
1LE
1O0
C
D
1D0
TO 7 OTHER CHANNELS
2OE
2LE
2O0
C
D
2D0
TO 7 OTHER CHANNELS
PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
2PS2033A 03/11/96
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Product Pin Description
Pin Name Description
xOE Output Enable Inputs (Active LOW)
xLE Latch Enable Inputs (Active HIGH)
xDx Inputs(1)
xOx 3-State Outputs
GND Ground
VCC Power
Inputs(1) Outputs(1)
XDXXOE xLE xOx
HLH H
LLH L
XHX Z
Truth Table
Note: 1. H = High Voltage Level, X = Don’t Care, L = Low
Voltage Level, Z = High Impedance
Product Pin Configuration
Note: 1. For the PI74FCT162H373T, these pins have “Bus
Hold.” All other pins are standard, outputs, or I/Os.
1
2
3
4
5
6
7
8
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
32
31
30
29
28
27
26
25
1
OE
1
O
0
1
O
1
GND
1
O
2
1
O
3
V
CC
1
O
4
1
O
5
GND
1
O
6
1
O
7
2
O
0
2
O
1
GND
2
O
2
2
O
3
V
CC
2
O
4
2
O
5
GND
2
O
6
2
O
7
2
OE
1
LE
1
D
0
1
D
1
GND
1
D
2
1
D
3
V
CC
1
D
4
1
D
5
GND
1
D
6
1
D
7
2
D
0
2
D
1
GND
2
D
2
2
D
3
V
CC
2
D
4
2
D
5
GND
2
D
6
2
D
7
2
LE
48-PIN
V48
A48
PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
3PS2033A 03/11/96
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DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 5.0V ± 10%)
Parameters Description Test Conditions(1) Min. Typ(2) Max. Units
VIH Input HIGH Voltage Guaranteed Logic HIGH Level 2.0 V
VIL Input LOW Voltage Guaranteed Logic LOW Level 0.8 V
IIH Input HIGH Current Standard Input , VCC = Max. VIN = VCC 1µA
IIH Input HIGH Current Standard I/O, VCC = Max. VIN = VCC 1µA
IIH Input HIGH Current Bus Hold Input(4), VCC = Max. VIN = VCC ±100 µA
IIH Input HIGH Current Bus Hold I/O(4), VCC = Max. VIN = VCC ±100 µA
IIL Input LOW Current Standard Input , VCC = Min. VIN = GND –1 µA
IIL Input LOW Current Standard I/O, VCC = Min. VIN = GND –1 µA
IIL Input LOW Current Bus Hold Input(4), VCC = Min. VIN = GND ±100 µA
IIL Input LOW Current Bus Hold I/O(4), VCC = Min. VIN = GND ±100 µA
IBHH Bus Hold Bus Hold Input(4), VCC = Min. VIN = 2.0V –50 µA
IBHL Sustain Current VIN = 0.8V +50
IOZH(5) High Impedance VCC = Max. VOUT = 2.7V 1 µA
IOZL(5) Output Current V CC = Max. VOUT = 0.5V –1 µA
VIK Clamp Diode Voltage VCC = Min., IIN = –18 mA –0.7 –1.2 V
IOS Short Circuit Current VCC = Max.(3), VOUT = GND –80 –140 –200 mA
IOOutput Drive Current VCC = Max.(3), VOUT = 2.5V –50 –180 mA
VHInput Hysteresis 100 mV
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature....................................................................–65°C to +150°C
Ambient Temperature with Power Applied ....................................–40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) ..............–0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only)...........–0.5V to +7.0V
DC Input Voltage ............................................................................ –0.5V to +7.0V
DC Output Current..................................................................................... 120 mA
Power Dissipation ..........................................................................................1.0W
Note:
Stresses greater than those listed under
MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to
absolute maximum rating conditions for
extended periods may affect reliability.
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Pins with Bus Hold are identified in the pin description.
5. This specification does not apply to bi-directional functionalities with Bus Hold.
PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
4PS2033A 03/11/96
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PI74FCT16373T Output Drive Characteristics (Over the Operating Range)
Parameters Description Test Conditions(1) Min. Typ(2) Max. Units
VOH Output HIGH Voltage VCC = Min., VIN = VIH or VIL IOH = –3.0 mA 2.5 3 .5 V
IOH = –15.0 mA 2.4 3.5
IOH = –32.0 mA 2.0 3.0
VOL Output LOW Voltage VCC = Min., VIN = VIH or VIL IOL = 64 mA 0.2 0.55 V
IOFF Power Down Disable VCC = 0V, VIN or VOUT ≤≤
≤≤
≤ 4.5V — — ±100 µA
PI74FCT162373T/162H373T Output Drive Characteristics (Over the Operating Range)
Parameters Description Test Conditions(1) Min. Typ(2) Max. Units
VOH Output HIGH Voltage VCC = Min., VIN = VIH or VIL IOH = –24.0 mA 2.4 3.3 V
VOL Output LOW Voltage VCC = Min., VIN = VIH or VIL IOL = 24 mA 0.3 0.55 V
IODL Output LOW Current VCC = 5V, VIN = VIH OR VIL, VOUT = 1.5V(3) 60 115 150 mA
IODH Output HIGH Current VCC = 5V, VIN = VIH OR VIL, VOUT = 1.5V(3) –60 –115 –150 mA
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is determined by device characterization but is not production tested.
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(4) Description Test Conditions Typ Max. Units
CIN Input Capacitance VIN = 0V 4.5 6 pF
COUT Output Capacitance VOUT = 0V 5.5 8 pF
PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
5PS2033A 03/11/96
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Power Supply Characteristics
Parameters Description Test Conditions(1) Min. Typ(2) Max. Units
ICC Quiescent Power VCC = Max. VIN = GND or VCC 0.1 500 µA
Supply Current
∆ICC Supply Current per VCC = Max. VIN = 3.4V(3) 0.5 1.5 mA
Input @ TTL HIGH
ICCD Supply Current per VCC = Max., VIN = VCC 60 100 µA/
Input per MHz(4) Outputs Open VIN = GND MHz
XOE = GND, XLE = VCC
One Bit Toggling
50% Duty Cycle
ICTotal Power Supply VCC = Max., VIN = VCC 0.6 1.5(5) mA
Current(6) Outputs Open VIN = GND
fI = 10 MHZ
50% Duty Cycle
XOE = GND, XLE = VCC
One Bit Toggling VIN = 3.4V 0.9 2.3(5)
VIN = GND
VCC = Max., VIN = VCC 2.4 4.5(5)
Outputs Open VIN = GND
fI = 2.5 MHZ
50% Duty Cycle
XOE = GND, XLE = VCC
16 Bits Toggling VIN = 3.4V 6.4 16.5(5)
VIN = GND
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. IC =IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
6PS2033A 03/11/96
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PI74FCT16373T Switching Characteristics over Operating Range
16373T 16373AT 16373CT 16373DT 16373ET
Com. Com. Com. Com. Com.
Parameters Description Conditions
(1)
Min Max Min Max Min Max Min Max Min Max Unit
t
PLH
Propagation Delay C
L
= 50 pF 1.5 8.0 1.5 5.2 1.5 4.2 1.5 3.8 1.5 3.4 ns
t
PHL
xDx to xOx R
L
= 500Ω
t
PLH
Propagation Delay 2.0 13.0 2.0 8.5 2.0 5.5 1.5 4.0 1.5 3.7 ns
t
PHL
xLE to xOx
t
PZH
Output Enable Time 1.5 12.0 1.5 6.5 1.5 5.5 1.5 4.8 1.5 4.4 ns
t
PZL
xOE to xOx
t
PHZ
Output Disable Time
(3)
1.5 7.5 1.5 5.5 1.5 5.0 1.5 4.0 1.5 4.0 ns
t
PLZ
xOE to xOx
t
SU
Setup Time HIGH 2.0 — 2.0 — 2.0 — 1.5 — 1.0 — ns
or LOW,
X
D
X
to
X
LE
t
H
Hold Time HIGH 1.5 — 1.5 — 1.5 — 1 .0 — 1.0 — ns
or LOW,
X
D
X
to
X
LE
t
W
xLE Pulse Width 6.0 — 5.0 — 5.0 — 3 .0 — 3.0 — ns
HIGH
(3)
t
SK
(o) Output Skew
(4)
— 0.5 — 0.5 — 0.5 — 0.5 — 0.5 ns
PI74FCT162373T Switching Characteristics over Operating Range
162373T 162373AT 162373CT 162373DT 162373ET
Com. Com. Com. Com. Com.
Parameters Description Conditions
(1)
Min Max Min Max Min Max Min Max Min Max Unit
t
PLH
Propagation Delay C
L
= 50 pF 1.5 8.0 1.5 5.2 1.5 4.2 1.5 3.8 1.5 3.4 ns
t
PHL
xDx to xOx R
L
= 500Ω
t
PLH
Propagation Delay 2.0 13.0 2.0 8.5 2.0 5.5 1.5 4.0 1.5 3.7 ns
t
PHL
xLE to xOx
t
PZH
Output Enable Time 1.5 12.0 1.5 6.5 1.5 5.5 1.5 4.8 1.5 4.4 ns
t
PZL
xOE to xOx
t
PHZ
Output Disable Time
(3)
1.5 7.5 1.5 5.5 1.5 5.0 1.5 4.0 1.5 4.0 ns
t
PLZ
xOE to xOx
t
SU
Setup Time HIGH 2.0 — 2.0 — 2.0 — 1.5 — 1.0 — ns
or LOW,
X
D
X
to
X
LE
t
H
Hold Time HIGH 1.5 — 1.5 — 1.5 — 1 .0 — 1.0 — ns
or LOW,
X
D
X
to
X
LE
t
W
xLE Pulse Width 6.0 — 5.0 — 5.0 — 3 .0 — 3.0 — ns
HIGH
(3)
t
SK
(o) Output Skew
(4)
— 0.5 — 0.5 — 0.5 — 0.5 — 0.5 ns
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
PI74FCT16373/162373/162H373T
16-BIT TRANSPARENT LATCHES
7PS2033A 03/11/96
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PI74FCT162H373T Switching Characteristics over Operating Range
162H373T 162H373AT 162H373CT 162H373DT 162H373ET
Com. Com. Com. Com. Com.
Parameters Description Conditions
(1)
Min Max Min Max Min Max Min Max Min Max Unit
t
PLH
Propagation Delay C
L
= 50 pF 1.5 8.0 1.5 5.2 1.5 4.2 1.5 3.8 1.5 3.4 ns
t
PHL
xDx to xOx R
L
= 500Ω
t
PLH
Propagation Delay 2.0 13.0 2.0 8.5 2.0 5.5 1.5 4.0 1.5 3.7 ns
t
PHL
xLE to xOx
t
PZH
Output Enable Time 1.5 12.0 1.5 6.5 1.5 5.5 1.5 4.8 1.5 4.4 ns
t
PZL
xOE to xOx
t
PHZ
Output Disable Time
(3)
1.5 7.5 1.5 5.5 1.5 5.0 1.5 4.0 1.5 4.0 ns
t
PLZ
xOE to xOx
t
SU
Setup Time HIGH 2.0 — 2.0 — 2.0 — 1.5 — 1.0 — ns
or LOW,
X
D
X
to
X
LE
t
H
Hold Time HIGH 1.5 — 1.5 — 1.5 — 1.0 — 1.0 — ns
or LOW,
X
D
X
to
X
LE
t
W
xLE Pulse Width 6.0 — 5.0 — 5.0 — 3.0 — 3.0 — ns
HIGH
(3)
t
SK
(o) Output Skew
(4)
— 0.5 — 0.5 — 0.5 — 0.5 — 0.5 ns
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
