Philips
Semiconductors
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
Product data sheet
Supersedes data of 2003 Jun 27 2004 May 19
INTEGRATED CIRCUITS
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2
2004 May 19
FEATURES
•5-bit 3-to-1 multiplexer, 1-bit latch DIP switch
•5-bit external hardware pins
•Two 6-bit internal non-volatile registers, fully pin-to-pin compatible
with PCA9559
•Selection between the two non-volatile registers
•Selection between non-volatile registers and external hardware
pins
•I2C/SMBus interface logic
•Internal pull-up resistors on input pin and control signals
•Active high write protect on input controls the ability to write to the
non-volatile registers
•2 address pins, allowing up to 4 devices on the I2C-bus
•5 open drain multiplexed outputs
•Open drain non-multiplexed output
•Internal 6-bit non-volatile registers programmable and readable via
I2C-bus
•External hardware 5-bit value readable via I2C-bus
•Multiplexer selection can be overridden by I2C-bus
•Operating power supply voltage 3.0 V to 3.6 V
•5 V and 2.5 V tolerant inputs/outputs
•0 to 400 kHz clock frequency
•ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V
MM per JESD22-A115, and 1000 V CDM per JESD22-C101
•Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA.
•Package offering: SO20, TSSOP20
DESCRIPTION
The PCA9560 is a 20-pin CMOS device consisting of two 6-bit
non-volatile EEPROM registers, 5 hardware pin inputs and a 5-bit
multiplexed output with one latched EEPROM bit. It is used for DIP
switch-free or jumper-less system configuration and supports Mobile
and Desktop VID Configuration, where 3 preset values (2 sets of
internal non-volatile registers and 1 set of external hardware pins)
set processor voltage for operation in either performance, deep
sleep or deeper sleep modes. The PCA9560 is also useful in server
and telecom/networking applications when used to replace DIP
switches or jumpers, since the settings can be easily changed via
I2C/SMBus without having to power down the equipment to open the
cabinet. The non-volatile memory retains the most current setting
selected before the power is turned off.
The PCA9560 typically resides between the CPU and Voltage
Regulator Module (VRM) when used for CPU VID (Voltage
IDentification code) configuration. It is used to bypass the
CPU-defined VID values and provide a different set of VID values to
the VRM, if an increase in the CPU voltage is desired. An increase
in CPU voltage combined with an increase in CPU frequency leads
to a performance boost of up to 7.5%. Lower CPU voltage reduces
power consumption. The main advantage of the PCA9560 over the
older PCA9559 device in this application is that it contains two
internal non-volatile EEPROM registers instead of just one, allowing
three independent settings (performance operation, deep sleep
mode and deeper sleep mode) instead of only two (performance
operation and deep sleep mode). The PCA9560 is footprint
compatible and a drop-in replacement for the PCA9559, without any
software modifications required.
The PCA9560 has 2 address pins allow up to 4 devices to be placed
on the same I2C bus or SMBus.
PIN CONFIGURATION
SCL
SDA
MUX_IN B
VDD
120
219
318
417
516
615
714
813
MUX_IN C
MUX_IN D
MUX_IN E
MUX_OUT B
MUX_OUT C
MUX_OUT D
MUX_OUT E
SW00829
GND
9
10
A1
A0
12
11
NON-MUXED_OUT
MUX_OUT A
MUX_IN A
WP
MUX_SELECT_1
MUX_SELECT_0
Figure 1. Pin configuration
PIN DESCRIPTION
PIN SYMBOL FUNCTION
1 SCL Serial I2C-bus clock
2 SDA Serial bi-directional I2C-bus data
3 A1 Programmable LSBs of I
2
C
4 A0
g
address
5–9 MUX_IN A–E External inputs to multiplexer
10 GND Ground
11 MUX_
SELECT_0 Selects MUX_IN inputs or register
contents for MUX_OUT outputs
12–16 MUX_OUT E–A Open drain multiplexed outputs
17 NON-MUXED_
OUTPUT Open drain output from
non-volatile memory
18 MUX_
SELECT_1 Selects between the two
non-volatile registers
19 WP Active high non-volatile register
write-protect input
20 VDD Power supply: +3.0 to +3.6 V
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER
20-Pin Plastic SO –40 to +85 °C PCA9560D PCA9560D SOT163-1
20-Pin Plastic TSSOP –40 to +85 °C PCA9560PW PCA9560 SOT360-1
Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 3
BLOCK DIAGRAM
MUX_OUT_A
MUX_OUT_B
MUX_OUT_C
MUX_OUT_D
MUX_OUT_E
MUX_IN_A
MUX_IN_B
MUX_IN_C
MUX_IN_D
MUX_IN_E
NON-VOLATILE
REGISTER 0
6-BIT EEPROM
NON-VOLATILE
REGISTER 1
6-BIT EEPROM
SELECT LOGIC
WRITE PROTECT
MUX_SELECT_1
MUX_SELECT_0
6
6
3
5
5
NON-MUXED_OUT
8
A0
A1
SW00841
PCA9560
I2C/SMBus
CONTROL
LOGIC
6-BIT
2 to 1
DEMULTIPLEXER
5-BIT
2 to 1
DEMULTIPLEXER
SDA
SCL
VDD
GND
INPUT
FILTER
POWER-ON
RESET
LATCH
NMO
Figure 2. Block diagram
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 4
DEVICE ADDRESS
Following a START condition the bus master must output the
address of the slave it is accessing. The address of the PCA9560 is
shown in Figure 3. To conserve power , no internal pull-up resistors
are incorporated on the hardware selectable address pins and they
must be pulled HIGH or LOW.
The last bit of the slave address byte defines the operation to be
performed. When set to logic 1 a read is selected while a logic 0
selects a write operation.
0 0 1 A1 A0 R/W11
SW00955
MSB LSB
FIXED PROGRAMMABLE
Figure 3. Slave address
CONTROL REGISTER
Following the successful acknowledgement of the slave address,
the bus master will send a byte to the PCA9560, which will be stored
in the control register. This register can be written and read via the
I2C-bus.
SW00954
D7 D6 D5 D4 D3 D2 D1 D0
Figure 4. Control Register
CONTROL REGISTER DEFINITION
Following the address and acknowledge bit with logic 0 in the read/write bit, the first byte written is the command byte. If the command byte is
reserved and therefore not valid, it will not be acknowledged. Only valid command bytes will be acknowledged.
Table 1. Register Addresses
D7 D6 D5 D4 D3 D2 D1 D0 REGISTER
NAME TYPE REGISTER
FUNCTION
0 0 0 0 0 0 0 0 EEPROM 0 Read/W rite EEPROM byte 0
register
0 0 0 0 0 0 0 1 EEPROM 1 Read/W rite EEPROM byte 1
register
1 1 1 1 1 1 1 1 MUX_IN Read MUX_IN values
register
Table 2. Commands
D7 D6 D5 D4 D3 D2 D1 D0 COMMAND
1 1 1 1 1 0 0 0 MUX_OUT from EEPROM byte 0
1 1 1 1 1 1 0 0 MUX_OUT from EEPROM byte 1
1 1 1 1 1 X 1 0 MUX_OUT from MUX_IN
1 1 1 1 1 X X 1 MUX_OUT from MUX_SELECT2
NOTE:
1. All other combinations are reserved.
2. MUX_SELECT pins select between MUX_IN and EEPROM to MUX_OUT.
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 5
REGISTER DESCRIPTION
If the command byte is an EEPROM address, the next byte sent will be programmed into that EEPROM address on the following STOP
condition, if the WP is logic 0. If more than one byte is sent sequentially, the second byte will be written in the other-volatile register , on the
following ST OP condition. If any more data bytes are sent after the second byte, they will not be acknowledged and no bytes wil l be written to
the non-volatile registers. After a byte is read from or written to the EEPROM, the part automatically points to the next non-volatile register. If the
command code was FFH, the MUX_IN values are sent with the three MSBs padded with zeroes as shown below. If the command codes was
00H, then the non-volatile register 1 is sent, and if the command code was 01H, then the non-volatile register 1 is sent.
EEPROM Byte 0 Register
D7 D6 D5 D4 D3 D2 D1 D0
Write X X Non-Muxed
Data EEPROM 0
Data E EEPROM 0
Data D EEPROM 0
Data C EEPROM 0
Data B EEPROM 0
Data A
Read 0 0 Non-Muxed
Data EEPROM 0
Data E EEPROM 0
Data D EEPROM 0
Data C EEPROM 0
Data B EEPROM 0
Data A
Default 0 0 0 0 0 0 0 0
EEPROM Byte 1 Register
D7 D6 D5 D4 D3 D2 D1 D0
Write X X Non-Muxed
Data EEPROM 1
Data E EEPROM 1
Data D EEPROM 1
Data C EEPROM 1
Data B EEPROM 1
Data A
Read 0 0 Non-Muxed
Data EEPROM 1
Data E EEPROM 1
Data D EEPROM 1
Data C EEPROM 1
Data B EEPROM 1
Data A
Default 0 0 0 0 0 0 0 0
MUX_IN Register
D7 D6 D5 D4 D3 D2 D1 D0
Read 0 0 0 MUX_IN
Data E MUX_IN
Data D MUX_IN
Data C MUX_IN
Data B MUX_IN
Data A
If the command byte is a MUX command byte, any additional data bytes sent after the MUX command code will not be acknowledged. If the
read/write bit in the address is a logic 1, then a read operation follows and the data sent out depends on the previously stored command code.
The MUX_SELECT_1 pin can function as the over-ride pin as on the PCA9559 if the non-volatile register 1 is left at all 0s.
The NON_MUXED_OUT pin is a latched output. It is latched when MUX_SELECT_0 = 1. It is transparent when the MUX_SELECT_0 = 0. The
data sent out on the NON_MUXED_OUT output is the 6th most significant bit of the non-volatile register. Whether this comes from the
non-volatile register 0 or non-volatile register 1 depends on the command code or the external mux-select pins.
After a valid I2C write operation to the EEPROM, the part cannot be addressed via the I2C for 3.6 ms. If the part is addressed prior to this time,
the part will not acknowledge its address.
NOTE:
1. To ensure data integrity, the non-volatile register must be internally write protected when VDD to the I2C bus is powered down or VDD to the
component is dropped below normal operating levels.
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 6
CONVERSION FROM THE PCA9559 TO THE PCA9560
The PCA9560 is a drop in replacement to the PCA9559 with no software modifications. The PCA9559 has only one MUX_SELECT pin to
choose between the MUX_IN values and the single non-volatile register. Since the PCA9560 has two internal non-volatile registers, if Register 1
is left to all 0’s (default condition) then the MUX_SELECT_1 pin can function the same as the PCA9559 OVERRIDE # pin and MUX_SELECT_0
pin can function the same as the PCA9559 MUX_IN pin.
The PCA9560 can read the MUX_IN_X values via I2C that the PACA9559 cannot do. Another difference is that the MUX_SELECT_X control
pins can be overridden by I2C. To replace the PCA9559 with the PCA9560, the function table for the MUX_OUT outputs and the
NON_MUXED_OUT output must stay the same and the MUX_SELECT pin functions should not be overridden by I2C.
EXTERNAL CONTROL SIGNALS
The Write Protect (WP) input is used to control the ability to write the content of the non-volatile registers. If the WP signal is logic 0, the I2C bus
will be able to write the contents of the non-volatile registers. If the WP signal is logic 1, data will not be allowed to be written into the
non-volatile registers. In this case, the slave address and the command code will be acknowledged but the following data bytes will not be
acknowledged and the EEPROM is not updated.
The factory default for the contents of the non-volatile register are all logic 0. These stored values can be read or written using the I2C-bus
(described in the next section).
The WP, MUX_IN*, MUX_SELECT_0, and MUX_SELECT_1 signals have internal pull-up resistors. See the DC and AC Characteristics for
hysteresis and signal spike suppression figures.
Function Table1
WP MUX_SELECT_0 MUX_SELECT_1 COMMANDS
0 X X Write to the non-volatile registers through I 2C bus allowed
1 X X Write to the non-volatile registers through I2C bus not
allowed
X 0 1 MUX_OUT and NON_MUXED_OUT (transparent) from
EEPROM byte 0
X 0 0 MUX_OUT and NON_MUXED_OUT (transparent) from
EEPROM byte 1
X 1 1 MUX_OUT from MUX_IN inputs and NON_MUXED_OUT
latched (from EEPROM 0)
X 1 0 MUX_OUT from MUX_IN inputs and NON_MUXED_OUT
latched (from EEPROM 1)
NOTE:
1. This table is valid when not overridden by I2C control register.
POWER-ON RESET (POR)
When power is applied to VDD, an internal power-on reset holds the PCA9560 in a reset state until VDD has reached VPOR. At that point, the
reset condition is released and the PCA9560 volatile registers and I2C/SMBus state machine will initialize to their default states.
The MUX_OUT and NON_MUXED_OUT pin values depend on:
–the MUX_SELECT_0 and MUX_SELECT_1 logic levels, selecting either the MUX_IN input pins or one of the two 6-bit EEPROMs
–the previously stored values in the EEPROM registers/current MUX_IN pin values as shown in the Function Table
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 7
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line
(SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may
be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as
changes in the data line at this time will be interpreted as control signals (see Figure 5).
SDA
SCL
SW00363
data line
stable;
data valid
change
of data
allowed
Figure 5. Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined
as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Figure 6).
System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device initiates a transfer is the ‘master’ and the
devices which are controlled by the master are the ‘slaves’ (see Figure 7).
SDA
SCL
SW00365
S P
SDA
SCL
START condition STOP condition
Figure 6. Definition of start and stop conditions
MASTER
TRANSMITTER/
RECEIVER SLAVE
RECEIVER SLAVE
TRANSMITTER/
RECEIVER MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
SW00366
I2C
MULTIPLEXER
SLAVE
Figure 7. System configuration
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 8
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH-level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
SW00368
DATA OUTPUT
BY RECEIVER
12 89
S
START condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
Figure 8. Acknowledgement on the I2C-bus
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 9
Bus Transactions
Data is transmitted to the PCA9560 registers using Write Byte transfers (see Figures 9 and 10). Data is read from the PCA9560 r egisters using
Read and Receive Byte transfers (see Figure 11).
D5 D4 D3 D2 D1X X0 1 1 A1 A01 0
S0A A A
R/W
D0
slave address EEPROM byte 0 data
SW00956
0000000 0 P
stop condition
control register
write on EEPROM byte 0
acknowledge
from slave acknowledge
from slave acknowledge
from slave
start condition
Figure 9. WRITE on 1 EEPROM — assuming WP = 0
D4 D3 D2 D1 D0D5D4 D3 D2 D1 D0X D50 1 1 A1 A01 0
S0A A X
R/W
P
X
SW00957
A
slave address
stop condition
start condition
00000000 XA
acknowledge
from slave acknowledge
from slave
control register write on
EEPROM byte 0 EEPROM byte 0 data EEPROM byte 1 data
Figure 10. WRITE on 2 EEPROMs — assuming WP = 0
SW00958
slave address
no acknowledge
from master
4 3 2 1 000 1 1 A1 A01 00 1 1 A1 A01 0S0A A 0
R/W
PS A
slave address
stop condition
start condition
11111111 0 NA
acknowledge
from master
control register read
MUX_IN values data from MUX_IN
acknowledge
from master acknowledge
from master
1
R/W
restart
Figure 11. READ MUX_IN register
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 10
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL PARAMETER CONDITIONS RATING UNIT
VDD DC supply voltage –0.5 to +4.0 V
VIN DC input voltage Note 3 –0.5 to +5.5 V
VOUT DC output voltage Note 3 –0.5 to +5.5 V
Tstg Storage temperature range –60 to +150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The maximum input or output voltage is the lesser of 5.5 V or VDD + 4.0 V, except for very short (e.g., system start-up or shut-down)
durations.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN MAX
UNIT
VDD DC supply voltage — 3.0 3.6 V
VIL LOW-level input voltage SCL, SDA IOL= 3 mA –0.5 0.9 V
VIH HIGH-level input voltage SCL, SDA IOL= 3 mA 2.7 5.5 1V
VO
LOW level out
p
ut voltage
SCL SDA
IOL= 3 mA — 0.4
V
V
OL
LOW
-
le
v
el
o
u
tp
u
t
v
oltage
SCL
,
SDA
IOL= 6 mA — 0.6
V
VIL LOW-level input voltage MUX_IN,
MUX_SELECT_0,
MUX_SELECT_1 — –0.5 0.8 V
VIH HIGH-level input voltage MUX_IN,
MUX_SELECT_0,
MUX_SELECT_1 — 2.0 5.5 1V
IOL LOW-level output current MUX_OUT,
NON_MUXED_OUT — — 8 mA
IOH HIGH-level output current MUX_OUT,
NON_MUXED_OUT — — 100 µA
dt/dv Input transition rise or fall time dt/dv — 0 10 ns/V
Tamb Operating ambient temperature Tamb — –40 85 °C
NOTES:
1. The maximum input voltage is the lesser of 5.5 V or VDD + 4.0 V, except for very short (e.g., system start-up or shut-down) durations.
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 11
DC CHARACTERISTICS
SYMBOL
TEST CONDITION
LIMITS
UNIT
SYMBOL
TEST
CONDITION
MIN. TYP. MAX.
UNIT
Supply
VDD Supply voltage 3 — 3.6 V
IDDL Supply current Operating mode ALL inputs = 0 V — — 1 mA
IDDH Supply current Operating mode ALL inputs = VDD — — 600 µA
VPOR Power-on reset voltage No load; VI = VDD or GND — 2.3 2.7 V
Input SCL: Input/Output SDA
VIL LOW-level input voltage –0.5 — 0.8 V
VIH HIGH-level input voltage 2 — 5.5 1V
IOL LOW-level output current VOL = 0.4 V 3 — — mA
IOL LOW-level output current VOL = 0.6 V 6 — — mA
IIH Leakage current HIGH VI = VDD –1 — 1 µA
IIL Input current LOW VI = GND –1 — 1 µA
CIInput capacitance — 3 6 pF
WP, MUX_SELECT_0, MUX_SELECT_1
IIH Leakage current HIGH VI = VDD –1 — 1 µA
IIL Input current LOW VDD = 3.6 V ; VI = GND –20 — –50 µA
CIInput capacitance — 2.5 5 pF
MUX_IN A → E
IIH Leakage current HIGH VI = VDD –1 — 1 µA
IIL Input current LOW VDD = 3.6 V ; VI = GND –20 — –50 µA
CIInput capacitance — 2.5 5 pF
A0, A1 Inputs
IIH Leakage current HIGH VI = VDD –1 — 1 µA
IIL Input current LOW VDD = 3.6 V ; VI = GND –20 — –50 µA
CIInput capacitance — 2 4 pF
MUX_OUT
VOL LOW-level output voltage IOL = 100 µA — — 0.4 V
VOL LOW-level output voltage IOL = 4 mA — — 0.7 V
IOH HIGH-level output current VOH = VDD — — 100 µA
NON-MUXED_OUT
VOL LOW-level output voltage IOL = 100 µA — — 0.4 V
VOL LOW-level output voltage IOL = 2 mA — — 0.7 V
NOTE:
1. The maximum input voltage is the lesser of 5.5 V or VDD + 4.0 V, except for very short (e.g., system start-up or shut-down) durations.
NON-VOLATILE STORAGE SPECIFICATIONS
PARAMETER SPECIFICATION
Memory cell data retention 10 years min
Number of memory cell write cycles 100,000 cycles min
Application Note
AN250 I
2
C DIP Switch
provides additional information on memory cell data retention and the minimum number of write cycles.
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 12
SAC CHARACTERISTICS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN. TYP. MAX.
UNIT
MUX_IN ⇒ MUX_OUT
tPLH LOW-to-HIGH transition time — 28 40 ns
tPHL HIGH-to-LOW transition time — 8 15 ns
Select ⇒ MUX_OUT
tPLH LOW-to-HIGH transition time — 30 43 ns
tPHL HIGH-to-LOW transition time — 10 15 ns
tROutput rise time 1.0 — 3 ns/V
tFOutput fall time 1.0 — 3 ns/V
CLTest load capacitance on outputs — — 50 pF
Select ⇒ NON-MUXED_OUT
tPLH LOW-to-HIGH transition time — 30 40 ns
tPHL HIGH-to-LOW transition time — 9 15 ns
AC SPECIFICATIONS
SYMBOL PARAMETER STANDARD MODE
I2C-BUS FAST MODE
I2C-BUS UNITS
MIN MAX MIN MAX
fSCL Operating frequency 0 100 0 400 kHz
tBUF Bus free time between STOP and START conditions 4.7 — 1.3 — µs
tHD;STA Hold time after (repeated) ST ART condition 4.0 — 0.6 — µs
tSU;STA Repeated START condition setup time 4.7 — 0.6 — µs
tSU;STO Set-up time for ST OP condition 4.0 — 0.6 — µs
tHD;DAT Data in hold time 0 — 0 — ns
tVD;ACK Valid time for ACK condition20.3 3.45 0.1 0.9 µs
tVD;DAT Data out valid time3300 — 50 — ns
tSU;DAT Data set-up time 250 — 100 — ns
tLOW Clock LOW period 4.7 — 1.3 — µs
tHIGH Clock HIGH period 4.0 — 0.6 — µs
tFClock/Data fall time — 300 20 + 0.1 Cb1300 ns
tRClock/Data rise time — 1000 20 + 0.1 Cb1300 ns
tSP Pulse width of spikes that must be suppressed by the
input filters — 50 — 50 ns
NOTES:
1. Cb = total capacitance of one bus line in pF.
2. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
3. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 13
tSP
tBUF
tHD;STA
PP S
tLOW tR
tHD;DAT
tF
tHIGH tSU;DAT
tSU;STA
Sr
tHD;STA
tSU;STO
SDA
SCL
SU00645
Figure 12. Definition of timing
MUX INPUT VMVM
VM
MUX OUTPUT
VOL
tPHL tPLZ
VOL + 0.3 V
SW00500
VO
Figure 13. Open drain output enable and disable times DEFINITIONS
RL = Load resistor; 1 kΩ
CL = Load capacitance includes jig and probe capacitance;
10 pF
RT = Termination resistance should be equal to ZOUT of
pulse generators.
PULSE
GENERATOR
VIN D.U.T.
VOUT
CL
VCC
RL
Test Circuit for Open Drain Outputs
RT
SW00510
VO
Figure 14. Test circuit
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 14
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 15
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 16
REVISION HISTORY
Rev Date Description
_4 20040519 Product data sheet (9397 750 13154). Supersedes data of 2003 Jun 27 (9397 750 11676).
Modifications:
•Features section, 16th bullet: from “inputs” to “inputs/outputs”
•Absolute maximum ratings table: VDD, VIN, and VOUT limits modified. Note 3 re-written.
•Recommended operating conditions
–VIH max. (on SCL, SDA) changed from 4.0 V to 5.5 V (with Note 1 added).
–VIH max. (on MUX_IN, MUX_SELECT_0, MUX_SELECT_1) changed from 4.0 V to 5.5 V (with Note 1
added).
•DC characteristics table: Input SCL: Input/Output SDA; VIH parameter max. limit modified, and Note 1 added.
_3 20030627 Product data (9397 750 11676); ECN 853-2286 29936 dated 19 May 2003.
Supersedes data of 2002 May 24 (9397 750 09892).
_2 20020524 Product data (9397 750 09892); ECN 853–2286 28310 of 24 May 2002.
Philips Semiconductors Product data sheet
PCA9560
Dual 5-bit multiplexed 1-bit latched
I2C EEPROM DIP switch
2004 May 19 17
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Koninklijke Philips Electronics N.V. 2004
All rights reserved. Printed in U.S.A.
Date of release: 05-04
Document order number: 9397 750 13154
Philips
Semiconductors
Data sheet status[1]
Objective data sheet
Preliminary data sheet
Product data sheet
Product
status[2] [3]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Level
I
II
III