24AA256/24LC256/24FC256 256K I2CTM CMOS Serial EEPROM Device Selection Table Description VCC Range Max. Clock Frequency 24AA256 1.8-5.5V 400 kHz(1) I 24LC256 2.5-5.5V 400 kHz I, E 24FC256 2.5-5.5V 1 MHz I Part Number The Microchip Technology Inc. 24AA256/24LC256/ 24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial Electrically Erasable PROM, capable of operation across a broad voltage range (1.8V to 5.5V). It has been developed for advanced, low-power applications such as personal communications or data acquisition. This device also has a page write capability of up to 64 bytes of data. This device is capable of both random and sequential reads up to the 256K boundary. Functional address lines allow up to eight devices on the same bus, for up to 2 Mbit address space. This device is available in the standard 8-pin plastic DIP, SOIC, TSSOP, MSOP, DFN and 14-lead TSSOP packages. Temp. Ranges Note 1: 100 kHz for VCC < 2.5V. Features * Low-power CMOS technology - Maximum write current 3 mA at 5.5V - Maximum read current 400 A at 5.5V - Standby current 100 nA typical at 5.5V * 2-wire serial interface bus, I2CTM compatible * Cascadable for up to eight devices * Self-timed ERASE/WRITE cycle * 64-byte Page Write mode available * 5 ms max write cycle time * Hardware write-protect for entire array * Output slope control to eliminate ground bounce * Schmitt Trigger inputs for noise suppression * 1,000,000 erase/write cycles * Electrostatic discharge protection > 4000V * Data retention > 200 years * 8-pin PDIP, SOIC, TSSOP, MSOP and DFN packages * 14-lead TSSOP package * Standard and Pb-free finishes available * Temperature ranges: - Industrial (I): -40C to +85C - Automotive (E): -40C to +125C Block Diagram A0 A1A2 WP I/O Control Logic Memory Control Logic HV Generator EEPROM Array XDEC Page Latches I/O SCL YDEC SDA VCC Sense AMP R/W Control VSS Package Types PDIP/SOIC A2 VSS 3 4 A0 1 7 WP A1 2 6 5 SCL SDA A2 VSS 3 4 8 VCC 7 WP 6 5 SCL SDA A0 A1 NC NC NC A2 VSS 1 2 3 4 5 6 7 DFN 14 13 12 11 10 9 8 VCC WP NC NC NC SCL SDA A0 1 A1 2 A2 3 VSS 4 24XX256 2 VCC 24XX256 A1 8 24XX256 1 24XX256 A0 TSSOP TSSOP/MSOP * 8 VCC 7 WP 6 SCL 5 SDA NOTE: Pins A0 and A1 are no connects for the MSOP package only. *24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices. 2003 Microchip Technology Inc. DS21203K-page 1 24AA256/24LC256/24FC256 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings () VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65C to +150C Ambient temperature with power applied ................................................................................................-65C to +125C ESD protection on all pins ...................................................................................................................................................... 4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 1.1 24XX256 DC Electrical Specifications Electrical Characteristics: Industrial (I): VCC = +1.8V to 5.5V Automotive (E): VCC = +2.5V to 5.5V DC Specifications Param. No. Sym Characteristic Min Max Units -- -- TAMB = -40C to +85C TAMB = -40C to +125C Conditions D1 -- A0, A1, A2, SCL, SDA and WP pins: -- D2 VIH High-level input voltage 0.7 VCC -- V -- D3 VIL Low-level input voltage -- 0.3 VCC 0.2 VCC V V VCC 2.5V VCC < 2.5V D4 VHYS Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) 0.05 VCC -- V VCC 2.5V (Note) D5 VOL Low-level output voltage -- 0.40 V IOL = 3.0 ma @ VCC = 4.5V IOL = 2.1 ma @ VCC = 2.5V D6 ILI Input leakage current -- 10 A VIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC D7 ILO Output leakage current -- 10 A VOUT = VSS or VCC D8 CIN, COUT Pin capacitance (all inputs/outputs) -- 10 pF VCC = 5.0V (Note) TAMB = 25C, fC = 1 MHz ICC Read Operating current -- 400 A VCC = 5.5V, SCL = 400 kHz ICC Write -- 3 mA VCC = 5.5V -- 1 A TAMB = -40C to +85C SCL = SDA = VCC = 5.5V A0, A1, A2, WP = VSS -- 5 A TAMB = -40C to +125C SCL = SDA = VCC = 5.5V A0, A1, A2, WP = VSS D9 D10 Note: ICCS Standby current -- This parameter is periodically sampled and not 100% tested. DS21203K-page 2 2003 Microchip Technology Inc. 24AA256/24LC256/24FC256 1.2 24XX256 AC Electrical Specifications Electrical Characteristics: Industrial (I): VCC = +1.8V to 5.5V Automotive (E): VCC = +2.5V to 5.5V AC Specifications Param. No. Sym Characteristic Min Max Units TAMB = -40C to +85C TAMB = -40C to +125C Conditions 1 FCLK Clock frequency -- -- -- 100 400 1000 kHz 1.8V VCC < 2.5V 2.5V VCC 5.5V 2.5V VCC 5.5V 24FC256 2 THIGH Clock high time 4000 600 500 -- -- -- ns 1.8V VCC < 2.5V 2.5V VCC 5.5V 2.5V VCC 5.5V 24FC256 3 TLOW Clock low time 4700 1300 500 -- -- -- ns 1.8V VCC < 2.5V 2.5V VCC 5.5V 2.5V VCC 5.5V 24FC256 4 TR SDA and SCL rise time (Note 1) -- -- -- 1000 300 300 ns 1.8V VCC < 2.5V 2.5V VCC 5.5V 2.5V VCC 5.5V 24FC256 5 TF SDA and SCL fall time (Note 1) -- -- 300 100 ns All except, 24FC256 2.5V VCC 5.5V 24FC256 6 THD:STA Start condition hold time 4000 600 250 -- -- -- ns 1.8V VCC < 2.5V 2.5V VCC 5.5V 2.5V VCC 5.5V 24FC256 7 TSU:STA Start condition setup time 4700 600 250 -- -- -- ns 1.8V VCC < 2.5V 2.5V VCC 5.5V 2.5V VCC 5.5V 24FC256 8 THD:DAT Data input hold time 0 -- ns (Note 2) 9 TSU:DAT Data input setup time 250 100 100 -- -- -- ns 1.8V VCC < 2.5V 2.5V VCC 5.5V 2.5V VCC 5.5V 24FC256 10 TSU:STO Stop condition setup time 4000 600 250 -- -- -- ns 1.8V VCC < 2.5V 2.5V VCC 5.5V 2.5V VCC 5.5V 24FC256 11 TSU:WP WP setup time 4000 600 600 -- -- -- ns 1.8V VCC < 2.5V 2.5V VCC 5.5V 2.5V VCC 5.5V 24FC256 12 THD:WP WP hold time 4700 1300 1300 -- -- -- ns 1.8V VCC < 2.5V 2.5V VCC 5.5V 2.5V VCC 5.5V 24FC256 13 TAA Output valid from clock (Note 2) -- -- -- 3500 900 400 ns 1.8 V VCC < 2.5V 2.5 V VCC 5.5V 2.5 V VCC 5.5V 24FC256 14 TBUF Bus free time: Time the bus must be free before a new transmission can start 4700 1300 500 -- -- -- ns 1.8V VCC < 2.5V 2.5V VCC 5.5V 2.5V VCC 5.5V 24FC256 Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model, which can be obtained from Microchip's web site: www.microchip.com. 2003 Microchip Technology Inc. DS21203K-page 3 24AA256/24LC256/24FC256 Electrical Characteristics: Industrial (I): VCC = +1.8V to 5.5V Automotive (E): VCC = +2.5V to 5.5V AC Specifications (Continued) Param. No. Sym Characteristic TAMB = -40C to +85C TAMB = -40C to +125C Min Max Units Conditions 10 + 0.1CB 250 250 ns All except, 24FC256 (Note 1) 15 TOF Output fall time from VIH minimum to VIL maximum CB 100 pF 16 TSP Input filter spike suppression (SDA and SCL pins) -- 50 ns All except, 24FC256 (Notes 1 and 3) 17 TWC Write cycle time (byte or page) -- 5 ms -- 18 -- Endurance 1,000,000 -- cycles 25C (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model, which can be obtained from Microchip's web site: www.microchip.com. FIGURE 1-1: BUS TIMING DATA 5 SCL 7 SDA IN 3 4 D4 2 8 10 9 6 16 14 13 SDA OUT WP DS21203K-page 4 (protected) (unprotected) 11 12 2003 Microchip Technology Inc. 24AA256/24LC256/24FC256 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: Name A0 PIN FUNCTION TABLE 8-pin PDIP 8-pin SOIC 8-pin TSSOP 14-pin TSSOP 8-pin MSOP 8-pin DFN 1 1 1 1 -- 1 User Configurable Chip Select Function A1 2 2 2 2 -- 2 User Configurable Chip Select (NC) -- -- -- 3, 4, 5 1,2 -- Not Connected A2 3 3 3 6 3 3 User Configurable Chip Select VSS 4 4 4 7 4 4 Ground SDA 5 5 5 8 5 5 Serial Data SCL 6 6 6 9 6 6 Serial Clock (NC) -- -- -- 10, 11, 12 -- -- Not Connected WP 7 7 7 13 7 7 Write-Protect Input VCC 8 8 8 14 8 8 +1.8V to 5.5V (24AA256) +2.5V to 5.5V (24LC256) +2.5V to 5.5V (24FC256) 2.1 A0, A1, A2 Chip Address Inputs The A0, A1 and A2 inputs are used by the 24XX256 for multiple device operations. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. For the MSOP package only, pins A0 and A1 are not connected. Up to eight devices (two for the MSOP package) may be connected to the same bus by using different chip select bit combinations. If these pins are left unconnected, the inputs will be pulled down internally to VSS. If they are tied to VCC or driven high, the internal pull-down circuitry is disabled. 2.3 Serial Clock (SCL) This input is used to synchronize the data transfer to and from the device. 2.4 Write-Protect (WP) This pin can be connected to either VSS, VCC or left floating. Internal pull-down circuitry on this pin will keep the device in the unprotected state if left floating. If tied to VSS or left floating, normal memory operation is enabled (read/write the entire memory 0000-7FFF). If tied to VCC, write operations are inhibited. Read operations are not affected. In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic `0' or logic `1'. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic `0' or logic `1' before normal device operation can proceed. 2.2 Serial Data (SDA) This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open drain terminal. Therefore, the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz and 1 MHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 2003 Microchip Technology Inc. DS21203K-page 5 24AA256/24LC256/24FC256 3.0 FUNCTIONAL DESCRIPTION The 24XX256 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the Start and Stop conditions while the 24XX256 works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. DS21203K-page 6 2003 Microchip Technology Inc. 24AA256/24LC256/24FC256 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line, while the clock line is high, will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Bus not Busy (A) Both data and clock lines remain high. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device. 4.5 Each receiving device, when addressed, is obliged to generate an Acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high, determines a Start condition. All commands must be preceded by a Start condition. 4.3 Stop Data Transfer (C) A low-to-high transition of the SDA line, while the clock (SCL) is high, determines a Stop condition. All operations must end with a Stop condition. 4.4 Data Valid (D) Acknowledge The 24XX256 does not generate any Acknowledge bits if an internal programming cycle is in progress. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX256) will leave the data line high to enable the master to generate the Stop condition. The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. FIGURE 4-1: (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA 2003 Microchip Technology Inc. Data Allowed to Change Stop Condition DS21203K-page 7 24AA256/24LC256/24FC256 FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit 1 SCL SDA 2 3 4 5 6 7 Data from transmitter Transmitter must release the SDA line at this point, allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. DS21203K-page 8 8 9 1 2 3 Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data. 2003 Microchip Technology Inc. 24AA256/24LC256/24FC256 5.0 DEVICE ADDRESSING FIGURE 5-1: A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a 4-bit control code. For the 24XX256, this is set as 1010 binary for read and write operations. The next three bits of the control byte are the chip select bits (A2, A1, A0). The chip select bits allow the use of up to eight 24XX256 devices on the same bus and are used to select which device is accessed. The chip select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are, in effect, the three Most Significant bits of the word address. For the MSOP package, the A0 and A1 pins are not connected. During device addressing, the A0 and A1 chip select bits (Figures 5-1 and 5-2) should be set to `0'. Only two 24XX256 MSOP packages can be connected to the same bus. The last bit of the control byte defines the operation to be performed. When set to a one, a read operation is selected. When set to a zero, a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2). Because only A14...A0 are used, the upper address bits are a don't care. The upper address bits are transferred first, followed by the less significant bits. Following the Start condition, the 24XX256 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a 1010 code and appropriate device select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX256 will select a read or write operation. FIGURE 5-2: 0 1 CONTROL CODE Read/Write Bit Chip Select Bits Control Code S 1 0 1 0 A2 A1 A0 R/W ACK Slave Address Start Bit 5.1 Acknowledge Bit Contiguous Addressing Across Multiple Devices The chip select bits A2, A1, A0 can be used to expand the contiguous address space for up to 2 Mbit by adding up to eight 24XX256s on the same bus. In this case, software can use A0 of the control byte as address bit A15; A1 as address bit A16; and A2 as address bit A17. It is not possible to sequentially read across device boundaries. For the MSOP package, up to two 24XX256 devices can be added for up to 512 Kbit of address space. In this case, software can use A2 of the control byte as address bit A17. Bits A0 (A15) and A1 (A16) of the control byte must always be set to a logic `0' for the MSOP. ADDRESS SEQUENCE BIT ASSIGNMENTS CONTROL BYTE 1 CONTROL BYTE FORMAT 0 A 2 A 1 ADDRESS HIGH BYTE A 0 R/W CHIP SELECT BITS 2003 Microchip Technology Inc. X A A A A A 14 13 12 11 10 A 9 ADDRESS LOW BYTE A 8 A 7 * * * * * * A 0 X = Don't Care Bit DS21203K-page 9 24AA256/24LC256/24FC256 6.0 WRITE OPERATIONS 6.1 Byte Write pointer bits are internally incremented by one. If the master should transmit more than 64 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written and the device will immediately accept a new command. Following the Start condition from the master, the control code (four bits), the chip select (three bits) and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24XX256. The next byte is the Least Significant Address Byte. After receiving another Acknowledge signal from the 24XX256, the master device will transmit the data word to be written into the addressed memory location. The 24XX256 acknowledges again and the master generates a Stop condition. This initiates the internal write cycle and during this time, the 24XX256 will not generate Acknowledge signals (Figure 6-1). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written, and the device will immediately accept a new command. After a byte Write command, the internal address counter will point to the address location following the one that was just written. 6.2 6.3 Write-Protection The WP pin allows the user to write-protect the entire array (0000-7FFF) when the pin is tied to VCC. If tied to VSS or left floating, the write-protection is disabled. The WP pin is sampled at the Stop bit for every Write command (Figure 1-1). Toggling the WP pin after the Stop bit will have no effect on the execution of the write cycle. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or `page size') and end at addresses that are integer multiples of [page size - 1]. If a page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is, therefore, necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Page Write The write control byte, word address and the first data byte are transmitted to the 24XX256 in much the same way as in a byte write. The exception is that instead of generating a Stop condition, the master transmits up to 63 additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory once the master has transmitted a Stop condition. Upon receipt of each word, the six lower address FIGURE 6-1: BYTE WRITE SDA LINE S T A R T BUS ACTIVITY AA S1 0 1 0A 2 10 0 BUS ACTIVITY MASTER CONTROL BYTE BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY X = don't care bit DS21203K-page 10 ADDRESS LOW BYTE S T O P DATA X P A C K X = don't care bit FIGURE 6-2: ADDRESS HIGH BYTE A C K A C K A C K PAGE WRITE S T A R T CONTROL BYTE ADDRESS HIGH BYTE AAA S10 1 0 2 1 00 ADDRESS LOW BYTE S T O P DATA BYTE 63 DATA BYTE 0 X A C K P A C K A C K A C K A C K 2003 Microchip Technology Inc. 24AA256/24LC256/24FC256 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (This feature can be used to maximize bus throughput.) Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition, followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, the Start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 7-1 for flow diagram. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? NO YES Next Operation 2003 Microchip Technology Inc. DS21203K-page 11 24AA256/24LC256/24FC256 8.0 READ OPERATION 8.2 Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is done by sending the word address to the 24XX256 as part of a write operation (R/W bit set to `0'). Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. The master then issues the control byte again but with the R/W bit set to a one. The 24XX256 will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer, though it does generate a Stop condition, which causes the 24XX256 to discontinue transmission (Figure 8-2). After a random Read command, the internal address counter will point to the address location following the one that was just read. Read operations are initiated in much the same way as write operations, with the exception that the R/W bit of the control byte is set to `1'. There are three basic types of read operations: current address read, random read and sequential read. 8.1 Current Address Read The 24XX256 contains an address counter that maintains the address of the last word accessed, internally incremented by `1'. Therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to `1', the 24XX256 issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24XX256 discontinues transmission (Figure 8-1). FIGURE 8-1: 8.3 S T A R T SDA LINE S 1 0 1 0 A AA 1 2 1 0 CONTROL BYTE FIGURE 8-2: BUS ACTIVITY MASTER SDA LINE P A C K BUS ACTIVITY S T O P DATA BYTE Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24XX256 transmits the first data byte, the master issues an acknowledge as opposed to the Stop condition used in a random read. This acknowledge directs the 24XX256 to transmit the next sequentially addressed 8-bit word (Figure 8-3). Following the final byte transmitted to the master, the master will NOT generate an acknowledge but will generate a Stop condition. To provide sequential reads, the 24XX256 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The internal address pointer will automatically roll over from address 7FFF to address 0000 if the master acknowledges the byte received from the array address 7FFF. CURRENT ADDRESS READ BUS ACTIVITY MASTER Random Read N O A C K RANDOM READ S T A R T CONTROL BYTE ADDRESS HIGH BYTE S1 0 1 0 AAA0 2 1 0 CONTROL BYTE S T O P DATA BYTE S 1 0 1 0 A A A1 2 1 0 X A C K BUS ACTIVITY S T A R T ADDRESS LOW BYTE A C K A C K DATA (n + 1) DATA (n + 2) P N O A C K A C K X = Don't Care Bit FIGURE 8-3: BUS ACTIVITY MASTER SEQUENTIAL READ CONTROL BYTE DATA (n) S T O P DATA (n + X) P SDA LINE BUS ACTIVITY DS21203K-page 12 A C K A C K A C K A C K N O A C K 2003 Microchip Technology Inc. 24AA256/24LC256/24FC256 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) Example: 24AA256 I/P017 0310 XXXXXXXX T/XXXNNN YYWW 8-Lead SOIC (150 mil) XXXXXXXX T/XXYYWW NNN 24LC256 I/SN0310 017 8-Lead SOIC (208 mil) XXXXXXXX T/XXXXXX YYWWNNN 8-Lead TSSOP Example: Example: 24LC256 I/SM 0310017 Example: XXXX TYWW NNN Legend: XX...X T Y YY WW NNN 4LD I301 017 Customer specific information* Temperature grade (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Note:In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. *Standard device marking consists of Microchip part number, year code, week code, and traceability code. For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. 2003 Microchip Technology Inc. DS21203K-page 13 24AA256/24LC256/24FC256 Package Marking Information (Continued) 8-Lead MSOP Example: XXXXXT YWWNNN 4L256I 101017 Example: 8-Lead DFN-S 24LC256 I/MF YYWW NNN XXXXXXX T/XXXXX YYWW NNN Example: 14-Lead TSSOP XXXXXXXT YYWW NNN 24LC256I 0110 017 TSSOP Package Codes MSOP Package Codes Part No. STD Pb-free STD Pb-free 24AA256 4AD G4AD 4A256 G4AD 24LC256 4LD G4LD 4L256 G4LD 24FC256 4FD G4FD 4F256 G4FD DS21203K-page 14 2003 Microchip Technology Inc. 24AA256/24LC256/24FC256 8-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c A1 B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B1 B eB MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 2003 Microchip Technology Inc. DS21203K-page 15 24AA256/24LC256/24FC256 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45x c A2 A f L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D h L f c B MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21203K-page 16 2003 Microchip Technology Inc. 24AA256/24LC256/24FC256 8-Lead Plastic Small Outline (SM) - Medium, 208 mil (SOIC) E E1 p D 2 n 1 B c A2 A f L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L f c B MIN .070 .069 .002 .300 .201 .202 .020 0 .008 .014 0 0 INCHES* NOM 8 .050 .075 .074 .005 .313 .208 .205 .025 4 .009 .017 12 12 A1 MAX .080 .078 .010 .325 .212 .210 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.78 1.97 1.75 1.88 0.05 0.13 7.62 7.95 5.11 5.28 5.13 5.21 0.51 0.64 0 4 0.20 0.23 0.36 0.43 0 12 0 12 MIN MAX 2.03 1.98 0.25 8.26 5.38 5.33 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Drawing No. C04-056 2003 Microchip Technology Inc. DS21203K-page 17 24AA256/24LC256/24FC256 8-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP) E E1 p D 2 1 n B A c A1 A2 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L c B MIN INCHES NOM MAX 8 .026 .033 .002 .246 .169 .114 .020 0 .004 .007 0 0 .035 .004 .251 .173 .118 .024 4 .006 .010 5 5 .043 .037 .006 .256 .177 .122 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 8 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 2.90 3.00 3.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086 DS21203K-page 18 2003 Microchip Technology Inc. 24AA256/24LC256/24FC256 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E p E1 D 2 B n 1 A2 A c A1 (F) L Number of Pins Pitch Overall Height MILLIMETERS* INCHES Units Dimension Limits n p MAX NOM MIN MIN NOM 8 0.65 .026 .044 A 1.18 .038 0.76 0.86 .006 0.05 0.97 .193 .200 4.67 4.90 .5.08 .114 .118 .114 .118 .122 2.90 3.00 3.10 .122 2.90 3.00 L .016 3.10 .022 .028 0.40 0.55 .035 Foot Angle F 0.70 .037 .039 0.90 0.95 1.00 Lead Thickness c 6 0 .004 .006 .008 0.10 0.15 0.20 Lead Width Mold Draft Angle Top B .010 .012 .016 0.25 0.30 0.40 Mold Draft Angle Bottom Molded Package Thickness A2 .030 Standoff A1 .002 E .184 Molded Package Width E1 Overall Length D Foot Length Footprint (Reference) Overall Width MAX 8 .034 0 0.15 6 7 7 7 7 *Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Drawing No. C04-111 2003 Microchip Technology Inc. DS21203K-page 19 24AA256/24LC256/24FC256 8-Lead Micro Lead Frame Package (MF) 6x5 mm Body (DFN-S) (Formerly MLF-S) E p B E1 n L R D1 D 1 D2 PIN 1 ID EXPOSED METAL PADS 2 E2 TOP VIEW BOTTOM VIEW A2 A3 A A1 Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Base Thickness Overall Length Molded Package Length Exposed Pad Length Overall Width Molded Package Width Exposed Pad Width Lead Width Lead Length Tie Bar Width Mold Draft Angle Top A A2 A1 A3 E E1 E2 D D1 D2 B L R MIN .000 .152 .085 .014 .020 INCHES NOM 8 .050 BSC .033 .026 .0004 .008 REF. .194 BSC .184 BSC .158 .236 BSC .226 BSC .091 .016 .024 .014 MAX MILLIMETERS* NOM 8 1.27 BSC 0.85 0.65 0.01 0.00 0.20 REF. 4.92 BSC 4.67 BSC 3.85 4.00 5.99 BSC 5.74 BSC 2.16 2.31 0.40 0.35 0.60 0.50 .356 MIN .039 .031 .002 .163 .097 .019 .030 12 MAX 1.00 0.80 0.05 4.15 2.46 0.47 0.75 12 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: pending Drawing No. C04-113 DS21203K-page 20 2003 Microchip Technology Inc. 24AA256/24LC256/24FC256 8-Lead Micro Leadframe Package (MF) 6x5 mm Body (DFN-S) (Continued) M SOLDER MASK M p B PACKAGE EDGE L Units Pitch Dimension Limits p MILLIMETERS* INCHES MIN NOM MAX MIN NOM MAX 1.27 BSC .050 BSC Pad Width B .014 .016 .019 0.35 0.40 Pad Length L .020 .024 .030 0.50 0.60 Pad to Solder Mask M .005 .006 0.13 0.47 0.75 0.15 *Controlling Parameter Drawing No. C04-2113 2003 Microchip Technology Inc. DS21203K-page 21 24AA256/24LC256/24FC256 14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP) E E1 p D 2 1 n B A c f A1 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic A A2 A1 E E1 D L f c B MIN .033 .002 .246 .169 .193 .020 0 .004 .007 0 0 INCHES NOM 14 .026 .035 .004 .251 .173 .197 .024 4 .006 .010 5 5 A2 MAX .043 .037 .006 .256 .177 .201 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 14 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 4.90 5.00 5.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 DS21203K-page 22 2003 Microchip Technology Inc. 24AA256/24LC256/24FC256 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X Device Device: Temperature Range 24AA256: 24AA256T: 24LC256: 24LC256T: 24FC256: 24FC256T: Temperature Range: I E Package: P = SN = SM = ST = ST14 = MF = MS Lead Finish = = /XX X Package Lead Finish 256 Kbit 1.8V I2C Serial EEPROM 256 Kbit 1.8V I2C Serial EEPROM Tape and Reel) 256 Kbit 2.5V I2C Serial EEPROM 256 Kbit 2.5V I2C Serial EEPROM Tape and Reel) 256 Kbit 1 MHz I2C Serial EEPROM 256 Kbit 1 MHz I2C Serial EEPROM Tape and Reel) -40C to +85C -40C to +125C Plastic DIP (300 mil body), 8-lead Plastic SOIC (150 mil body), 8-lead Plastic SOIC (208 mil body), 8-lead Plastic TSSOP (4.4 mm), 8-lead Plastic TSSOP (4.4 mm), 14-lead Dual, Flat, No Lead (DFN)(6x5 mm body), 8-lead = Plastic Micro Small Outline (MSOP), 8-lead Blank = Standard 63%/37% Sn/Pb G = Pb-free (Pure Matte Sn) Examples: a) 24AA256-I/P: Industrial Temperature, 1.8V, PDIP package. b) 24AA256T-I/SN: Tape and Reel, Industrial Temp., 1.8V, SOIC package. c) 24AA256-I/ST: Industrial Temperature, 1.8V, TSSOP package. d) 24AA256-I/MS: Industrial Temperature, 1.8V, MSOP package. e) 24LC256-E/P: Extended Temperature, 2.5V, PDIP package. f) 24LC256-I/SN: Industrial Temperature, 2.5V, SOIC package. g) 24LC256T-I/SN: Tape and Reel, Industrial Temperature, 2.5V, SOIC package. h) 24LC256-I/MS: Industrial Temperature, 2.5V, MSOP package. i) 24FC256-I/P: Industrial Temperature, 2.5V, High Speed, PDIP package. j) 24FC256-I/SN: Industrial Temperature, 2.5V, High Speed, SOIC package. k) 24FC256T-I/SN: Tape and Reel, Industrial Temperature, 2.5V, High Speed, SOIC package l) 24LC256T-I/STG: Industrial Temperature, 2.5V, TSSOP package, Tape & Reel, Pb-free m) 24LC256-I/PG: Industrial Temperature, 2.5V, PDIP package, Pb-free Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2003 Microchip Technology Inc. DS21203K-page 23 24AA256/24LC256/24FC256 NOTES: DS21203K-page 24 2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Accuron, Application Maestro, dsPICDEM, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, InCircuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. 2003 Microchip Technology Inc. DS21203K-page 25 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Korea Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Atlanta Unit 915 Bei Hai Wan Tai Bldg. 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A. De Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 07/28/03 2003 Microchip Technology Inc.