Vishay Siliconix
Si7469DP
Document Number: 73438
S09-0271-Rev. C, 16-Feb-09
www.vishay.com
1
P-Channel 80-V (D-S) MOSFET
FEATURES
• Halogen-free According to IEC 61249-2-21
Available
• TrenchFET® Power MOSFET
PRODUCT SUMMARY
VDS (V) RDS(on) (Ω)ID (A)aQg (Typ.)
- 80 0.025 at VGS = - 10 V - 28 55 nC
0.029 at VGS = - 4.5 V - 28
Ordering Information: Si7469DP-T1-E3 (Lead (Pb)-free)
Si7469DP-T1-GE3 (Lead (Pb)-free and Halogen-free)
1
2
3
4
5
6
7
8
S
S
S
G
D
D
D
D
6.15 mm 5.15 mm
PowerPAK SO-8
Bottom View
S
G
D
P-Channel MOSFET
Notes:
a. Package Limited.
b. Surface Mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK SO-8 is a leadless package. The end of the lead terminal is exposed copper
(not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not
required to ensure adequate bottom side solder interconnection.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under Steady State conditions is 65 °C/W.
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol Limit Unit
Drain-Source Voltage VDS - 80 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current (TJ = 150 °C)
TC = 25 °C
ID
- 28a
A
TC = 70 °C - 28a
TA = 25 °C - 10.2b, c
TA = 70 °C - 8.1b, c
Pulsed Drain Current IDM - 40
Continuous Source-Drain Diode Current TC = 25 °C IS- 28a
TA = 25 °C - 4.3b, c
Avalanche Current L = 0.1 mH IAS - 45
Single-Pulse Avalanche Energy EAS 100 mJ
Maximum Power Dissipation
TC = 25 °C
PD
83
W
TC = 70 °C 53
TA = 25 °C 5.2b, c
TA = 70 °C 3.3b, c
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
Soldering Recommendations (Peak Temperature)d, e 260
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambientb, f t ≤ 10 s RthJA 19 24 °C/W
Maximum Junction-to-Case (Drain) Steady State RthJC 1.2 1.5
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2
Document Number: 73438
S09-0271-Rev. C, 16-Feb-09
Vishay Siliconix
Si7469DP
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolut e Maximum Ratings” may cause permanent damage to t he device. These are stress rating s only, and functiona l operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 µA - 80 V
VDS Temperature Coefficient ΔVDS/TJ ID = - 250 µA - 79.6 mV/°C
VGS(th) Temperature Coefficient ΔVGS(th)/TJ 5.3
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 1 - 3 V
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = - 80 V, VGS = 0 V - 1 µA
VDS = - 80 V, VGS = 0 V, TJ = 55 °C - 10
On-State Drain CurrentaID(on) V
DS ≥ 5 V, VGS = - 10 V - 40 A
Drain-Source On-State ResistanceaRDS(on)
VGS = - 10 V, ID = - 10.2 A 0.021 0.025 Ω
VGS = - 4.5 V, ID = - 8.1 A 0.024 0.029
Forward Transconductanceagfs VDS = - 15 V, ID = - 10.2 A 52 S
Dynamicb
Input Capacitance Ciss
VDS = - 40 V, VGS = 0 V, f = 1 MHz
4700
pFOutput Capacitance Coss 320
Reverse Transfer Capacitance Crss 235
Total Gate Charge Qg
VDS = - 40 V, VGS = - 10 V, ID = - 10.2 A 105 160
nC
VDS = - 40 V, VGS = - 4.5 V, ID = - 10.2 A
55 85
Gate-Source Charge Qgs 16
Gate-Drain Charge Qgd 26
Gate Resistance Rgf = 1 MHz 4 Ω
Tur n - O n D e l ay Time td(on)
VDD = - 40 V, RL = 4.9 Ω
ID ≅ - 8.1 A, VGEN = - 10 V, Rg = 1 Ω
45 70
ns
Rise Time tr220 330
Turn-Off Delay Time td(off) 95 145
Fall Time tf110 165
Tur n - O n D e l ay Time td(on)
VDD = - 40 V, RL = 4.9 Ω
ID ≅ - 8.1 A, VGEN = - 4.5 V, Rg = 1 Ω
15 25
ns
Rise Time tr25 40
Turn-Off Delay Time td(off) 105 160
Fall Time tf100 150
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current ISTC = 25 °C - 28 A
Pulse Diode Forward CurrentaISM - 40
Body Diode Voltage VSD IS = - 8.1 A - 0.8 - 1.2 V
Body Diode Reverse Recovery Time trr
IF = - 8.1 A, dI/dt = 100 A/µs, TJ = 25 °C
55 85 ns
Body Diode Reverse Recovery Charge Qrr 110 165 nC
Reverse Recovery Fall Time ta37 ns
Reverse Recovery Rise Time tb18
Document Number: 73438
S09-0271-Rev. C, 16-Feb-09
www.vishay.com
3
Vishay Siliconix
Si7469DP
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Output Characteristics
On-Resistance vs. Drain Current and Gate Voltage
Gate Charge
0
5
10
15
20
25
30
35
40
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VGS = 10 V thru 4 V
3 V
VDS - Drain-to-Source Voltage (V)
ID - Drain Current (A)
0.020
0.021
0.022
0.023
0.024
0.025
0.026
0 5 10 15 20 25 30 35 40
VGS = 10 V
ID - Drain Current (A)
VGS = 4.5 V
RDS(on) - On-Resistance (Ω)
0
2
4
6
8
10
0 20406080100120
ID = 10.2 A
- Gate-to-Source Voltage (V)
Qg - Total Gate Charge (nC)
V
GS
VDS = 64 V
VDS = 40 V
Transfer Characteristics
Capacitance
On-Resistance vs. Junction Temperature
0
4
8
12
16
20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
25 °C
TA = 125 °C
VGS - Gate-to-Source Voltage (V)
ID - Drain Current (A)
- 55 °C
0
1000
2000
3000
4000
5000
6000
7000
8000
0 1020304050607080
Coss
Ciss
VDS - Drain-to-Source Voltage (V)
C - Capacitance (pF)
Crss
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
- 50 - 25 0 25 50 75 100 125 150
VGS = 10 V
TJ - Junction Temperature (°C)
RDS(on) - On-Resistance
(Normalized)
ID = 10.2 A
VGS = 4.5 V
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Document Number: 73438
S09-0271-Rev. C, 16-Feb-09
Vishay Siliconix
Si7469DP
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Source-Drain Diode Forward Voltage
Threshold Voltage
1.0 1.2
1
10
40
0.00 0.2 0.4 0.6 0.8
TJ = 25 °C
TJ = 150 °C
VSD - Source-to-Drain Voltage (V)
IS - Source Current (A)
1.2
1.4
1.6
1.8
2.0
2.2
2.4
- 50 - 25 0 25 50 75 100 125 150
ID = 250 µA
TJ - Temperature (°C)
VGS(th) (V)
On-Resistance vs. Gate-to-Source Voltage
Single Pulse Power, Junction-to-Ambient
0.01
0.02
0.03
0.04
0.05
2345678910
VGS - Gate-to-Source Voltage (V)
RDS(on) - Drain-to-Source On-Resistance (Ω)
TA= 25 °C
TA = 125 °C
0
20
35
5
10
Power (W)
Time (s)
25
15
30
0.01 0.1 1 10 100 1000
Safe Operating Area, Junction-to-Ambient
100
1
0.1 1 10 1000
0.001
10
ID - Drain Current (A)
0.1
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
0.01
100
1 ms
10 ms
100 ms
DC
1 s
10 s
TA = 25 °C
Single Pulse
100 µs
Limited by
RDS(on)*
Document Number: 73438
S09-0271-Rev. C, 16-Feb-09
www.vishay.com
5
Vishay Siliconix
Si7469DP
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
Current Derating*
Single Pulse Avalanche Capability
0
10
20
30
40
50
0 25 50 75 100 125 150
ID
- Drain Current (A)
TC - Case Temperature (°C)
Package Limited
100
0.000001 0.0001 0.01
1
10
0.00001
TA - Time In Avalanche (s)
IC - Peak Avalanche Current (A)
T
A
=L.I
D
BV - V
DD
0.001
Power Derating
0
20
40
60
80
100
25 50 75 100 125 150
TC - Case Temperature (°C)
Power (W)
www.vishay.com
6
Document Number: 73438
S09-0271-Rev. C, 16-Feb-09
Vishay Siliconix
Si7469DP
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73438.
Normalized Thermal Transient Impedance, Junction-to-Ambient
10-2 1 10 100010-1 100
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
1. Duty Cycle, D =
2. Per Unit Base = RthJA = 65 °C/W
3. T JM - TA = PDMZthJA(t)
t1
t2
t1
t2
Notes:
4. Surface Mounted
PDM
Normalized Thermal Transient Impedance, Junction-to-Case
10-3 10-2 110-1
10-4
2
1
0.1
0.01
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
Square Wave Pulse Duration (s)
Normalized Effective Transient
Thermal Impedance
Document Number: 71655 www.vishay.com
Revison: 15-Feb-10 1
Package Information
Vishay Siliconix
PowerPAK® SO-8, (SINGLE/DUAL)
MILLIMETERS INCHES
DIM. MIN. NOM. MAX. MIN. NOM. MAX.
A 0.97 1.04 1.12 0.038 0.041 0.044
A1 0.00 - 0.05 0.000 - 0.002
b 0.33 0.41 0.51 0.013 0.016 0.020
c 0.23 0.28 0.33 0.009 0.011 0.013
D 5.05 5.15 5.26 0.199 0.203 0.207
D1 4.80 4.90 5.00 0.189 0.193 0.197
D2 3.56 3.76 3.91 0.140 0.148 0.154
D3 1.32 1.50 1.68 0.052 0.059 0.066
D4 0.57 TYP. 0.0225 TYP.
D5 3.98 TYP. 0.157 TYP.
E 6.05 6.15 6.25 0.238 0.242 0.246
E1 5.79 5.89 5.99 0.228 0.232 0.236
E2 3.48 3.66 3.84 0.137 0.144 0.151
E3 3.68 3.78 3.91 0.145 0.149 0.154
E4 0.75 TYP. 0.030 TYP.
e 1.27 BSC 0.050 BSC
K1.27 TYP. 0.050 TYP.
K1 0.56 - - 0.022 - -
H 0.51 0.61 0.71 0.020 0.024 0.028
L 0.51 0.61 0.71 0.020 0.024 0.028
L1 0.06 0.13 0.20 0.002 0.005 0.008
θ0° - 12° 0° - 12°
W 0.15 0.25 0.36 0.006 0.010 0.014
M0.125 TYP. 0.005 TYP.
ECN: T10-0055-Rev. J, 15-Feb-10
DWG: 5881
3. Dimensions exclusive of mold flash and cutting burrs.
1.
Notes
2
Inch will govern.
Dimensions exclusive of mold gate burrs.
Backside View of Single Pad
Backside View of Dual Pad
Detail Z
D
D1
D2
c
θ
A
θ
E1
θ
D1
E2
D2
e
b
1
2
3
4
H
4
3
2
1
θ
1
2
3
4
b
L
D2
D3(2x)
Z
A1
K1
K
D
E
W
L1
D5
E3
D4
E4
E4
KL
HE2
D4
D5
M
E3
0.150 ± 0.008
2
2
Vishay Siliconix
AN821
Document Number 71622
28-Feb-06
www.vishay.com
1
PowerPAK® SO-8 Mounting and Thermal Considerations
Wharton McDaniel
MOSFETs for switching applications are now available
with die on resistances around 1 mΩ and with the
capability to handle 85 A. While these die capabilities
represent a major advance over what was available
just a few years ago, it is important for power MOSFET
packaging technology to keep pace. It should be obvi-
ous that degradation of a high performance die by the
package is undesirable. PowerPAK is a new package
technology that addresses these issues. In this appli-
cation note, PowerPAK’s construction is described.
Following this mounting information is presented
including land patterns and soldering profiles for max-
imum reliability. Finally, thermal and electrical perfor-
mance is discussed.
THE PowerPAK PACKAGE
The PowerPAK package was developed around the
SO-8 package (Figure 1). The PowerPAK SO-8 uti-
lizes the same footprint and the same pin-outs as the
standard SO-8. This allows PowerPAK to be substi-
tuted directly for a standard SO-8 package. Being a
leadless package, PowerPAK SO-8 utilizes the entire
SO-8 footprint, freeing space normally occupied by the
leads, and thus allowing it to hold a larger die than a
standard SO-8. In fact, this larger die is slightly larger
than a full sized DPAK die. The bottom of the die attach
pad is exposed for the purpose of providing a direct,
low resistance thermal path to the substrate the device
is mounted on. Finally, the package height is lower
than the standard SO-8, making it an excellent choice
for applications with space constraints.
PowerPAK SO-8 SINGLE MOUNTING
The PowerPAK single is simple to use. The pin
arrangement (drain, source, gate pins) and the pin
dimensions are the same as standard SO-8 devices
(see Figure 2). Therefore, the PowerPAK connection
pads match directly to those of the SO-8. The only dif-
ference is the extended drain connection area. To take
immediate advantage of the PowerPAK SO-8 single
devices, they can be mounted to existing SO-8 land
patterns.
The minimum land pattern recommended to take full
advantage of the PowerPAK thermal performance see
Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Sili-
conix MOSFETs. Click on the PowerPAK SO-8 single
in the index of this document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight and layer stack,
experiments have found that more than about 0.25 to
0.5 in2 of additional copper (in addition to the drain
land) will yield little improvement in thermal perfor-
mance.
Figure 1. PowerPAK 1212 Devices
Figure 2.
Standard SO-8PowerPAK SO-8
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2
Document Number 71622
28-Feb-06
Vishay Siliconix
AN821
PowerPAK SO-8 DUAL
The pin arrangement (drain, source, gate pins) and the
pin dimensions of the PowerPAK SO-8 dual are the
same as standard SO-8 dual devices. Therefore, the
PowerPAK device connection pads match directly to
those of the SO-8. As in the single-channel package,
the only exception is the extended drain connection
area. Manufacturers can likewise take immediate
advantage of the PowerPAK SO-8 dual devices by
mounting them to existing SO-8 dual land patterns.
To take the advantage of the dual PowerPAK SO-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
The gap between the two drain pads is 24 mils. This
matches the spacing of the two drain pads on the Pow-
erPAK SO-8 dual package.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a test preconditioning and are then
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-
ture profile used, and the temperatures and time
duration, are shown in Figures 3 and 4.
For the lead (Pb)-free solder profile, see http://
www.vishay.com/doc?73257.
Ramp-Up Rate + 6 °C /Second Maximum
Temperature at 155 ± 15 °C 120 Seconds Maximum
Temperature Above 180 °C 70 - 180 Seconds
Maximum Temperature 240 + 5/- 0 °C
Time at Maximum Temperature
20 - 40 Seconds
Ramp-Down Rate
+ 6 °C/Second Maximum
Figure 3. Solder Reflow Temperature Profile
Figure 3. Solder Reflow Temperatures and Time Durations
210 - 220 °C
3 °C(max) 4 ° C/s (max)
10 s (max)
183 °C
50 s (max)
Reflow Zone
60 s (min)
Pre-Heating Zone
3 °C(max)
140 - 170 °C
Maximum peak temperature at 240 °C is allowed.
Vishay Siliconix
AN821
Document Number 71622
28-Feb-06
www.vishay.com
3
THERMAL PERFORMANCE
Introduction
A basic measure of a device’s thermal performance is
the junction-to-case thermal resistance, Rθjc, or the
junction-to-foot thermal resistance, Rθjf. This parameter
is measured for the device mounted to an infinite heat
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the DPAK, PowerPAK SO-8, and stan-
dard SO-8. The PowerPAK has thermal performance
equivalent to the DPAK, while having an order of magni-
tude better thermal performance over the SO-8.
Thermal Performance on Standard SO-8 Pad Pattern
Because of the common footprint, a PowerPAK SO-8
can be mounted on an existing standard SO-8 pad pat-
tern. The question then arises as to the thermal perfor-
mance of the PowerPAK device under these conditions.
A characterization was made comparing a standard SO-8
and a PowerPAK device on a board with a trough cut out
underneath the PowerPAK drain pad. This configuration
restricted the heat flow to the SO-8 land pads. The
results are shown in Figure 5.
Because of the presence of the trough, this result sug-
gests a minimum performance improvement of 10 °C/W
by using a PowerPAK SO-8 in a standard SO-8 PC
board mount.
The only concern when mounting a PowerPAK on a
standard SO-8 pad pattern is that there should be no
traces running between the body of the MOSFET.
Where the standard SO-8 body is spaced away from the
pc board, allowing traces to run underneath, the Power-
PAK sits directly on the pc board.
Thermal Performance - Spreading Copper
Designers may add additional copper, spreading cop-
per, to the drain pad to aid in conducting heat from a
device. It is helpful to have some information about the
thermal performance for a given area of spreading cop-
per.
Figure 6 shows the thermal resistance of a PowerPAK
SO-8 device mounted on a 2-in. 2-in., four-layer FR-4
PC board. The two internal layers and the backside layer
are solid copper. The internal layers were chosen as
solid copper to model the large power and ground
planes common in many applications. The top layer was
cut back to a smaller area and at each step junction-to-
ambient thermal resistance measurements were taken.
The results indicate that an area above 0.3 to 0.4 square
inches of spreading copper gives no additional thermal
performance improvement. A subsequent experiment
was run where the copper on the back-side was
reduced, first to 50 % in stripes to mimic circuit traces,
and then totally removed. No significant effect was
observed.
TABLE 1.
DPAK and PowerPAK SO-8
Equivalent Steady State Performance
DPAK PowerPAK
SO-8
Standard
SO-8
Thermal
Resistance Rθjc 1.2 °C/W 1.0 °C/W 16 °C/W
Figure 5.
PowerPAK SO-8 and Standard SO-0 Land Pad Thermal Path
Si4874DY vs. Si7446DP PPAK on a 4-Layer Board
SO-8 Pattern, Trough Under Drain
Pulse Duration (sec)
)
s
ttaw/
C
( e
cn
adep
m
I
0.0001
0
1
50
60
10
100000.01
40
20
Si4874DY
Si7446DP
100
30
Figure 6. Spreading Copper Junction-to-Ambient Performance
R
th
vs. Spreading Copper
(0 %, 50 %, 100 % Back Copper)
)sttaw/C(
ecn
adep
m
I
0.00
56
51
46
41
36
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
0 %
50 %
100 %
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4
Document Number 71622
28-Feb-06
Vishay Siliconix
AN821
SYSTEM AND ELECTRICAL IMPACT OF
PowerPAK SO-8
In any design, one must take into account the change in
MOSFET rDS(on) with temperature (Figure 7).
A MOSFET generates internal heat due to the current
passing through the channel. This self-heating raises
the junction temperature of the device above that of the
PC board to which it is mounted, causing increased
power dissipation in the device. A major source of this
problem lies in the large values of the junction-to-foot
thermal resistance of the SO-8 package.
PowerPAK SO-8 minimizes the junction-to-board ther-
mal resistance to where the MOSFET die temperature is
very close to the temperature of the PC board. Consider
two devices mounted on a PC board heated to 105 °C
by other components on the board (Figure 8).
Suppose each device is dissipating 2.7 W. Using the
junction-to-foot thermal resistance characteristics of the
PowerPAK SO-8 and the standard SO-8, the die tem-
perature is determined to be 107 °C for the PowerPAK
(and for DPAK) and 148 °C for the standard SO-8. This
is a 2 °C rise above the board temperature for the Pow-
erPAK and a 43 °C rise for the standard SO-8. Referring
to Figure 7, a 2 °C difference has minimal effect on
rDS(on) whereas a 43C difference has a significant effect
on rDS(on).
Minimizing the thermal rise above the board tempera-
ture by using PowerPAK has not only eased the thermal
design but it has allowed the device to run cooler, keep
rDS(on) low, and permits the device to handle more cur-
rent than the same MOSFET die in the standard SO-8
package.
CONCLUSIONS
PowerPAK SO-8 has been shown to have the same
thermal performance as the DPAK package while hav-
ing the same footprint as the standard SO-8 package.
The PowerPAK SO-8 can hold larger die approximately
equal in size to the maximum that the DPAK can accom-
modate implying no sacrifice in performance because of
package limitations.
Recommended PowerPAK SO-8 land patterns are pro-
vided to aid in PC board layout for designs using this
new package.
Thermal considerations have indicated that significant
advantages can be gained by using PowerPAK SO-8
devices in designs where the PC board was laid out for
the standard SO-8. Applications experimental data gave
thermal performance data showing minimum and typical
thermal performance in a SO-8 environment, plus infor-
mation on the optimum thermal performance obtainable
including spreading copper. This further emphasized the
DPAK equivalency.
PowerPAK SO-8 therefore has the desired small size
characteristics of the SO-8 combined with the attractive
thermal characteristics of the DPAK package.
Figure 7.
MOSFET
rDS(on)
vs. Temperature
Figure 8.
Temperature of Devices on a PC Board
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50 -25 0 25 50 75 100 125 150
VGS = 10 V
ID = 23 A
On-Resistance vs. Junction Temperature
TJ- Junction Temperature (°C)
)dezilamroN(
( ecnatsiseR-nO -r )no(SD )
0.8 °C/W
107 °C
PowerPAK SO-8
16 C/W
148 °C
Standard SO-8
PC Board at 105 °C
Application Note 826
Vishay Siliconix
Document Number: 72599 www.vishay.com
Revision: 21-Jan-08 15
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR PowerPAK® SO-8 Single
0.174
(4.42)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.260
(6.61)
0.024
(0.61)
0.154
(3.91)
0.150
(3.81)
0.050
(1.27)
0.050
(1.27)
0.032
(0.82)
0.040
(1.02)
0.026
(0.66)
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Legal Disclaimer Notice
www.vishay.com Vishay
Revision: 12-Mar-12 1Document Number: 91000
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
