1
®
FN9209.4
ISL6310
Two-Phase Buck PWM Controller with
High Current Integrated MOSFET Drivers
The ISL6310 is a two-phase PWM control IC with integrated
MOSFET drivers. It provides a precision voltage regulation
system for multiple applications including, bu t not limited to,
high current low voltage point-of-load converters, embedded
applications and other general purpose lo w voltage medium
to high current applications. The integration of power
MOSFET drivers into the controller IC marks a departure
from the separate PWM controller and driver configuration of
previous multi-phase product famil ies. By reducing the
number of external parts, this integration allows for a cost
and space saving power management solution.
Output voltage can be programmed using the on-chip DAC
or an external precision reference. A two bit code programs
the DAC reference to one of 4 possibl e values (0.6V, 0.9V,
1.2V and 1.5V). A unity gain, differential amplifier is provided
for remote voltage sensing, compensating for any potential
difference between remote and local grounds. The output
voltage can also be offset through the use of single external
resistor. An optional droop function is also implemented and
can be disabled for applications having less stringent output
voltage variation requirements or experiencing less severe
step loads.
A unique feature of the ISL6310 is the combined use of both
DCR and rDS(ON) current sensing. Load line voltage
positioning and overcurrent protection are accomplished
through continuous inductor DCR current sensing, while
rDS(ON) current sensing is used for accurate channel-current
balance. Using both methods of current sampling utilizes the
best advantages of each technique.
Protection features of this controller IC include a set of
sophisticated overvoltage and overcurrent protection.
Overvoltage results in the converter turning the lower
MOSFETs ON to clamp the rising output voltage and protect
the load. An OVP output is also provided to drive an optional
crowbar device. The overcurrent protection level is set
through a single external resistor. Other protection features
include protection against an open circuit on the remote
sensing inputs. Combine d , th ese features provid e advanced
protection for the output load.
Features
• Integrated Multi-Phase Po wer Conversion
- 1 or 2-Phase Operation
• Precision Output Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.8% System Accuracy Over-Temperature
(for REF = 0.6V and 0.9V)
- ±0.5% System Accuracy Over-Temperature
(for REF=1.2V and 1.5V)
- Usable for Output Voltages not Exceeding 2.3V
- Adjustable Reference-Voltage Offset
• Precision Channel Current Sha r ing
- Uses Loss-Less rDS(ON) Current Sampling
• Optional Load Line (Droop) Programming
- Uses Loss-Less Inductor DCR Current Sampling
• Variable Gate-Drive Bias - 5V to 12V
• Internal or External Reference Voltage Setting
- On-Chip Adjustable Fixed DAC Reference Voltage with
2-bit Logic Input Selects from Four Fixed Reference
Voltages (0.6V, 0.9V, 1.2V, 1.5V)
- Reference can be Changed Dynamically
- Can use an External Voltage Reference
• Overcurrent Protection
• Multi-tiered Overvoltage Protection
- OVP Pin to Drive Optional Crowbar Device
• Selectable Operation Frequency up to 1.5MHz Per Phase
• Digital Soft-Start
• Capable of Start-up in a Pre-Biased Load
• Pb-Free (RoHS Compliant)
Applications
• High Current DDR/Chipset core voltage regulators
• High Current, Low voltage DC/DC converters
• High Current, Low voltage FPGA/ASIC DC/DC converters
Data Sheet August 7, 2008
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN9209.4
August 7, 2008
Pinout ISL6310
(32 LD QFN)
TOP VIEW
Ordering Information
PART
NUMBER PART
MARKING TEMP. RANGE
(°C) PACKAGE
(Pb-Free) PKG.
DWG. #
ISL6310CRZ* (Note) ISL6310 CRZ 0 to +70 32 Ld 5x5 QFN L32.5x5
ISL6310IRZ* (Note) ISL6310 IRZ -40 to +85 32 Ld 5x5 QFN L32.5x5
ISL6310EVAL1Z Evaluation Platform (Pb-free)
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
RGND
REF1
REF0
PGOOD
LGATE1
BOOT1
2PH
FS
ISEN1
UGATE1
PHASE1
OVP
ENLL
BOOT2
PHASE2
VSEN
OCSET
ICOMP
ISUM
IREF
LGATE2
PVCC
ISEN2
UGATE2
DAC
REF
OFST
VCC
COMP
FB
VDIFF
DROOP
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
9 10111213141516
33
GND
ISL6310
3FN9209.4
August 7, 2008
Block Diagram
DAC
DAC
REF1
REF0
E/A
REF
FB
OFFSET
OFST
COMP
ISUM
IREF
ICOMP
ISEN AMP
OC
OCSET
RGND
VSEN
VDIFF
100µA
+150mV
OVP
x 0.82
OVP
UVP
ISEN1 ISEN2
CHANNEL
CURRENT
SENSE
∑
1
N
∑
PWM1
∑
PWM2
CHANNEL
CURRENT
BALANCE
THROUGH
SHOOT-
PROTECTION
BOOT1
UGATE1
PHASE1
LGATE1
PVCC
LOGIC
CONTROL
GATE
THROUGH
SHOOT-
PROTECTION
BOOT2
UGATE2
PHASE2
LGATE2
LOGIC
CONTROL
GATE
CLOCK AN D
GENERATOR
SAWTOOTH
SOFT-START
AND
FAULT LOGIC
PHASE 2
DETECT
VCC
RESET
POWER-ON
0.66V
ENLL
FS
PGOOD
GND
0.2V
+1V
DROOP OVP
2PH
x1
x1
ISL6310
4FN9209.4
August 7, 2008
Typical Application - ISL6310
PGOOD
VDIFF FB COMP
VCC ISEN1
ISL6310
REF1
FS
OFST
REF
+12V
+12V
PHASE1
UGATE1
BOOT1
LGATE1
ISEN2
PHASE2
UGATE2
BOOT2
LGATE2
ISUMICOMP
IREF
LOAD
VSEN
RGND
OCSET
REF0
+5V
PVCC
ENLL
+12V GND
OVP
2PH
DAC
DROOP
ISL6310
5FN9209.4
August 7, 2008
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V
Supply Voltage, PVCC. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V
Absolute Boot Voltage, VBOOT . . . . . . . .GND - 0.3V to GND + 36V
Phase Voltage, VPHASE . . . . . . . . GND - 0.3V to 15V (PVCC = 12)
GND - 8V (<400ns, 20µJ) to 24V (<200ns, VBOOT-PHASE = 12V)
Upper Gate Voltage, VUGATE . . . .VPHASE - 0.3V to VBOOT + 0.3V
VPHASE - 3.5V (<100ns Pulse Width, 2µJ) to VBOOT + 0.3V
Lower Gate Voltage, VLGATE. . . . . . . . GND - 0.3V to PVCC + 0.3V
GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V
Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V
Recommended Operating Conditions
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .+5V to 12V ±5%
Ambient Temperature (ISL6310CR, ISL6310CRZ) . . . 0°C to +70°C
Ambient Temperature (ISL6310IR, ISL6310IRZ) . . .-40°C to +85°C
Thermal Information
Thermal Resistance θJA (°C/W) θJC (°C/W)
QFN Package (Notes 1, 2). . . . . . . . . . 35 5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limit s are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
BIAS SUPPLY AND INTERNAL OSCILLATOR
Input Bias Supply Current IVCC; ENLL = high - 15 20 mA
Gate Drive Bias Current IPVCC; ENLL = high, all gate outputs open,
Fsw = 250kHz -1.53.0mA
VCC POR (Power-On Reset) Threshold VCC Rising 4.25 4.38 4.50 V
VCC Falling 3.75 3.88 4.00 V
PVCC POR (Power-On Reset) Threshold PVCC Rising 4.25 4.38 4.50 V
PVCC Falling 3.75 3.88 4.00 V
Oscillator Ramp Amplitude (Note 3) VP-P -1.50-V
Maximum Duty Cycle (Note 3) - 66.6 - %
CONTROL THRESHOLDS
ENLL Rising Threshold -0.66-V
ENLL Hysteresis - 100 - mV
COMP Shutdown Threshold COMP Falling 0.25 0.35 0.5 V
REFERENCE AND DAC
System Accuracy (DAC = 0.6V, 0.9V) DROOP connected to IREF -0.8 - 0.8 %
System Accuracy (DAC = 1.2V, 1.50V) DROOP connected to IREF -0.5 - 0.5 %
DAC Input Low Voltage (REF0, REF1) - - 0.4 V
DAC Input High Voltage (REF0, REF1) 0.8 - - V
External Reference 0.6 - 1.75 V
OFS Sink Current Accuracy (Negative Offset) ROFS = 30kΩ from OFS to VCC 47.5 50.0 52.5 µA
OFS Source Current Accuracy (Positive Offset) ROFS = 10kΩ from OFS to GND 47.5 50.0 52.5 µA
ISL6310
6FN9209.4
August 7, 2008
ERROR AMPLIFIER
DC Gain (Note 3) RL = 10k to ground - 96 - dB
Gain-Bandwidth Product (Note 3) CL = 100pF, RL = 10k to ground - 20 - MHz
Slew Rate (Note 3) CL = 100pF, Load = ±400µA - 8 - V/µs
Maximum Output Voltage Load = 1mA 3.90 4.20 - V
Minimum Output Voltage Load = -1mA - 0.85 1.0 V
REMOTE SENSE DIFFERENTIAL AMPLIFIER
Input bias current (VSEN) (VSEN = 1.5V) 49 55 60 µA
Bandwidth (Note 3) -20-MHz
Slew Rate (Note 3) -8-V/µs
OVERCURRENT PROTECTION
OCSET Trip Current 93 100 107 µA
OCSET Accuracy OC Comparator offset (OCSET and ISUM
Difference) -5 0 5 mV
ICOMP Offset ISEN Amplifier offset -5 0 5 mV
PROTECTION
Undervoltage Threshold VSEN falling 80 82 84 %DAC
Undervoltage Hysteresis VSEN Rising - 3 - %DAC
Overvoltage Threshold While IC Disabled 1.62 1.67 1.72 V
Overvoltage Threshold VSEN Rising DAC +
125mV DAC +
150mV DAC +
175mV V
Overvoltage Hysteresis VSEN Falling - 50 - mV
Open Sense-Line Protection Threshold IREF Rising and Falling VDIFF
+ 0.9V VDIFF +
1V VDIFF
+ 1.1V V
OVP Output High Drive Voltage IOVP = 15mA, VCC = 5V 2.2 3.4 - V
SWITCHING TIME
UGATE Rise Time (Note 3) tRUGATE; VPVCC = 12V, 3nF Load, 10% to 90% - 26 - ns
LGATE Rise Time (Note 3) tRLGATE; VPVCC = 12V, 3nF Load, 10% to 90% - 18 - ns
UGAT E Fall Time (Note 3) tFUGATE; VPVCC = 12V, 3nF Load, 90% to 10% - 18 - ns
LGATE Fall Time (Note 3) tFLGATE; VPVCC = 12V, 3nF Load, 90% to 10% - 12 - ns
UGATE Turn-On Non-Overlap (Note 3) tPDHUGATE; VPVCC = 12V, 3nF Load, Adaptive - 10 - ns
LGATE Turn-On Non-Overlap (Note 3) tPDHLGATE; VPVCC = 12V, 3nF Load, Adaptive - 10 - ns
GATE DRIVE RESISTANCE (Note 4)
Upper Drive Source Resistance VPVCC = 12V, 150mA Source Current 1.25 2.0 3.0 Ω
Upper Drive Sink Resistance VPVCC = 12V, 150mA Sink Current 0.9 1.6 3.0 Ω
Lower Drive Source Resistance VPVCC = 12V, 150mA Source Current 0.85 1.4 2.2 Ω
Lower Drive Sink Resistance VPVCC = 12V, 150mA Sink Current 0.60 0.94 1.35 Ω
OVER-TEMPERATURE SHUTDOWN
Thermal Shutdown Setpoint (Note 3) - 160 - °C
Thermal Recovery Setpoint (Note 3) - 100 - °C
NOTES:
3. Limits should be considered typical and are not production tested.
4. Limits established by characterization and are not production tested.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. Parameters with MIN and/or MAX limit s are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
ISL6310
7FN9209.4
August 7, 2008
Timing Diagram
Simplified Power System Diagram
Functional Pin Description
VCC (Pin 3)
Bias supply for the IC’s small-signal ci rcuitry. Connect this pin
to a +5V supply and locally decouple usi ng a quality 1 .0µF
ceramic capacitor.
PVCC (Pin 15)
Power supply pin for the MOSFET drive. This pin can be
connected to any voltage from +5V to +12V, depending on
the desired MOSFET gate drive level.
GND (Pin 33)
Bias and reference ground for the IC.
ENLL (Pin 20)
This pin is a threshold sensitive (approximately 0.66V) enable
input for the controller. Held low , this pin disables co ntroller
operation. Pulled high, the pi n enables th e cont roller fo r
operation.
FS (Pin 29)
A resistor, placed from FS to ground, will set the switching
frequency. Refer to Equation 43 and Figure 24 for proper
resistor calculation.
2PH (Pin 31)
This pin is used to choose between single or two phase
operation. Tying this pin to VCC allows fo r 2-Phase operation.
Tying the 2PH pin to GND causes the contro ller to operate in
a single phase mode.
REF0 and REF1 (Pins 30, 21)
These pins make up the 2-Bit input th at select s the fixed DAC
reference voltage. These pins respond to TTL l ogic
thresholds. The ISL6310 decodes these input s to establish
one of four fixed reference voltages; se e Table 1 for
correspondence between REF0 and REF1 input s and
reference voltage settings.
UGATE
LGATE
tFLGATE
tPDHUGATE
tRUGATE tFUGATE
tPDHLGATE
tRLGATE
CHANNEL1
+5VIN
VOUT
Q1
Q2
ISL6310
DAC
CHANNEL2
Q3
Q4
+12VIN
ENLL
PGOOD
2
REF0,REF1
OVP
ISL6310
8FN9209.4
August 7, 2008
These pins are internally pulled hig h, to approximately 1.2V,
by 40µA (typically) internal current sources; the internal
pull-up current decreases to 0 as the R EF0 and REF1
voltages approach the internal pull-up volt a ge. Both REF0
and REF1 pins are comp atible with extern al pull-u p voltages
not exceeding the IC’ s bias volt age (VC C).
VSEN and RGND (Pins 8, 7)
VSEN and RGND are input s to th e precision differential
remote-sense amplifier and shou ld be connected to the sense
pins of the remote load.
ICOMP, ISUM, and IREF (Pins 10, 12, 13)
ISUM, IREF, and ICOMP are the DCR current sense
amplifier’s negative in put, positive input, an d output
respectively. For accurate DCR current sensing, connect a
resistor from each channel’ s phase nod e to ISUM and
connect IREF to the summing point of the ou tp ut inductors,
roughly VOUT. A parallel R-C feedback circuit con necte d
between ISUM and ICOMP will then create a volt age fro m
IREF to ICOMP proportional to the voltage dro p across the
inductor DCR. This vo lt age is referred to as the droop volt a ge
and is added to the diff erenti al remote-sense ampli fier’s
output
An optional 0.001µF to 0.01µF ceramic capacitor can be
placed from the IREF pin to the ISUM pin to help reduce
common mode noise that might be introduced by the layout.
DROOP (Pin 11)
This pin enables or disables droop. Tie this pin to the ICOMP
pin to enable droop. To disable droop, tie this pin to the IREF
pin.
VDIFF (Pin 6)
VDIFF is the output of the diff erential remote-sense amplifi er.
The voltage on this pin is equal to the di f ference betw een
VSEN and RGND added to the difference between IREF and
ICOMP. VDIFF therefore represents the VOUT volt age plu s
the droop volt age.
FB and COMP (Pins 5, 4)
The internal error amplifier’s inverting input and output
respectively. FB is connected to VDIFF through an external
R or R-C network depending on the desired type of
compensation (Type II or III). COMP is tied back to FB
through an external R-C network to co mpensate the
regulator.
DAC (Pin 32)
The DAC pin is the direct output of the internal DAC. This pin
is connected to REF pin using 1kΩ to 5kΩ resistor, This pin
can be left open if an external reference is used.
REF (Pin 1)
The REF input pin is the positive input of the error amplifier.
This pin can be connected to the DAC pin using a resistor
(1kΩ to 5kΩ) when the internal DAC voltage is used as the
reference voltage. When an external voltage reference is used,
it must be connected directly to the REF pin, while the DAC pin
is left unconnected. The output volt age will be regulated to the
voltage at the REF pin unless this voltage is greater than the
voltage at the DAC pin. If an external reference is used at this
pin, its magnitude cannot exceed 1.75V.
A capacitor is used between the R EF pin and ground to
smooth the DAC voltage during soft-start.
OFST (Pin 2)
The OFST pin provides a means to program a DC current for
generating an of fset vol t age ac ross the re sistor betwe en FB
and VDIFF. The offset current is generate d via an extern al
resistor and precision internal volt age references. The polarity
of the offset is selected by connecting the resisto r to GND or
VCC. For no offset, the OFST pin should be lef t unconnected.
OCSET (Pin 9)
This is the overcurrent set pin. Placing a re sistor from OCSET
to ICOMP, allows a 100μA current to flow out of this pin,
producing a voltag e reference. Intern al circuitry comp ares the
voltage at OCSET to the voltage at ISUM, and if ISUM ever
exceeds OCSET, the overcurrent protection activates.
ISEN1, ISEN2 (Pins 26, 16)
These pins are used for balancing the channel currents by
sensing the current through each channel’s lower MOSFET
when it is conducting. Connect a resistor between the ISEN1
and ISEN2 pins and their respective phase node. This
resistor sets a current proportional to the current in the lower
MOSFET during its conduction interval.
UGATE1 and UGATE2 (Pins 25, 17)
Connect these pins to the upper MOSFETs’ gates. These
pins are used to control the upper MOSFETs and are
monitored for shoot-through prevention purposes. Maximum
individual channel duty cycle is limited to 66%.
BOOT1 and BOOT2 (Pins 24,18)
These pins provide the bias voltage for the upper MOSFETs’
drives. Connect these pins to appropriately-chosen external
bootstrap capacitors. Internal bootstrap diodes connected to
the PVCC pins provide the necessary bootstrap charge.
PHASE1 and PHASE2 (Pins 23, 19)
Connect these pins to the sources of the upper MOSFETs.
These pins are the return path for the upper MOSFETs’
drives.
LGATE1 and LGATE2 (Pins 27, 14)
These pins are used to control the lower MOSFETs and are
monitored for shoot-through prevention p urposes. Connect
these pins to the lower MOSFETs’ gates. Do not use external
series gate resistors as this mi ght lead to shoot-through .
ISL6310
9FN9209.4
August 7, 2008
PGOOD (Pin 28)
PGOOD is used as an indication of the end of sof t-st art. It is
an open-drain logic output that is low impedance un til the
soft- st art is comple ted and V OUT is equal to the VID setting.
Once in normal operation, PGOOD indicates whether the
output volt age is withi n speci fied overvo lt age an d
undervoltage li mits. If the output voltage exceeds these limit s
or a reset event occurs (suc h as an overcurrent event),
PGOOD becomes high impedance again. The potential at this
pin should not exceed that of the potential at VCC p in by more
than a typical forward diode drop a t a ny time
OVP (Pin 22)
Overvoltage protection pin. This pin pulls to VCC when an
overvoltage condition is detected. Connect this pin to the
gate of an SCR or MOSFET tied across VIN and ground to
prevent damage to a load device.
Operation
Multi-Phase Power Conversion
Modern low voltage DC/DC con verter load current profiles
have changed to the point that the advant ages of mu lti-phase
power conversion are impossible to ignore. The technical
challenges associated with produci ng a single-p hase
converter that is both cost-effe ctive and thermally viable have
forced a change to the cost-saving approach of mul ti-phase.
The ISL6310 controller help s simplify implemen ta tion by
integrating vital fun ctions an d requiring mini mal exte rna l
components. The “Block Diagram ” on p age 3 provides a top
level view of multi-phase power conversion using the ISL6310
controller.
Interleaving
The switching of each channel in an ISL6310-based
converter is timed to be symmetrically out-of-phase with the
other channel. As a result, the two-phase converte r has a
combined ripple frequency twice the frequency of one of its
phases. In addition, the peak-to-peak amplitude of the
combined inductor currents is proportionately reduced
(Equations 1 and 2).
Increased ripple frequency and lower ripple amplitude
generally translate to lower per-channel inductance and
lower total output capacitance for a given set of performance
specifications. Figure 1 illustrates the additive effect on
output ripple frequency. The two channel currents (IL1 and
IL2), combine to form the AC ripple current and th e DC load
current. The ripple component has two times the ripple
frequency of each individual channel current.
To understand the reduction of ripple current amplitude in the
multi-phase circuit, examine Equation 1, which represents
an individual channel peak-to-peak inductor current.
In Equation 1, VIN and VOUT are the input and output
voltages respectively, L is the single-channel inductor value,
and FSW is the switching frequency.
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decrea ses by an
amount proportional to the number of channels. Output
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current all ows the
designer to use fewer or less costly output capacitors.
Another benefit of interleavin g is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a two-phase converter combining to reduce
the total input ripple current.
FIGURE 1. PWM AND INDUCTOR-CURRENT W A VEFORMS
FOR 2-PHASE CONVERTER
PWM2
PWM1
IL2
IL1
IL1 + IL2
IPP VIN VOUT
–()VOUT
⋅
LF
SW VIN
⋅⋅
----------------------------------------------------------= (EQ. 1)
ICPP,VIN NV
OUT
⋅–()VOUT
⋅
LF
SW V⋅IN
⋅
--------------------------------------------------------------------= (EQ. 2)
ISL6310
10 FN9209.4
August 7, 2008
Figures 25 and 26 in the section entitle d “Input Capacitor
Selection” on page 24 can be used to determine the input
capacitor RMS current based on load current, duty cycle,
and the number of channels. They are provid ed as aids in
determining the optimal input capacitor solution.
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the ISL6310
is two. One switching cycle is defined as the time between
the internal PWM1 pulse termination signals. The pulse
termination signal is the internally generated clock signal
that triggers the falling edge of PWM1. The cycle time of the
pulse termination signal is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. Each cycle begins when the clock signal commands
PWM1 to go low . The PWM1 transition signals the internal
channel 1 MOSFET driver to turn off the Channel 1 upper
MOSFET and turn on the Channel 1 synchronous MOSFET.
In the default channel configur ation, the PWM2 pulse
terminates 1/2 of a cycle after the PWM1 pulse.
One switching cycle for the ISL6310 is defined as the time
between consecutive PWM pulse terminations (turn-off of
the upper MOSFET on a channel). Each cycle begins when
a switching clock signal commands the upper MOSFET to
go off. The other channel’s upper MOSFET conduction is
terminated 1/2 of a cycle later.
Once a PWM pulse transitions low, it is held low for a
minimum of 1/3 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
VCOMP, minus the current correction signal relative to the
sawtooth ramp as illustrated in Figure 3. When the modified
VCOMP voltage crosses the sawtooth ramp, the PWM output
transitions high. The internal MOSF ET driver detects the
change in state of the PWM signal and turns off the
synchronous MOSFET and turns on the upper MOSFET.
The PWM signal will remain high until the pulse termination
signal marks the beginning of the next cycle by triggering the
PWM signal low.
Single phase operation can be selected by connecting 2PH
to GND.
Channel Current Balance
One important benefit of multi-phase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sink s and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multi-pha se converter be controlled to
carry about the same amount of current at any load level. To
achieve this, the currents through each channel must be
sampled every switching cycle. The sampled currents, In,
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, IAVG, provides a measure of the total load
current demand on the converter during each switching
cycle. Channel current balance is achieved by comparing
the sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented current
balance method is illustrated in Figure 3, with error
correction for Channel 1 represented. In Figure 3, the cycle
average current, IAVG, is compared with the Channel 1
sample, I1, to create an error signal IER.
The filtered error signal modifies the pul se width
commanded by VCOMP to correct any unbalance and force
IER toward zero. The same method for error signal
correction is applied to each active channel.
Current Sampling
In order to realize proper current balance, the currents in
each channel must be sampled every switching cycle. Th is
sampling occurs during the forced off-time, following a PWM
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-
CAPACITOR RMS CURRENT FOR 2-PHASE
CONVERTER
Q1 D-S CURRENT
Q2 D-S CURRENT
CIN CURRENT
FIGURE 3. CHANNEL 1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
÷ N
IAVG I2
Σ
-
+
+-
+
-
f(s)
PWM1
I1
VCOMP
SAWTOOTH SIGNAL
IER
NOTE: CHANNEL 2 IS OPTIONAL.
FILTER
TO GATE
CONTROL
LOGIC
ISL6310
11 FN9209.4
August 7, 2008
transition low. During this time the current sense amplifier
uses the ISEN inputs to reproduce a signal proportional to
the inductor current, IL. This sensed current, ISEN, is simply
a scaled version of the inductor current. The sample window
opens exactly 1/6 of the switching period, tSW, after the
PWM transitions low. The sample window then stays open
the rest of the switching cycle until PWM transitions high
again, as illustrated in Figure 4.
The sampled current, at the end of the tSAMPLE, is
proportional to the inductor current and is held until the next
switching period sample. The sampled current is used only
for channel curr en t ba l a nce .
The ISL6310 supports MOSFET rDS(ON) current sensing to
sample each channel’ s current for channel curren t balance.
The internal circu itry, shown in Figure 5 represents Channel N
of an N-Channel converter. This circuitry is repeated for ea ch
channel in the converter, but may not be active depending on
the status of the 2PH pin, as described in the “PWM
Operation” on page 10.
The ISL6310 senses the channel load current by sampling
the voltage across the lower MOSFET rDS(ON), as shown in
Figure 5. A ground-referenced operational amplifier, internal
to the ISL6310, is connected to the PHASE node through a
resistor, RISEN. The voltage across RISEN is equivalent to
the voltage drop across the rDS(ON) of the lower MOSFET
while it is conducting. The resulting current into the ISEN pin
is proportional to the channel current, IL. The ISEN current is
sampled and held as described in the See “Current
Sampling” on page 10. From Figure 5, Equation 3 for In is
derived where I L is the channel current.
Output Voltage Setting
The ISL6310 uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at the
REF0 and REF1 pins. The DAC decodes the 2-bit logic signals
into one of the discrete voltages shown in Table 1. Each REF0
and REF1 pins are pulled up to an internal 1.2V voltage by
weak current sources (40µA current, decrea sing to 0 as t he
voltage at the REF0, REF1 pins varies from 0 to the internal
1.2V pull-up voltage). External pull-up resistors or active-high
output stages can augment the pull-up current sources, up to a
voltage of 5V. The DAC pin must be connected to REF pin
through a 1kΩ to 5kΩ resistor and a filter capacitor (0.022µF) is
connected between REF and GND.
The ISL6310 accommodates the use of external voltage
reference connected to REF pin if a different output voltage
is required. The DAC voltage must be set at least as high as
external reference. The error amp internal noninverting input
is the lower of REF or (DAC +300mV).
A third method for setting the output voltage is to use a
resistor divider (RP1, RS1) from the output terminal (VOUT)
to VSEN pin to set the output voltage level as shown in
Figure 6. This method is good for generating voltages up to
2.3V (with the REF voltage set to 1.5V).
For this case, the output voltage can be obtained as follows:
It is recommended to choose resistor values of less than
500Ω for RS1 and RP1 resistors in order to get better output
voltage DC accuracy.
FIGURE 4. SAMPLE AND HOLD TIMING
TIME
PWM
IL
ISEN
SWITCHING PERIOD
SAMPLING PERIOD
OLD SAMPLE
CURRENT NEW SAMPLE
CURRENT
FIGURE 5. ISL6310 INTERNAL AND EXTERNAL CURRENT-
SENSING CIRCUITRY FOR CURRENT BALANCE
In
ISEN ILxrDS ON()
RISEN
--------------------------=
-
+
ISEN(n)
RISEN
SAMPLE
AND
HOLD
ISL6310 INTERNAL CIRCUIT EXTERNAL CIRCUIT
VIN
CHANNEL N
UPPER MOSFET
CHANNEL N
LOWER MOSFET
-
+
ILxr
DS ON()
IL
TABLE 1. ISL6310 DAC VOLTAGE SELECTION TABLE
REF1 REF0 DAC
0 0 0.600V
0 1 0.900V
1 0 1.200V
1 1 1.500V
InILrDS ON()
RISEN
----------------------
⋅=(EQ. 3)
VOUT VREF RS1 RP1
+()
RP1
----------------------------------VOFS VDROOP
–
+
−
⋅=(EQ. 4)
ISL6310
12 FN9209.4
August 7, 2008
Voltage Regulation
In order to re gulate the ou tp ut volt age to a specified level , th e
ISL6310 uses the integrating compe nsation network shown in
Figure 6. This compensation network insures that the steady
state error in the output volt age is limite d only to the erro r in
the reference voltage (output of the DAC or the external
voltage re feren ce) and offset errors in the OFS current
source, remote sense and error amplifiers. Intersil specifies
the guaranteed tolerance of the ISL6310 to includ e the
combined tolerances of each of the se element s, except when
an external reference or voltage di vider is used, then the
tolerances of these componen ts has to be taken into account.
The ISL6310 incorporates an internal differential remote
sense amplifier in the feedback p ath. The a mplifier re moves
the voltage erro r encountere d when measuring the output
voltage re lative to the contro ller ground reference point,
resulting in a more accurate means of se nsing output voltag e.
Connect the load’ s outp ut sense pi ns to the non-inverting
input, VSEN, and inverting input, RGND, of the remote sense
amplifier. The droop volt age, VDROOP, also feeds into the
remote sense amplifier. The remote sense output, VDIFF, is
therefore equal to the sum of the output voltage, V OUT, and
the droop volt age. VDIFF is connected to the inverting input of
the error amplifier through an external resistor.
The output of the error amplifier, VCOMP, is compared to the
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Internal MOSFET drivers
and regulate the converter output so that the voltage at FB is
equal to the voltage at REF. This will regulate the output
voltage to be equal to Equation 5. The intern al and external
circuitry that controls voltage regulation is illustrated in
Figure 6.
Load Line (Droop) Regulation
In some high current applications, a requirement on a
precisely controlled output impedance is imposed. This
dependence of output voltage on load current is often
termed “droop” or “load line” regulation.
The Droop is an optional featu r e in the ISL6310. It can be
enabled by connecting ICOMP pin to DROOP pin, as shown
in Figure 6. To disable it, connect the DROOP pin to IREF
pin.
As shown in Figure 6, a voltage, VDROOP, proportional to the
total current in all active channels, IOUT, feeds into the
differential remote-sense amplifier. The resulting voltage at
the output of the remote-sense amplifier is the sum of the
output voltage and the droop voltage. As Equation 5 shows,
feeding this voltage into the compensation network causes
the regulator to adjust the output voltage so that it’s equal to
the reference voltage minus the droop voltage.
The droop voltage, VDROOP, is created by sensing the
current through the output inductors. This is accomplished
by using a continuous DCR current sensing method.
Inductor windings have a characteristic distributed
resistance or DCR (Direct Current Resistance). For
simplicity, the inductor DCR is considered as a separate
lumped quantity, as shown in Figure 7. The channel current,
IL, flowing through the inductor, passes through the DCR.
Equation 6 shows the s-domain equivalent voltage, VL,
across the inductor.
The inductor DCR is important because the voltage dropped
across it is proportional to the channel current. By using a
simple R-C network and a current sense amplifier , as shown
in Figure 7, the voltage drop across all of the inductors DCRs
can be extracted. The output of the current sense amplifier,
VDROOP, can be shown to be proportional to the channel
currents IL1 and IL2, shown in Equation 7.
FIGURE 6. OUTPUT VOL T AGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
I
OFS
EXTERNAL CIRCUIT ISL6310 INTERNAL CIRCUIT
COMP
R2
R1
FB
VDIFF
VSEN
RGND
-
+VOFS ERROR AMPLIFIER
-
+
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
VCOMP
C1
REF
CREF
-
+
VID DAC
IREF
DROOP
+
-
+
VDROOP
-
+
VOUT
-
DAC
ICOMP +
-
ISUM
ISENSE
AMP
RP1
RS1
CSUM
VOUT VREF VOFS
±VDROOP
–=(EQ. 5)
VLs() ILsL DCR+⋅()⋅=(EQ. 6)
VDROOP s()
sL⋅
DCR
------------- 1+
⎝⎠
⎛⎞
sR
COMP CCOMP
⋅⋅ 1+()
-------------------------------------------------------------------------- RCOMP
RS
----------------------- IL1 IL2
+()DCR⋅⋅⋅=
(EQ. 7)
ISL6310
13 FN9209.4
August 7, 2008
If the R-C network components are selected such that the
R-C time constant matches the inductor L/DCR time
constant, then VDROOP is equal to the sum of the voltage
drops across the individual DCRs, multiplied by a gain. As
Equation 8 shows, VDROOP is therefore proportional to the
total output current, IOUT.
By simply adjusting the value of RS, the load line can be set
to any level, giving the converter the right amount of droop at
all load currents. It may also be necessary to compensate for
any changes in DCR due to temperature. These changes
cause the load line to be skewed, and cause the R-C time
constant to not match the L/DCR time constant. If this
becomes a problem a simple negative temperature
coefficient resistor network can be used in the place of
RCOMP to compensate for the rise in DCR due to
temperature.
Output Voltage Offset Programming
The ISL6310 allows the designer to accurately adjust the offset
voltage by connecting a resistor , ROFS, from the OFS pin to
VCC or GND. When ROFS is connected between OFS and
VCC, the voltage across it is regulated to 1.5V. This causes a
proportional current (IOFS) to flow into the OFS pin and out of
the FB pin. If ROFS is connected to ground, the voltage across
it is regulated to 0.5V, and IOFS flows into the FB pin and out of
the OFS pin. The offset current flowing through the resistor
between VDIFF and FB will generate the desired offset voltage
which is equal to the product (IOFS x R1). These functions are
shown in Figures 8 and 9.
Once the desired output offset voltage has been determined,
use the following formulas to set ROFS:
For Positive Offset (connect ROFS to GND):
For Negative Offset (connect ROFS to VCC):
VDROOP RCOMP
RS
--------------------- IOUT DCR⋅⋅=(EQ. 8)
FIGURE 7. DCR SENSING CONFIGURATION
-
+
ICOMP
DCR
L
INDUCTOR VOUT
COUT
IL1
-
+
VL(s)
DCR
L
INDUCTOR
PHASE1
PHASE2
IL2
RS
RS
RCOMP
CCOMP
ISUM
IREF
ISL6310
-
+
VDROOP
IOUT
DROOP
CSUM
(OPTIONAL)
(EQ. 9)
ROFS 0.5 R1
⋅
VOFFSET
--------------------------
=
(EQ. 10)
ROFS 1.5 R1
⋅
VOFFSET
--------------------------
=
E/A
FB
OFS
VCC
GND
+
-
+
-0.5V
1.5V
GND
ROFS
R1
VDIFF
ISL6310
FIGURE 8. POSITIVE OFFSET OUTPUT VOLT AGE
PROGRAMMING
VREF
VOFS
+
-
IOFS
E/A
FB
OFS
VCC
GND
+
-
+
-0.5V
1.5V
VCC
ROFS
R1
VDIFF
ISL6310
VREF
VOFS
+
-
IOFS
FIGURE 9. NEGATIVE OFFSET OUTPUT VOL TAGE
PROGRAMMING
ISL6310
14 FN9209.4
August 7, 2008
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime
control technique to minimize deadtime, resulting in high
efficiency from the reduced freewheeling time of the lower
MOSFET body-diode conduction, and to prevent the upper and
lower MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
During turn-off of the lower MOSFET, the PHASE volt age is
monitored until it reaches a -0.3V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is released
to rise. An auto-zero comparator is used to correct the rDS(ON)
drop in the phase voltage preventing false detection of the
-0.3V phase level during rDS(ON) conduction period. In the
case of zero current, the UGA TE is released after 35ns delay of
the LGATE dropping below 0.5V. During the phase detection,
the disturbance of LGATE falling transition on the PHASE node
is blanked out to prevent falsely tripping. Once the PHASE is
high, the advanced adaptive shoot-through circuitry monitors
the PHASE and UGATE voltages during a PWM falling edge
and the subsequent UGATE turn-off. If either the UGATE falls
to less than 1.75V above the PHASE or the PHASE falls to less
than +0.8V, the LGATE is released to turn on.
Internal Bootstra p De vi ce
The two integrated driver s feature an internal bootstrap
schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces vo ltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V and its capacitance value can be
chosen from Equation 11:
where QG1 is the amount of gate charge per upper MOSFET
at VGS1 gate-source voltage and NQ1 is the number of
control MOSFETs. Th e ΔVBOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive . Figure 10
shows the boot capacitor ripple voltage as a function of boot
capacitor value and total upper MOSFET gate charge.
Gate Drive Voltage Versatility
The ISL6310 provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together . Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
Initialization
Prior to initialization, pro per condition s must exist on the
ENLL, VCC, PVCC and the REF0 and REF1 pins. When the
conditions are met, the controller begins soft-st art. Once the
output voltage is within th e proper win dow of opera tion, the
controller asserts PGOOD.
Enable and Disa ble
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6310 is
released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper opera tion of all aspects of
the ISL6310 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6310 will not inadvertently turn off unless the bias
voltage drops substantially (see “Electrical
Specifications” on page 5)
CBOOT_CAP QGATE
ΔVBOOT_CAP
--------------------------------------
≥
QGATE QG1 PVCC⋅
VGS1
---------------------------------- NQ1
⋅=(EQ. 11)
50nC
20nC
FIGURE 10. BOOTSTRAP CAP ACIT ANCE vs BOOT RIPPLE
VOLTAGE
ΔVBOOT_CAP (V)
CBOOT_CAP (µF)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0 0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0
QGATE = 100nC
ISL6310
15 FN9209.4
August 7, 2008
2. The voltage on ENLL must be above 0.66V . The EN input
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6310 in shutdown until the voltage at ENLL
rises above 0.66V. The enable comparator has 100mV of
hysteresis to prevent bounce.
3. The driver bias voltage applied at the PVCC pins must
reach the internal power-on reset (POR) rising threshold.
In order for the ISL6310 to begin operation, PVCC is the
only pin that is required to have a voltage applied that
exceeds POR. Hysteresis between the rising and falling
thresholds assure that once enabled, the ISL6310 will not
inadvertently turn off unless the PVCC bias voltage drops
substantially (see “Electrical Specifications” on page 5)
When each of these conditions is true, the controller
immediately begins the soft-start sequence.
Soft-Start
During soft-st ar t, the DAC voltage ramps linearly from zero
to the programmed level. The PWM signals remain in the
high-impedance state until the controller detects that the
ramping DAC level has reached the output-voltage level.
This protects the system against the large, negative inductor
currents that would otherwise occur when starting with a
pre-existing charge on the output as the controller attempted
to regulate to zero volts at the beginning of the soft-start
cycle. The Output soft-start time, tSS, begins with a delay
period equal to 64 switching cycles after the ENLL has
exceeded its POR level, followed by a linear ramp with a rate
determined by the switching period, 1/FSW.
For example, a regulator with 450kHz switching frequency
having REF voltage set to 1.2V has tSS equal to 3.55ms.
A 100mV offset exists on the remote-sense amplifier at the
beginning of soft-start and ramps to zero during the first 640
cycles of soft-start (704 cycles following enable). This
prevents the large inrush current that would otherwise occur
should the output voltage start out with a slight negative
bias.
During the first 640 cycles of soft-start (704 cycles following
enable) the DAC voltage increments the reference in 25mV
steps. The remainder of soft-start sees the DAC ramping
with 12.5mV steps.
The ISL6310 also has the ability to start up into a
pre-charged output as shown in Fi gure 12, without causing
any unnecessary disturbance. The FB pin is monitored
during soft-start, and should it be higher than the equivalent
internal ramping reference voltage, the output drives hold
both MOSFETs off. Once the internal ramping reference
exceeds the FB pin potential, the output drives are enabled,
allowing the output to ramp from the pre-charged level to the
final level dictated by the reference setting. Should the
output be pre-charged to a leve l exceeding the reference
setting, the output drives are enabled at the end of the
soft-st art period, leading to an abrupt correction in the output
voltage down to the “reference set” level.
Fault Monitoring and Protection
The ISL6310 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to the sensitive load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 13
outlines the interaction between the fault mo nitors and the
power good signal.
FIGURE 11. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (ENLL) FUNCTION
-
+
0.66V
EXTERNAL CIRCUITISL6310 INTERNAL CIRCUIT
ENLL
+12V
POR
CIRCUIT 10.7kΩ
1.40kΩ
ENABLE
COMPARATOR
SOFT-START
AND
FAULT LOGIC
VCC
PVCC
tSS 64 DAC+1280⋅
FSW
--------------------------------------------
=(EQ. 12)
FIGURE 12. SOFT -ST ART W A VEFORMS FOR ISL6310-BASED
MULTI-PHASE CONVERTER
ENLL (5V/DIV)
VOUT (0.5V/DIV)
GND>
T1
GND>
T2 T3
OUTPUT PRECHARGED
BELOW DAC LEVEL
OUTPUT PRECHARGED
ABOVE DAC LEVEL
ISL6310
16 FN9209.4
August 7, 2008
Power-Good Signal
The power-good pin (PGOOD) is an open-drain logic output
that transitions high when the converter is operating after
soft-start. PGOOD pulls low during shutdown and releases
high after a successful soft-start. PGOOD transitions low
when an undervoltage, overvoltage, or overcurrent condition
is detected or when the controller is disabled by a reset from
ENLL or POR. If after an undervoltage or overvoltage event
occurs the output returns to within under and overvoltage
limits, PGOOD will return high.
Undervoltage Detection
The undervoltage threshold is set at 82% of th e RE F
voltage. When the output voltage (VSEN-RGND) is below
the undervoltage threshold, PGOOD gets pulled low. No
other action is taken by the controller. PGOOD will return
high if the output voltage rises above 85% of the REF
voltage.
Overvoltage Protection
The ISL6310 constantly monitors the dif ference betwe en the
VSEN and RGND volt ages to detect if an ove rvolt age event
occurs. During soft-st art, while the DAC/REF is ramping up,
the overvoltage trip level is the higher of REF plus 150mV or a
fixed voltage, VOVP. The fixed volt age, V OVP, is 1.67V. Upon
successful soft-st a rt, the overvoltage trip level is only REF
plus 150mV. OVP releases 50mV bel ow it s trip point if it was
“REF plus 150mV” that tripped it, and releases 100mV be low
its trip point if it wa s the fixed volt age, V OVP, that tripped it.
Actions are t aken by the ISL631 0 to protect the load w hen an
overvoltage condition occu rs, until the output voltage falls
back within set limits.
At the inception of an overvoltage event, all LGATE signals
are commanded high, and the PGOOD signal is driven low.
This causes the controller to turn on the lower MOSFETs
and pull the output voltage below a level that might cause
damage to the load. The LGATE outputs remain high until
VDIFF falls to within the overvoltage limits explained above.
The ISL6310 will continue to protect the load in this fashion
as long as the overvoltage condition recurs.
Once an overvoltage condition ends the ISL6310 continues
normal operation and PGOOD returns high.
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6310 is designed to protect the load from any overvoltage
events that may occur. This is accomplished by means of an
internal 10kΩ resistor tied from PHASE to LGATE, which
turns on the lower MOSFET to control the output voltage
until the overvoltage event ceases or the input power supply
cuts off. For complete protection, the low side MOSFET
should have a gate threshold well below the maximum
voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6310 is designed to detect this
and shut down the controller. This event is detected by
monitoring the voltage on the IREF pin, which is a local
version of VOUT sensed at the outputs of the inductors.
If VSEN or RGND become opened, VDIFF falls, causing the
duty cycle to increase and the output voltage on IREF to
increase. If the voltage on IREF exceeds “VDIFF+1V”, the
controller will shut down. Once the voltage on IREF falls
below “VDIFF+1V”, the ISL6310 will restart at the beginning
of soft-star t.
Overcurrent Protection
The ISL6310 detects overcurrent events by comparing the
droop voltage, VDROOP, to the OCSET volt age, VOCSET, as
shown in Figure 13. The droop voltage, set by the external
current sensing circuitry, is proportional to the output current
as shown in Equation 8. A constant 100µA flows through
ROCSET, creating the OCSET voltage. When the droop
voltage exceeds the OCSET voltage, the overcurrent
FIGURE 13. POWER-GOOD AND PROTECTION CIRCUITRY
-
+
DAC + 150mV
VSEN
-
+
0.82 x DAC
OV
UV
PGOOD
SOFT-START, FAULT
AND CONTROL LOGIC
-
+
OC
-
+
ISEN
IREF
ISUM
ICOMP OCSET
ROCSET
+
-
VDROOP
VOCSET
+
-
VOVP
100µA
ISL6310 INTERNAL CIRCUITRY
-
+
RGND
x1
-
+
+1V
V
DIFF
DROOP*
*CONNECT DROOP TO IREF
TO DISABLE THE DROOP FEATURE
ISL6310
17 FN9209.4
August 7, 2008
protection circuitry activates. Since the droop voltage is
proportional to the output current, the overcurrent trip level,
IMAX, can be set by selecting the proper value for ROCSET,
as shown in Equation 13.
Once the output current exceeds the overcurrent trip level,
VDROOP will exceed VOCSET, and a comparator will trigger
the converter to begin overcurrent protection procedures. At
the beginning of overcurrent shutdown, the controller turns
off both upper and lower MOSFETs. The system remains in
this state for a period of 4096 switching cycles. If the
controller is still enabled at the end of this wait period, it will
attempt a soft-start (as shown in Figure 14). If the fault
remains, the trip-retry cycles will continue indefinitely until
either the controller is disabled or the fault is cleared. Note
that the energy delivered during trip-retry cycling is much
less than during full-load operation, so there is no thermal
hazard.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following. In addition to this guide, Intersil provides complete
reference designs that include schematics, bills of materials,
and example board layouts for many applications.
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that dif fer from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board, whether through-hole components are permitted, the
total board space available for power-supply circuitry, and
the maximum amount of load current. Generally speaking,
the most economical solutions are those in which each
phase handles between 25A and 30A. All surface-mount
designs will tend toward th e lower end of this current range.
If through-hole MOSFETs and inductors can be used, higher
per-phase currents are possible. In cases where board
space is the limiting constraint, current can be pushed as
high as 40A per phase, but these designs require heat sinks
and forced air to cool the MOSFETs, inductors and heat-
dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air fl ow.
Lower MOSFET Power Calculation
The calculation for the approximate power loss in the lowe r
MOSFET can be simplified, since virtually all of the loss in
the lower MOSFET is due to current conducted through the
channel resistance (rDS(ON)). In Equation 14, IM is the
maximum continuous output current, IPP is the peak-to-peak
inductor current (see Equation 1), and d is the duty cycle
(VOUT/VIN).
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor curre nt is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at IM, VD(ON), the switching
frequency, FSW, and the length of dead times, td1 and td2, at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of PLOW,1 and PLOW,2.
Upper MOSFET Power Calculation
In addition to rDS(ON) losses, a large portion of the uppe r
MOSFET losses are due to currents conducted across the
input voltage (VIN) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower MOSFET body-diode reverse-
recovery charge, Qrr, and the upper MOSFET rDS(ON)
conduction loss.
ROCSET IMAX RCOMP DCR⋅⋅
100μAR
S
⋅
----------------------------------------------------------
=(EQ. 13)
0A
0V
OUTPUT CURRENT
FIGURE 14. OVERCURRENT BEHA VIOR IN HICCUP MODE
OUTPUT VOLTAGE
PLOW 1,rDS ON()
·IM
N
------
⎝⎠
⎜⎟
⎛⎞
21d–()⋅ILPP,21d–()⋅
12
-------------------------------------+⋅=(EQ. 14)
PLOW 2,VDON()
FSW IM
N
------IPP
2
---------+
⎝⎠
⎛⎞
td1
⋅IM
N
------IPP
2
---------
–
⎝⎠
⎛⎞
td2
⋅+⋅⋅=
(EQ. 15)
ISL6310
18 FN9209.4
August 7, 2008
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current unti l the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 16,
the required time for this commutation is t1 and the
approximated associated power loss is PUP,1.
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t2. In Equation 17, the
approximate power loss is PUP,2.
A third component involves the lower MOSFET reverse
recovery charge, Qrr. Since the inductor current has fully
commutated to the upper MOSFET before the lower
MOSFET body diode can recover all of Qrr, it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is PUP,3.
Finally, the resistive part of the upper MOSFET is given in
Equation 19 as PUP,4.
The total power dissipated by the upper MOSFET at full load
can now be appr oximated as the summation of the results
from Equations 16, 17, 18 and 19. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a to tal of two dri vers
in the controller package, the total power dissipated by both
drivers must be less than the maximum allowable power
dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 5x5 QFN package is approximately 4W at
room temperature. See “Layout Considerations” on page 24.
paragraph for thermal transfer improvement suggestions.
When designing the ISL6310 into an application, it is
recommended that the following calculation is used to
ensure safe operatio n at the desi re d frequency for the
selected MOSFETs. The total gate drive power losses,
PQg_TOT, due to the gate charge of MOSFETs and the
integrated driver’s internal circuitry and their corresponding
average driver current can be estimated with Equations 20
and 21, respectively.
In Equations 20 and 21, PQg_Q1 is the total upper gate drive
power loss and PQg_Q2 is the total lower gate drive power
loss; the gate charge (QG1 and QG2) is defined at th e
particular gate to source drive volt a ge PVCC in the
corresponding MOSFET data sheet; IQ is the driver total
quiescent current with no load at both drive output s; NQ1 and
NQ2 are the number of upper and low er MOSFETs per phase,
respectively; NPHASE is the number of active phases. The
IQ*VCC product is the qui escent power of th e control ler
without cap acitive load and is typi cally 75mW at 300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, PDR_UP, the lower drive path resistance,
PDR_LOW, and in the boot strap diode, PBOOT. The rest of
the power will be dissipated by the external gate resistors
(RG1 and RG2) and the internal gate resistors (RGI1 and
RGI2) of the MOSFETs. Figures 15 and 16 sho w the typical
upper and lower gate drives turn-on transition path. The total
power dissipation in the controller itself, PDR, can be roughly
estimated as:
PUP1,VIN IM
N
------IPP
2
---------+
⎝⎠
⎛⎞
t1
2
----
⎝⎠
⎜⎟
⎛⎞FSW
⋅⋅⋅≈(EQ. 16)
PUP 2,VIN IM
N
------IPP
2
---------
–
⎝⎠
⎜⎟
⎛⎞
t2
2
----
⎝⎠
⎜⎟
⎛⎞
FSW
⋅⋅⋅≈(EQ. 17)
PUP3,VIN Qrr FSW
⋅⋅=(EQ. 18)
PUP4,rDS ON()
dIM
N
------
⎝⎠
⎜⎟
⎛⎞
2IPP
2
12
----------
+⋅⋅≈(EQ. 19)
PQg_TOT PQg_Q1 PQg_Q2 IQVCC⋅++=(EQ. 20)
PQg_Q1 3
2
---QG1 PVCC FSW NQ1 NPHASE
⋅⋅ ⋅⋅⋅=
PQg_Q2 QG2 PVCC FSW NQ2 NPHASE
⋅⋅⋅⋅=
IDR 3
2
---QG1 N⋅Q1
⋅QG2 NQ2
⋅+
⎝⎠
⎛⎞
NPHASE FSW IQ
+⋅⋅=(EQ. 21)
PDR PDR_UP PDR_LOW PBOOT IQVCC•()+++=
(EQ. 22)
PDR_UP RHI1
RHI1 REXT1
+
-------------------------------------- RLO1
RLO1 REXT1
+
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
PQg_Q1
3
---------------------
⋅=
PDR_LOW RHI2
RHI2 REXT2
+
-------------------------------------- RLO2
RLO2 REXT2
+
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
PQg_Q2
2
---------------------
⋅=
REXT1 RG1 RGI1
NQ1
-------------
+= REXT2 RG2 RGI2
NQ2
-------------
+=
PBOOT PQg_Q1
3
---------------------
=
ISL6310
19 FN9209.4
August 7, 2008
Current Balancing Component Selection
The ISL6310 senses the channel load current by sampling
the voltage across the lower MOSFET rDS(ON), as shown in
Figure 17. The ISEN pins are denoted ISEN1, and ISEN2.
The resistors con nected between these pins and the
respective phase nodes determine the gains in the channel
current balance loop.
Select values for these resistors based on the room
temperature rDS(ON) of the lower MOSFETs; the full-load
operating current, IFL; and the number of phases, N using
Equation 23.
In certa in circ umstances, it may be necessary to adjust the
value of one or more ISEN re sistors. When the components of
one or more channels are in hibited from effectivel y dissipating
their heat so that the affecte d ch annels run hotter than
desired, choose new, smaller values of RISEN for the affected
phases (see the section entitled “Channel Curren t Balance ”
on page 10). Choose RISEN,2 in proportion to the desired
decrease in temperature rise in order to cause propo rtionally
less current to flow in the hotter phase.
In Equation 24, make su re that ΔT2 is th e desired temperature
rise above the ambie nt temperature, and ΔT1 is the measured
temperature rise above the ambient tempe rature. While a
single adjustment according to Equation 24 is u sually
sufficient, it may occasionally be necessa ry to adju st RISEN
two or more times to achieve opti ma l thermal bala nce
between all channels.
Load Line Regulation Component Selection (DCR
Current Sensing)
For accurate load line regulation, the ISL6310 senses the
total output current by detecting the voltage across the
output inductor DCR of each channel (As described in “Load
Line (Droop) Regulatio n” on page 12). As Figure 18
illustrates, an R-C network is required to accurately sense
the inductor DCR voltage and convert this information into a
“droop” voltage, which is proportional to the total output
current.
Choosing the components for this current sense network is a
two step process. First, RCOMP and CCOMP must be
chosen so that the time constant of this RCOMP-CCOMP
network matches the time constant of the inductor L/DCR.
Then the resistor RS must be chosen to set the current
sense network gain, obtaining the desired full load droop
voltage. Follow the steps below to choose the component
values for this R-C network.
1. Choose an arbitrary value for CCOMP. The recommended
value is 0.01µF.
2. Plug the inductor L and DCR component values, and the
values for CCOMP chosen in Step 1, into Equation 25 to
calculate the value for RCOMP.
3. Use the new value for RCOMP obt ained from Equation 25,
as well as the desired full load current, IFL, full load droop
voltage, VDROOP, and inductor DCR in E qu a ti on 26 to
calculate the value for RS.
FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Q1
D
S
G
RGI1
RG1
BOOT
RHI1 CDS
CGS
CGD
RLO1
PHASE
PVCC
UGATE
PVCC
Q2
D
S
G
RGI2RG2
RHI2 CDS
CGS
CGD
RLO2
LGATE
FIGURE 17. ISL6310 INTERNAL AND EXTERNAL CURRENT-
SENSING CIRCUITRY
ISEN(n)
RISEN
VIN
CHANNEL N
UPPER MOSFET
CHANNEL N
LOWER MOSFET
-
+
ILxrDS ON()
IL
ISL6310
RISEN rDS ON()
50 10 6
–
⋅
----------------------- IFL
N
--------
⋅=(EQ. 23)
RISEN 2,RISEN
ΔT2
ΔT1
----------
⋅=(EQ. 24)
RCOMP L
DCR CCOMP
⋅
---------------------------------------
=(EQ. 25)
RSIFL
VDROOP
-------------------------RCOMP DCR⋅⋅=(EQ. 26)
ISL6310
20 FN9209.4
August 7, 2008
Due to errors in the inductance or DCR it may be necessary
to adjust the va lue of RCOMP to match the time constants
correctly. The effects of time constant mismatch can be seen
in the form of droop overshoot or undershoot during the
initial load transient spike, as shown in Figure 19. Follow the
steps below to ensure the R-C and inductor L/DCR time
constants are matched accurately.
1. Capture a tra n s i en t event with the oscillo sco pe set to
about L/DCR/2 (sec/div). For example, with L = 1µH and
DCR = 1mΩ, set the oscilloscope to 500µs/div.
2. Record ΔV1 and ΔV2 as shown in Figure 19.
3. Select a new value, RCOMP,2, for the time constant
resistor based on the original value, RCOMP,1, using
Equation 27.
4. Replace RCOMP with the new value and check to see that
the error is corrected. Repeat the procedure if necessary .
After choosing a new value for RCOMP, it will most likely be
necessary to adjust the value of RS to obtain the desired full
load droop voltage. Use Equation 26 to obtain the new value
for RS.
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in “Load Line (Droop) Regulation ” on page 12,
there are two distinct methods for achieving these goals.
Compensating the Load Line Regulated Converter
The load-line regulated co nverter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R2 and C1
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. T reating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
The feedback resistor, R1, has already been chosen as
outlined in “Load Line (Droop) Regulation” on page 12
Select a target bandwidth for the compensated system, F0.
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
FIGURE 18. DCR SENSING CONFIGURATION
-
+
ICOMP
DCR
L
INDUCTOR VOUT
COUT
IL1
-
+
VL(s)
DCR
L
INDUCTOR
PHASE1
PHASE2
IL2
RS
RS
RCOMP
CCOMP
ISUM
IREF
ISL6310
-
+
VDROOP
IOUT
DROOP
RCOMP 2,RCOMP 1,
V1
Δ
V2
Δ
----------
⋅=(EQ. 27)
FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR
ΔV1
VOUT
ITRAN
ΔV2
ΔI
FIGURE 20. COMPENSA TION CONFIGURA TION FOR
LOAD-LINE REGULATED ISL6310 CIRCUIT
ISL6310
COMP
C1
R2
R1
FB
VDIFF
C2 (OPTIONAL)
ISL6310
21 FN9209.4
August 7, 2008
per-channel switching freque ncy. The values of the
compensation components depend on the relationships of f0
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
In Equation 28, L is the per-channel filter inductance divided by
the number of active channels; C is the sum total of all output
capacitors; ESR is the equivalent series resistance of the bulk
output filter capacitance; and VOSC is the peak-to-peak
sawtooth signal amplitude as described in the “Electrical
Specifications” on page 5.
Once selected, the compensation values in Equation 28
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R2. Slowly increase the
value of R2 while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C1 will not need adjustment. Keep the value of C1 from
Equation 28 unless some perfo r mance issue is noted.
The optional capacitor C2, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 20). Keep
a position available for C2, and be prepared to install a high
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
Compensating the Converter operating without
Load-Line Regulation
The ISL6310 multi-phase converter operating without load
line regulation behaves in a similar manner to a voltage
mode controller. This section highlights the design
consideration for a voltage-mode controller requiring external
compensation. To address a broad range of applications, a
type-3 feedback network is recommended (see Figure 21).
Figure 22 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable, with a
small number of adjustments, to the multi-phase ISL6310
circuit. The output voltage (VOUT) is regulated to the
reference voltage, VREF, level. The error amplifie r output
(COMP pin voltage) is compared with the oscillator (OSC)
modified saw-tooth wave to provide a pulse-width modulated
wave with an amplitude of VIN at the PHASE node. The
PWM wave is smoothed by the output filter (L and C). The
output filter capacitor bank’s equivalent series resistance is
represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of VOUT/VCOMP. This function is dominated by a
DC gain, given by dMAXVIN/VOSC, and shaped by the
output filter , with a double pole break frequency at FLC and a
zero at FCE. For the purpose of this analysis, L and DCR
represent the individual channel inductance and its DCR
divided by 2 (equivalent parallel value of the two output
inductors), while C and ESR represents the total output
capacitance and its equivalen t serie s resistance.
The compensation network consist s o f the error amplifier
(internal to the ISL6310) and the external R1 to R3, C1 to C3
components. The goal of the comp ensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F0; typicall y 0.1 to 0.3 of FSW) and adequ ate
phase margin (better than 45°). Phase margin is the
difference betwe en the closed loop phase at F0dB and 180°.
The equations that follow relate the compensation netwo rk’s
poles, zeros and gain to the component s (R1, R2, R3, C1, C2,
1
2πLC⋅⋅
--------------------------- F 0
>
R2R12πF0VOSC LC⋅⋅⋅ ⋅
0.66 VIN
⋅
------------------------------------------------------------
⋅=
C10.66 VIN
⋅
2πVOSC R1f0
⋅⋅⋅
-------------------------------------------------=
Case 1:
1
2πLC⋅⋅
--------------------------- F01
2πCESR⋅⋅
---------------------------------<≤
R2R1VOSC 2π()
2F0
2LC⋅⋅⋅⋅
0.66 VIN
⋅
----------------------------------------------------------------
⋅=
C10.66 VIN
⋅
2π()
2F0
2VOSC R1LC⋅⋅⋅ ⋅⋅
--------------------------------------------------------------------------------=
Case 2:
(EQ. 28)
F01
2πC ESR⋅⋅
--------------------------------->
R2R12πF0VOSC L⋅⋅ ⋅
0.66 VIN ESR⋅⋅
-----------------------------------------------
⋅=
C20.66 VIN ESR C⋅⋅ ⋅
2πVOSC R1F0L⋅⋅⋅⋅
---------------------------------------------------------------=
Case 3:
FIGURE 21. COMPENSA TION CONFIGURA TION FOR
NON-LOAD-LINE REGULATED ISL6310 CIRCUIT
ISL6310
COMP
C1
R2
R1
FB
VDIFF
C2
R3
C3
FLC 1
2πLC⋅⋅
---------------------------
=FCE 1
2πC ESR⋅⋅
---------------------------------
=(EQ. 29)
ISL6310
22 FN9209.4
August 7, 2008
and C3) in Figures 20 an d 21. Use the following gu idelines for
locating the poles and ze ros of the compensation network:
1. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate
value for R2 for desired converter bandwidth (F 0). If
setting the output voltage to be equal to the reference set
voltage as shown in Figure 22, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 6), in order
to compensate for the attenuation introduced by the
resistor divider, the obtained R2 value needs be
multiplied by a factor of (RP1 + RS1)/RP1. The remainder
of the calculations remain unchanged, as long as the
compensated R2 value is used.
2. Calculate C1 such that FZ1 is placed at a fraction of the FLC,
at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio FCE/FLC, the lower the FZ1
frequency (to maximize phase boost at FLC).
3. Calculate C2 such that FP1 is placed at FCE.
4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3
such that FP2 is placed belo w FSW (typically, 0.5 to 1.0
times FSW). FSW represents the per-channel switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of FP2 lower in frequency
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizin g result ant duty cycle jitter.
It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (GMOD), feedback
compensation (GFB) and closed-loop response (GCL):
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 23 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter ,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at FP2 against the capabilities of the error
amplifier . The closed loop gain, GCL, is constructed on the
log-log graph of Figure 23 by adding the modulator gain,
GMOD (in dB), to the feedback compensation gain, GFB (in
R2VOSC R1F0
⋅⋅
dMAX VIN FLC
⋅⋅
---------------------------------------------
=(EQ. 30)
FIGURE 22. VOL T AGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
-
+
E/A
VREF
COMP C1
R2
R1
FB
C2
R3C3
L
C
VIN
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
OSCILLATOR
ESR
EXTERNAL CIRCUITISL6310
VOUT
VOSC
DCR
UGATE
PHASE
LGATE
-
+
VDIFF
VSEN
RGND
C11
2πR20.5 FLC
⋅⋅ ⋅
-----------------------------------------------
=(EQ. 31)
C2C1
2πR2C1FCE 1–⋅⋅⋅
--------------------------------------------------------
=(EQ. 32)
R3R1
FSW
FLC
------------ 1–
----------------------
=
C31
2πR30.7 FSW
⋅⋅ ⋅
-------------------------------------------------
=
(EQ. 33)
GMOD f() dMAX VIN
⋅
VOSC
------------------------------1sf() ESR C⋅⋅+
1sf() ESR DCR+()C⋅⋅s2f() LC⋅⋅++
-----------------------------------------------------------------------------------------------------------
⋅=
GFB f() 1sf() R2C1
⋅⋅+
sf() R1C1C2
+()⋅⋅
---------------------------------------------------- ⋅=
1sf() R1R3
+()C3
⋅⋅+
1sf() R3C3
⋅⋅+()1sf() R2C1C2
⋅
C1C2
+
---------------------
⎝⎠
⎜⎟
⎛⎞
⋅⋅+
⎝⎠
⎜⎟
⎛⎞
⋅
-------------------------------------------------------------------------------------------------------------------------
GCL f() GMOD f() GFB f()⋅=where s f(),2πfj⋅⋅=
(EQ. 34)
FZ1 1
2πR2C1
⋅⋅
-------------------------------
=(EQ. 35)
FZ2 1
2πR1R3
+()C3
⋅⋅
-------------------------------------------------
=(EQ. 36)
FP1 1
2πR2C1C2
⋅
C1C2
+
---------------------
⋅⋅
---------------------------------------------
=(EQ. 37)
FP2 1
2πR3C3
⋅⋅
-------------------------------
=(EQ. 38)
ISL6310
23 FN9209.4
August 7, 2008
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variation s when determining
phase margin. The mathematical mo del presented makes a
number of approximations and is genera lly not accurate at
frequencies approachin g or exceedi ng half the switching
frequency. Whe n designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the per-channel switching frequency, FSW.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter respons ib l e fo r smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until th e regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter limits the system
transient response. The output capacitors must supply or
sink load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output cap acitor bank is usually
the most costly (and often the largest) part of the circuit.
Output filter design begins with mini mizing the cost of this pa rt
of the circuit. The critical load parameters i n choosi ng the
output cap acitors are the maximu m size of the load step, ΔI,
the load-current slew rate, di/d t, an d the ma ximum allowab le
output-volt age deviatio n under transient loa ding , ΔVMAX.
Capacitors are characteri zed according to their cap aci ta nce,
ESR, and ESL (equivalent seri es in duct ance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulato r
response, the output voltage initially deviates by an amount
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔVMAX.
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see “Interleaving” on
page 9 and Equ ation 2), a voltage develops across the bulk
capacitor ESR equal to IC,PP(ESR). Thus, once the output
capacitors are selected, the maximum allowable ripple
voltage, VPP(MAX), determines the lower limit on the
inductance.
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔVMAX. This places an upper limi t on inductance.
Equation 41 gives the upper limit on L for the cases when
the trailing edge of the current tran sient causes a greater
output-voltage deviation than the lea ding edge. Equation 42
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities shoul d be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
0
FP1
FZ2
OPEN LOOP E/A GAIN
FZ1 FP2
FLC FCE
COMPENSATION GAIN
GAIN
FREQUENCY
MODULATOR GAIN
FIGURE 23. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
CLOSED LOOP GAIN
20 R2
R1
--------
⎝⎠
⎛⎞
log
LOG
LOG
F0
GMOD
GFB
GCL
20 dMAX V
⋅IN
VOSC
---------------------------------log
ΔV ESL()
di
dt
-----
⋅ESR()ΔI⋅+≈(EQ. 39)
L ESR()
VIN NV⋅OUT
–
⎝⎠
⎛⎞
VOUT
⋅
FSW VIN VPP MAX()
⋅⋅
--------------------------------------------------------------------≥(EQ. 40)
L2NCV
O
⋅⋅⋅
ΔI
()
2
--------------------------------- ΔVMAX ΔIESR⋅()–⋅≤ (EQ. 41)
L1.25
()
NC⋅⋅
ΔI
()
2
----------------------------------ΔVMAX ΔI ESR⋅()–VIN VO
–
⎝⎠
⎛⎞
⋅⋅≤(EQ. 42)
ISL6310
24 FN9209.4
August 7, 2008
Switching Frequency
There are a number of variables to consider when choosi ng
the switching frequency , as there are considerable effects on
the upper MOSFET loss calculation. These effects are
outlined in “MOSFETs” on page 17, and they establish the
upper limit for the switching frequency. The lower limit is
established by the requirement for fast transient response
and small output-voltage ripple as outlined in “Output Filter
Design” on page 23. Choose the lowest switching frequency
that allows the regulator to meet the transient-respo nse
requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, RFS. Figure 24 and Equati on 43
are provided to assist in selecting the correct value for RFS.
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the ac component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
For a two-phase design, use Figure 25 to determine the
input-capacitor RMS current requirement set by the duty
cycle, maximum sustained output current (IO), and the ratio
of the peak-to-peak inductor current (IL,PP) to IO. Select a
bulk capacitor with a ripple current rating which will minimize
the total number of input capacitors required to support the
RMS current calculated. The voltage rating of the capacitors
should also be at least 1.25 times greater than the maximum
input voltage. Figure 26 provides the same input RMS
current information for single-phase designs. Use the same
approach for selecting the bulk capacitor type and number.
Low ESL, high-frequency cerami c cap acitors are n eeded in
addition to the input bulk cap a citors to sup press lead ing and
falling edge volt age spikes. The sp ikes result from the high
current slew rate produced by the upper MOSFET turn on and
off. Place them as close as possible to each upper MOSFET
drain to minimize board p arasitics and maximize suppressio n.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate no ise into the circuit
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter . Consider, as an example, the turnoff
transition of the upper PWM MOSFET. Prior to turnoff, the
upper MOSFET was carrying channel current. During the
turnoff, current stops flowing in the upper MOSFET and is
picked up by the lower MOSFET. Any inductance in the
switched current path generates a large voltage spike during
the switching interval. Careful component selection, tight
RFS 10 10.61 1.035 FSW
()log⋅–
[]
=(EQ. 43)
FIGURE 24. RFS vs SWITCHING FREQUENCY
100k 200k 500k 1M 2M
SWITCHING FREQUENCY (Hz)
RFS VALUE (kΩ)
10
20
50
100
200 FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS
CURRENT FOR 2-PHASE CONVERTER
0.3
0.1
0
0.2
INPUT-CAPACITOR CURRENT (IRMS/IO)
00.4 1.00.2 0.6 0.8
DUTY CYCLE (VIN/VO)
IL,PP = 0
IL,PP = 0.5 IO
IL,PP = 0.75 IO
FIGURE 26. NORMALIZED INPUT-CAP ACITOR RMS
CURRENT FOR SINGL E-PHASE CONVERTER
00.4 1.00.2 0.6 0.8
DUTY CYCLE (VIN/VO)
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.6
0.2
0
0.4
IL,PP = 0
IL,PP = 0.5 IO
IL,PP = 0.75 IO
ISL6310
25 FN9209.4
August 7, 2008
layout of the critical compone nts, and short, wide circuit
traces minimize the magnitude of voltage spikes.
There are two sets of critical componen ts in a DC/DC
converter using a ISL6310 controller. The power-
components are the most critical because they switch large
amounts of energy. Next are small signal components that
connect to sensitive nodes or supply critical bypassing
current and signal coupling.
It is important to have a symmet rical layou t, preferably with
the controller equidist antly located from the two power trains it
controls. Equally important are the gate drive lines (UGATE,
LGATE, PHASE): since they drive the power train MOSFETs
using short, high current pulses, it is importan t to size them as
large and as short as possibl e to reduce their overall
impedance and induct a nce. Extra care shou ld be given to th e
LGATE traces in particular since keeping the impedance and
inductance of these traces helps to significantly reduce the
possibility of shoot-through . Equidist ant placement of the
controller to the two power trains also help s keeping these
traces equally short (equal impedances, resu lting in simil ar
driving of both sets of MOSFETs).
The power components should be placed first. Locate the input
capacitors close to the power switches. Minimize the length of
the connections between the input capacitors, CIN, and the
power switches. Locate the output inductors and output
capacitors between the MOSFETs and the load. Locate the
high-frequency decoupling capacitors (ceramic) as close as
practicable to the decoupling target, making use of the shortest
connection paths to any internal planes, such as vias to GND
immediately next, or even onto the capacitor solder pad.
The critical small components include the bypass capacitors
for VCC and PVCC. Locate the bypass capacitors, CBP,
close to the device. It is especially important to locate the
components associated with the feedback circuit close to
their respective controller pins, since they belong to a high
impedance circuit loop, sensitive to EMI pick-up. It is also
important to place current sense components close to their
respective pins on the ISL 6310, including the RISEN
resistors, RS, RCOMP, CCOMP. For prop er current sharing
route two separate symmetrical as possible traces from the
corresponding phase node for each RISEN.
A multi-layer printed circuit board is recommended. Figure 2 7
shows the connections of the critical component s fo r the
converter . N ote that capacitors CxxIN and CxxOUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually the one underne ath the co mponent side of the
board, for a ground plane and make all criti cal component
ground connections with vias to th is l ayer. Dedicate another
solid layer as a power plane and break this p lane into sma ller
islands of common volt age level s. Keep the met al runs from
the PHASE terminal to inductor LOUT short. The power pla ne
should support the input power and output power nodes. Use
copper filled polygons on the top and bo tto m circuit layers for
the phase nodes. Use the remainin g pri nted circuit layers fo r
small signal wiring. The wiring traces from the IC to the
MOSFETs’ gates and sources should be sized to carry at least
one ampere of current (0.0 2” to 0.05”).
ISL6310
26
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN9209.4
August 7, 2008
VIA CONNECTION TO GROUND PLANE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
KEY
FIGURE 27. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
HEAVY TRACE ON CIRCUIT PLANE LAYER
+12V
+12V
LOAD
C
BOOT1
R
ISEN1
R
ISEN2
C
BOOT2
C
BIN1
(C
HFOUT
)C
BOUT
C
HF1
C
BIN2
LOCATE CLOSE TO IC
LOCATE NEAR LOAD;
(MINIMIZE CONNECTION PATH)
LOCATE NEAR SWITCHING TRANSISTORS;
(MINIMIZE CONNECTION PATH)
(MINIMIZE CONNECTION PATH)
C
HF2
C
COMP
R
COMP
R
S
R
S
R
OCSET
PGOOD
VDIFF FB COMP
VCC ISEN1
ISL6310
REF1
FS
OFST
REF
PHASE1
UGATE1
BOOT1
LGATE1
ISEN2
PHASE2
UGATE2
BOOT2
LGATE2
ISUM
ICOMP
IREF
VSEN
RGND
OCSET
REF0
+5V
PVCC
ENLL
+12V GND
OVP
2PH
DAC
DROOP
C
1
R
2
C
2
R
1
C
HF0
R
OFST
R
REF
C
REF
C
SUM
to PV C C
C
HF01
L
OUT1
L
OUT2
R
FS
ISL6310
27 FN9209.4
August 7, 2008
ISL6310
Package Outline Drawing
L32.5x5
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 02/07
located within the zone indicated. Th e pin #1 indentifier may be
Unless otherwise specified, tol erance : Decim al ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optio nal, but must be
between 0.15mm an d 0.3 0m m from the te rminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994 .
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
5.00 A
5.00
B
INDEX AREA
PIN 1
6
(4X) 0.15
32X 0.40 ± 0.10 4
A
32X 0.23
M0.10 C B
16 9
4X
0.50
28X
3.5
6
PIN #1 INDEX AREA
3 .10 ± 0 . 15
0 . 90 ± 0.1
BASE PLANE
SEE DETAIL "X"
SEATING PLANE
0.10 C
C
0.08 C
0 . 2 REF
C
0 . 05 MAX.
0 . 00 MIN.
5
( 3. 10 )
( 4. 80 TYP ) ( 28X 0 . 5 )
(32X 0 . 23 )
( 32X 0 . 60)
+ 0.07
- 0.05
17
25
24
8
1
32
