DATASHEET
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER 5V41235
IDT®
2 OUTPUT PCIE GEN1/2/3 SYNTHES IZER 1
5V41235 MAY 5, 2017
Recommended Applications
2 Output synthesizer for PCIe Gen1/2/3 and Ethernet
General Description
The 5V41235 is a PCIe Gen2/3 compliant spread spectrum
capable clock generator. The device has 2 differential
HCSL outputs and can be used in communication or
embedded systems to substantially reduce
electro-magnetic interference (EMI). The spread amount
and output frequency are selectable via select pins. The
5V41235 can also supply 25 MHz, 125 MHz and 200 MHz
outputs for applications such as Ethernet.
Output Features
•2 - 0.7V current mode differential HCSL output pairs
Features/Benefits
•16-pin TSSOP and QFN packages; small board footprint
•Spread-spectrum capable; reduces EMI
•Outputs can be terminated to LVDS; can drive a wider
variety of devices
•TSSOP package: 25MHz, 100MHz, 125MHz and
200MHz output frequencies.
•QFN package: 100MHz and 200MHz output frequencies.
•OE control pin; greater system power management
•Spread% and frequency pin selection; no software
required to configure device
•Industrial temperature range available; supports
demanding embedded applications
Key Specifications
•Cycle-to-cycle jitter < 100 ps
•Output-to-output skew < 50 ps
•PCIe Gen2 phase jitter < 3.0ps RMS
•PCIe Gen3 phase jitter <1.0ps RMS
Block Diagram
Phase Lock Loop
Clock
Buffer/
Crystal
Oscillator
VDD
GND
X1/ICLK
X2
25 MHz
crystal or clock
Control
Logic
SS1:SS0 2
S1:S0 2
CLK0
CLK0
Rr(IREF)
CLK1
CLK1
2
2
OE
Optional tuning crystal
capacitors
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Pin Assignments
Output Select Table 1 (MHz) - TSSOP Only
Spread Selection Table 2 - TSSOP Only
Output/Spread Select Table 3 - QFN Only
1
2
3
X2
4
S1
5
6
CLK0
7
8
CLK0
GNDODA
VDDXD
OE
SS0
16
X1/ICLK
SS1
CLK1
VDDODA
15
14
13
12
11
10
9
16-pin (173 mil) TSSOP
GNDXD
S0
IREF
CLK1
S0
VDDXD
CLK0
CLK0#
16 15 14 13
S1 1 12 GNDODA
SS0 2 11 VDDODA
X1/CLK 3 10 CLK1
X2 4 9 CLK1#
5678
OE
GNDXD
SS1
IREF
16-pi n QF N
5V41235
S1 S0 CLK(1:0), CLK(1:0)
00 25M
0 1 100M
1 0 125M
1 1 200M
SS1 SS0 Spread%
00 No Spread
0 1 Down -0.5
1 0 Down -0.75
11 No Spread
S1 S0 SS1 SS0 Output Spread%
0000100MHz -0.5
0001200MHz -0.5
0 0 1 0 100MHz No spread
0011 Reserved
0100100MHz -1
0101200MHz -1
0110 Reserved
0111 Reserved
1000100MHz -1.5
1001200MHz -1.5
1010 Reserved
1011 Reserved
1100 Reserved
1 1 0 1 200MHz No spread
1110 Reserved
1111 Reserved
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Pin Descriptions
QFN Pin
Number
TSSOP
Pin
Number
Pin
Name
Pin
Type
Pin Description
16 1 S0 Input Select pin 0. See Table1. Internal pull-up resistor.
1 2 S1 Input Select pin 1. See Table 1. Internal pull-up resistor.
2 3 SS0 Input Spread Select pin 0. See Table 2. Internal pull-up resistor.
3 4 X1/ICLK Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
4 5 X2 Output Crystal connection. Leave unconnected for clock input.
5 6 OE Input Output enable. Tri-states outputs and device is not shut down. Internal
pull-up resistor.
6 7 GNDXD Power Connect to ground.
7 8 SS1 Input Spread Select pin 1. See Table 2. Internal pull-up resistor.
8 9 IREF Output Precision resistor attached to this pin is connected to the internal current
reference.
9 10 CLK1 Output HCSL complementary clock output 1.
10 11 CLK1 Output HCSL true clock output 1.
11 12 VDDODA Power Connect to voltage supply +3.3 V for output driver and analog circuits
12 13 GNDODA Power Connect to ground.
13 14 CLK0 Output HCSL complementary clock output 0.
14 15 CLK0 Output HCSL true clock output 0.
15 16 VDDXD Power Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.
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Applications Information
External Components
A minimum number of external components are required for
proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01F should be connected
between each VDD pin and the ground plane, as close to
the VDD pin as possible. Do not share ground vias between
components. Route power from power source through the
capacitor pad and then into ICS pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal
should be used. This crystal must have less than 300 ppm
of error across temperature in order for the 5V41235 to meet
PCI Express specifications.
Crystal Capacitors
Crystal capacitors are connected from pins X1 to ground
and X2 to ground to optimize the accuracy of the output
frequency.
CL= Crystal’s load capacitance in pF
Crystal Capacitors (pF) = (CL- 7) * 2
For example, for a crystal with a 8pF load cap, each external
crystal cap would be 2pF [(8-7)*2=2].
Current Source (Iref) Reference Resistor - RR
If board target trace impedance (Z) is 50, then RR = 475
(1%), providing IREF of 2.32 mA. The output current (IOH) is
equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the 5V41235
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines section.
The 5V41235 can also be configured for LVDS compatible
voltage levels. See the LVDS Compatible Layout
Guidelines section.
Output Structures
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the 5V41235.This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
RR 475
6*IREF
=2.3 mA
IREF
See Output Termination
Sections - Pages 3 ~ 5
5V41235
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Layout Guidelines
Common Recommendations for Differential Routing Dimension or Value Unit Fi gure
L1 length, route as non-coupled 50ohm trace 0.5 max i nch 1
L2 length, route as non-coupled 50ohm trace 0.2 max i nch 1
L3 length, route as non-coupled 50ohm trace 0.2 max i nch 1
Rs 33 ohm 1
Rt 49.9 ohm 1
Down Device Different ial Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max i nch 1
L4 length, route as coupled striplin e 100ohm differential trace 1.8 min to 14.4 max inch 1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max i nch 2
L4 length, route as coupled striplin e 100ohm differential trace 0.225 min to 12.6 max i nch 2
SRC Refere nc e Clock
HCSL Output Buffer
L1
L1' Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Down Device
REF_CLK Input
Figure 1: Down Device Routing
HCSL Output Buffer
L1
L1' Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt PCI Express
Add-in Board
REF_CLK Input
Figure 2: PCI Express Connector Routing
5V41235
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HCSL Output Buffer
L1
L1' R1b
L2
L2'
R1a
L4'
L4
L3
R2a R2b Down Device
REF_CLK Input
Figure 3
L3'
R3 R4
Component Value Note
R5a, R5b 8.2 K 5%
R6a, R6b 1K 5%
Cc 0.1 µF
Vcm 0.350 volts
Cable Connected AC Coupled Application (figure 4)
PCIe Device
REF_CLK Input
Figure 4
R5a
L4'
L4
3.3 Volts
R5b
R6a R6b
Cc
Cc
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Typical PCI-Express (HCSL) Waveform
Typical LVDS Waveform
0.175 V
0.525 V 0.175 V
0.525 V
tOR tOF
500 ps 500 ps
700 mV
0
1150 mV
1250 mV
tOR tOF
500 ps 500 ps
1325 mV
1000 mV
1150 mV
1250 mV
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Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 5V41235. These ratings are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product
reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85C
1. Single edge is monotonic when transitioning through region.
2. Inputs with pull-ups/-downs are not included.
Item Rating
Supply Voltage, VDDXD, VDDODA 4.6 V
All Inputs and Outputs -0.5 V to VDD+0.5 V
Ambient Operating Temperature (commercial) 0 to +70C
Ambient Operating Temperature (industrial) -40 to +85C
Storage Temperature -65 to +150C
Junction Temperature 125C
Soldering Temperature 260C
ESD Protection (Input) 2000 V min. (HBM)
Parameter Symbol Conditions Min. Typ. Max. Units
Supply Voltage V 3.135 3.3 3.465 V
Input High Voltage1VIH S0, S1, OE, ICLK, SS0, SS1 2.2 VDD +0.3 V
Input Low Voltage1VIL S0, S1, OE, ICLK, SS0, SS1 VSS-0.3 0.8 V
Input Leakage Current2IIL 0 < Vin < VDD -5 5 A
Operating Supply Current
@100 MHz
IDD RS=33RP=50, CL=2 pF 63 85 mA
IDDOE OE =Low 42 50 mA
Input Capacitance CIN Input pin capacitance 7 pF
Output Capacitance COUT Output pin capacitance 6 pF
X1, X2 Capacitance CINX 5pF
Pin Inductance LPIN 5nH
Output Impedance ZOCLK outputs 3.0 k
Pull-up Resistor RPU S0, S1, OE, SS0, SS1 100 k
5V41235
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
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AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1
Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85C
Note 1: Test setup is RS=33RP=50 with CL=2 pF, Rr = 475 (1%).
Note 2: Measurement taken from a single-ended waveform.
Note 3: Measurement taken from a differential waveform.
Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.
Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.
Electrical Characteristics - Differential Phase Jitter Parameters
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency 25 MHz
Output Frequency HCSL termination 25 200 MHz
LVDS termination 25 100 MHz
Output High Voltage1,2 VOH HCSL 850 mV
Output Low Voltage1,2 VOL HCSL -150 mV
Crossing Point Voltage1,2 Absolute 250 550 mV
Crossing Point Voltage1,2,4 Variation over all edges 140 mV
Jitter, Cycle-to-Cycle1,3 100 ps
Frequency Synthesis Error All outputs 0 ppm
Modulation Frequency Spread spectrum 30 32.9 33 kHz
Rise Time1,2 tOR From 0.175 V to 0.525 V 175 700 ps
Fall Time1,2 tOF From 0.525 V to 0.175 V 175 700 ps
Rise/Fall Time Variation1,2 125 ps
Output to Output Skew 50 ps
Duty Cycle1,3 45 55 %
Output Enable Time5All outputs 50 100 ns
Output Disable Time5All outputs 50 100 ns
Stabilization Time tSTABLE From power-up VDD=3.3 V 1.8 ms
Spread Spectrum Transition
Time
tSPREAD Stabilization time after spread
spectrum changes
730ms
PARAMETER Symbol Conditions Min Typ Max Units Notes
t
jp
haseG1
PCIe Gen 1 28 86 ps (p-p) 1,2,3
tjphaseG2Lo
PCIe Gen 2
10kHz < f < 1.5MHz 0.7 3 ps
(RMS) 1,2,3
tjphaseG2High
PCIe Gen 2
1.5MHz < f < Nyquist (50MHz) 1.8 3.1 ps
(RMS) 1,2,3
tjphaseG3 PCIe Gen 3 0.48 1ps
(RMS) 1,2,3
1
Guaranteed by design and characterization, not 100% tested in production.
TA = Commercial and Industrial, Supply Voltage VDD = 3.3 V +/-5%
2See http://www.pcisig.com for complete specs
3Applies to 100MHz, spread off and 0.5% down spread only.
SPEC
Jitter, Phase
5V41235
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Thermal Characteristics (16TSSOP)
Thermal Characteristics (16QFN)
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient
JA Still air 78 C/W
JA 1 m/s air flow 70 C/W
JA 3 m/s air flow 68 C/W
Thermal Resistance Junction to Case JC 37 C/W
Parameter Symbol Conditions Min. Typ. Max. Units
Thermal Resistance Junction to
Ambient
JA Still air 63.2 C/W
JA 1 m/s air flow 55.9 C/W
JA 3 m/s air flow 51.4 C/W
Thermal Resistance Junction to Case JC 65.8 C/W
5V41235
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
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5V41235 MAY 5, 2017
Marking Diagram (5V41235PGG) Marking Diagram (5V41235PGGI)
Notes:
1. Line 1 and 2: IDT part number.
2. Line 3: YYWW – Date code; $ – Assembly location.
3. “G” after the two-letter package code designates RoHS compliant package.
4. “I” at the end of part number indicates industrial temperature range.
5. Bottom marking: country of origin if not USA.
Marking Diagram (5V41235NLGI) Marking Diagram (5V41235NLGI)
Notes:
1. Line 1: Lot number.
2. Line 2: YWW – Date code; $ – Assembly location.
3. “G” designates RoHS compliant package.
4. “I” at the end of part number indicates industrial temperature range.
5. Bottom marking: country of origin if not USA.
18
9
16
IDT5V412
35PGG
YYWW$
LOT
18
9
16
IDT5V412
35PGGI
YYWW$
LOT
XXX
YWW$
235G
XXX
YWW$
235GI
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Package Outline and Package Dimensions (3 x 3 mm 16-QFN)
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Package Outline and Package Dimensions (3 x 3 mm 16-QFN), cont.
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Package Outline and Package Dimensions (4.4 mm 16-TSSOP)
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Package Outline and Package Dimensions (4.4 mm 16-TSSOP), cont.
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Package Outline and Package Dimensions (4.4 mm 16-TSSOP), cont.
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Ordering Information
“G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
Revision History
Part / Order Number Marking Shipping Packaging Package Temperature
5V41235PGG See Page 10 Tubes 16-pin TSSOP 0 to +70 C
5V41235PGG8 Tape and Reel 16-pin TSSOP 0 to +70 C
5V41235PGGI Tubes 16-pin TSSOP -40 to +85 C
5V41235PGGI8 Tape and Reel 16-pin TSSOP -40 to +85 C
5V41235NLG See Page 10 Tubes 16-pin QFN 0 to +70 C
5V41235NLG8 Tape and Reel 16-pin QFN 0 to +70 C
5V41235NLGI Tubes 16-pin QFN -40 to +85 C
5V41235NLGI8 Tape and Reel 16-pin QFN -40 to +85 C
Rev. Originator Date Description of Change
A RDW 11/02/11 Initial release.
B RDW 11/22/11 1. Changed title to “2 Output PCIe GEN1/2/3 Synthesizer”
2. Updated Differential Phase Jitter table.
C RDW 06/06/12 1. Updated Features bullet(s) from: “• 25 MHz, 125 MHz and 200 MHz output frequencies; supports
Ethernet applications”, to: “• 25 MHz, 100MHz, 125 MHz and 200 MHz output frequencies;
TSSOP-only
• 100MHz output frequency; MLF package”.
2. Added table 3, Output/Spread Select table for MLF only
D S. Sharma 10/16/12 1. Updated and expanded Output Select table per char review.
2. Changed crystal capacitance load spec from 16pF to 8pF.
E IH 09/09/15 Corrected typo in Ordering information; NLG and NLGI shipping packaging changed from “Tray” to
“Tubes”.
F IH 07/08/16 Updated marking diagrams for TSSOP devices.
G RDW 10/11/16 1. Updated Features bullets for package output frequencies.
2. Changed all MLF references to QFN.
H B.Shen 01/12/17 Updated 16QFN POD drawing to latest showing chamfered epad.
J C.P. 05/05/17 Updated PGG16 package outline drawing to latest version.
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described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an
independent state and are not guaranteed to perfor m the same way when instal led in customer products . The information contained herei n is provided without represe ntation or
warranty of any kind, whethe r express or implie d, including , but not limited to, th e suitabi lity of ID T's product s for any p articula r purpose, an implie d warranty o f merchantabi lity, or
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5V41235
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER