SST39VF3202C-70-4I-B3KE - Microchip Technology, Inc.

Preliminary Specifications

S71410-01-000 08/10

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

32 Mbit (x16) Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FEATURES:

• Organized as 2M x16

• Single Voltage Read and Write Operations

– 2.7-3.6V

• Superior Reliability

– Endurance: 100,000 Cycles (Typical)

– Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 6 mA (typical)

– Standby Current: 4 µA (typical)

– Auto Low Power Mode: 4 µA (typical)

• Hardware Block-Protection/WP# Input Pin

– Top Block-Protection (top two 4-KWord blocks)

for SST39VF3202C

– Bottom Block-Protection (bottom two 4-KWord

blocks) for SST39VF3201C

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Block-Erase Capability

– Flexible block architecture

– Eight 4-KWord blocks, 63 32-KWord blocks

• Chip-Erase Capability

• Erase-Suspend/Erase-Resume Capabilities

• Hardware Reset Pin (RST#)

• Security-ID Feature

– SST: 128 bits; User: 128 words

• Fast Read Access Time:

–70ns

• Latched Address and Data

• Fast Erase and Word-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 35 ms (typical)

– Word-Program Time: 7 µs (typical)

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bits

– Data# Polling

– RY/BY# Pin

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pin Assignments

• Packages Available

– 48-lead TSOP (12mm x 20mm)

– 48-ball TFBGA (6mm x 8mm)

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST39VF3201C and SST39VF3202C devices are

2M x16 CMOS Multi-Purpose Flash Plus (MPF+) manu-

factured with SST’s proprietary, high-performance CMOS

SuperFlash technology. The split-gate cell design and

thick-oxide tunneling injector attain better reliability and

manufacturability compared with alternate approaches.

The SST39VF3201C/3202C write (Program or Erase)

with a 2.7-3.6V power supply. These devices conform to

JEDEC standard pin assignments for x16 memories.

Featuring high performance Word-Program, the

SST39VF3201C/3202C devices provide a typical Word-

Program time of 7 µsec. These devices use Toggle Bit,

Data# Polling, or RY/BY# pin to indicate the completion of

Program operation. To protect against inadvertent write,

they have on-chip hardware and Software Data Protection

schemes. Designed, manufactured, and tested for a wide

spectrum of applications, these devices are offered with a

guaranteed typical endurance of 100,000 cycles. Data

retention is rated at greater than 100 years.

The SST39VF3201C/3202C devices are suited for applica-

tions that require convenient and economical updating of

program, configuration, or data memory. For all system

applications, they significantly improve performance and reli-

ability, while lowering power consumption. They inherently

use less energy during Erase and Program than alternative

flash technologies. The total energy consumed is a function

of the applied voltage, current, and time of application. Since

for any given voltage range, the SuperFlash technology

uses less current to program and has a shorter erase time,

the total energy consumed during any Erase or Program

operation is less than alternative flash technologies. These

devices also improve flexibility while lowering the cost for

program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles.

To meet high-density, surface mount requirements, the

SST39VF3201C/3202C devices are offered in 48-lead

TSOP and 48-ball TFBGA packages. See Figure 2 and

Figure 3 for pin assignments.

SST39VF640xB2.7V 64Mb (x16) MPF+ memories

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asserting WE# low while keeping CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever occurs last. The data bus is latched on

the rising edge of WE# or CE#, whichever occurs first.

The SST39VF3201C/3202C also have the Auto Low

Power mode which puts the device in a near standby

mode after data has been accessed with a valid Read

operation. This reduces the IDD active read current from

typically 9 mA to typically 4 µA. The Auto Low Power mode

reduces the typical IDD active read current to the range of 2

mA/MHz of Read cycle time. The device exits the Auto Low

Power mode with any address transition or control signal

transition used to initiate another Read cycle, with no

access time penalty. Note that the device does not enter

Auto-Low Power mode after power-up with CE# held

steadily low, until the first address transition or CE# is

driven high.

Read

The Read operation of the SST39VF3201C/3202C is

controlled by CE# and OE#, both have to be low for the

system to obtain data from the outputs. CE# is used for

device selection. When CE# is high, the chip is dese-

lected and only standby power is consumed. OE# is the

output control and is used to gate data from the output

pins. The data bus is in high impedance state when

either CE# or OE# is high. Refer to the Read cycle timing

diagram for further details (Figure 5).

Word-Program Operation

The SST39VF3201C/3202C are programmed on a word-

by-word basis. Before programming, the sector where the

word exists must be fully erased. The Program operation is

accomplished in three steps. The first step is the three-byte

load sequence for Software Data Protection. The second

step is to load word address and word data. During the

Word-Program operation, the addresses are latched on the

falling edge of either CE# or WE#, whichever occurs last.

The data is latched on the rising edge of either CE# or

WE#, whichever occurs first. The third step is the internal

Program operation which is initiated after the rising edge of

the fourth WE# or CE#, whichever occurs first. The Pro-

gram operation, once initiated, will be completed within 10

µs. See Figure 6 and Figure 7 for WE# and CE# controlled

Program operation timing diagrams and Figure 21 for flow-

charts. During the Program operation, the only valid reads

are Data# Polling and Toggle Bit. During the internal Pro-

gram operation, the host is free to perform additional tasks.

Any commands issued during the internal Program opera-

tion are ignored. During the command sequence, WP#

should be statically held high or low.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST39VF3201C/3202C offer both Sec-

tor-Erase and Block-Erase mode. The sector architecture

is based on uniform sector size of 2 KWord. The Block-

Erase mode is based on block sizes of 4 and 32 KWord.

The Sector-Erase operation is initiated by executing a six-

byte command sequence with Sector-Erase command

(50H) and sector address (SA) in the last bus cycle. The

Block-Erase operation is initiated by executing a six-byte

command sequence with Block-Erase command (30H)

and block address (BA) in the last bus cycle. The sector or

block address is latched on the falling edge of the sixth

WE# pulse, while the command (50H or 30H) is latched on

the rising edge of the sixth WE# pulse. The internal Erase

operation begins after the sixth WE# pulse. The End-of-

Erase operation can be determined using either Data#

Polling or Toggle Bit methods. See Figure 11 and Figure 12

for timing waveforms and Figure 25 for the flowchart. Any

commands issued during the Sector- or Block-Erase oper-

ation are ignored. When WP# is low, any attempt to Sector-

(Block-) Erase the protected block will be ignored. During

the command sequence, WP# should be statically held

high or low.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a

Sector- or Block-Erase operation thus allowing data to be

read from any memory location, or program data into any

sector/block that is not suspended for an Erase operation.

The operation is executed by issuing one byte command

sequence with Erase-Suspend command (B0H). The

device automatically enters read mode typically within 10

µs after the Erase-Suspend command had been issued.

Valid data can be read from any sector or block that is not

suspended from an Erase operation. Reading at address

location within erase-suspended sectors/blocks will output

DQ2toggling and DQ6at ‘1’. While in Erase-Suspend

mode, a Word-Program operation is allowed except for the

sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has

been suspended the system must issue Erase Resume

command. The operation is executed by issuing one byte

command sequence with Erase Resume command (30H)

at any address in the last Byte sequence.

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

Chip-Erase Operation

The SST39VF3201C/3202C provide a Chip-Erase opera-

tion, which allows the user to erase the entire memory

array to the “1” state. This is useful when the entire device

must be quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command

(10H) at address 555H in the last byte sequence. The

Erase operation begins with the rising edge of the sixth

WE# or CE#, whichever occurs first. During the Erase

operation, the only valid read is Toggle Bit or Data# Polling.

See Table 7 for the command sequence, Figure 10 for tim-

ing diagram, and Figure 25 for the flowchart. Any com-

mands issued during the Chip-Erase operation are

ignored. When WP# is low, any attempt to Chip-Erase will

be ignored. During the command sequence, WP# should

be statically held high or low.

Write Operation Status Detection

The SST39VF3201C/3202C provide two software means

to detect the completion of a Write (Program or Erase)

cycle, in order to optimize the system write cycle time. The

software detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE#, which initi-

ates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asyn-

chronous with the system; therefore, either a Data# Poll-

ing or Toggle Bit read may be simultaneous with the

completion of the write cycle. If this occurs, the system

may possibly get an erroneous result, i.e., valid data may

appear to conflict with either DQ7or DQ6. In order to pre-

vent spurious rejection, if an erroneous result occurs, the

software routine should include a loop to read the

accessed location an additional two (2) times. If both

reads are valid, then the device has completed the Write

cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST39VF3201C/3202C are in the internal Pro-

gram operation, any attempt to read DQ7will produce the

complement of the true data. Once the Program operation

is completed, DQ7will produce true data. Note that even

though DQ7may have valid data immediately following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycles after an interval of 1 µs. During internal Erase oper-

ation, any attempt to read DQ7will produce a ‘0’. Once the

internal Erase operation is completed, DQ7will produce a

‘1’. The Data# Polling is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector-,

Block- or Chip-Erase, the Data# Polling is valid after the

rising edge of sixth WE# (or CE#) pulse. See Figure 8 for

Data# Polling timing diagram and Figure 22 for a flowchart.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6will produce alternating “1”s

and “0”s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the DQ6bit will

stop toggling. The device is then ready for the next opera-

tion. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6)

is valid after the rising edge of sixth WE# (or CE#) pulse.

DQ6will be set to ‘1’ if a Read operation is attempted on an

Erase-Suspended Sector/Block. If Program operation is ini-

tiated in a sector/block not selected in Erase-Suspend

mode, DQ6will toggle.

An additional Toggle Bit is available on DQ2, which can be

used in conjunction with DQ6to check whether a particular

sector is being actively erased or erase-suspended. Table 1

shows detailed status bits information. The Toggle Bit

(DQ2) is valid after the rising edge of the last WE# (or CE#)

pulse of Write operation. See Figure 9 for Toggle Bit timing

diagram and Figure 22 for a flowchart.

Note: DQ7,DQ

6and DQ2require a valid address when reading

status information.

TABLE 1: Write Operation Status

Status

RY/BY#

Normal

Operation

Standard

Program

DQ7# Toggle No

Toggle

Standard

Erase

0 Toggle Toggle 0

Erase-

Suspend

Mode

Read from

Erase-Sus-

pended

Sector/Block

1 1 Toggle 1

Read from

Non- Erase-

Suspended

Sector/Block

Data Data Data 1

Program DQ7# Toggle N/A 0

T1.0 1410

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

Ready/Busy# (RY/BY#)

The devices include a Ready/Busy# (RY/BY#) output sig-

nal. RY/BY# is an open drain output pin that indicates

whether an Erase or Program operation is in progress.

Since RY/BY# is an open drain output, it allows several

devices to be tied in parallel to VDD via an external pull-up

resistor. After the rising edge of the final WE# pulse in the

command sequence, the RY/BY# status is valid.

When RY/BY# is actively pulled low, it indicates that an

Erase or Program operation is in progress. When RY/BY#

is high (Ready), the devices may be read or left in standby

mode.

Data Protection

The SST39VF3201C/3202C provide both hardware and

software features to protect nonvolatile data from inadvertent

writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5

ns will not initiate a write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Write operation. This prevents inadver-

tent writes during power-up or power-down.

Hardware Block Protection

The SST39VF3202C support top hardware block protec-

tion, which protects the top two 4-KWord blocks of the

device. The SST39VF3201C support bottom hardware

block protection, which protects the bottom two 4-KWord

blocks of the device. The Boot Block address ranges are

described in Table 2. Program and Erase operations are

prevented on the two 4-KWord blocks when WP# is low. If

WP# is left floating, it is internally held high via a pull-up

resistor, and the Boot Block is unprotected, enabling Pro-

gram and Erase operations on that block.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the

device to read array data. When the RST# pin is held low

for at least TRP, any in-progress operation will terminate and

return to Read mode. When no internal Program/Erase

operation is in progress, a minimum period of TRHR is

required after RST# is driven high before a valid Read can

take place. See Figure 17.

The Erase or Program operation that has been interrupted

needs to be re-initiated after the device resumes normal

operation mode to ensure data integrity.

Software Data Protection (SDP)

The SST39VF3201C/3202C provide the JEDEC approved

Software Data Protection scheme for all data alteration

operations, i.e., Program and Erase. Any Program opera-

tion requires the inclusion of the three-byte sequence. The

three-byte load sequence is used to initiate the Program

operation, providing optimal protection from inadvertent

Write operations, e.g., during the system power-up or

power-down. Any Erase operation requires the inclusion of

six-byte sequence. These devices are shipped with the

Software Data Protection permanently enabled. See Table

7 for the specific software command codes. During SDP

command sequence, invalid commands will abort the

device to read mode within TRC. The contents of DQ15-DQ8

can be VIL or VIH, but no other value, during any SDP com-

mand sequence.

Common Flash Memory Interface (CFI)

The SST39VF3201C/3202C also contain the CFI informa-

tion to describe the characteristics of the device. In order

to enter the CFI Query mode, the system must write the

three-byte sequence, same as product ID entry command

with 98H (CFI Query command) to address 555H in the

last byte sequence. The system can also enter the CFI

Query mode, by using the one-byte sequence with 55H on

Address and 98H on Data Bus. Once the device enters

the CFI Query mode, the system can read CFI data at the

addresses given in Tables 8 through 10. The system must

write the CFI Exit command to return to Read mode from

the CFI Query mode.

TABLE 2: Boot Block Address Ranges

Product Address Range

Bottom Boot Block

SST39VF3201C 000000H-001FFFH

Top Boot Block

SST39VF3202C 1FE000H-1FFFFFH

T2.0 1410

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

Product Identification

The Product Identification mode identifies the devices as

the SST39VF3201Cand SST39VF3202C, and the manu-

facturer as SST. This mode may be accessed through

software operations. Users may use the Software Product

Identification operation to identify the part (i.e., using the

device ID) when using multiple manufacturers in the same

socket. For details, see Table 7 for software operation,

Figure 13 for the Software ID Entry and Read timing dia-

gram and Figure 23 for the Software ID Entry command

sequence flowchart.

Product Identification Mode Exit/

CFI Mode Exit

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read mode.

This command may also be used to reset the device to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Please note that the Software ID Exit/

CFI Exit command is ignored during an internal Program or

Erase operation. See Table 7 for software command

codes, Figure 15 for timing waveform, and Figure 23 and

Figure 24 for flowcharts.

Security ID

The SST39VF3201C/3202C devices offer a 136 word

Security ID space. The Secure ID space is divided into two

segments - one factory programmed segment and one

user programmed segment. The first segment is pro-

grammed and locked at SST with a random 128-bit num-

ber. The 128-word user segment is left un-programmed for

the customer to program as desired.

To program the user segment of the Security ID, the user

must use the Security ID Word-Program command. To

detect end-of-write for the SEC ID, read the toggle bits. Do

not use Data# Polling. Once this is complete, the Sec ID

should be locked using the User Sec ID Program Lock-Out.

This disables any future corruption of this space. Note that

regardless of whether or not the Sec ID is locked, neither

Sec ID segment can be erased.

The Secure ID space can be queried by executing a three-

byte command sequence with Enter Sec ID command

(88H) at address 555H in the last byte sequence. To exit

this mode, the Exit Sec ID command should be executed.

Refer to Table 7 for more details.

TABLE 3: Product Identification

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST39VF3201C 0001H 235F

SST39VF3202C 0001H 235E

T3.0 1410

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 1: Functional Block Diagram

FIGURE 2: Pin Assignments for 48-lead TSOP

Y-Decoder

I/O Buffers and Data Latches

1410 B1.0

Address Buffer Latches

X-Decoder

DQ15 -DQ

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

WP#

RESET#

RY/BY#

A15

A14

A13

A12

A11

A10

A19

A20

WE#

RST#

WP#

RY/BY#

A18

A17

A16

VSS

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VDD

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

1410 48-tsop EK P1.0

Standard Pinout

Top View

Die Up

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 3: pin assignments for 48-ball TFBGA

TABLE 4: Pin Description

Symbol Pin Name Functions

AMS1-A0

1. AMS = Most significant address

AMS =A

20 for SST39VF3201C/3202C

Address Inputs To provide memory addresses.

During Sector-Erase AMS-A11 address lines will select the sector.

During Block-Erase AMS-A15 address lines will select the block.

DQ15-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when grounded.

RST# Reset To reset and return the device to Read mode.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide power supply voltage: 2.7-3.6V

VSS Ground

NC No Connection Unconnected pins.

RY/BY# Ready/Busy# To output the status of a Program or Erase operation

RY/BY# is a open drain output, so a 10KΩ- 100KΩpull-up resistor is required

to allow RY/BY# to transition high indicating the device is ready to read.

T4.0 1410

1410 4-tfbga B1K P2.0

ABCDEFGH

TOP VIEW (balls facing down)

A13

WE#

RY/BY#

A12

RST#

WP#

A17

A14

A10

A18

A15

A11

A19

A20

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

TABLE 5: Top / Bottom Boot Block Address (1 of 2)

Top Boot Block Address SST39VF3202C Bottom Boot Block Address SST39VF3201C

# Size (KWord) Address Range # Size (KWord) Address Range

70 4 1FF000H-1FFFFFH 70 32 1F8000H-1FFFFFH

69 4 1FE000H-1FEFFFH 69 32 1F0000H-1F7FFFH

68 4 1FD000H-1FDFFFH 68 32 1E8000H-1EFFFFH

67 4 1FC000H-1FCFFFH 67 32 1E0000H-1E7FFFH

66 4 1FB000H-1FBFFFH 66 32 1D8000H-1DFFFFH

65 4 1FA000H-1FAFFFH 65 32 1D0000H-1D7FFFH

64 4 1F9000H-1F9FFFH 64 32 1C8000H-1CFFFFH

63 4 1F8000H-1F8FFFH 63 32 1C0000H-1C7FFFH

62 32 1F0000H-1F7FFFH 62 32 1B8000H-1BFFFFH

61 32 1E8000H-1EFFFFH 61 32 1B0000H-1B7FFFH

60 32 1E0000H-1E7FFFH 60 32 1A8000H-1AFFFFH

59 32 1D8000H-1DFFFFH 59 32 1A0000H-1A7FFFH

58 32 1D0000H-1D7FFFH 58 32 198000H-19FFFFH

57 32 1C8000H-1CFFFFH 57 32 190000H-197FFFH

56 32 1C0000H-1C7FFFH 56 32 188000H-18FFFFH

55 32 1B8000H-1BFFFFH 55 32 180000H-187FFFH

54 32 1B0000H-1B7FFFH 54 32 178000H-17FFFFH

53 32 1A8000H-1AFFFFH 53 32 170000H-177FFFH

52 32 1A0000H-1A7FFFH 52 32 168000H-16FFFFH

51 32 198000H-19FFFFH 51 32 160000H-167FFFH

50 32 190000H-197FFFH 50 32 158000H-15FFFFH

49 32 188000H-18FFFFH 49 32 150000H-157FFFH

48 32 180000H-187FFFH 48 32 148000H-14FFFFH

47 32 178000H-17FFFFH 47 32 140000H-147FFFH

46 32 170000H-177FFFH 46 32 138000H-13FFFFH

45 32 168000H-16FFFFH 45 32 130000H-137FFFH

44 32 160000H-167FFFH 44 32 128000H-12FFFFH

43 32 158000H-15FFFFH 43 32 120000H-127FFFH

42 32 150000H-157FFFH 42 32 118000H-11FFFFH

41 32 148000H-14FFFFH 41 32 110000H-117FFFH

40 32 140000H-147FFFH 40 32 108000H-10FFFFH

39 32 138000H-13FFFFH 39 32 100000H-107FFFH

38 32 130000H-137FFFH 38 32 0F8000H-0FFFFFH

37 32 128000H-12FFFFH 37 32 0F0000H-0F7FFFH

36 32 120000H-127FFFH 36 32 0E8000H-0EFFFFH

35 32 118000H-11FFFFH 35 32 0E0000H-0E7FFFH

34 32 110000H-117FFFH 34 32 0D8000H-0DFFFFH

33 32 108000H-10FFFFH 33 32 0D0000H-0D7FFFH

32 32 100000H-107FFFH 32 32 0C8000H-0CFFFFH

31 32 0F8000H-0FFFFFH 31 32 0C0000H-0C7FFFH

30 32 0F0000H-0F7FFFH 30 32 0B8000H-0BFFFFH

29 32 0E8000H-0EFFFFH 29 32 0B0000H-0B7FFFH

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

28 32 0E0000H-0E7FFFH 28 32 0A8000H-0AFFFFH

27 32 0D8000H-0DFFFFH 27 32 0A0000H-0A7FFFH

26 32 0D0000H-0D7FFFH 26 32 098000H-09FFFFH

25 32 0C8000H-0CFFFFH 25 32 090000H-097FFFH

24 32 0C0000H-0C7FFFH 24 32 088000H-08FFFFH

23 32 0B8000H-0BFFFFH 23 32 080000H-087FFFH

22 32 0B0000H-0B7FFFH 22 32 078000H-07FFFFH

21 32 0A8000H-0AFFFFH 21 32 070000H-077FFFH

20 32 0A0000H-0A7FFFH 20 32 068000H-06FFFFH

19 32 098000H-09FFFFH 19 32 060000H-067FFFH

18 32 090000H-097FFFH 18 32 058000H-05FFFFH

17 32 088000H-08FFFFH 17 32 050000H-057FFFH

16 32 080000H-087FFFH 16 32 048000H-04FFFFH

15 32 078000H-07FFFFH 15 32 040000H-047FFFH

14 32 070000H-077FFFH 14 32 038000H-03FFFFH

13 32 068000H-06FFFFH 13 32 030000H-037FFFH

12 32 060000H-067FFFH 12 32 028000H-02FFFFH

11 32 058000H-05FFFFH 11 32 020000H-027FFFH

10 32 050000H-057FFFH 10 32 018000H-01FFFFH

9 32 048000H-04FFFFH 9 32 010000H-017FFFH

8 32 040000H-047FFFH 8 32 008000H-00FFFFH

7 32 038000H-03FFFFH 7 4 007000H-007FFFH

6 32 030000H-037FFFH 6 4 006000H-006FFFH

5 32 028000H-02FFFFH 5 4 005000H-005FFFH

4 32 020000H-027FFFH 4 4 004000H-004FFFH

3 32 018000H-01FFFFH 3 4 003000H-003FFFH

2 32 010000H-017FFFH 2 4 002000H-002FFFH

1 32 008000H-00FFFFH 1 4 001000H-001FFFH

0 32 000000H-007FFFH 0 4 000000H-000FFFH

T5.1410

TABLE 6: Operation Modes Selection

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector or block address,

XXH for Chip-Erase

Standby VIH X X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Product Identification

Software Mode VIL VIL VIH See Table 7

T6.0 1410

TABLE 5: Top / Bottom Boot Block Address (Continued) (2 of 2)

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

TABLE 7: Software Command Sequence

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Word-Program 555H AAH 2AAH 55H 555H A0H WA3Data

Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX450H

Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX430H

Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Erase-Suspend XXXXH B0H

Erase-Resume XXXXH 30H

Query Sec ID5555H AAH 2AAH 55H 555H 88H

User Security ID

Word-Program

555H AAH 2AAH 55H 555H A5H WA6Data

User Security ID

Program Lock-Out

555H AAH 2AAH 55H 555H 85H XXH60000H

Software ID Entry7,8 555H AAH 2AAH 55H 555H 90H

CFI Query Entry 555H AAH 2AAH 55H 555H 98H

CFI Query Entry 55H 98H

Software ID Exit9,10

/CFI Exit/Sec ID Exit

555H AAH 2AAH 55H 555H F0H

Software ID Exit9,10

/CFI Exit/Sec ID Exit

XXH F0H

T7.0 1410

1. Address format A10-A0(Hex).

Addresses A11-A

20 can be VIL or VIH, but no other value, for Command sequence for SST39VF3201C/3202C.

2. DQ15-DQ8can be VIL or VIH, but no other value, for Command sequence

3. WA = Program Word address

4. SAXfor Sector-Erase; uses AMS-A11 address lines

BAX, for Block-Erase; uses AMS-A15 address lines

AMS = Most significant address

AMS =A

20 for SST39VF3201C/3202C

5. With AMS-A4= 0; Sec ID is read with A3-A0,

SST ID is read with A3= 0 (Address range = 000000H to 000007H),

User ID is read with A3= 1 (Address range = 000008H to 000087H).

Lock Status is read with A7-A0= 0000FFH. Unlocked: DQ3= 1 / Locked: DQ3=0.

6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H to 000087H.

7. The device does not remain in Software Product ID Mode if powered down.

8. For Manufacture ID

With AMS-A0=0;SST Manufacturer ID = 00BFH is read

For Device ID -

Device ID can be read either in one cycle (address 01H) or in three cycles (addresses 01H, 0EH and 0FH)

One-cycle method -

With AMS-A1=0, A0=1; SST39VF3201C/3202C Device ID = 235F/235E is read

Three-cycle method -

With AMS-A1=0, A0=1; SST39VF3201C/3202C Device ID = 235F/235E is read (cycle 1)

With AMS-A4=0; A3-A1=1; A0=0; SST39VF3201C/3202C Device ID additional info = 1A/1A is read (Note: 1A = 32 Mbit) (cycle 2)

With AMS-A4=0; A3-A0=1; SST39VF3201C/3202C Device ID additional info = 00/01 is read (00/01 = Bottom/Top Boot) (cycle 3)

AMS = Most significant address

AMS =A

20 for SST39VF3201C/3202C

9. Both Software ID Exit operations are equivalent

10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID

mode again (the programmed “0” bits cannot be reversed to “1”). Valid Word-Addresses for Sec ID are from 000000H-000007H and

000008H to 000087H.

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

TABLE 8: CFI Query Identification String1for SST39VF3201C/3202C

Address Data Data

10H 0051H Query Unique ASCII string “QRY”

11H 0052H

12H 0059H

13H 0002H Primary OEM command set

14H 0000H

15H 0000H Address for Primary Extended Table

16H 0000H

17H 0000H Alternate OEM command set (00H = none exists)

18H 0000H

19H 0000H Address for Alternate OEM extended Table (00H = none exits)

1AH 0000H

T8.0 1410

1. Refer to CFI publication 100 for more details.

TABLE 9: System Interface Information for SST39VF3201C/3202C

Address Data Data

1BH 0027H VDD Min (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH 0036H VDD Max (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH 0000H VPP min. (00H = no VPP pin)

1EH 0000H VPP max. (00H = no VPP pin)

1FH 0003H Typical time out for Word-Program 2Nµs (23= 8 µs)

20H 0000H Typical time out for min. size buffer program 2Nµs (00H = not supported)

21H 0004H Typical time out for individual Sector/Block-Erase 2Nms (24=16ms)

22H 0005H Typical time out for Chip-Erase 2Nms (25=32ms)

23H 0001H Maximum time out for Word-Program 2Ntimes typical (21x2

3=16µs)

24H 0000H Maximum time out for buffer program 2Ntimes typical

25H 0001H Maximum time out for individual Sector/Block-Erase 2Ntimes typical (21x2

4=32ms)

26H 0001H Maximum time out for Chip-Erase 2Ntimes typical (21x2

5=64ms)

T9.0 1410

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

TABLE 10: Device Geometry Information for SST39VF3201C/3202C

Address Data Data

27H 0016H Device size = 2NBytes (16H = 22; 222 = 4MByte)

28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface

29H 0000H

2AH 0000H Maximum number of bytes in multi-byte write = 2N(00H = not supported)

2BH 0000H

2CH 0003H Number of Erase Sector/Block sizes supported by device

2DH 0007H Erase Block1 region information.

2EH 0000H

2FH 0020H

30H 0000H

31H 003EH Erase Block2 region information.

32H 0000H

33H 0000H

34H 0001H

35H 0000H Erase Block3 region information.

36H 0000H

37H 0000H

38H 0000H

39H 0000H Erase Block4 region information.

3AH 0000H

3BH 0000H

3CH 0000H

T10.0 1410

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

Power Up Specifications

All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 3V

in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware reset is required. The recom-

mended VDD power-up to RESET# high time should be greater than 100 µs to ensure a proper reset.

FIGURE 4: Power-Up Diagram

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias .........................................................-55°C to +125°C

Storage Temperature ...........................................................-65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential .......................................-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential .............................-2.0V to VDD+2.0V

Voltage on A9Pin to Ground Potential ................................................-0.5V to 13.2V

Package Power Dissipation Capability (TA= 25°C) .............................................1.0W

Surface Mount Solder Reflow Temperature.......................................260°C for 10 seconds

Output Short Circuit Current1.............................................................50mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

Operating Range

Range Ambient Temp VDD

Commercial

Industrial

0°C to +70°C

-40°C to +85°C

2.7-3.6V

AC Conditions of Test

Input Rise/Fall Time .............. 5ns

Output Load ..................... C

L=30pF

See Figures 19 and 20

1410 F24.0

VDD

RESET#

CE#

TPU-READ 10 0 µs

VDD min

VIH

TRHR 50 ns

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

TABLE 11: DC Operating Characteristics VDD = 2.7-3.6V1

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT2, at f=5 MHz,

VDD=VDD Max

Read315 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

Program and Erase 45 mA CE#=WE#=VIL, OE#=VIH

ISB Standby VDD Current 50 µA CE#=VIHC,V

DD=VDD Max

IALP Auto Low Power 50 µA CE#=VILC,V

DD=VDD Max

All inputs=VSS or VDD, WE#=VIHC

ILI Input Leakage Current 1 µA VIN=GND to VDD,V

DD=VDD Max

ILIW Input Leakage Current

on WP# pin and RST#

10 µA WP#=GND to VDD or RST#=GND to VDD

ILO Output Leakage Current 1 µA VOUT=GND to VDD,V

DD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T11.0 1410

1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C

(room temperature), and VDD = 3V. Not 100% tested.

2. See Figure 19

3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.

TABLE 12: Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T12.0 1410

TABLE 13: Capacitance (TA = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O =0V 10pF

CIN1Input Capacitance VIN =0V 10pF

T13.0 1410

TABLE 14: Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a

higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T14.0 1410

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

AC CHARACTERISTICS

TABLE 15: Read Cycle Timing Parameters VDD = 2.7-3.6V

Symbol Parameter Min Max Units

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1CE# High to High-Z Output 16 ns

TOHZ1OE# High to High-Z Output 16 ns

TOH1Output Hold from Address Change 0 ns

TRP1RST# Pulse Width 500 ns

TRHR1RST# High before Read 50 ns

TRY1,2

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

This parameter does not apply to Chip-Erase operations.

RST# Pin Low to Read Mode 20 µs

T15.0 1410

TABLE 16: Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

TBP Word-Program Time 10 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 50 ms

TBY1,2

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

RY/BY# Delay Time 90 ns

TBR1Bus Recovery Time 0µs

T16.0 1410

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 5: Read Cycle Timing Diagram

FIGURE 6: WE# Controlled Program Cycle Timing Diagram

1410 F03.0

ADDRESS AMS-0

DQ15-0

WE#

OE#

CE#

TCE

TRC TAA

TOE

TOLZ

VIH

HIGH-Z

TCLZ TOH TCHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

Note: AMS = Most significant address

AMS =A

20 for SST39VF3201C/3202C

1410 F04.0

ADDRESSES

DQ15-0

CE#

555 2AA 555 ADDR

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

OE#

WE#

RY/BY#

VALID

TDH

TWPH

TAS

TCH

TCS

TAH

TWP

TDS

TBY TBR

TBP

Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 7: CE# Controlled Program Cycle Timing Diagram

FIGURE 8: Data# Polling Timing Diagram

1410 F05.0

ADDRESSES

DQ15-0

CE#

555 2AA 555 ADDR

XXAA XX55 XXA0 DATA

WORD

(ADDR/DATA)

OE#

WE#

RY/BY#

VALID

TDH

TCPH

TAS

TCH

TCS

TAH

TCP

TDS

TBY TBR

TBP

Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

1410 F06.0

ADDRESS A19-0-AMS-0

DQ7DATA

WE#

OE#

CE#

RY/BY#

DATA # DATA # DATA

TOES

TOEH

TBY

TCE

TOE

Note: AMS = Most significant address

AMS =A

20 for SST39VF3201C/3202C

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 9: Toggle Bits Timing Diagram

FIGURE 10: WE# Controlled Chip-Erase Timing Diagram

1410 F07.0

ADDRESS AMS-0

DQ6and DQ2

WE#

OE#

CE#

TOE

TOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note: AMS = Most significant address

AMS =A

20 for SST39VF3201C/3202C

1410 F08.0

ADDRESSES

DQ15-0

WE#

555 2AA 2AA555 555

XX55 XX10

XX55XXAA XX80 XXAA

555

OE#

CE#

RY/BY#

VALID

SIX-BYTE CODE FOR CHIP-ERASE

TOEH

TSCE

TBY TBR

Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are

interchangeable as long as minimum timings are met. (See Table 16)

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 11: WE# Controlled Block-Erase Timing Diagram

FIGURE 12: WE# Controlled Sector-Erase Timing Diagram

1410 F09.0

ADDRESSES

DQ15-0

WE#

555 2AA 2AA555 555

XX55 XX30

XX55XXAA XX80 XXAA

BAX

OE#

CE#

RY/BY#

VALID

SIX-BYTE CODE FOR BLOCK-ERASE

TWP

TBE

TBY TBR

Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchange-

able as long as minimum timings are met. (See Table 16).

BAX= Block Address

WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

1410 F10.0

ADDRESSES

DQ15-0

WE#

555 2AA 2AA555 555

XX55 XX50

XX55XXAA XX80 XXAA

SAX

OE#

CE#

RY/BY#

VALID

SIX-BYTE CODE FOR SECTOR-ERASE

TWP

TSE

TBY TBR

Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchange-

able as long as minimum timings are met. (See Table 16).

SAX= Block Address

WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1µs after the command sequence.

X can be VIL or VIH, but no other value.

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 13: Software ID Entry and Read

FIGURE 14: CFI Query Entry and Read

1410 F11.0

ADDRESS

TIDA

DQ15-0

WE#

SW0 SW1 SW2

555 2AA 555 0000 0001

OE#

CE#

Three-Byte Sequence for Software ID Entry

TWP

TWPH TAA

00BF Device ID

XX55XXAA XX90

Note: Device ID = 235E for SST39VF3201Cand 235E for SST39VF3202C

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

1410 F12.0

ADDRESS

TIDA

DQ15-0

WE#

SW0 SW1 SW2

555 2AA 555

OE#

CE#

Three-Byte Sequence for CFI Query Entry

TWP

TWPH TAA

XX55XXAA XX98

Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 15: Software ID Exit/CFI Exit

FIGURE 16: Sec ID Entry

1410 F13.0

ADDRESS A14-0

DQ15-0

TIDA

TWP

TWHP

WE#

SW0 SW1 SW2

555 2AA 555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

XXAA XX55 XXF0

Note: WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

1410 F14.0

ADDRESS AMS-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

555 2AA 555

OE#

CE#

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

TWP

TWPH TAA

XX55XXAA XX88

Note: AMS = Most significant address

AMS =A

20 for SST39VF3201C/3202C

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 17: RST# Timing Diagram (When no internal operation is in progress)

FIGURE 18: RST# Timing Diagram (During Program or Erase operation)

1410 F15.0

RY/BY#

RST#

CE#/OE#

TRP

TRHR

1410 F16.0

RY/BY#

CE#

OE#

TRP

TRY

TBR

RST#

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 19: AC Input/Output Reference Waveforms

FIGURE 20: A Test Load Example

1410 F17.0

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points

for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔90%) are <5 ns.

Note: VIT -V

INPUT Test

VOT -V

OUTPUT Test

VIHT -V

INPUT HIGH Test

VILT -V

INPUT LOW Test

1410 F18.0

TO TESTER

TO DUT

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 21: Word-Program Algorithm

1410 F19.0

Start

Load data: XXAAH

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XXA0H

Address: 555H

Load Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

X can be VIL or VIH, but no other value

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 22: Wait Options

1410 F20.0

Wait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7=

true data

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

Ye s

RY/BY#

RY/BY# = 1

Read RY/BY#

Program/Erase

Initiated

Program/Erase

Completed

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 23: Software ID/CFI Entry Command Flowcharts

1410 F21.0

Load data: XXAAH

Address: 555H

Software Product ID Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX90H

Address: 555H

Wait TIDA

Read Software ID

Load data: XXAAH

Address: 555H

CFI Query Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX98H

Address: 555H

Wait TIDA

Read CFI data

Load data: XXAAH

Address: 555H

Sec ID Query Entry

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX88H

Address: 555H

Wait TIDA

Read Sec ID

X can be VIL or VIH, but no other value

Load data: XX98H

Address: 55H

Wait TIDA

Read CFI data

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 24: Software ID/CFI Exit Command Flowcharts

1410 F22.0

Load data: XXAAH

Address: 555H

Software ID Exit/CFI Exit/Sec ID Exit

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XXF0H

Address: 555H

Load data: XXF0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

X can be VIL or VIH, but no other value

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 25: Erase Command Sequence

1410 F23.0

Load data: XXAAH

Address: 555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX10H

Address: 555H

Load data: XXAAH

Address: 555H

Wait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX50H

Address: SAX

Load data: XXAAH

Address: 555H

Wait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAH

Load data: XX80H

Address: 555H

Load data: XX55H

Address: 2AAH

Load data: XX30H

Address: BAX

Load data: XXAAH

Address: 555H

Wait TBE

Block erased

to FFFFH

X can be VIL or VIH, but no other value

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

PRODUCT ORDERING INFORMATION

Valid Combinations for SST39VF3201C

SST39VF3201C-70-4C-EKE SST39VF3201C-70-4C-B3KE

SST39VF3201C-70-4I-EKE SST39VF3201C-70-4I-B3KE

Valid Combinations for SST39VF3202C

SST39VF3202C-70-4C-EKE SST39VF3202C-70-4C-B3KE

SST39VF3202C-70-4I-EKE SST39VF3202C-70-4I-B3KE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Environmental Attribute

E1= non-Pb

Package Modifier

K = 48 balls or leads

Package Type

E = TSOP (type1, die up, 12mm x 20mm)

B3 = TFBGA (6mm x 8mm, 0.8mm pitch)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70=70ns

Hardware Block Protection

1 = Bottom Boot-Block

2 = Top Boot-Block

Device Density

320= 32Mbit

Voltage

V = 2.7-3.6V

Product Series

39 = Multi-Purpose Flash Plus

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

SST 39 VF 320 2C - 70 - 4C - EK E

XX XX XXX XC - XX - XX- XX X

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

PACKAGING DIAGRAMS

FIGURE 26: 48-lead Thin Small Outline Package (TSOP) 12mm x 20mm,

SST Package Code: EK

1.05

0.95

0.70

0.50

18.50

18.30

20.20

19.80

0.70

0.50

12.20

11.80

0.27

0.17

0.15

0.05

48-tsop-EK-8

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

0°- 5°

DETAIL

Pin # 1 Identifier

0.50

BSC

Preliminary Specifications

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

FIGURE 27: 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm,

SST Package Code: B3K

TABLE 17: Revision History

Number Description Date

00 •Initial release Nov 2009

01 •Revised ISB and IALP in Table 11 on page 14 Aug 2010

A1 CORNER

HGFEDCBA

ABCDEFGH

BOTTOM VIEWTOP VIEW

SIDE VIEW

SEATING PLANE

0.35 0.05

1.10 0.10

0.12

6.00 0.20

0.45 0.05

(48X)

A1 CORNER

8.00 0.20

0.80

4.00

0.80

5.60

48-tfbga-B3K-6x8-450mic-4

Note: 1. Complies with JEDEC Publication 95, MO-210, variant AB-1 , although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm ( 0.05 mm)

1mm

Silicon Storage Technology, Inc.