MTP3055V - ON Semiconductor - Datasheet.Directory

August, 2006 − Rev. 4

1Publication Order Number:

MTP3055V/D

MTP3055V

Preferred Device

Power MOSFET

12 Amps, 60 Volts

N−Channel TO−220

This Power MOSFET is designed to withstand high energy in the

avalanche and commutation modes. Designed for low voltage, high

speed switching applications in power supplies, converters and power

motor controls, these devices are particularly well suited for bridge

circuits where diode speed and commutating safe operating areas are

critical and offer additional safety margin against unexpected voltage

transients.

•On−resistance Area Product about One−half that of Standard

MOSFETs with New Low Voltage, Low RDS(on) Technology

•Faster Switching than E−FET Predecessors

•Avalanche Energy Specified

•IDSS and VDS(on) Specified at Elevated Temperature

•Static Parameters are the Same for both TMOS V and

TMOS E−FET

MAXIMUM RATINGS (TC = 25°C unless otherwise noted)

Rating Symbol Value Unit

Drain−Source Voltage VDSS 60 Vdc

Drain−Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc

Gate−Source Voltage

− Continuous

− Non−Repetitive (tp ≤ 10 ms)

VGS

VGSM

±20

±25

Vdc

Vpk

Drain Current − Continuous @ 25°C

Drain Current − Continuous @ 100°C

Drain Current − Single Pulse (tp ≤ 10 μs)

IDM

7.3

Adc

Apk

Total Power Dissipation @ 25°C

Derate above 25°C

PD48

0.32

Watts

W/°C

Operating and Storage Temperature Range TJ, Tstg −55 to

175

°C

Single Pulse Drain−to−Source Avalanche

Energy − Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 10 Vdc,

IL = 12 Apk, L = 1.0 mH, RG = 25 Ω)

EAS 72 mJ

Thermal Resistance − Junction to Case

Thermal Resistance − Junction to Ambient

RθJC

RθJA

3.13

62.5

°C/W

Maximum Lead Temperature for Soldering

Purposes, 1/8″ from case for 10 seconds

TL260 °C

12 AMPERES

50 VOLTS

RDS(on) = 150 mΩ

Preferred devices are recommended choices for future use

and best overall value.

Device Package Shipping

ORDERING INFORMATION

MTP3055V TO−220AB 50 Units/Rail

TO−220AB

CASE 221A

STYLE 5

123

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N−Channel

MARKING DIAGRAM

& PIN ASSIGNMENT

MTP3055V = Device Code

LL = Location Code

Y = Year

WW = Work Week

MTP3055V

LLYWW

Gate

Source

Drain

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ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain−Source Breakdown Voltage

(VGS = 0 Vdc, ID = 250 μAdc)

Temperature Coefficient (Positive)

V(BR)DSS

−

Vdc

mV/°C

Zero Gate Voltage Drain Current

(VDS = 60 Vdc, VGS = 0 Vdc)

(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)

IDSS

−

100

μAdc

Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0) IGSS − − 100 nAdc

ON CHARACTERISTICS (Note 1)

Gate Threshold Voltage

(VDS = VGS, ID = 250 μAdc)

Temperature Coefficient (Negative)

VGS(th)

2.0

−

2.7

5.4

4.0

−

Vdc

mV/°C

Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 6.0 Adc) RDS(on) −0.10 0.15 Ohm

Drain−Source On−Voltage (VGS = 10 Vdc)

(ID = 12 Adc)

(ID = 6.0 Adc, TJ = 150°C)

VDS(on)

−

1.3

−

2.2

1.9

Vdc

Forward Transconductance (VDS = 7.0 Vdc, ID = 6.0 Adc) gFS 4.0 5.0 −mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Ciss −410 500 pF

Output Capacitance Coss −130 180

Reverse Transfer Capacitance Crss −25 50

SWITCHING CHARACTERISTICS (Note 2)

Turn−On Delay Time

(VDD = 30 Vdc, ID = 12 Adc,

VGS = 10 Vdc,

RG = 9.1 Ω)

td(on) −7.0 10 ns

Rise Time tr−34 60

Turn−Off Delay Time td(off) −17 30

Fall Time tf−18 50

Gate Charge

(See Figure 8)

(VDS = 48 Vdc, ID = 12 Adc,

VGS = 10 Vdc)

QT−12.2 17 nC

Q1−3.2 −

Q2−5.2 −

Q3−5.5 −

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage (Note 1) (IS = 12 Adc, VGS = 0 Vdc)

(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C)

VSD

−

1.0

0.91

1.6

−

Vdc

Reverse Recovery Time

(See Figure 15)

(IS = 12 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/μs)

trr −56 −ns

ta−40 −

tb−16 −

Reverse Recovery Stored

Charge

QRR −0.128 −μC

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from contact screw on tab to center of die)

(Measured from the drain lead 0.25″ from package to center of die)

−3.5

4.5

−

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

LS−7.5 −nH

1. Pulse Test: Pulse Width ≤300 μs, Duty Cycle ≤ 2%.

2. Switching characteristics are independent of operating junction temperature.

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TYPICAL ELECTRICAL CHARACTERISTICS

RDS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS)

RDS(on), DRAIN−TO−SOURCE RESISTANCE

(NORMALIZED)

01234 5

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics

ID, DRAIN CURRENT (AMPS)

24 6 810

ID, DRAIN CURRENT (AMPS)

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

048 16 24

0.10

0.20

0.30

RDS(on), DRAIN−TO−SOURCE RESISTANCE (OHMS)

0 8 20 24

0.08

0.09

0.13

0.15

ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus Drain Current

and Temperature

ID, DRAIN CURRENT (AMPS)

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

−50

0.6

0.8

1.2

1.6

020 5060

100

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 6. Drain−To−Source Leakage

Current versus Voltage

IDSS , LEAKAGE (nA)

−25 0 25 50 75 100 125 150

TJ = 25°CVDS ≥ 10 V TJ = −55°C

25°C

100°C

TJ = 25°C

VGS = 0 V

VGS = 10 V

ID = 6 A

9 V

8 V

6 V

5 V

4 V

7 V

3579

VGS = 10 V

TJ = 100°C

25°C

−55°C

12 20 4 12 16

10 30 40

0.05

0.15

0.25

0.10

0.12

0.14

0.11

1.0

1.4

TJ = 125°C

VGS = 10 V

15 V

175

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POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge

controlled. The lengths of various switching intervals (Δt)

are determined by how fast the FET input capacitance can

be charged by current from the generator.

The published capacitance data is difficult to use for

calculating rise and fall because drain−gate capacitance

varies greatly with applied voltage. Accordingly, gate

charge data is used. In most cases, a satisfactory estimate of

average input current (IG(AV)) can be made from a

rudimentary analysis of the drive circuit so that

t = Q/IG(AV)

During the rise and fall time interval when switching a

resistive load, VGS remains virtually constant at a level

known as the plateau voltage, VSGP

. Therefore, rise and fall

times may be approximated by the following:

tr = Q2 x RG/(VGG − VGSP)

tf = Q2 x RG/VGSP

where

VGG = the gate drive voltage, which varies from zero to VGG

RG = the gate drive resistance

and Q2 and VGSP are read from the gate charge curve.

During the turn−on and turn−off delay times, gate current is

not constant. The simplest calculation uses appropriate

values from the capacitance curves in a standard equation for

voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG − VGSP)]

td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve at

a voltage corresponding to the off−state condition when

calculating td(on) and is read at a voltage corresponding to the

on−state when calculating td(off).

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET

source lead, inside the package and in the circuit wiring

which is common to both the drain and gate current paths,

produces a voltage at the source which reduces the gate drive

current. The voltage is determined by Ldi/dt, but since di/dt

is a function of drain current, the mathematical solution is

complex. The MOSFET output capacitance also

complicates the mathematics. And finally, MOSFETs have

finite internal gate resistance which effectively adds to the

resistance of the driving source, but the internal resistance

is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate

resistance (Figure 9) shows how typical switching

performance is affected by the parasitic circuit elements. If

the parasitics were not present, the slope of the curves would

maintain a value of unity regardless of the switching speed.

The circuit used to obtain the data is constructed to minimize

common inductance in the drain and gate circuit loops and

is believed readily achievable with board mounted

components. Most power electronic loads are inductive; the

data in the figure is taken with a resistive load, which

approximates an optimally snubbed inductive load. Power

MOSFETs may be safely operated into an inductive load;

however, snubbing reduces switching losses.

10 0 10 15 25

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

C, CAPACITANCE (pF)

Figure 7. Capacitance Variation

VGS VDS

TJ = 25°C

VDS = 0 V VGS = 0 V

1200

1000

800

600

400

200

Ciss

Coss

Crss

Ciss

Crss

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VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

0.50 0.60 0.70 0.80 1.0

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 8. Gate−To−Source and Drain−To−Source

Voltage versus Total Charge

IS, SOURCE CURRENT (AMPS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

RG, GATE RESISTANCE (OHMS)

1 10 100

t, TIME (ns)

VDD = 30 V

ID = 12 A

VGS = 10 V

TJ = 25°C

td(off)

VGS = 0 V

TJ = 25°C

Figure 10. Stored Charge

QT, TOTAL CHARGE (nC)

2468 13

ID = 12 A

TJ = 25°C

VGS

1000

100

VDS

13579

0.55 0.65 0.75 0.85 0.90

0.95

Q1 Q2

1110 12

td(on)

04 12

IS, SOURCE CURRENT (AMPS)

QRR, STORED CHARGE ( C)

dIS/dt = 100 A/μs

VDD = 25 V

TJ = 25°C

0.08

0.10

0.11

0.12

0.13

0.09

26810

Figure 11. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous drain−to−source voltage and

drain current that a transistor can handle safely when it is

forward biased. Curves are based upon maximum peak

junction temperature and a case temperature (TC) of 25°C.

Peak repetitive pulsed power limits are determined by using

the thermal response data in conjunction with the procedures

discussed in AN569, “Transient Thermal

Resistance−General Data and Its Use.”

Switching between the off−state and the on−state may

traverse any load line provided neither rated peak current

(IDM) nor rated voltage (VDSS) is exceeded and the

transition time (tr,tf) do not exceed 10 μs. In addition the total

power averaged over a complete switching cycle must not

exceed (TJ(MAX) − TC)/(RθJC).

A Power MOSFET designated E−FET can be safely used

in switching circuits with unclamped inductive loads. For

reliable operation, the stored energy from circuit inductance

dissipated in the transistor while in avalanche must be less

than the rated limit and adjusted for operating conditions

differing from those specified. Although industry practice is

to rate in terms of energy, avalanche energy capability is not

a constant. The energy rating decreases non−linearly with an

increase of peak current in avalanche and peak junction

temperature.

Although many E−FETs can withstand the stress of

drain−to−source avalanche at currents up to rated pulsed

current (IDM), the energy rating is specified at rated

continuous current (ID), in accordance with industry

custom. The energy rating must be derated for temperature

as shown in the accompanying graph (Figure 13). Maximum

energy at currents below rated continuous ID can safely be

assumed to equal the values indicated.

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SAFE OPERATING AREA

TJ, STARTING JUNCTION TEMPERATURE (°C)

AS, SINGLE PULSE DRAIN−TO−SOURCE

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

0.1 10 100

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 13. Maximum Avalanche Energy versus

Starting Junction Temperature

AVALANCHE ENERGY (mJ)

ID, DRAIN CURRENT (AMPS)

25 50 75 100 125

VGS = 20 V

SINGLE PULSE

TC = 25°C

ID = 12 A

1.0 150

t, TIME (s)

Figure 14. Thermal Response

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

RθJC(t) = r(t) RθJC

D CURVES APPLY FOR POWER

PULSE TRAIN SHOWN

READ TIME AT t1

TJ(pk) − TC = P(pk) RθJC(t)

P(pk)

DUTY CYCLE, D = t1/t2

Figure 15. Diode Reverse Recovery Waveform

di/dt

trr

0.25 IS

TIME

1.0

100

0.1 0

1.0

0.1

0.01

0.2

D = 0.5

0.05

0.01

SINGLE PULSE

0.1

1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01

100 μs

1 ms

10 ms

10 μs

RDS(on) LIMIT

THERMAL LIMIT

PACKAGE LIMIT

0.02

175

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PACKAGE DIMENSIONS

TO−220 THREE−LEAD

TO−220AB

CASE 221A−09

ISSUE AA

STYLE 5:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES ARE

ALLOWED.

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.570 0.620 14.48 15.75

B0.380 0.405 9.66 10.28

C0.160 0.190 4.07 4.82

D0.025 0.035 0.64 0.88

F0.142 0.147 3.61 3.73

G0.095 0.105 2.42 2.66

H0.110 0.155 2.80 3.93

J0.018 0.025 0.46 0.64

K0.500 0.562 12.70 14.27

L0.045 0.060 1.15 1.52

N0.190 0.210 4.83 5.33

Q0.100 0.120 2.54 3.04

R0.080 0.110 2.04 2.79

S0.045 0.055 1.15 1.39

T0.235 0.255 5.97 6.47

U0.000 0.050 0.00 1.27

V0.045 −−− 1.15 −−−

Z−−− 0.080 −−− 2.04

123

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