SPC560B40x, SPC560B44x, SPC560B50x SPC560C40x, SPC560C44x, SPC560C50x 32-bit MCU family built on the Power Architecture(R) embedded category for automotive body electronics applications Features High-performance 64 MHz e200z0h CPU - 32-bit Power Architecture(R) technology - Up to 60 DMIPs operation - Variable length encoding (VLE) LQFP100 (14 x 14 x 1.4 mm) Memory - Up to 512 Kbytes Code Flash, with ECC - 64 Kbytes Data Flash, with ECC - Up to 48 Kbytes SRAM, with ECC - 8-entry memory protection unit (MPU) Interrupts - 16 priority levels - Non-maskable interrupt (NMI) - Up to 34 ext. int. including 18 wakeup lines GPIO: QFP64/45, QFP100/75, QFP144/123 Timer units - 6-channel 32-bit periodic interrupt timers - 4-channel 32-bit system timer module - System watchdog timer - Real-time clock timer 16-bit counter time-triggered I/Os - Up to 56 channels with PWM/MC/IC/OC - ADC diagnostic via CTU Communications interface - Up to 6 FlexCAN interfaces (2.0B active) with 64-message objects each - Up to 4 LINFlex/UART - 3 DSPI / I2C Table 1. Package LQFP64 (10 x 10 x 1.4 mm) LQFP144 (20 x 20 x 1.4 mm) 10-bit A/D converter with up to 36 channels - Up to 64 channels via external multiplexing - Individual conversion registers - Cross triggering unit Dedicated diagnostic module for lighting - Advanced PWM generation - Time-triggered diagnostic - PWM-synchronized ADC measurements Clock generation - 4 to 16 MHz fast external crystal oscillator - 32 KHz slow external crystal oscillator - 16 MHz fast internal RC oscillator - 128 kHz slow internal RC oscillator - Software-controlled FMPLL - Clock monitoring unit Exhaustive debugging capability - Nexus1 on all devices - Nexus2+ available on emulation package Low power capabilities - Ultra-low power standby with RTC, SRAM and CAN monitoring - Fast wakeup schemes Operating temp. range up to -40 to 125 C Single 5 V or 3.3 V supply Device summary 256 Kbyte code Flash SPC560B40L5 LQFP100 SPC560B40L3 SPC560C40L3 SPC560B44L3 SPC560C44L3 SPC560B50L3 SPC560C50L3 LQFP64 SPC560B40L1 SPC560C40L1 -- -- SPC560B44L5 -- 512 Kbyte code Flash LQFP144 LBGA208(1) -- 384 Kbyte code Flash SPC560B50L5 -- -- -- SPC560B50L1 SPC560C50L1 -- -- SPC560B50B2 -- 1. LBGA208 available only as development package for Nexus2+ July 2010 Doc ID 14619 Rev 7 1/113 www.st.com 1 Contents SPC560Bx, SPC560Cx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 13 4 3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . 41 4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.5 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.7 2/113 4.3.1 4.6.1 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.6.2 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.7.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.7.2 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.7.3 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.7.4 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.7.5 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.8 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.9 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 59 4.9.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 59 4.9.2 Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 62 4.10 Low voltage domain power consumption . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.11 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx 4.12 6 4.11.1 Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.11.2 Flash power supply DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.11.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . . 67 4.12.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 67 4.12.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.12.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 68 4.13 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . 69 4.14 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . 72 4.15 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.16 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . 76 4.17 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . 76 4.18 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.19 5 Contents 4.18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.18.2 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.18.3 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.19.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.19.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.19.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.19.4 JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.1 ECOPACK(R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.2.1 LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.2.2 LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.2.3 LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.2.4 LBGA208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Appendix A Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Doc ID 14619 Rev 7 3/113 List of tables SPC560Bx, SPC560Cx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. 4/113 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPC560Bx and SPC560Cx device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SPC560Bx and SPC560Cx series block summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 OSCILLATOR_MARGIN field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 48 MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 49 FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 50 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I/O supply segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Low voltage power domain electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Code Flash power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 71 Crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 75 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 76 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 77 ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Table 49. Table 50. Table 51. Table 52. List of tables LBGA208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Order Codes for Engineering Samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Doc ID 14619 Rev 7 5/113 List of figures SPC560Bx, SPC560Cx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. 6/113 SPC560Bx and SPC560Cx series block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 LQFP 64-pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LQFP 100-pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LQFP 144-pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LBGA208 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Low voltage monitor vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 71 Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Equivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 74 ADC characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 DSPI classic SPI timing - master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 DSPI classic SPI timing - master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 DSPI classic SPI timing - slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 DSPI classic SPI timing - slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 DSPI modified transfer format timing - master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 92 DSPI modified transfer format timing - master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 93 DSPI modified transfer format timing - slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 93 DSPI modified transfer format timing - slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Timing diagram - JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 LQFP64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 LBGA208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx 1 Introduction 1.1 Document overview Introduction This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet. 1.2 Description This family of 32-bit system-on-chip (SoC) microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU, providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. Doc ID 14619 Rev 7 7/113 SPC560Bx and SPC560Cx device comparison(1) Device Feature SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 B40L1 B40L3 B40L5 C40L1 C40L3 B44L3 B44L5 C44L3 B50L1 B50L3 B50L5 C50L1 C50L3 B50B2 CPU e200z0h Execution speed(2) Static - up to 64 MHz Code Flash 256 KB 384 KB Data Flash 24 KB 32 KB 28 KB MPU 40 KB 32 KB 48 KB 8-entry Doc ID 14619 Rev 7 12 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit 8 ch, 10-bit 28 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit CTU Total timer I/O(3) eMIOS 512 KB 64 KB (4 x 16 KB) RAM ADC 28 ch, 10-bit 12 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit 8 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit Yes 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 28 ch, 16-bit 56ch, 16-bit 28 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit - PWM + MC + IC/OC(4) 2 ch 5 ch 10 ch 2 ch 5 ch 5 ch 10 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 10 ch - PWM + IC/OC(4) 10 ch 20 ch 40 ch 10 ch 20 ch 20 ch 40 ch 20 ch 10 ch 20 ch 40 ch 10 ch 20 ch 40 ch - IC/OC(4) 0 ch 3 ch 6 ch 0 ch 3 ch 3 ch 6 ch 3 ch 0 ch 3 ch 6 ch 0 ch 3 ch 6 ch CAN (FlexCAN) I2C 32 kHz oscillator 3 (5) 2 4 3 2(6) 2 3 3 3 5 6 3(7) 6 1 Yes 2 3 3(7) 2 3 5 6 SPC560Bx, SPC560Cx SCI (LINFlex) SPI (DSPI) Introduction 8/113 Table 2. SPC560Bx and SPC560Cx device comparison(1) (continued) Device Feature GPIO(8) SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 SPC560 B40L1 B40L3 B40L5 C40L1 C40L3 B44L3 B44L5 C44L3 B50L1 B50L3 B50L5 C50L1 C50L3 B50B2 45 79 123 45 79 79 Debug Package 123 79 45 79 123 45 79 JTAG LQFP 64(9) LQFP 100 LQFP 144 LQFP 64(9) LQFP 100 LQFP 100 LQFP 144 123 Nexus2+ LQFP 100 LQFP 64(9) LQFP 100 LQFP 144 LQFP 64(9) LQFP 100 LBGA 208(10) SPC560Bx, SPC560Cx Table 2. 1. Feature set dependent on selected peripheral multiplexing--table shows example implementation 2. Based on 105 C ambient operating temperature 3. Refer to eMIOS section of device reference manual for information on the channel configuration and functions 4. IC - Input Capture; OC - Output Compare; PWM - Pulse Width Modulation; MC - Modulus counter Doc ID 14619 Rev 7 5. SCI0, SCI1 and SCI2 are available. SCI3 is not available. 6. CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available. 7. CAN0, CAN1 and CAN2 are available. CAN3, CAN4 and CAN5 are not available. 8. I/O count based on multiplexing with peripherals 9. All LQFP64 information is indicative and must be confirmed during silicon validation. 10. LBGA208 available only as development package for Nexus2+ Introduction 9/113 Block diagram 2 SPC560Bx, SPC560Cx Block diagram Figure 1 shows a top-level block diagram of the SPC560Bx and SPC560Cx device series. SPC560Bx and SPC560Cx series block diagram SRAM 48 KB Code Flash Data Flash 512 KB 64 KB SRAM controller Flash controller eDMA JTAG Instructions Nexus port e200z0h Nexus (Master) Data NMI Nexus 2+ (Master) SIUL Voltage regulator Interrupt requests from peripheral blocks NMI INTC Clocks MPU (Master) JTAG port 64-bit 2 x 3 Crossbar Switch Figure 1. (Slave) (Slave) (Slave) MPU registers CMU FMPLL RTC STM SWT ECSM MC_RGM MC_CGM MC_ME PIT MC_PCU SSCM BAM Peripheral bridge Interrupt request SIUL Reset control 36 Ch. ADC 2x eMIOS CTU 4x LINFlex 3x DSPI 6x FlexCAN I2C External interrupt request IMUX WKPU GPIO and pad control I/O ... ... ... ... ... Legend: ADC BAM FlexCAN CMU CTU DSPI eDMA eMIOS FMPLL I2C IMUX INTC JTAG LINFlex ECSM 10/113 Analog-to-Digital Converter Boot Assist Module Controller Area Network Clock Monitor Unit Cross Triggering Unit Deserial Serial Peripheral Interface Enhanced Direct Memory Access Enhanced Modular Input Output System Frequency-Modulated Phase-Locked Loop Inter-integrated Circuit Bus Internal Multiplexer Interrupt Controller JTAG controller Serial Communication Interface (LIN support) Error Correction Status Module MC_CGM MC_ME MC_PCU MC_RGM MPU Nexus NMI PIT RTC SIUL SRAM SSCM STM SWT WKPU Doc ID 14619 Rev 7 Clock Generation Module Mode Entry Module Power Control Unit Reset Generation Module Memory Protection Unit Nexus Development Interface (NDI) Level Non-Maskable Interrupt Periodic Interrupt Timer Real-Time Clock System Integration Unit Lite Static Random-Access Memory System Status Configuration Module System Timer Module Software Watchdog Timer Wakeup Unit Interrupt request with wakeup functionality SPC560Bx, SPC560Cx Block diagram Table 3 summarizes the functions of all blocks present in the SPC560Bx and SPC560Cx series of microcontrollers. Please note that the presence and number of blocks varies by device and package. Table 3. SPC560Bx and SPC560Cx series block summary Block Function Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to digital-converter Boot assist module (BAM) A block of read-only memory containing VLE code which is executed according to the boot mode of the device Clock monitor unit (CMU) Monitors clock source (internal and external) integrity Cross triggering unit (CTU) Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT Deserial serial peripheral interface (DSPI) Provides a synchronous serial interface for communication with external devices Error Correction Status Module (ECSM) Provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host (eDMA) processor via "n" programmable channels. Enhanced modular input output system (eMIOS) Provides the functionality to generate or measure events Flash memory Provides non-volatile storage for program code, constants and variables FlexCAN (controller area network) Supports the standard CAN communications protocol FMPLL (frequency-modulated phase-locked loop) Generates high-speed system clocks and supports programmable frequency modulation Internal multiplexer (IMUX) SIU subblock Allows flexible mapping of peripheral interface on the different pins of the device Inter-integrated circuit (I2CTM) bus A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests JTAG controller Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode LINflex controller Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Clock generation module (MC_CGM) Provides logic and control required for the generation of system and peripheral clocks Mode entry module (MC_ME) Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Power control unit (MC_PCU) Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called "power domains" which are controlled by the PCU Doc ID 14619 Rev 7 11/113 Block diagram Table 3. SPC560Bx, SPC560Cx SPC560Bx and SPC560Cx series block summary (continued) Block Function Reset generation module (MC_RGM) Centralizes reset sources and manages the device reset sequence of the device Memory protection unit (MPU) Provides hardware access control for all memory references generated in a device Nexus development interface (NDI) Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2003 standard Periodic interrupt timer (PIT) Produces periodic interrupts and triggers Real-time counter (RTC) A free running counter used for time keeping applications, the RTC can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) System integration unit (SIU) Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration Static random-access memory (SRAM) Provides storage for program code, constants, and variables System status configuration module (SSCM) Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable System timer module (STM) Provides a set of output compare events to support AUTOSAR and operating system tasks System watchdog timer (SWT) Provides protection from runaway code Wakeup unit (WKPU) The wakeup unit supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. Crossbar (XBAR) switch Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width 12/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Package pinouts and signal descriptions 3 Package pinouts and signal descriptions 3.1 Package pinouts The available LQFP pinouts and the LBGA208 ballmap are provided in the following figures. For pin signal descriptions, please refer to the device reference manual (RM0017). LQFP 64-pin configuration (top view)(a) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PB[2] PC[8] PC[4] PC[5] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] Figure 2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LQFP64 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PA[11] PA[10] PA[9] PA[8] PA[7] PA[3] PB[15] PB[14] PB[13] PB[12] PB[11] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PB[4] 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PB[3] PC[9] PA[2] PA[1] PA[0] VPP_TEST VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[10] PB[0] PB[1] PC[6] a. All LQFP64 information is indicative and must be confirmed during silicon validation. Doc ID 14619 Rev 7 13/113 Package pinouts and signal descriptions LQFP 100-pin configuration (top view) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PE[12] Figure 3. SPC560Bx, SPC560Cx 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PA[11] PA[10] PA[9] PA[8] PA[7] VDD_HV VSS_HV PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4] 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PB[3] PC[9] PC[14] PC[15] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[11] PC[10] PB[0] PB[1] PC[6] Note: Availability of port pin alternate functions depends on product selection. LQFP 144-pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 PC[7] PF[10] PF[11] PA[15] PF[13] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4] 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PB[3] PC[9] PC[14] PC[15] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PG[9] PG[8] PC[11] PC[10] PG[7] PG[6] PB[0] PB[1] PF[9] PF[8] PF[12] PC[6] 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12] Figure 4. Note: Availability of port pin alternate functions depends on product selection. 14/113 Doc ID 14619 Rev 7 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PA[11] PA[10] PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13] PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC SPC560Bx, SPC560Cx Figure 5. Package pinouts and signal descriptions LBGA208 configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A PC[8] PC[13] NC NC PH[8] PH[4] PC[5] PC[0] NC NC PC[2] NC PE[15] NC NC NC A B PC[9] PB[2] NC PC[12] PE[6] PH[5] PC[4] PH[9] PH[10] NC PC[3] PG[11] PG[15] PG[14] PA[11] PA[10] B C PC[14] VDD_HV PB[3] PE[7] PH[7] PE[5] PE[3] VSS_LV PC[1] NC PA[5] NC PE[14] PE[12] PA[9] PA[8] C PH[6] PE[4] PE[2] VDD_LV VDD_HV NC PA[6] NC PG[10] PF[14] PE[13] PA[7] D D NC NC PC[15] NC E PG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[15] VDD_HV E F PE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2] F G PE[9] PE[8] PE[10] PA[0] VSS_HV VSS_HV VSS_HV VSS_HV VDD_HV NC NC MSEO G H VSS_HV PE[11] VDD_HV NC VSS_HV VSS_HV VSS_HV VSS_HV MDO3 MDO2 MDO0 MDO1 H J NC VSS_HV VSS_HV VSS_HV VSS_HV NC NC NC NC J VSS_HV VSS_HV VSS_HV VSS_HV NC PG[12] PA[3] PG[13] K RESET VSS_LV NC K EVTI NC L PG[9] PG[8] NC EVTO PB[15] PD[15] PD[14] PB[14] L M PG[7] PG[6] PC[10] PC[11] PB[13] PD[13] PD[12] PB[12] M N PB[1] PF[9] PB[0] NC NC PA[4] VSS_LV P PF[8] NC PC[7] NC NC PA[14] VDD_LV XTAL R PF[12] PC[6] PF[10] PF[11] VDD_HV PA[15] PA[13] T NC NC NC MCKO NC PF[13] 1 2 3 4 5 6 VDD_BV VDD_LV PF[0] PF[4] NC PB[11] PD[10] PD[9] PD[11] N PB[10] PF[1] PF[5] PD[0] PD[3] VDD_HV _ADC PB[6] PB[7] P NC OSC32K _XTAL PF[3] PF[7] PD[2] PD[4] PD[7] VSS_HV _ADC PB[5] R PA[12] NC OSC32K _EXTAL PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4] T 7 8 9 10 11 12 13 14 15 16 EXTAL VDD_HV Note: LBGA208 available only as development package for Nexus 2+. Doc ID 14619 Rev 7 NC = Not connected 15/113 Pin muxing Table 4 defines the pin list and muxing for this device. Each entry of Table 4 shows all the possible configurations for each pin, via the alternate functions. The default function assigned to each pin after reset is indicated by AF0. Table 4. Functional port pin descriptions Pin No. Port pin PA[0] Doc ID 14619 Rev 7 PA[1] PA[2] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[0] AF0 AF1 AF2 AF3 -- GPIO[0] E0UC[0] CLKOUT -- WKUP[19](4) SIUL eMIOS0 CGL -- WKPU I/O I/O O -- I M PCR[1] AF0 AF1 AF2 AF3 -- -- GPIO[1] E0UC[1] -- -- NMI(5) WKUP[2](4) SIUL eMIOS0 -- -- WKPU WKPU I/O I/O -- -- I I PCR[2] AF0 AF1 AF2 AF3 -- GPIO[2] E0UC[2] -- -- WKUP[3](4) SIUL eMIOS0 -- -- WKPU PCR[3] AF0 AF1 AF2 AF3 -- GPIO[3] E0UC[3] -- -- EIRQ[0] SIUL eMIOS0 -- -- SIUL LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate 5 12 16 G4 S Tristate 4 7 11 F3 I/O I/O -- -- I S Tristate 3 5 9 F2 I/O I/O -- -- I S Tristate 43 68 90 K15 SPC560Bx, SPC560Cx PA[3] PCR register Package pinouts and signal descriptions 16/113 3.2 Functional port pin descriptions (continued) Pin No. Port pin PA[4] PA[5] PA[7] PA[8] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[4] AF0 AF1 AF2 AF3 -- GPIO[4] E0UC[4] -- -- WKUP[9](4) SIUL eMIOS0 -- -- WKPU I/O I/O -- -- I S PCR[5] AF0 AF1 AF2 AF3 GPIO[5] E0UC[5] -- -- SIUL eMIOS0 -- -- I/O I/O -- -- PCR[6] AF0 AF1 AF2 AF3 -- GPIO[6] E0UC[6] -- -- EIRQ[1] SIUL eMIOS0 -- -- SIUL PCR[7] AF0 AF1 AF2 AF3 -- GPIO[7] E0UC[7] LIN3TX -- EIRQ[2] PCR[8] AF0 AF1 AF2 AF3 -- N/A(6) -- GPIO[8] E0UC[8] -- -- EIRQ[3] ABS[0] LIN3RX LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate 20 29 43 N6 M Tristate 51 79 118 C11 I/O I/O -- -- I S Tristate 52 80 119 D11 SIUL eMIOS0 LINFlex_3 -- SIUL I/O I/O O -- I S Tristate 44 71 104 D16 SIUL eMIOS0 -- -- SIUL BAM LINFlex_3 I/O I/O -- -- I I I S Input, weak pull-up 45 72 105 C16 17/113 Package pinouts and signal descriptions Doc ID 14619 Rev 7 PA[6] PCR register SPC560Bx, SPC560Cx Table 4. Functional port pin descriptions (continued) Pin No. Port pin PA[9] PA[10] Doc ID 14619 Rev 7 PA[11] PA[12] PA[13] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[9] AF0 AF1 AF2 AF3 N/A(6) GPIO[9] E0UC[9] -- -- FAB SIUL eMIOS_0 -- -- BAM I/O I/O -- -- I S PCR[10] AF0 AF1 AF2 AF3 GPIO[10] E0UC[10] SDA -- SIUL eMIOS_0 I2C_0 -- I/O I/O I/O -- PCR[11] AF0 AF1 AF2 AF3 GPIO[11] E0UC[11] SCL -- SIUL eMIOS0 I2C_0 -- PCR[12] AF0 AF1 AF2 AF3 -- GPIO[12] -- -- -- SIN_0 PCR[13] AF0 AF1 AF2 AF3 PCR[14] AF0 AF1 AF2 AF3 -- LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Pulldown 46 73 106 C15 S Tristate 47 74 107 B16 I/O I/O I/O -- S Tristate 48 75 108 B15 SIUL -- -- -- DSPI0 I/O -- -- -- I S Tristate 22 31 45 T7 GPIO[13] SOUT_0 -- -- SIUL DSPI_0 -- -- I/O O -- -- M Tristate 21 30 44 R7 GPIO[14] SCK_0 CS0_0 -- EIRQ[4] SIUL DSPI_0 DSPI_0 -- SIUL I/O I/O I/O -- I M Tristate 19 28 42 P6 SPC560Bx, SPC560Cx PA[14] PCR register Package pinouts and signal descriptions 18/113 Table 4. Functional port pin descriptions (continued) Pin No. Port pin PA[15] PB[0] PB[2] PB[3] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[15] AF0 AF1 AF2 AF3 -- GPIO[15] CS0_0 SCK_0 -- WKUP[10](4) SIUL DSPI_0 DSPI_0 -- WKPU I/O I/O I/O -- I M PCR[16] AF0 AF1 AF2 AF3 GPIO[16] CAN0TX -- -- SIUL FlexCAN_0 -- -- I/O O -- -- PCR[17] AF0 AF1 AF2 AF3 -- -- GPIO[17] -- -- -- WKUP[4](4) CAN0RX SIUL -- -- -- WKPU FlexCAN_0 PCR[18] AF0 AF1 AF2 AF3 GPIO[18] LIN0TX SDA -- PCR[19] AF0 AF1 AF2 AF3 -- -- GPIO[19] -- SCL -- WKUP[11](4) LIN0RX LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate 18 27 40 R6 M Tristate 14 23 31 N3 I/O -- -- -- I I S Tristate 15 24 32 N1 SIUL LINFlex_0 I2C_0 -- I/O O I/O -- M Tristate 64 100 144 B2 SIUL -- I2C_0 -- WKPU LINFlex_0 I/O -- I/O -- I I S Tristate 1 1 1 C3 19/113 Package pinouts and signal descriptions Doc ID 14619 Rev 7 PB[1] PCR register SPC560Bx, SPC560Cx Table 4. Functional port pin descriptions (continued) Pin No. Port pin PB[4] PB[5] Doc ID 14619 Rev 7 PB[6] PB[7] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[20] AF0 AF1 AF2 AF3 -- GPIO[20] -- -- -- ANP[0] SIUL -- -- -- ADC I -- -- -- I I PCR[21] AF0 AF1 AF2 AF3 -- GPIO[21] -- -- -- ANP[1] SIUL -- -- -- ADC I -- -- -- I PCR[22] AF0 AF1 AF2 AF3 -- GPIO[22] -- -- -- ANP[2] SIUL -- -- -- ADC PCR[23] AF0 AF1 AF2 AF3 -- GPIO[23] -- -- -- ANP[3] PCR[24] AF0 AF1 AF2 AF3 -- -- GPIO[24] -- -- -- ANS[0] OSC32K_XTAL(7) LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate 32 50 72 T16 I Tristate 35 53 75 R16 I -- -- -- I I Tristate 36 54 76 P15 SIUL -- -- -- ADC I -- -- -- I I Tristate 37 55 77 P16 SIUL -- -- -- ADC SXOSC I -- -- -- I I/O I Tristate 30 39 53 R9 SPC560Bx, SPC560Cx PB[8] PCR register Package pinouts and signal descriptions 20/113 Table 4. Functional port pin descriptions (continued) Pin No. Port pin PB[9] PB[11](8) PB[12] PB[13] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[25] AF0 AF1 AF2 AF3 -- -- GPIO[25] -- -- -- ANS[1] OSC32K_EXTAL(7) SIUL -- -- -- ADC SXOSC I -- -- -- I I/O I PCR[26] AF0 AF1 AF2 AF3 -- -- GPIO[26] -- -- -- ANS[2] WKUP[8](4) SIUL -- -- -- ADC WKPU I/O -- -- -- I I PCR[27] AF0 AF1 AF2 AF3 -- GPIO[27] E0UC[3] -- CS0_0 ANS[3] SIUL eMIOS_0 -- DSPI_0 ADC PCR[28] AF0 AF1 AF2 AF3 -- GPIO[28] E0UC[4] -- CS1_0 ANX[0] PCR[29] AF0 AF1 AF2 AF3 -- GPIO[29] E0UC[5] -- CS2_0 ANX[1] LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate 29 38 52 T9 J Tristate 31 40 54 P9 I/O I/O -- I/O I J Tristate 38 59 81 N13 SIUL eMIOS -- DSPI_0 ADC I/O I/O -- O I J Tristate 39 61 83 M16 SIUL eMIOS_0 -- DSPI_0 ADC I/O I/O -- O I J Tristate 40 63 85 M13 21/113 Package pinouts and signal descriptions Doc ID 14619 Rev 7 PB[10] PCR register SPC560Bx, SPC560Cx Table 4. Functional port pin descriptions (continued) Pin No. Port pin PB[14] PB[15] Doc ID 14619 Rev 7 PC[0](9) PC[1](9) PC[2] PCR register Alternate function(1) Pad type RESET config. Function PCR[30] AF0 AF1 AF2 AF3 -- GPIO[30] E0UC[6] -- CS3_0 ANX[2] SIUL eMIOS0 -- DSPI_0 ADC I/O I/O -- O I J PCR[31] AF0 AF1 AF2 AF3 -- GPIO[31] E0UC[7] -- CS4_0 ANX[3] SIUL eMIOS_0 -- DSPI_0 ADC I/O I/O -- O I PCR[32] AF0 AF1 AF2 AF3 GPIO[32] -- TDI -- SIUL -- JTAGC -- PCR[33] AF0 AF1 AF2 AF3 GPIO[33] -- TDO(10) -- PCR[34] AF0 AF1 AF2 AF3 -- GPIO[34] SCK_1 CAN4TX(11) -- EIRQ[5] LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate 41 65 87 L16 J Tristate 42 67 89 L13 I/O -- I -- M Input, weak pull-up 59 87 126 A8 SIUL -- JTAGC -- I/O -- O -- M Tristate 54 82 121 C9 SIUL DSPI_1 LINFlex_4 -- SIUL I/O I/O O -- I M Tristate 50 78 117 A11 SPC560Bx, SPC560Cx Peripheral I/O direction(2) Package pinouts and signal descriptions 22/113 Table 4. Functional port pin descriptions (continued) Pin No. Port pin PC[3] PC[5] PC[6] PC[7] Alternate function(1) 23/113 Peripheral I/O direction(2) Pad type RESET config. Function PCR[35] AF0 AF1 AF2 AF3 -- -- -- GPIO[35] CS0_1 MA[0] -- CAN1RX CAN4RX(11) EIRQ[6] SIUL DSPI_1 ADC -- FlexCAN_1 FlexCAN_4 SIUL I/O I/O O -- I I I S PCR[36] AF0 AF1 AF2 AF3 -- -- GPIO[36] -- -- -- SIN_1 CAN3RX(11) SIUL -- -- -- DSPI_1 FlexCAN_3 I/O -- -- -- I I PCR[37] AF0 AF1 AF2 AF3 -- GPIO[37] SOUT_1 CAN3TX(11) -- EIRQ[7] SIUL DSPI1 FlexCAN_3 -- SIUL PCR[38] AF0 AF1 AF2 AF3 GPIO[38] LIN1TX -- -- PCR[39] AF0 AF1 AF2 AF3 -- -- GPIO[39] -- -- -- LIN1RX WKUP[12](4) LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate 49 77 116 B11 M Tristate 62 92 131 B7 I/O O O -- I M Tristate 61 91 130 A7 SIUL LINFlex_1 -- -- I/O O -- -- S Tristate 16 25 36 R2 SIUL -- -- -- LINFlex_1 WKPU I/O -- -- -- I I S Tristate 17 26 37 P3 Package pinouts and signal descriptions Doc ID 14619 Rev 7 PC[4] PCR register SPC560Bx, SPC560Cx Table 4. Functional port pin descriptions (continued) Pin No. Port pin PC[8] PC[9] Doc ID 14619 Rev 7 PC[10] PC[11] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[40] AF0 AF1 AF2 AF3 GPIO[40] LIN2TX -- -- SIUL LINFlex_2 -- -- I/O O -- -- S PCR[41] AF0 AF1 AF2 AF3 -- -- GPIO[41] -- -- -- LIN2RX WKUP[13](4) SIUL -- -- -- LINFlex_2 WKPU I/O -- -- -- I I PCR[42] AF0 AF1 AF2 AF3 GPIO[42] CAN1TX CAN4TX(11) MA[1] SIUL FlexCAN_1 FlexCAN_4 ADC PCR[43] AF0 AF1 AF2 AF3 -- -- -- GPIO[43] -- -- -- CAN1RX CAN4RX(11) WKUP[5](4) PCR[44] AF0 AF1 AF2 AF3 -- GPIO[44] E0UC[12] -- -- SIN_2 LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate 63 99 143 A1 S Tristate 2 2 2 B1 I/O O O O M Tristate 13 22 28 M3 SIUL -- -- -- FlexCAN_1 FlexCAN_4 WKPU I/O -- -- -- I I I S Tristate -- 21 27 M4 SIUL eMIOS_0 -- -- DSPI_2 I/O I/O -- -- I M Tristate -- 97 141 B4 SPC560Bx, SPC560Cx PC[12] PCR register Package pinouts and signal descriptions 24/113 Table 4. Functional port pin descriptions (continued) Pin No. Port pin PC[13] PC[14] PD[0] PD[1] PD[2] Alternate function(1) 25/113 Peripheral I/O direction(2) Pad type RESET config. Function PCR[45] AF0 AF1 AF2 AF3 GPIO[45] E0UC[13] SOUT_2 -- SIUL eMIOS_0 DSPI_2 -- I/O I/O O -- S PCR[46] AF0 AF1 AF2 AF3 -- GPIO[46] E0UC[14] SCK_2 -- EIRQ[8] SIUL eMIOS_0 DSPI_2 -- SIUL I/O I/O I/O -- I PCR[47] AF0 AF1 AF2 AF3 GPIO[47] E0UC[15] CS0_2 -- SIUL eMIOS_0 DSPI_2 -- PCR[48] AF0 AF1 AF2 AF3 -- GPIO[48] -- -- -- ANP[4] PCR[49] AF0 AF1 AF2 AF3 -- PCR[50] AF0 AF1 AF2 AF3 -- LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate -- 98 142 A2 S Tristate -- 3 3 C1 I/O I/O I/O -- M Tristate -- 4 4 D3 SIUL -- -- -- ADC I -- -- -- I I Tristate -- 41 63 P12 GPIO[49] -- -- -- ANP[5] SIUL -- -- -- ADC I -- -- -- I I Tristate -- 42 64 T12 GPIO[50] -- -- -- ANP[6] SIUL -- -- -- ADC I -- -- -- I I Tristate -- 43 65 R12 Package pinouts and signal descriptions Doc ID 14619 Rev 7 PC[15] PCR register SPC560Bx, SPC560Cx Table 4. Functional port pin descriptions (continued) Pin No. Port pin PD[3] PD[4] Doc ID 14619 Rev 7 PD[5] PD[6] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[51] AF0 AF1 AF2 AF3 -- GPIO[51] -- -- -- ANP[7] SIUL -- -- -- ADC I -- -- -- I I PCR[52] AF0 AF1 AF2 AF3 -- GPIO[52] -- -- -- ANP[8] SIUL -- -- -- ADC I -- -- -- I PCR[53] AF0 AF1 AF2 AF3 -- GPIO[53] -- -- -- ANP[9] SIUL -- -- -- ADC PCR[54] AF0 AF1 AF2 AF3 -- GPIO[54] -- -- -- ANP[10] PCR[55] AF0 AF1 AF2 AF3 -- GPIO[55] -- -- -- ANP[11] LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate -- 44 66 P13 I Tristate -- 45 67 R13 I -- -- -- I I Tristate -- 46 68 T13 SIUL -- -- -- ADC I -- -- -- I I Tristate -- 47 69 T14 SIUL -- -- -- ADC I -- -- -- I I Tristate -- 48 70 R14 SPC560Bx, SPC560Cx PD[7] PCR register Package pinouts and signal descriptions 26/113 Table 4. Functional port pin descriptions (continued) Pin No. Port pin PD[8] PD[9] PD[11] PD[12](8) Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[56] AF0 AF1 AF2 AF3 -- GPIO[56] -- -- -- ANP[12] SIUL -- -- -- ADC I -- -- -- I I PCR[57] AF0 AF1 AF2 AF3 -- GPIO[57] -- -- -- ANP[13] SIUL -- -- -- ADC I -- -- -- I PCR[58] AF0 AF1 AF2 AF3 -- GPIO[58] -- -- -- ANP[14] SIUL -- -- -- ADC PCR[59] AF0 AF1 AF2 AF3 -- GPIO[59] -- -- -- ANP[15] PCR[60] AF0 AF1 AF2 AF3 -- GPIO[60] CS5_0 E0UC[24] -- ANS[4] LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate -- 49 71 T15 I Tristate -- 56 78 N15 I -- -- -- I I Tristate -- 57 79 N14 SIUL -- -- -- ADC I -- -- -- I I Tristate -- 58 80 N16 SIUL DSPI_0 eMIOS_0 -- ADC I/O O I/O -- I J Tristate -- 60 82 M15 27/113 Package pinouts and signal descriptions Doc ID 14619 Rev 7 PD[10] PCR register SPC560Bx, SPC560Cx Table 4. Functional port pin descriptions (continued) Pin No. Port pin PD[13] PD[14] Doc ID 14619 Rev 7 PD[15] PE[0] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[61] AF0 AF1 AF2 AF3 -- GPIO[61] CS0_1 E0UC[25] -- ANS[5] SIUL DSPI_1 eMIOS_0 -- ADC I/O I/O I/O -- I J PCR[62] AF0 AF1 AF2 AF3 -- GPIO[62] CS1_1 E0UC[26] -- ANS[6] SIUL DSPI_1 eMIOS_0 -- ADC I/O O I/O -- I PCR[63] AF0 AF1 AF2 AF3 -- GPIO[63] CS2_1 E0UC[27] -- ANS[7] SIUL DSPI_1 eMIOS_0 -- ADC PCR[64] AF0 AF1 AF2 AF3 -- -- GPIO[64] E0UC[16] -- -- CAN5RX(11) WKUP[6](4) PCR[65] AF0 AF1 AF2 AF3 GPIO[65] E0UC[17] CAN5TX(11) -- LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate -- 62 84 M14 J Tristate -- 64 86 L15 I/O O I/O -- I J Tristate -- 66 88 L14 SIUL eMIOS_0 -- -- FlexCAN_5 WKPU I/O I/O -- -- I I S Tristate -- 6 10 F1 SIUL eMIOS_0 FlexCAN_5 -- I/O I/O O -- M Tristate -- 8 12 F4 SPC560Bx, SPC560Cx PE[1] PCR register Package pinouts and signal descriptions 28/113 Table 4. Functional port pin descriptions (continued) Pin No. Port pin PE[2] PE[3] PE[5] PE[6] PE[7] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[66] AF0 AF1 AF2 AF3 -- GPIO[66] E0UC[18] -- -- SIN_1 SIUL eMIOS0 -- -- DSPI_1 I/O I/O -- -- I M PCR[67] AF0 AF1 AF2 AF3 GPIO[67] E0UC[19] SOUT_1 -- SIUL eMIOS0 DSPI_1 -- I/O I/O O -- PCR[68] AF0 AF1 AF2 AF3 -- GPIO[68] E0UC[20] SCK_1 -- EIRQ[9] SIUL eMIOS0 DSPI_1 -- SIUL PCR[69] AF0 AF1 AF2 AF3 GPIO[69] E0UC[21] CS0_1 MA[2] PCR[70] AF0 AF1 AF2 AF3 PCR[71] AF0 AF1 AF2 AF3 LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate -- 89 128 D7 M Tristate -- 90 129 C7 I/O I/O I/O -- I M Tristate -- 93 132 D6 SIUL eMIOS_0 DSPI_1 ADC I/O I/O I/O O M Tristate -- 94 133 C6 GPIO[70] E0UC[22] CS3_0 MA[1] SIUL eMIOS_0 DSPI_0 ADC I/O I/O O O M Tristate -- 95 139 B5 GPIO[71] E0UC[23] CS2_0 MA[0] SIUL eMIOS_0 DSPI_0 ADC I/O I/O O O M Tristate -- 96 140 C4 29/113 Package pinouts and signal descriptions Doc ID 14619 Rev 7 PE[4] PCR register SPC560Bx, SPC560Cx Table 4. Functional port pin descriptions (continued) Pin No. Port pin PE[8] PE[9] Doc ID 14619 Rev 7 PE[10] PE[11] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[72] AF0 AF1 AF2 AF3 GPIO[72] CAN2TX(12) E0UC[22] CAN3TX(11) SIUL FlexCAN_2 I/O FlexCAN_3 I/O O eMIOS0 O M PCR[73] AF0 AF1 AF2 AF3 -- -- -- GPIO[73] -- E0UC[23] -- WKUP[7](4) CAN2RX(12) CAN3RX(11) SIUL -- eMIOS_0 -- WKPU FlexCAN_2 FlexCAN_3 I/O -- I/O -- I I I PCR[74] AF0 AF1 AF2 AF3 -- GPIO[74] LIN3TX CS3_1 -- EIRQ[10] SIUL LINFlex_3 DSPI_1 -- SIUL PCR[75] AF0 AF1 AF2 AF3 -- -- GPIO[75] -- CS4_1 -- LIN3RX WKUP[14](4) PCR[76] AF0 AF1 AF2 AF3 -- -- GPIO[76] -- E1UC[19](13) -- SIN_2 EIRQ[11] LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate -- 9 13 G2 S Tristate -- 10 14 G1 I/O O O -- I S Tristate -- 11 15 G3 SIUL -- DSPI_1 -- LINFlex_3 WKPU I/O -- O -- I I S Tristate -- 13 17 H2 SIUL -- eMIOS_1 -- DSPI_2 SIUL I/O -- I/O -- I I S Tristate -- 76 109 C14 SPC560Bx, SPC560Cx PE[12] PCR register Package pinouts and signal descriptions 30/113 Table 4. Functional port pin descriptions (continued) Pin No. Port pin PE[13] PE[14] PF[0] PF[1] PF[2] Alternate function(1) 31/113 Peripheral I/O direction(2) Pad type RESET config. Function PCR[77] AF0 AF1 AF2 AF3 GPIO[77] SOUT2 E1UC[20] -- SIUL DSPI_2 eMIOS_1 -- I/O O I/O -- S PCR[78] AF0 AF1 AF2 AF3 -- GPIO[78] SCK_2 E1UC[21] -- EIRQ[12] SIUL DSPI_2 eMIOS_1 -- SIUL I/O I/O I/O -- I PCR[79] AF0 AF1 AF2 AF3 GPIO[79] CS0_2 E1UC[22] -- SIUL DSPI_2 eMIOS_1 -- PCR[80] AF0 AF1 AF2 AF3 -- GPIO[80] E0UC[10] CS3_1 -- ANS[8] PCR[81] AF0 AF1 AF2 AF3 -- PCR[82] AF0 AF1 AF2 AF3 -- LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate -- -- 103 D15 S Tristate -- -- 112 C13 I/O I/O I/O -- M Tristate -- -- 113 A13 SIUL eMIOS_0 DSPI_1 -- ADC I/O I/O O -- I J Tristate -- -- 55 N10 GPIO[81] E0UC[11] CS4_1 -- ANS[9] SIUL eMIOS_0 DSPI_1 -- I I/O I/O O -- I J Tristate -- -- 56 P10 GPIO[82] E0UC[12] CS0_2 -- ANS[10] SIUL eMIOS_0 DSPI_2 -- ADC I/O I/O I/O -- I J Tristate -- -- 57 T10 Package pinouts and signal descriptions Doc ID 14619 Rev 7 PE[15] PCR register SPC560Bx, SPC560Cx Table 4. Functional port pin descriptions (continued) Pin No. Port pin PF[3] PF[4] Doc ID 14619 Rev 7 PF[5] PF[6] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[83] AF0 AF1 AF2 AF3 -- GPIO[83] E0UC[13] CS1_2 -- ANS[11] SIUL eMIOS_0 DSPI_2 -- ADC I/O I/O O -- I J PCR[84] AF0 AF1 AF2 AF3 -- GPIO[84] E0UC[14] CS2_2 -- ANS[12] SIUL eMIOS_0 DSPI_2 -- ADC I/O I/O O -- I PCR[85] AF0 AF1 AF2 AF3 -- GPIO[85] E0UC[22] CS3_2 -- ANS[13] SIUL eMIOS_0 DSPI_2 -- ADC PCR[86] AF0 AF1 AF2 AF3 -- GPIO[86] E0UC[23] -- -- ANS[14] PCR[87] AF0 AF1 AF2 AF3 -- GPIO[87] -- -- -- ANS[15] LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate -- -- 58 R10 J Tristate -- -- 59 N11 I/O I/O O -- I J Tristate -- -- 60 P11 SIUL eMIOS_0 -- -- ADC I/O I/O -- -- I J Tristate -- -- 61 T11 SIUL -- -- -- ADC I/O -- -- -- I J Tristate -- -- 62 R11 SPC560Bx, SPC560Cx PF[7] PCR register Package pinouts and signal descriptions 32/113 Table 4. Functional port pin descriptions (continued) Pin No. Port pin PF[8] PF[9] PF[11] PF[12] PF[13] Alternate function(1) 33/113 Peripheral I/O direction(2) Pad type RESET config. Function PCR[88] AF0 AF1 AF2 AF3 GPIO[88] CAN3TX(14) CS4_0 CAN2TX(15) SIUL FlexCAN_3 DSPI_0 FlexCAN_2 I/O O O O M PCR[89] AF0 AF1 AF2 AF3 -- -- GPIO[89] -- CS5_0 -- CAN2RX(15) CAN3RX(14) SIUL -- DSPI_0 -- FlexCAN_2 FlexCAN_3 I/O -- O -- I I PCR[90] AF0 AF1 AF2 AF3 GPIO[90] -- -- -- SIUL -- -- -- PCR[91] AF0 AF1 AF2 AF3 -- GPIO[91] -- -- -- WKUP[15](4) PCR[92] AF0 AF1 AF2 AF3 PCR[93] AF0 AF1 AF2 AF3 -- LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate -- -- 34 P1 S Tristate -- -- 33 N2 I/O -- -- -- M Tristate -- -- 38 R3 SIUL -- -- -- WKPU I/O -- -- -- I S Tristate -- -- 39 R4 GPIO[92] E1UC[25] -- -- SIUL eMIOS_1 -- -- I/O I/O -- -- M Tristate -- -- 35 R1 GPIO[93] E1UC[26] -- -- WKUP[16](4) SIUL eMIOS_1 -- -- WKPU I/O I/O -- -- I S Tristate -- -- 41 T6 Package pinouts and signal descriptions Doc ID 14619 Rev 7 PF[10] PCR register SPC560Bx, SPC560Cx Table 4. Functional port pin descriptions (continued) Pin No. Port pin PF[14] PF[15] Doc ID 14619 Rev 7 PG[0] PG[1] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[94] AF0 AF1 AF2 AF3 GPIO[94] CAN4TX(11) E1UC[27] CAN1TX SIUL FlexCAN_4 eMIOS_1 FlexCAN_4 I/O O I/O O M PCR[95] AF0 AF1 AF2 AF3 -- -- -- GPIO[95] -- -- -- CAN1RX CAN4RX(11) EIRQ[13] SIUL -- -- -- FlexCAN_1 FlexCAN_4 SIUL I/O -- -- -- I I I PCR[96] AF0 AF1 AF2 AF3 GPIO[96] CAN5TX(11) E1UC[23] -- SIUL FlexCAN_5 eMIOS_1 -- PCR[97] AF0 AF1 AF2 AF3 -- -- GPIO[97] -- E1UC[24] -- CAN5RX(11) EIRQ[14] PCR[98] AF0 AF1 AF2 AF3 GPIO[98] E1UC[11] -- -- LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate -- -- 102 D14 S Tristate -- -- 101 E15 I/O O I/O -- M Tristate -- -- 98 E14 SIUL -- eMIOS_1 -- FlexCAN_5 SIUL I/O -- I/O -- I I S Tristate -- -- 97 E13 SIUL eMIOS_1 -- -- I/O I/O -- -- M Tristate -- -- 8 E4 SPC560Bx, SPC560Cx PG[2] PCR register Package pinouts and signal descriptions 34/113 Table 4. Functional port pin descriptions (continued) Pin No. Port pin PG[3] PG[4] PG[6] PG[7] PG[8] Alternate function(1) 35/113 Peripheral I/O direction(2) Pad type RESET config. Function PCR[99] AF0 AF1 AF2 AF3 -- GPIO[99] E1UC[12] -- -- WKUP[17](4) SIUL eMIOS_1 -- -- WKPU I/O I/O -- -- I S PCR[100] AF0 AF1 AF2 AF3 GPIO[100] E1UC[13] -- -- SIUL eMIOS_1 -- -- I/O I/O -- -- PCR[101] AF0 AF1 AF2 AF3 -- GPIO[101] E1UC[14] -- -- WKUP[18](4) SIUL eMIOS_1 -- -- WKPU PCR[102] AF0 AF1 AF2 AF3 GPIO[102] E1UC[15] -- -- PCR[103] AF0 AF1 AF2 AF3 PCR[104] AF0 AF1 AF2 AF3 -- LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate -- -- 7 E3 M Tristate -- -- 6 E1 I/O I/O -- -- I S Tristate -- -- 5 E2 SIUL eMIOS_1 -- -- I/O I/O -- -- M Tristate -- -- 30 M2 GPIO[103] E1UC[16] -- -- SIUL eMIOS_1 -- -- I/O I/O -- -- M Tristate -- -- 29 M1 GPIO[104] E1UC[17] -- CS0_2 EIRQ[15] SIUL eMIOS_1 -- DSPI_2 SIUL I/O I/O -- I/O I S Tristate -- -- 26 L2 Package pinouts and signal descriptions Doc ID 14619 Rev 7 PG[5] PCR register SPC560Bx, SPC560Cx Table 4. Functional port pin descriptions (continued) Pin No. Port pin PG[9] PG[10] Doc ID 14619 Rev 7 PG[11] PG[12] PG[13] PG[15] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[105] AF0 AF1 AF2 AF3 GPIO[105] E1UC[18] -- SCK_2 SIUL eMIOS1 -- DSPI_2 I/O I/O -- I/O S PCR[106] AF0 AF1 AF2 AF3 GPIO[106] E0UC[24] -- -- SIUL eMIOS_0 -- -- I/O I/O -- -- PCR[107] AF0 AF1 AF2 AF3 GPIO[107] E0UC[25] -- -- SIUL eMIOS_0 -- -- PCR[108] AF0 AF1 AF2 AF3 GPIO[108] E0UC[26] -- -- PCR[109] AF0 AF1 AF2 AF3 LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate -- -- 25 L1 S Tristate -- -- 114 D13 I/O I/O -- -- M Tristate -- -- 115 B12 SIUL eMIOS_0 -- -- I/O I/O -- -- M Tristate -- -- 92 K14 GPIO[109] E0UC[27] -- -- SIUL eMIOS_0 -- -- I/O I/O -- -- M Tristate -- -- 91 K16 PCR[110] AF0 AF1 AF2 AF3 GPIO[110] E1UC[0] -- -- SIUL eMIOS_1 -- -- I/O I/O -- -- S Tristate -- -- 110 B14 PCR[111] AF0 AF1 AF2 AF3 GPIO[111] E1UC[1] -- -- SIUL eMIOS_1 -- -- I/O I/O -- -- M Tristate -- -- 111 B13 SPC560Bx, SPC560Cx PG[14] PCR register Package pinouts and signal descriptions 36/113 Table 4. Functional port pin descriptions (continued) Pin No. Port pin PH[0] PH[1] PH[3] PH[4] PH[5] Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[112] AF0 AF1 AF2 AF3 -- GPIO[112] E1UC[2] -- -- SIN1 SIUL eMIOS_1 -- -- DSPI_1 I/O I/O -- -- I M PCR[113] AF0 AF1 AF2 AF3 GPIO[113] E1UC[3] SOUT1 -- SIUL eMIOS_1 DSPI_1 -- I/O I/O O -- PCR[114] AF0 AF1 AF2 AF3 GPIO[114] E1UC[4] SCK_1 -- SIUL eMIOS_1 DSPI_1 -- PCR[115] AF0 AF1 AF2 AF3 GPIO[115] E1UC[5] CS0_1 -- PCR[116] AF0 AF1 AF2 AF3 PCR[117] AF0 AF1 AF2 AF3 LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate -- -- 93 F13 M Tristate -- -- 94 F14 I/O I/O I/O -- M Tristate -- -- 95 F16 SIUL eMIOS_1 DSPI_1 -- I/O I/O I/O -- M Tristate -- -- 96 F15 GPIO[116] E1UC[6] -- -- SIUL eMIOS_1 -- -- I/O I/O -- -- M Tristate -- -- 134 A6 GPIO[117] E1UC[7] -- -- SIUL eMIOS_1 -- -- I/O I/O -- -- S Tristate -- -- 135 B6 37/113 Package pinouts and signal descriptions Doc ID 14619 Rev 7 PH[2] PCR register SPC560Bx, SPC560Cx Table 4. Functional port pin descriptions (continued) Pin No. Port pin PH[6] PH[7] Doc ID 14619 Rev 7 PH[8] PH[9](9) PH[10](9) PCR register Alternate function(1) Peripheral I/O direction(2) Pad type RESET config. Function PCR[118] AF0 AF1 AF2 AF3 GPIO[118] E1UC[8] -- MA[2] SIUL eMIOS_1 -- ADC I/O I/O -- O M PCR[119] AF0 AF1 AF2 AF3 GPIO[119] E1UC[9] CS3_2 MA[1] SIUL eMIOS_1 DSPI_2 ADC I/O I/O O O PCR[120] AF0 AF1 AF2 AF3 GPIO[120] E1UC[10] CS2_2 MA[0] SIUL eMIOS_1 DSPI_2 ADC PCR[121] AF0 AF1 AF2 AF3 GPIO[121] -- TCK -- PCR[122] AF0 AF1 AF2 AF3 GPIO[122] -- TMS -- LQFP 64 LQFP 100 LQFP 144 LBGA 208(3) Tristate -- -- 136 D5 M Tristate -- -- 137 C5 I/O I/O O O M Tristate -- -- 138 A5 SIUL -- JTAGC -- I/O -- I -- S Input, weak pull-up -- 88 127 B8 SIUL -- JTAGC -- I/O -- I -- S Input, weak pull-up -- 81 120 B9 2. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx bitfields inside the SIUL module. 3. LBGA208 available only as development package for Nexus2+ 4. All WKUP pins also support external interrupt capability. See wakeup unit chapter for further details. 5. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored. 6. "Not applicable" because these functions are available only while the device is booting. Refer to BAM chapter of the reference manual for details. SPC560Bx, SPC560Cx 1. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00 -> AF0; PCR.PA = 01 -> AF1; PCR.PA = 10 -> AF2; PCR.PA = 11 -> AF3. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to `1', regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as "--". Package pinouts and signal descriptions 38/113 Table 4. 8. This pad is used on SPC560B64L3 and SPC560B64L5 to provide supply for the second ADC. Therefore it is recommended not using it to keep the compatibility with the family devices. 9. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO. PC[0:1] are available as JTAG pins (TDI and TDO respectively). PH[9:10] are available as JTAG pins (TCK and TMS respectively). It is up to the user to configure these pins as GPIO when needed, in this case SPC560Bx and SPC560Cx get incompliance with IEEE 1149.1-2001. 10. The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in STANDBY mode. However, no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad is configured as an input. When no debugger is connected the TDO pad is floating causing additional current consumption. To avoid the extra consumption TDO must be connected. An external pull-up resistor in the range of 47-100 kOhms should be added between the TDO pin and VDD. Only in case the TDO pin is used as application pin and a pull-up cannot be used then a pull-down resistor with the same value should be used between TDO pin and GND instead. SPC560Bx, SPC560Cx 7. Value of PCR.IBE bit must be 0 11. Available only on SPC560Cx versions and SPC560B50B2 devices 12. Not available on SPC560B40L3 and SPC560B40L5 devices 13. Not available in LQFP100 package 14. Available only on SPC560B50B2 devices 15. Not available on SPC560B44L3 devices 39/113 Package pinouts and signal descriptions Doc ID 14619 Rev 7 Electrical characteristics SPC560Bx, SPC560Cx 4 Electrical characteristics 4.1 Introduction This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol "SR" for System Requirement is included in the Symbol column. Caution: All LQFP64 information is indicative and must be confirmed during silicon validation. 4.2 Parameter classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 5 are used and the parameters are tagged accordingly in the tables where appropriate. Table 5. Parameter classifications Classification tag Note: 40/113 Tag description P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. The classification is shown in the column labeled "C" in the parameter tables where appropriate. Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx 4.3 Electrical characteristics NVUSRO register Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are controlled via bit values in the Non-Volatile User Options Register (NVUSRO) register. 4.3.1 NVUSRO[PAD3V5V] field description Table 6 shows how NVUSRO[PAD3V5V] controls the device configuration. PAD3V5V field description(1) Table 6. Value(2) Description 0 High voltage supply is 5.0 V 1 High voltage supply is 3.3 V 1. See the device reference manual for more information on the NVUSRO register. 2. '1' is delivery value. It is part of shadow Flash, thus programmable by customer. The DC electrical characteristics are dependent on the PAD3V5V bit value. 4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description Table 7 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration. OSCILLATOR_MARGIN field description(1) Table 7. Value(2) Description 0 Low consumption configuration (4 MHz/8 MHz) 1 High margin configuration (4 MHz/16 MHz) 1. See the device reference manual for more information on the NVUSRO register. 2. '1' is delivery value. It is part of shadow Flash, thus programmable by customer. The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. For a detailed description of the NVUSRO register, please refer to the SPC560Bx and SPC560Cx Reference Manual. 4.4 Absolute maximum ratings Table 8. Absolute maximum ratings Value Symbol Parameter Conditions VSS SR Digital ground on VSS_HV pins VDD SR Voltage on VDD_HV pins with respect to ground (VSS) Doc ID 14619 Rev 7 Unit Min Max -- 0 0 V -- 0.3 6.0 V 41/113 Electrical characteristics Table 8. SPC560Bx, SPC560Cx Absolute maximum ratings (continued) Value Symbol Parameter Conditions Unit Min VSS_LV SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) VDD_BV SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) VDD_ADC SR Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) Voltage on any GPIO pin with respect to ground (VSS) VIN SR IINJPAD SR Injected input current on any pin during overload condition IINJSUM SR Absolute sum of all injected input currents during overload condition -- -- Relative to VDD -- -- Relative to VDD Max VSS0.1 VSS+0.1 0.3 6.0 0.3 VDD+0.3 V V VSS0.1 VSS+0.1 0.3 V 6.0 VDD 0.3 VDD+0.3 V 0.3 6.0 -- VDD+0.3 -- 10 10 -- 50 50 VDD = 5.0 V 10%, PAD3V5V = 0 -- 70 VDD = 3.3 V 10%, PAD3V5V = 1 -- 64 -- -- 150 mA -- 55 150 C -- V Relative to VDD mA IAVGSEG ICORELV Sum of all the static I/O current within a supply SR segment mA SR Low voltage static current sink through VDD_BV TSTORAGE SR Storage temperature Note: Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values. 4.5 Recommended operating conditions Table 9. Recommended operating conditions (3.3 V) Value Symbol VSS Parameter SR Digital ground on VSS_HV pins Conditions Unit Min Max -- 0 0 V VDD(1) SR Voltage on VDD_HV pins with respect to ground (VSS) -- 3.0 3.6 V VSS_LV(2) SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) -- VSS0.1 VSS+0.1 V 42/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Table 9. Electrical characteristics Recommended operating conditions (3.3 V) (continued) Value Symbol Parameter Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) Conditions Unit Min Max 3.0 3.6 VDD0.1 VDD+0.1 -- VSS0.1 VSS+0.1 -- 3.0(5) 3.6 VDD0.1 VDD+0.1 VSS0.1 -- -- VDD+0.1 -- VDD_BV(3) SR VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) VDD_ADC(4) SR Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) VIN SR IINJPAD SR Injected input current on any pin during overload condition -- 5 5 IINJSUM SR Absolute sum of all injected input currents during overload condition -- 50 50 -- -- 0.25 Voltage on any GPIO pin with respect to ground (VSS) Relative to VDD Relative to VDD -- Relative to VDD V V V V mA TVDD SR VDD slope to ensure correct power up(6) V/s 1. 100 nF capacitance needs to be provided between each VDD/VSS pair 2. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 3. 400 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 4. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. 5. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is reset. 6. Guaranteed by device validation Table 10. Recommended operating conditions (5.0 V) Value Symbol VSS Parameter SR Digital ground on VSS_HV pins Voltage on VDD_HV pins with respect to ground (VSS) VDD(1) SR VSS_LV(3) SR VDD_BV(4) Voltage on VDD_BV pin (regulator supply) with SR respect to ground (VSS) Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) Conditions Max -- 0 0 -- 4.5 5.5 Voltage drop(2) 3.0 5.5 -- -- VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS Doc ID 14619 Rev 7 Unit Min Voltage drop(2) V V VSS0.1 VSS+0.1 4.5 5.5 3.0 5.5 V V Relative to VDD VDD0.1 VDD+0.1 -- VSS0.1 VSS+0.1 V 43/113 Electrical characteristics Table 10. SPC560Bx, SPC560Cx Recommended operating conditions (5.0 V) (continued) Value Symbol Parameter Conditions Unit -- VDD_ADC(5) Voltage on VDD_HV_ADC pin (ADC reference) with SR respect to ground (VSS) VIN SR IINJPAD SR IINJSUM SR Voltage drop(2) Min Max 4.5 5.5 3.0 5.5 Relative to VDD VDD0.1 VDD+0.1 -- VSS0.1 -- Relative to VDD -- VDD+0.1 Injected input current on any pin during overload condition -- 5 5 Absolute sum of all injected input currents during overload condition -- 50 50 -- -- 0.25 Voltage on any GPIO pin with respect to ground (VSS) V V mA TVDD SR VDD slope to ensure correct power up(6) V/s 1. 100 nF capacitance needs to be provided between each VDD/VSS pair. 2. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits. 3. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 4. 100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 5. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. 6. Guaranteed by device validation Note: RAM data retention is guaranteed with VDD_LV not below 1.08 V. 4.6 Thermal characteristics 4.6.1 Package thermal characteristics Table 11. LQFP thermal characteristics(1) Symbol C Conditions(2) Parameter Single-layer board - 1s RJA CC D Thermal resistance, junction-toambient natural convection(3) Value 64 TBD 100 64 144 64 64 TBD 100 51 144 49 Unit C/W Four-layer board - 2s2p 44/113 Pin count Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Table 11. Symbol Electrical characteristics LQFP thermal characteristics(1) (continued) C Conditions(2) Parameter Single-layer board - 1s RJB CC D Thermal resistance, junction-toboard(4) Single-layer board - 1s D Thermal resistance, junction-tocase(5) Single-layer board - 1s CC D Junction-to-board thermal characterization parameter, natural convection Single-layer board - 1s CC D TBD 100 36 144 37 64 TBD 100 34 144 35 64 TBD 100 22 144 22 64 TBD 100 22 144 22 64 TBD 100 33 144 34 64 TBD 100 34 144 35 64 TBD 100 9 144 10 64 TBD 100 9 144 10 C/W Four-layer board - 2s2p JC 64 Unit C/W Four-layer board - 2s2p JB Value C/W Four-layer board - 2s2p RJC CC Pin count Junction-to-case thermal characterization parameter, natural convection C/W Four-layer board - 2s2p 1. Thermal characteristics are based on simulation. 2. VDD = 3.3 V 10% / 5.0 V 10%, TA = -40 to 125 C 3. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA. 4. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. When Greek letters are not available, the symbols are typed as RthJB. 5. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. When Greek letters are not available, the symbols are typed as RthJC. 4.6.2 Power considerations The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1: Equation 1 TJ = TA + (PD x RJA) Doc ID 14619 Rev 7 45/113 Electrical characteristics SPC560Bx, SPC560Cx Where: TA is the ambient temperature in C. RJA is the package junction-to-ambient thermal resistance, in C/W. PD is the sum of PINT and PI/O (PD = PINT + PI/O). PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power. PI/O represents the power dissipation on input and output pins; user determined. Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device is configured to continuously drive external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: Equation 2 PD = K / (TJ + 273 C) Therefore, solving equations 1 and 2: Equation 3 K = PD x (TA + 273 C) + RJA x PD2 Where: K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations 1 and 2 iteratively for any value of TA. 4.7 I/O pad electrical characteristics 4.7.1 I/O pad types The device provides four main I/O pad types depending on the associated alternate functions: Slow pads--These pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. Medium pads--These pads provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. Fast pads--These pads provide maximum speed. There are used for improved Nexus debugging capability. Input only pads--These pads are associated to ADC channels and the external 32 kHz crystal oscillator (SXOSC) providing low input leakage. Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance. 4.7.2 I/O input DC characteristics Table 12 provides input DC electrical characteristics as described in Figure 6. 46/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Figure 6. Electrical characteristics I/O input DC electrical characteristics definition VIN VDD VIH VHYS VIL PDIx = `1' (GPDI register of SIUL) PDIx = `0' Table 12. Symbol I/O input DC electrical characteristics C Value Conditions(1) Parameter Unit Min Typ Max VIH SR P Input high level CMOS (Schmitt Trigger) -- 0.65VDD -- VDD+0.4 VIL SR P Input low level CMOS (Schmitt Trigger) -- 0.4 -- 0.35VDD Input hysteresis CMOS (Schmitt Trigger) -- 0.1VDD -- -- TA = 40 C -- 2 -- -- 2 -- D No injection on TA = 25 C adjacent pin TA = 105 C -- 12 500 P TA = 125 C -- 70 1000 VHYS CC C P P ILKG WFI (2) WNFI( 2) CC Digital input leakage V nA SR P Wakeup input filtered pulse -- -- -- 40 ns SR P Wakeup input not filtered pulse -- 1000 -- -- ns 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage. Doc ID 14619 Rev 7 47/113 Electrical characteristics 4.7.3 SPC560Bx, SPC560Cx I/O output DC characteristics The following tables provide DC characteristics for bidirectional pads: Table 13. Table 13 provides weak pull figures. Both pull-up and pull-down resistances are supported. Table 14 provides output driver characteristics for I/O pads when in SLOW configuration. Table 15 provides output driver characteristics for I/O pads when in MEDIUM configuration. Table 16 provides output driver characteristics for I/O pads when in FAST configuration. I/O pull-up/pull-down DC electrical characteristics Symbol C Parameter Value Conditions(1) Unit Min Typ Max PAD3V5V = 0 10 -- 150 10 -- 250 VIN = VIL, VDD = 3.3 V 10% PAD3V5V = 1 10 -- 150 PAD3V5V = 0 10 -- 150 PAD3V5V = 1 10 -- 250 VIN = VIH, VDD = 3.3 V 10% PAD3V5V = 1 10 -- 150 P Weak pull-up current |IWPU| CC C absolute value P VIN = VIL, VDD = 5.0 V 10% P Weak pull-down current |IWPD| CC C absolute value P VIN = VIH, VDD = 5.0 V 10% PAD3V5V = 1(2) A A 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified. 2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Table 14. SLOW configuration output buffer electrical characteristics Symbol C P VOH CC C Parameter IOH = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) I = 2 mA, Output high level Push Pull OH VDD = 5.0 V 10%, PAD3V5V = 1(2) SLOW configuration Unit Min Typ Max 0.8VDD -- -- 0.8VDD -- -- C IOH = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) VDD0.8 -- -- P IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) -- -- 0.1VDD -- -- 0.1VDD -- -- 0.5 VOL CC C C Output low level I = 2 mA, Push Pull OL SLOW configuration VDD = 5.0 V 10%, PAD3V5V = 1(2) IOL = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 48/113 Value Conditions(1) Doc ID 14619 Rev 7 V V SPC560Bx, SPC560Cx Electrical characteristics 2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Table 15. MEDIUM configuration output buffer electrical characteristics Symbol C Value Conditions(1) Parameter Unit Min Typ Max C IOH = 3.8 mA, VDD = 5.0 V 10%, PAD3V5V = 0 0.8VDD -- -- P IOH = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) 0.8VDD -- -- IOH = 1 mA, VDD = 5.0 V 10%, PAD3V5V = 1(2) 0.8VDD -- -- C IOH = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) VDD0.8 -- -- C IOH = 100 A, VDD = 5.0 V 10%, PAD3V5V = 0 0.8VDD -- -- C IOL = 3.8 mA, VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 0.2VDD P IOL = 2 mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) -- -- 0.1VDD IOL = 1 mA, VDD = 5.0 V 10%, PAD3V5V = 1(2) -- -- 0.1VDD C IOL = 1 mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) -- -- 0.5 C IOH = 100 A, VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 0.1VDD Output high level VOH CC C MEDIUM configuration Output low level VOL CC C MEDIUM configuration Push Pull Push Pull V V 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Doc ID 14619 Rev 7 49/113 Electrical characteristics Table 16. SPC560Bx, SPC560Cx FAST configuration output buffer electrical characteristics Symbol C Value Conditions(1) Parameter Unit Min Typ Max 0.8VDD -- -- IOH = 7mA, 0.8VDD VDD = 5.0 V 10%, PAD3V5V = 1(2) -- -- C IOH = 11mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) VDD 0.8 -- -- P IOL = 14mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) -- -- 0.1VDD IOL = 7mA, VDD = 5.0 V 10%, PAD3V5V = 1(2) -- -- 0.1VDD IOL = 11mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) -- -- 0.5 IOH = 14mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) P VOH CC C VOL CC C Output high level Push FAST configuration Pull Output low level Push FAST configuration Pull C V V 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. 4.7.4 Output pin transition times Table 17. Output pin transition times Symbol C Value Conditions(1) Parameter Unit Min Typ Max D Ttr Ttr CC CC 50/113 CL = 25 pF VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 50 -- -- 100 T CL = 50 pF D Output transition time output pin(2) D SLOW configuration CL = 100 pF -- -- 125 CL = 25 pF -- -- 50 T CL = 50 pF -- -- 100 D CL = 100 pF -- -- 125 D CL = 25 pF -- -- 10 -- -- 20 ns VDD = 3.3 V 10%, PAD3V5V = 1 VDD = 5.0 V 10%, PAD3V5V = 0 SIUL.PCRx.SRC = 1 T CL = 50 pF D Output transition time output pin(2) D MEDIUM configuration CL = 100 pF -- -- 40 CL = 25 pF -- -- 12 T CL = 50 pF -- -- 25 D CL = 100 pF -- -- 40 ns VDD = 3.3 V 10%, PAD3V5V = 1 SIUL.PCRx.SRC = 1 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Table 17. Electrical characteristics Output pin transition times (continued) Symbol C Value Conditions(1) Parameter Unit Min Typ Max CL = 25 pF -- -- 4 -- -- 6 CL = 100 pF -- -- 12 CL = 25 pF -- -- 4 -- -- 7 -- -- 12 VDD = 5.0 V 10%, PAD3V5V = 0 CL = 50 pF Ttr Output transition time CC D output pin(2) FAST configuration ns VDD = 3.3 V 10%, PAD3V5V = 1 CL = 50 pF CL = 100 pF 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. CL includes device and package capacitances (CPKG < 5 pF). 4.7.5 I/O pad current specification The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 18. Table 19 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the IDYNSEG maximum value. Table 18. I/O supply segment Supply segment Package 1 LBGA208(1) 2 3 4 Equivalent to LQFP144 segment pad distribution pin100-pin122 pin 123-pin19 5 6 MCKO MDOn/MSEO -- -- LQFP144 pin20-pin49 pin51-pin99 LQFP100 pin16-pin35 pin37-pin69 pin70-pin83 pin 84-pin15 -- -- LQFP64(2) pin8-pin26 pin28-pin55 pin56-pin7 -- -- -- 1. LBGA208 available only as development package for Nexus2+ 2. All LQFP64 information is indicative and must be confirmed during silicon validation. Table 19. Symbol I/O consumption C Value Conditions(1) Parameter Unit Min Typ Max Dynamic I/O current for ISWTSLW(2) CC D SLOW configuration VDD = 5.0 V 10%, PAD3V5V = 0 CL = 25 pF Doc ID 14619 Rev 7 -- -- 20 mA VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 16 51/113 Electrical characteristics Table 19. Symbol SPC560Bx, SPC560Cx I/O consumption (continued) C Value Conditions(1) Parameter Unit Min Typ Max ISWTMED(2 ) Dynamic I/O current for CC D MEDIUM configuration Dynamic I/O current for ISWTFST(2) CC D FAST configuration VDD = 5.0 V 10%, PAD3V5V = 0 CL = 25 pF CL = 25 pF mA -- -- 17 VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 110 mA VDD = 3.3 V 10%, PAD3V5V = 1 -- 50 -- -- 2.3 -- -- 3.2 CL = 100 pF, 2 MHz -- -- 6.6 CL = 25 pF, 2 MHz -- -- 1.6 -- -- 2.3 -- -- 4.7 -- -- 6.6 -- -- 13.4 CL = 100 pF, 13 MHz -- -- 18.3 CL = 25 pF, 13 MHz -- -- 5 -- -- 8.5 -- -- 11 -- -- 22 -- -- 33 CL = 100 pF, 40 MHz -- -- 56 CL = 25 pF, 40 MHz -- -- 14 -- -- 20 CL = 100 pF, 40 MHz -- -- 35 VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 70 VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 65 CL = 25 pF, 4 MHz VDD = 5.0 V 10%, PAD3V5V = 0 mA VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF, 2 MHz CL = 25 pF, 13 MHz CL = 25 pF, 40 MHz IRMSMED Root medium square I/O CC D current for MEDIUM configuration CL = 25 pF, 40 MHz VDD = 5.0 V 10%, PAD3V5V = 0 mA VDD = 3.3 V 10%, PAD3V5V = 1 CL = 100 pF, 13 MHz CL = 25 pF, 40 MHz CL = 25 pF, 64 MHz IRMSFST Root medium square I/O CC D current for FAST configuration CL = 25 pF, 64 MHz IAVGSEG Sum of all the static I/O SR D current within a supply segment 29 -- CL = 25 pF, 4 MHz IRMSSLW -- VDD = 3.3 V 10%, PAD3V5V = 1 CL = 25 pF, 2 MHz Root medium square I/O CC D current for SLOW configuration -- VDD = 5.0 V 10%, PAD3V5V = 0 mA VDD = 3.3 V 10%, PAD3V5V = 1 mA 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to125 C, unless otherwise specified 2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. Table 20 provides the weight of concurrent switching I/Os. In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain below the 100%. 52/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Table 20. Electrical characteristics I/O weight(1) LQFP64(2) LQFP144/LQFP100 Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 PB[3] 10% -- 12% -- 10% -- 12% -- PC[9] 10% -- 12% -- 10% -- 12% -- PC[14] 9% -- 11% -- 9% -- 11% -- PC[15] 9% 13% 11% 12% 9% 13% 11% 12% PG[5] 9% -- 11% -- 9% -- 11% -- PG[4] 9% 12% 10% 11% 9% 12% 10% 11% PG[3] 9% -- 10% -- 9% -- 10% -- PG[2] 8% 12% 10% 10% 8% 12% 10% 10% PA[2] 8% -- 9% -- 8% -- 9% -- PE[0] 8% -- 9% -- 8% -- 9% -- PA[1] 7% -- 9% -- 7% -- 9% -- PE[1] 7% 10% 8% 9% 7% 10% 8% 9% PE[8] 7% 9% 8% 8% 7% 9% 8% 8% PE[9] 6% -- 7% -- 6% -- 7% -- PE[10] 6% -- 7% -- 6% -- 7% -- PA[0] 5% 8% 6% 7% 5% 8% 6% 7% PE[11] 5% -- 6% -- 5% -- 6% -- PG[9] 9% -- 10% -- 9% -- 10% -- PG[8] 9% -- 11% -- 9% -- 11% -- PC[11] 9% -- 11% -- 9% -- 11% -- PC[10] 9% 13% 11% 12% 9% 13% 11% 12% PG[7] 10% 14% 11% 12% 10% 14% 11% 12% PG[6] 10% 14% 12% 12% 10% 14% 12% 12% PB[0] 10% 14% 12% 12% 10% 14% 12% 12% PB[1] 10% -- 12% -- 10% -- 12% -- PF[9] 10% -- 12% -- 10% -- 12% -- PF[8] 10% 15% 12% 13% 10% 15% 12% 13% PF[12] 10% 15% 12% 13% 10% 15% 12% 13% PC[6] 10% -- 12% -- 10% -- 12% -- PC[7] 10% -- 12% -- 10% -- 12% -- PF[10] 10% 14% 12% 12% 10% 14% 12% 12% PF[11] 10% -- 11% -- 10% -- 11% -- PAD Doc ID 14619 Rev 7 53/113 Electrical characteristics Table 20. SPC560Bx, SPC560Cx I/O weight(1) LQFP64(2) LQFP144/LQFP100 Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 PA[15] 9% 12% 10% 11% 9% 12% 10% 11% PF[13] 8% -- 10% -- 8% -- 10% -- PA[14] 8% 11% 9% 10% 8% 11% 9% 10% PA[4] 8% -- 9% -- 8% -- 9% -- PA[13] 7% 10% 9% 9% 7% 10% 9% 9% PA[12] 7% -- 8% -- 7% -- 8% -- PB[9] 1% -- 1% -- 1% -- 1% -- PB[8] 1% -- 1% -- 1% -- 1% -- PB[10] 6% -- 7% -- 6% -- 7% -- PF[0] 6% -- 7% -- 6% -- 7% -- PF[1] 7% -- 8% -- 7% -- 8% -- PF[2] 7% -- 8% -- 7% -- 8% -- PF[3] 7% -- 9% -- 8% -- 9% -- PF[4] 8% -- 9% -- 8% -- 9% -- PF[5] 8% -- 10% -- 8% -- 10% -- PF[6] 8% -- 10% -- 9% -- 10% -- PF[7] 9% -- 10% -- 9% -- 11% -- PD[0] 1% -- 1% -- 1% -- 1% -- PD[1] 1% -- 1% -- 1% -- 1% -- PD[2] 1% -- 1% -- 1% -- 1% -- PD[3] 1% -- 1% -- 1% -- 1% -- PD[4] 1% -- 1% -- 1% -- 1% -- PD[5] 1% -- 1% -- 1% -- 1% -- PD[6] 1% -- 1% -- 1% -- 1% -- PD[7] 1% -- 1% -- 1% -- 1% -- PD[8] 1% -- 1% -- 1% -- 1% -- PB[4] 1% -- 1% -- 1% -- 1% -- PB[5] 1% -- 1% -- 1% -- 2% -- PB[6] 1% -- 1% -- 1% -- 2% -- PB[7] 1% -- 1% -- 1% -- 2% -- PD[9] 1% -- 1% -- 1% -- 2% -- PD[10] 1% -- 1% -- 1% -- 2% -- PAD 54/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Table 20. Electrical characteristics I/O weight(1) LQFP64(2) LQFP144/LQFP100 Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 PD[11] 1% -- 1% -- 1% -- 2% -- PB[11] 11% -- 13% -- 17% -- 21% -- PD[12] 11% -- 13% -- 18% -- 21% -- PB[12] 11% -- 13% -- 18% -- 21% -- PD[13] 10% -- 12% -- 18% -- 21% -- PB[13] 10% -- 12% -- 18% -- 21% -- PD[14] 10% -- 12% -- 18% -- 21% -- PB[14] 10% -- 12% -- 18% -- 21% -- PD[15] 10% -- 11% -- 18% -- 21% -- PB[15] 9% -- 11% -- 18% -- 21% -- PA[3] 9% -- 11% -- 18% -- 21% -- PG[13] 9% 13% 10% 11% 18% 26% 21% 23% PG[12] 9% 12% 10% 11% 18% 26% 21% 23% PH[0] 5% 8% 6% 7% 18% 26% 21% 23% PH[1] 5% 7% 6% 6% 18% 26% 21% 23% PH[2] 5% 6% 5% 6% 18% 25% 21% 22% PH[3] 4% 6% 5% 5% 18% 25% 21% 22% PG[1] 4% -- 4% -- 18% -- 21% -- PG[0] 3% 4% 4% 4% 17% 25% 21% 22% PF[15] 3% -- 4% -- 17% -- 20% -- PF[14] 4% 5% 5% 5% 16% 23% 20% 21% PE[13] 4% -- 5% -- 16% -- 19% -- PA[7] 5% -- 6% -- 16% -- 19% -- PA[8] 5% -- 6% -- 16% -- 19% -- PA[9] 5% -- 6% -- 15% -- 18% -- PA[10] 6% -- 7% -- 15% -- 18% -- PA[11] 6% -- 8% -- 14% -- 17% -- PE[12] 7% -- 8% -- 11% -- 14% -- PG[14] 7% -- 8% -- 10% -- 12% -- PG[15] 7% 10% 8% 9% 10% 14% 12% 12% PE[14] 7% -- 8% -- 9% -- 11% -- PE[15] 7% 9% 8% 8% 9% 12% 10% 11% PAD Doc ID 14619 Rev 7 55/113 Electrical characteristics Table 20. SPC560Bx, SPC560Cx I/O weight(1) LQFP64(2) LQFP144/LQFP100 Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 PG[10] 6% -- 8% -- 8% -- 10% -- PG[11] 6% 9% 7% 8% 8% 11% 9% 10% PC[3] 6% -- 7% -- 7% -- 9% -- PC[2] 6% 8% 7% 7% 6% 9% 8% 8% PA[5] 5% 7% 6% 6% 6% 8% 7% 7% PA[6] 5% -- 6% -- 5% -- 6% -- PC[1] 5% -- 5% -- 5% -- 5% -- PC[0] 6% 9% 7% 8% 6% 9% 7% 8% PE[2] 7% 10% 9% 9% 7% 10% 9% 9% PE[3] 8% 11% 9% 9% 8% 11% 9% 9% PC[5] 8% 11% 9% 10% 8% 11% 9% 10% PC[4] 8% 12% 10% 10% 8% 12% 10% 10% PE[4] 8% 12% 10% 11% 8% 12% 10% 11% PE[5] 9% 12% 10% 11% 9% 12% 10% 11% PH[4] 9% 13% 11% 11% 9% 13% 11% 11% PH[5] 9% -- 11% -- 9% -- 11% -- PH[6] 9% 13% 11% 12% 9% 13% 11% 12% PH[7] 9% 13% 11% 12% 9% 13% 11% 12% PH[8] 10% 14% 11% 12% 10% 14% 11% 12% PE[6] 10% 14% 12% 12% 10% 14% 12% 12% PE[7] 10% 14% 12% 12% 10% 14% 12% 12% PC[12] 10% 14% 12% 13% 10% 14% 12% 13% PC[13] 10% -- 12% -- 10% -- 12% -- PC[8] 10% -- 12% -- 10% -- 12% -- PB[2] 10% 15% 12% 13% 10% 15% 12% 13% PAD 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to125 C, unless otherwise specified 2. All LQFP64 information is indicative and must be confirmed during silicon validation. 4.8 RESET electrical characteristics The device implements a dedicated bidirectional RESET pin. 56/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Figure 7. Electrical characteristics Start-up reset requirements VDD VDDMIN RESET VIH VIL device reset forced by RESET Figure 8. device start-up phase Noise filtering on reset signal VRESET hw_rst VDD `1' VIH VIL `0' filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter unknown reset state device under hardware reset WFRST WNFRST Table 21. Reset electrical characteristics Symbol C Parameter Value Conditions(1) Unit Min Typ Max VIH SR P Input High Level CMOS (Schmitt Trigger) -- 0.65VDD -- VDD+0.4 V VIL SR P Input low Level CMOS (Schmitt Trigger) -- 0.4 -- 0.35VDD V Doc ID 14619 Rev 7 57/113 Electrical characteristics Table 21. Reset electrical characteristics (continued) Symbol VHYS VOL Ttr WFRST C CC C Parameter Output transition time CC D output pin(3) Typ Max 0.1VDD -- -- Push Pull, IOL = 2mA, VDD = 5.0 V 10%, PAD3V5V = 0 (recommended) -- -- 0.1VDD Push Pull, IOL = 1mA, VDD = 5.0 V 10%, PAD3V5V = 1(2) -- -- 0.1VDD Push Pull, IOL = 1mA, VDD = 3.3 V 10%, PAD3V5V = 1 (recommended) -- -- 0.5 CL = 25pF, VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 10 CL = 50pF, VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 20 CL = 100pF, VDD = 5.0 V 10%, PAD3V5V = 0 -- -- 40 -- V ns -- -- 12 CL = 50pF, VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 25 CL = 100pF, VDD = 3.3 V 10%, PAD3V5V = 1 -- -- 40 -- -- -- 40 ns -- 1000 -- -- ns VDD = 3.3 V 10%, PAD3V5V = 1 10 -- 150 VDD = 5.0 V 10%, PAD3V5V = 0 10 -- 150 VDD = 5.0 V 10%, PAD3V5V = 1(2) 10 -- 250 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. This transient configuration does not occurs when device is used in the VDD = 3.3 V 10% range. 3. CL includes device and package capacitance (CPKG < 5 pF). 58/113 V CL = 25pF, VDD = 3.3 V 10%, PAD3V5V = 1 RESET input not filtered pulse Weak pull-up current absolute value Unit Min SR P RESET input filtered pulse CC P Value Conditions(1) Input hysteresis CMOS (Schmitt Trigger) CC P Output low level WNFRST SR P |IWPU| SPC560Bx, SPC560Cx Doc ID 14619 Rev 7 A SPC560Bx, SPC560Cx Electrical characteristics 4.9 Power management electrical characteristics 4.9.1 Voltage regulator electrical characteristics The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved: HV--High voltage external power supply for voltage regulator module. This must be provided externally through VDD power pin. BV--High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV power pin. Voltage values should be aligned with VDD. LV--Low voltage internal power supply for core, FMPLL and flash digital logic. This is generated by the internal voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure noise isolation between critical LV modules within the device: - LV_COR--Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding. - LV_CFLA--Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. - LV_DFLA--Low voltage supply for data flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. - LV_PLL--Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding. Doc ID 14619 Rev 7 59/113 Electrical characteristics Figure 9. SPC560Bx, SPC560Cx Voltage regulator capacitance connection CREG2 (LV_COR/LV_CFLA) GND VDD VSS_LV VDD_BV Voltage Regulator I VDD_BV CREG1 (LV_COR/LV_DFLA) VDD_LVn CDEC1 (Ballast decoupling) VREF VDD_LV VDD_LV DEVICE VSS_LV GND VSS_LVn VSS_LV DEVICE VDD_LV VSS VDD GND GND CREG3 (LV_COR/LV_PLL) CDEC2 (supply/IO decoupling) The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 5 nH. Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see Section 4.5 Recommended operating conditions). Table 22. Symbol Voltage regulator electrical characteristics C Value Conditions(1) Parameter Unit Min Typ Max CREGn SR -- Internal voltage regulator external capacitance -- 200 -- 500 nF RREG SR -- Stability capacitor equivalent serial resistance -- -- -- 0.2 W CDEC1 CDEC2 60/113 SR -- Decoupling capacitance(2) ballast VDD_BV/VSS_LV pair: VDD_BV 100(3) = 4.5 V to 5.5 V VDD_BV/VSS_LV pair: VDD_BV = 3 V to 3.6 V SR -- Decoupling capacitance regulator VDD/VSS pair supply Doc ID 14619 Rev 7 -- 470(4) 400 10 nF -- 100 -- nF SPC560Bx, SPC560Cx Table 22. Electrical characteristics Voltage regulator electrical characteristics (continued) Symbol C T CC IMREG SR -- Main regulator current provided to VDD_LV domain IMREGINT CC D Main regulator module current consumption VLPREG CC P Low power regulator output voltage ILPREG SR -- Low power regulator current provided to VDD_LV domain Unit Min Typ Max -- 1.32 -- 1.15 1.28 1.32 -- -- -- 150 IMREG = 200 mA -- -- 2 IMREG = 0 mA -- -- 1 After trimming 1.15 1.23 1.32 V -- -- 15 mA ILPREG = 15 mA; TA = 55 C -- -- 600 ILPREG = 0 mA; TA = 55 C -- 5 -- After trimming 1.15 1.23 1.32 V -- -- 5 mA -- -- 100 Before exting from reset VMREG Main regulator output voltage P Low power regulator module current consumption ILPREGINT CC V After trimming D -- VULPREG CC P Ultra low power regulator output voltage IULPREG SR -- Ultra low power regulator current provided to VDD_LV domain -- -- IULPREG = 5 mA; Ultra low power regulator module TA = 55 C IULPREGINT CC D current consumption IULPREG = 0 mA; TA = 55 C IDD_BV Value Conditions(1) Parameter CC D In-rush current on VDD_BV during power-up(5) -- mA mA A A -- 2 -- -- -- 400(6) mA 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical value is in the range of 470 nF. 3. This value is acceptable to guarantee operation from 4.5 V to 5.5 V 4. External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in operating range. 5. In-rush current is seen only for short time during power-up and on standby exit (max 20 s, depending on external LV capacitances to be load) 6. The duration of the in-rush current depends on the capacitance placed on LV pins. BV decaps must be sized accordingly. Refer to IMREG value for minimum amount of current to be provided in cc. Doc ID 14619 Rev 7 61/113 Electrical characteristics 4.9.2 SPC560Bx, SPC560Cx Voltage monitor electrical characteristics The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well as four low voltage detectors (LVDs) to monitor the VDD and the VDD_LV voltage while device is supplied: Note: POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state LVDHV3 monitors VDD to ensure device reset below minimum functional supply LVDHV5 monitors VDD when application uses device in the 5.0 V 10% range LVDLVCOR monitors power domain No. 1 LVDLVBKP monitors power domain No. 0 When enabled, power domain No. 2 is monitored through LVD_DIGBKP. Figure 10. Low voltage monitor vs reset VDD VLVDHVxH VLVDHVxL RESET 62/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Table 23. Electrical characteristics Low voltage monitor electrical characteristics Symbol C P CC VPORH Power-on reset threshold Unit Min Typ Max -- 1.0 -- 5.5 TA = 25 C, after trimming 1.5 -- 2.6 -- 1.5 -- 2.6 SR P Supply for functional POR module VPORUP Value Conditions(1) Parameter T VLVDHV3H CC T LVDHV3 low voltage detector high threshold -- -- 2.95 VLVDHV3L CC P LVDHV3 low voltage detector low threshold 2.6 -- 2.9 VLVDHV5H CC T LVDHV5 low voltage detector high threshold -- -- 4.5 VLVDHV5L CC P LVDHV5 low voltage detector low threshold 3.8 -- 4.4 VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold 1.08 -- 1.5 VLVDLVBKPL 1.08 -- 1.14 V -- CC P LVDLVBKP low voltage detector low threshold 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 4.10 Low voltage domain power consumption Table 24 provides DC electrical characteristics for significant application modes. These values are indicative values; actual consumption depends on the application. Table 24. Low voltage power domain electrical characteristics Symbol C IDDMAX(2) CC D IDDRUN(4) Parameter RUN mode maximum average current -- Typ -- 115 Max 140(3) mA fCPU = 8 MHz -- 7 -- T fCPU = 16 MHz -- 18 -- fCPU = 32 MHz -- 29 -- fCPU = 48 MHz -- 40 -- fCPU = 64 MHz -- 51 -- TA = 25 C -- 8 15 TA = 125 C -- 14 25 TA = 25 C -- 180 700(8) TA = 55 C -- 500 -- TA = 85 C -- 1 -- TA = 105 C -- 2 -- TA = 125 C -- 4.5 12(8) RUN mode typical CC T average current(5) P C HALT mode current(6) CC P Slow internal RC oscillator (128 kHz) running P D IDDSTOP Unit Min T P IDDHALT Value Conditions(1) CC D STOP mode current(7) D Slow internal RC oscillator (128 kHz) running P Doc ID 14619 Rev 7 mA mA A mA 63/113 Electrical characteristics Table 24. Symbol SPC560Bx, SPC560Cx Low voltage power domain electrical characteristics (continued) C Value Conditions(1) Parameter Unit Min Typ Max TA = 25 C -- 30 100 TA = 55 C -- 75 -- TA = 85 C -- 180 -- TA = 105 C -- 315 -- P TA = 125 C -- 560 1700 T TA = 25 C -- 20 60 TA = 55 C -- 45 -- TA = 85 C -- 100 -- TA = 105 C -- 165 -- TA = 125 C -- 280 900 P D STANDBY2 mode IDDSTDBY2 CC D current(9) D D STANDBY1 mode IDDSTDBY1 CC D current(10) D Slow internal RC oscillator (128 kHz) running Slow internal RC oscillator (128 kHz) running D A A 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. Running consumption is given on voltage regulator supply (VDDREG). IDDMAX is composed of three components: IDDMAX = IDD(vdd_bv) + IDD(vdd_hv) + IDD(Vdd_hv_adc). It does not include a fourth component linked to I/Os toggling which is highly dependent on the application. The given value is thought to be a worst case value with all peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to be noticed that this value can be significantly reduced by application: switch-off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible. 3. Higher current may be sinked by device during power-up and standby exit. please refer to in rush current on Table 22. 4. RUN current measured with typical application with accesses on both flash and RAM. 5. Only for the "P" classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPi as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic SW/WDG timer reset enabled. 6. Data Flash Power Down. Code Flash in Low Power. RC-osc128kHz & RC-OSC 16MHz on. 10MHz XTAL clock. FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex: instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON (16 channels on PA[0]PA[11] and PC[12]-PC[15]) with PWM 20kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication). RTC/API ON.PIT ON. STM ON. ADC ON but not conversion except 2 analogue watchdog 7. Only for the "P" classification: No clock, RC 16MHz off, RC128kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All possible peripherals off and clock gated. Flash in power down mode. 8. When going from RUN to STOP mode and the core consumption is > 6 mA , it is normal operation for the main regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures exceeding 125 C and under these circumstances , it is possible for the current to initially exceed the maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA. 9. Only for the "P" classification: ULPreg on, HP/LPVreg off, 32kB RAM on, device configured for minimum consumption, all possible modules switched-off. 10. ULPreg on, HP/LPVreg off, 8kB RAM on, device configured for minimum consumption, all possible modules switched-off. 4.11 Flash memory electrical characteristics 4.11.1 Program/Erase characteristics Table 25 shows the program and erase characteristics. 64/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Table 25. Electrical characteristics Program and erase specifications Value Symbol C Parameter Unit Min Typ(1) Initial max(2) Max(3) Double word (64 bits) program time(4) -- 22 50 500 s 16 KB block pre-program and erase time -- 300 500 5000 ms T32Kpperase 32 KB block pre-program and erase time -- 400 600 5000 ms T128Kpperase 128 KB block pre-program and erase time -- 800 1300 7500 ms -- -- 30 30 s Tdwprogram T16Kpperase Teslat CC C CC D Erase Suspend Latency 1. Typical program and erase times assume nominal supply values and operation at 25 C. 2. Initial factory condition: < 100 program/erase cycles, 25 C, typical supply voltage. 3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed. 4. Actual hardware programming times. This does not include software overhead. Table 26. Flash module life Value Symbol C Parameter Conditions Unit Min Typ Max -- -- cycles P/E Number of program/erase cycles per CC C block for 16 Kbyte blocks over the operating temperature range (TJ) -- 100000 P/E Number of program/erase cycles per CC C block for 32 Kbyte blocks over the operating temperature range (TJ) -- 10000 100000 -- cycles P/E Number of program/erase cycles per CC C block for 128 Kbyte blocks over the operating temperature range (TJ) -- 1000 100000 -- cycles Blocks with 0-1000 P/E cycles 20 -- -- years Blocks with 1001- 10000 P/E cycles 10 -- -- years Blocks with 10001- 100000 P/E cycles 5 -- -- years Retention CC C Minimum data retention at 85 C average ambient temperature(1) 1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range. ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results. Some units will experience single bit corrections throughout the life of the product with no impact to product reliability. Doc ID 14619 Rev 7 65/113 Electrical characteristics Table 27. Flash read access timing Symbol fREAD SPC560Bx, SPC560Cx C CC Conditions(1) Parameter Max P 2 wait states 64 C Maximum frequency for Flash reading 1 wait state 40 C 0 wait states 20 Unit MHz 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 4.11.2 Flash power supply DC characteristics Table 28 shows the power supply DC characteristics on external supply. Table 28. Code Flash power supply DC electrical characteristics Symbol C Value Conditions(1) Parameter Unit Min Typ Max Sum of the current IFREAD(2) CC D consumption on VDDHV and VDDBV on read access Sum of the current consumption on VDDHV and (2) CC D IFMOD VDDBV on matrix modification (program/erase) Code Flash module read fCPU = 64 MHz(3) -- 15 33 Data Flash module read fCPU = 64 MHz(3) -- 15 33 Program/Erase on-going while reading Code Flash registers fCPU = 64 MHz(3) -- 15 33 Program/Erase on-going while reading Data Flash registers fCPU = 64 MHz(3) -- 15 33 mA mA Sum of the current CC D consumption on VDDHV and VDDBV during Code Flash low-power mode -- -- 900 IFLPW during Data Flash low-power mode -- -- 900 Sum of the current CC D consumption on VDDHV and VDDBV during Code Flash powe-down mode -- -- 150 IFPWD during Data Flash powe-down mode -- -- 150 A A 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. This value is only relative to the actual duration of the read cycle 3. fCPU 64 MHz can be achieved only at up to 105 C 66/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Electrical characteristics 4.11.3 Start-up/Switch-off timings Table 29. Start-up time/Switch-off time Symbol C Parameter CC TFLALPEXIT CC TFLAPDEXIT CC TFLALPENTRY CC TFLAPDENTRY CC Unit Min Typ Max Code Flash -- -- 125 T Data Flash -- -- 125 T Delay for Flash module to exit low-power T mode Code Flash -- -- 0.5 Data Flash -- -- 0.5 T Delay for Flash module to exit power-down T mode Code Flash -- -- 30 Data Flash -- -- 30 T Delay for Flash module to enter low-power T mode Code Flash -- -- 0.5 Data Flash -- -- 0.5 T Delay for Flash module to enter power- Code Flash -- -- 1.5 T down mode Data Flash -- -- 1.5 T TFLARSTEXIT Value Conditions(1) Delay for Flash module to exit reset mode s 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 4.12 Electromagnetic compatibility (EMC) characteristics Susceptibility tests are performed on a sample basis during product characterization. 4.12.1 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations:The software flowchart must include the management of runaway conditions such as: - Corrupted program counter - Unexpected reset - Critical data corruption (control registers...) Prequalification trials:Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note Software Techniques For Improving Microcontroller EMC Performance (AN1015)). Doc ID 14619 Rev 7 67/113 Electrical characteristics 4.12.2 SPC560Bx, SPC560Cx Electromagnetic interference (EMI) The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC 61967-1 standard, which specifies the general conditions for EMI measurements. Table 30. EMI radiated emission measurement(1)(2) Value Symbol C Parameter Conditions Unit Min -- fCPU SR -- Scan range -- 0.150 -- SR -- Operating frequency -- -- 64 -- MHz -- -- 1.28 -- V No PLL frequency modulation -- -- 18 dBV 2% PLL frequency modulation -- -- 14 dBV VDD_LV SR -- LV operating voltages SEMI Typ Max VDD = 5 V, TA = 25 C, LQFP144 package Test conforming to IEC 61967-2, fOSC = 8 MHz/fCPU = 64 MHz CC T Peak level 1000 MHz 1. EMI testing and I/O port waveforms per IEC 61967-1, -2, -4 2. For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local marketing representative. 4.12.3 Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the application note Electrostatic Discharge Sensitivity Measurement (AN1181). Table 31. Symbol ESD absolute maximum ratings(1) (2) C Ratings Conditions Class Max value VESD(HBM) CC T Electrostatic discharge voltage (Human Body Model) TA = 25 C conforming to AEC-Q100-002 H1C 2000 VESD(MM) CC T Electrostatic discharge voltage (Machine Model) TA = 25 C conforming to AEC-Q100-003 M2 200 VESD(CDM) CC T Electrostatic discharge voltage (Charged Device Model) TA = 25 C conforming to AEC-Q100-011 C3A 500 750 (corners) 1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. 68/113 Doc ID 14619 Rev 7 Unit V SPC560Bx, SPC560Cx Electrical characteristics Static latch-up (LU) Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin. A current injection is applied to each input, output and configurable I/O pin. These tests are compliant with the EIA/JESD 78 IC latch-up standard. Table 32. Symbol LU 4.13 CC Latch-up results C Parameter Conditions T Static latch-up class TA = 125 C conforming to JESD 78 Class II level A Fast external crystal oscillator (4 to 16 MHz) electrical characteristics The device provides an oscillator/resonator driver. Figure 11 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. Table 33 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations. Doc ID 14619 Rev 7 69/113 Electrical characteristics Figure 11. SPC560Bx, SPC560Cx Crystal oscillator and resonator connection scheme EXTAL C1 Crystal EXTAL XTAL C2 DEVICE VDD I R EXTAL XTAL Resonator DEVICE XTAL DEVICE Note: XTAL/EXTAL must not be directly used to drive external circuits. Table 33. Crystal description Crystal motional capacitance (Cm) fF Crystal motional inductance (Lm) mH Load on xtalin/xtalout C1 = C2 (pF)(1) Shunt capacitance between xtalout and xtalin C0(2) (pF) Nominal frequency (MHz) NDK crystal reference Crystal equivalent series resistance ESR 4 NX8045GB 300 2.68 591.0 21 2.93 8 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 120 3.11 56.5 15 2.93 120 3.90 25.3 10 3.00 12 16 NX5032GA 1. The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them. 2. The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package, etc.). 70/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Electrical characteristics Figure 12. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics S_MTRANS bit (ME_GS register) `1' `0' VXTAL 1/fFXOSC VFXOSC 90% VFXOSCOP 10% TFXOSCSU Table 34. Symbol fFXOSC valid internal clock Fast external crystal oscillator (4 to 16 MHz) electrical characteristics C SR -- gmFXOSC Unit Min Typ Max -- 4.0 -- 16.0 VDD = 3.3 V 10%, PAD3V5V = 1 OSCILLATOR_MARGIN = 0 2.2 -- 8.2 2.0 -- 7.4 Fast external crystal oscillator frequency CC C CC P Value Conditions(1) Parameter VDD = 5.0 V 10%, PAD3V5V = 0 Fast external crystal oscillator OSCILLATOR_MARGIN = 0 transconductance V = 3.3 V 10%, MHz mA/V DD CC C PAD3V5V = 1 OSCILLATOR_MARGIN = 1 CC C VFXOSC Oscillation amplitude at CC T EXTAL CC T -- 9.7 VDD = 5.0 V 10%, PAD3V5V = 0 OSCILLATOR_MARGIN = 1 2.5 -- 9.2 fOSC = 4 MHz, OSCILLATOR_MARGIN = 0 1.3 -- -- V VFXOSCOP CC P Oscillation operating point IFXOSC(2) 2.7 Fast external crystal oscillator consumption fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 1.3 -- -- -- 0.95 -- -- 2 3 -- -- 6 -- -- 1.8 fOSC = 4 MHz, Fast external crystal oscillator OSCILLATOR_MARGIN = 0 TFXOSCSU CC T start-up time fOSC = 16 MHz, OSCILLATOR_MARGIN = 1 Doc ID 14619 Rev 7 -- V mA ms 71/113 Electrical characteristics Table 34. SPC560Bx, SPC560Cx Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued) Symbol C Parameter Value Conditions(1) Unit Min Typ Max VIH SR P Input high level CMOS (Schmitt Trigger) Oscillator bypass mode 0.65VDD -- VDD+0.4 V VIL SR P Input low level CMOS (Schmitt Trigger) Oscillator bypass mode 0.4 -- 0.35VDD V 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled peripherals) 4.14 Slow external crystal oscillator (32 kHz) electrical characteristics The device provides a low power oscillator/resonator driver. Figure 13. Crystal oscillator and resonator connection scheme OSC32K_EXTAL OSC32K_EXTAL Crystal Resonator C1 OSC32K_XTAL DEVICE OSC32K_XTAL C2 DEVICE Note: OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits. 72/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Electrical characteristics Figure 14. Equivalent circuit of a quartz crystal C0 C1 Crystal Cm C2 C1 Doc ID 14619 Rev 7 Rm Lm C2 73/113 Electrical characteristics Table 35. SPC560Bx, SPC560Cx Crystal motional characteristics(1) Value Symbol Parameter Conditions Unit Min Typ Max Lm Motional inductance -- -- 11.796 -- KH Cm Motional capacitance -- -- 2 -- fF Load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground(2) -- 18 -- 28 pF AC coupled @ C0 = 2.85 pF(4) -- -- 65 AC coupled @ C0 = 4.9 pF(4) -- -- 50 (4) AC coupled @ C0 = 7.0 pF -- -- 35 AC coupled @ C0 = 9.0 pF(4) -- -- 30 C1/C2 Rm(3) Motional resistance kW 1. The crystal used is Epson Toyocom MC306. 2. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It includes all the parasitics due to board traces, crystal and package. 3. Maximum ESR (Rm) of the crystal is 50 k 4. C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins Figure 15. Slow external crystal oscillator (32 kHz) electrical characteristics OSCON bit (OSC_CTL register) 1 0 VOSC32K_XTAL 1/fSXOSC VSXOSC 90% 10% TSXOSCSU 74/113 Doc ID 14619 Rev 7 valid internal clock SPC560Bx, SPC560Cx Table 36. Electrical characteristics Slow external crystal oscillator (32 kHz) electrical characteristics Symbol C Value Conditions(1) Parameter Slow external crystal oscillator frequency Unit Min Typ Max -- 32 32.768 40 kHz fSXOSC SR -- VSXOSC CC T Oscillation amplitude -- -- 2.1 -- V ISXOSCBIAS CC T Oscillation bias current -- -- 2.5 -- A ISXOSC CC T Slow external crystal oscillator consumption -- -- -- 8 A TSXOSCSU CC T Slow external crystal oscillator start-up time -- -- -- 2(2) s 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified 2. Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal 4.15 FMPLL electrical characteristics The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main oscillator driver. Table 37. FMPLL electrical characteristics Symbol C Parameter Typ Max -- 4 -- 64 MHz FMPLL reference clock duty cycle(2) -- 40 -- 60 % FMPLL output clock frequency -- 16 -- 64 MHz P VCO frequency without frequency modulation -- 256 -- 512 P VCO frequency with frequency modulation -- 245 -- 533 SR -- FMPLL reference clock(2) PLLIN SR -- fPLLOUT CC D fVCO Unit Min fPLLIN (3) Value Conditions(1) CC MHz fCPU SR -- System clock frequency -- -- -- 64 MHz fFREE CC P Free-running frequency -- 20 -- 150 MHz tLOCK CC P FMPLL lock time Stable oscillator (fPLLIN = 16 MHz) 40 100 s tLTJIT CC -- FMPLL long term jitter fPLLIN = 16 MHz (resonator), fPLLCLK @ 64 MHz, 4000 cycles -- -- 10 ns CC C FMPLL consumption TA = 25 C -- -- 4 mA IPLL 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified. 2. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN. 3. Frequency modulation is considered 4% Doc ID 14619 Rev 7 75/113 Electrical characteristics 4.16 SPC560Bx, SPC560Cx Fast internal RC oscillator (16 MHz) electrical characteristics The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up of the device. Table 38. Symbol fFIRC Fast internal RC oscillator (16 MHz) electrical characteristics C CC P Fast internal RC oscillator high SR -- frequency Fast internal RC oscillator high IFIRCRUN(2) CC T frequency current in running mode IFIRCPWD IFIRCSTOP Value Conditions(1) Parameter Fast internal RC oscillator high CC D frequency current in power down mode Fast internal RC oscillator high CC T frequency and system clock current in stop mode TA = 25 C, trimmed -- Unit Min Typ Max -- 16 -- MHz 12 20 TA = 25 C, trimmed -- -- 200 A TA = 125 C -- -- 10 A sysclk = off -- 500 -- sysclk = 2 MHz -- 600 -- TA = 25 C sysclk = 4 MHz -- 700 -- sysclk = 8 MHz -- 900 -- sysclk = 16 MHz -- 1250 -- -- 1.1 2.0 s +1 % Fast internal RC oscillator startVDD = 5.0 V 10% up time TFIRCSU CC C FIRCPRE Fast internal RC oscillator CC T precision after software trimming of fFIRC TA = 25 C 1 -- Fast internal RC oscillator trimming step TA = 25 C -- 1.6 5 -- FIRCTRIM CC T FIRCVAR Fast internal RC oscillator variation in overtemperature CC P and supply with respect to fFIRC at TA = 25 C in high-frequency configuration -- % +5 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified. 2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. 4.17 Slow internal RC oscillator (128 kHz) electrical characteristics The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the RTC module. 76/113 Doc ID 14619 Rev 7 A % SPC560Bx, SPC560Cx Table 39. Symbol Electrical characteristics Slow internal RC oscillator (128 kHz) electrical characteristics C Value Conditions(1) Parameter Unit Min Typ Max fSIRC CC P Slow internal RC oscillator low SR -- frequency TA = 25 C, trimmed -- -- 128 -- 100 -- 150 kHz ISIRC(2) CC C Slow internal RC oscillator low frequency current TA = 25 C, trimmed -- -- 5 A TSIRCSU CC P Slow internal RC oscillator start-up time TA = 25 C, VDD = 5.0 V 10% -- 8 12 s 2 -- +2 Slow internal RC oscillator SIRCPRE CC C precision after software trimming of TA = 25 C fSIRC Slow internal RC oscillator trimming SIRCTRIM CC C step SIRCVAR % -- Slow internal RC oscillator variation in temperature and supply with CC C High frequency configuration respect to fSIRC at TA = 55 C in high frequency configuration -- 2.7 -- 10 -- +10 % 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified. 2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON. 4.18 ADC electrical characteristics 4.18.1 Introduction The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital converter. Doc ID 14619 Rev 7 77/113 Electrical characteristics SPC560Bx, SPC560Cx Figure 16. ADC characteristic and error definitions Offset Error OSE Gain Error GE 1023 1022 1021 1020 1019 1 LSB ideal = VDD_ADC / 1024 1018 (2) code out 7 (1) 6 (1) Example of an actual transfer curve 5 (2) The ideal transfer curve (5) (3) Differential non-linearity error (DNL) 4 (4) Integral non-linearity error (INL) (4) (5) Center of a step of the actual transfer curve 3 (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 Vin(A) (LSBideal) Offset Error OSE 4.18.2 Input impedance and ADC accuracy In the following analysis, the input circuit corresponding to the precise channels is considered. To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources charge during the sampling phase, when the analog signal source is a high-impedance source. A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC filtering may be limited according to the value of source 78/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Electrical characteristics impedance of the transducer or circuit supplying the analog signal to be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the ADC itself. In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS being substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of 330 k is obtained (REQ = 1 / (fc*CS), where fc represents the conversion rate at the considered channel). To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 4: Equation 4 R +R +R +R VA +R S F L SW AD --------------------------------------------------------------------------- 1--- LSB R EQ 2 Equation 4 generates a constraint for external network design, in particular on a resistive path. Internal switch resistances (RSW and RAD) can be neglected with respect to external resistances. Figure 17. Input equivalent circuit (precise channels) EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source RS VA Filter RF Current Limiter RL CF CP1 Channel Selection Sampling RSW1 RAD CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance Current Limiter Resistance RL RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Doc ID 14619 Rev 7 79/113 Electrical characteristics SPC560Bx, SPC560Cx Figure 18. Input equivalent circuit (extended channels) EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD Source Filter RS Current Limiter RF RS RF CF RL RSW RAD CP CS Extended Switch Sampling RSW1 RSW2 RAD RL CF VA Channel Selection CP1 CP3 CP2 CS Source Impedance Filter Resistance Filter Capacitance Current Limiter Resistance Channel Selection Switch Impedance (two contributions RSW1 and RSW2) Sampling Switch Impedance Pin Capacitance (three contributions, CP1, CP2 and CP3) Sampling Capacitance A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the equivalent circuit in Figure 17): A charge sharing phenomenon is installed when the sampling phase is started (A/D switch close). Figure 19. Transient behavior during sampling phase Voltage transient on CS VCS VA VA2 V <0.5 LSB 1 2 1 < (RSW + RAD) CS << TS 2 = RL (CS + CP1 + CP2) VA1 TS t In particular two different transient periods can be distinguished: 1. 80/113 A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Electrical characteristics CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series, and the time constant is Equation 5 1 = R SW + R AD C C P S ---------------------CP + CS Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS is always much longer than the internal time constant: Equation 6 1 R SW + R AD C S T S The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance according to Equation 7: Equation 7 V A1 C S + C P1 + C P2 = V A C P1 + C P2 2. A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality would be faster), the time constant is: Equation 8 2 R L C S + C P1 + C P2 In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time TS, a constraints on RL sizing is obtained: Equation 9 10 2 = 10 R L C S + C P1 + C P2 TS Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge balance assuming now CS already charged at VA1): Equation 10 VA2 C S + C P1 + C P2 + C F = V A C F + V A1 C P1 + C P2 + C S The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing. Doc ID 14619 Rev 7 81/113 Electrical characteristics SPC560Bx, SPC560Cx Figure 20. Spectral representation of input signal Analog source bandwidth (VA) TC < 2 RFCF (conversion rate vs. filter pole) Noise fF = f0 (anti-aliasing filtering condition) 2 f0 < fC (Nyquist) f0 f Anti-aliasing filter (fF = RC filter pole) fF Sampled signal spectrum (fC = conversion rate) f0 f fC f Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS, which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the sampling switch is closed. The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS: Equation 11 VA C P1 + C P2 + C F ------------ = -------------------------------------------------------V A2 C P1 + C P2 + C F + C S From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of half a count, a constraint is evident on CF value: Equation 12 C F 2048 C S 82/113 Doc ID 14619 Rev 7 ADC electrical characteristics Table 40. ADC input leakage current Value Symbol C Parameter C CC Table 41. Doc ID 14619 Rev 7 Symbol Unit Min Typ Max -- 1 -- -- 1 -- TA = 40 C C ILKG Conditions Input leakage current TA = 25 C No current injection on adjacent pin SPC560Bx, SPC560Cx 4.18.3 nA C TA = 105 C -- 8 200 P TA = 125 C -- 45 400 ADC conversion characteristics C Parameter Value Conditions(1) Unit Min Typ Max Voltage on VSS_HV_ADC (ADC SR -- reference) pin with respect to ground (VSS)(2) -- 0.1 -- 0.1 V VDD_ADC Voltage on VDD_HV_ADC pin (ADC SR -- reference) with respect to ground (VSS) -- VDD0.1 -- VDD+0.1 V VAINx SR -- Analog input voltage(3) -- VSS_ADC0.1 -- VDD_ADC+0.1 V fADC SR -- ADC analog frequency -- 6 -- 32 + 4% MHz 45 -- 55 % -- -- -- 50 s ADC_SYS SR -- ADC digital clock duty cycle (ipg_clk) ADC0 consumption in power down mode ADCLKSEL = 1(4) IADCPWD SR -- IADCRUN SR -- ADC0 consumption in running mode -- -- -- 4 ms tADC_PU SR -- ADC power up delay -- -- -- 1.5 s 83/113 Electrical characteristics VSS_ADC Symbol tADC_S tADC_C ADC conversion characteristics (continued) C Parameter CC T Sample time(5) CC P Conversion time(6) Value Conditions(1) fADC = 32 MHz, INPSAMP = 17 Unit Min Typ 0.5 -- Max s fADC = 6 MHz, INPSAMP = 255 -- -- fADC = 32 MHz, INPCMP = 2 0.625 -- 42 s Doc ID 14619 Rev 7 CS CC D ADC input sampling capacitance -- -- -- 3 pF CP1 CC D ADC input pin capacitance 1 -- -- -- 3 pF CP2 CC D ADC input pin capacitance 2 -- -- -- 1 pF CP3 CC D ADC input pin capacitance 3 -- -- -- 1 pF RSW1 CC D Internal resistance of analog source -- -- -- 3 k RSW2 CC D Internal resistance of analog source -- -- -- 2 k RAD CC D Internal resistance of analog source -- -- -- 2 k VDD = 3.3 V 10% 5 -- 5 VDD = 5.0 V 10% 5 -- 5 No overload -- 0.5 1.5 LSB No overload -- 0.5 1.0 LSB IINJ SR -- Input current Injection mA | INL | CC T | DNL | CC T Absolute differential non-linearity | OFS | CC T Absolute offset error -- -- 0.5 -- LSB | GNE | CC T Absolute gain error -- -- 0.6 -- LSB SPC560Bx, SPC560Cx Absolute value for integral nonlinearity Current injection on one ADC input, different from the converted one Electrical characteristics 84/113 Table 41. ADC conversion characteristics (continued) Symbol TUEp TUEx C CC CC Value Conditions(1) Parameter Unit Min Typ Max 0.6 2 P Total unadjusted error(7) for precise T channels, input only pins Without current injection 2 With current injection 3 T Total unadjusted error(7) for extended T channel Without current injection 3 With current injection 4 LSB 3 1 3 LSB SPC560Bx, SPC560Cx Table 41. 4 1. VDD = 3.3 V 10% / 5.0 V 10%, TA = 40 to 125 C, unless otherwise specified. 2. Analog and digital VSS must be common (to be tied together externally). 3. VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3FF. 4. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal divider by 2. Doc ID 14619 Rev 7 5. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tADC_S depend on programming. 6. This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the time to load the result's register with the conversion result. 7. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a combination of Offset, Gain and Integral Linearity errors. Electrical characteristics 85/113 On-chip peripherals 4.19.1 Current consumption Table 42. On-chip peripherals current consumption(1) Value Symbol C Parameter Conditions Unit Typ 500 Kbps IDD_BV(CAN) CC T CAN (FlexCAN) supply current on VDD_BV 125 Kbps Doc ID 14619 Rev 7 IDD_BV(eMIOS) IDD_BV(SCI) CC CC T eMIOS supply current on VDD_BV T SCI (LINFlex) supply current on VDD_BV Total (static + dynamic) consumption: - FlexCAN in loop-back mode - XTAL@ 8MHz used as CAN engine clock source - Message sending period is 580 s Static consumption: - eMIOS channel OFF - Global prescaler enabled Dynamic consumption: - It does not change varying the frequency (0.003 mA) Total (static + dynamic) consumption: - LIN mode - Baudrate: 20 Kbps Ballast static consumption (only clocked) CC Ballast dynamic consumption (continuus communication): - Baudrate: 2 Mbit - Trasmission every 8 s - Frame: 16 bits 8 * fperiph + 85 8 * fperiph + 27 29 * fperiph 3 A 5 * fperiph + 31 1 16 * fperiph SPC560Bx, SPC560Cx IDD_BV(SPI) SPI (DSPI) supply current on T VDD_BV Electrical characteristics 86/113 4.19 On-chip peripherals current consumption(1) (continued) Value Symbol C Parameter Conditions Unit Typ IDD_BV(ADC) CC T ADC supply current on VDD_BV VDD = 5.5 V Ballast static consumption (no conversion) 41 * fperiph VDD = 5.5 V Ballast dynamic consumption (continuus conversion) 5 * fperiph VDD = 5.5 V Analog static consumption (no conversion) 2 * fperiph VDD = 5.5 V Analog dynamic consumption (continuus conversion) 75 * fperiph + 32 VDD = 5.5 V -- 8.21 mA VDD = 5.5 V -- 3 * fperiph A A IDD_HV_ADC(ADC) CC T ADC supply current on VDD_HV_ADC Doc ID 14619 Rev 7 CFlash + DFlash supply current on VDD_HV_ADC IDD_HV(FLASH) CC T IDD_HV(PLL) CC T PLL supply current on VDD_HV SPC560Bx, SPC560Cx Table 42. 1. Operating conditions: TA = 25 C, fperiph = 8 MHz to 64 MHz 4.19.2 DSPI characteristics Table 43. DSPI characteristics(1) DSPI0/DSPI1 No. tSCK C DSPI2 Parameter Unit Min Typ Max Min Typ Max D Master mode (MTFE = 0) 125 -- -- 333 -- -- D Slave mode (MTFE = 0) 125 -- -- 333 -- -- SR SCK cycle time ns 87/113 D Master mode (MTFE = 1) 83 -- -- 125 -- -- D Slave mode (MTFE = 1) 83 -- -- 125 -- -- Electrical characteristics 1 Symbol DSPI characteristics(1) (continued) DSPI0/DSPI1 No. Symbol C DSPI2 Parameter Unit Min Typ Max Min Typ Max -- -- fCPU -- -- fCPU MHz -- fDSPI SR D DSPI digital controller frequency -- tCSC Internal delay between pad associated CC D to SCK and pad associated to CSn in master mode for CSn1->0 Master mode -- -- 130(2) -- -- 15(3) ns -- tASC Internal delay between pad associated CC D to SCK and pad associated to CSn in master mode for CSn1->1 Master mode -- -- 130(3) -- -- 130(3) ns Doc ID 14619 Rev 7 2 tCSCext(4) SR D CS to SCK delay Slave mode 32 -- -- 32 -- -- ns 3 tASCext(5) SR D After SCK delay Slave mode 1/fDSPI + 5 -- -- 1/fDSPI + 5 -- -- ns Master mode -- tSCK/2 -- -- tSCK/2 -- SR D Slave mode tSCK/2 -- -- tSCK/2 -- -- CC D 4 tSDC SCK duty cycle ns 5 tA SR D Slave access time Slave mode -- -- 1/fDSPI + 70 -- -- 1/fDSPI + 130 ns 6 tDI SR D Slave SOUT disable time Slave mode 7 -- -- 7 -- -- ns Master mode 43 -- -- 145 -- -- 9 tSUI SR D Data setup time for inputs Slave mode 5 -- -- 5 -- -- Master mode 0 -- -- 0 -- -- tHI SR D Data hold time for inputs Slave mode (6) 2 -- -- 2(6) -- -- Master mode -- -- 32 -- -- 50 Slave mode -- -- 52 -- -- 160 Master mode 0 -- -- 0 -- -- Slave mode 8 -- -- 13 -- -- 10 12 tSUO(7) CC D Data valid after SCK edge tHO(7) CC D Data hold time for outputs ns ns ns ns 1. Operating conditions: Cout = 10 to 50 pF, SlewIN = 3.5 to 15 ns. 2. Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK starts before CSn is asserted. DSPI2 has only SLOW SCK available. SPC560Bx, SPC560Cx 11 Electrical characteristics 88/113 Table 43. 4. The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tCSC to ensure positive tCSCext. 5. The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between internal CS and internal SCK must be higher than tASC to ensure positive tASCext. 6. This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register. 7. SCK and SOUT configured as MEDIUM pad SPC560Bx, SPC560Cx 3. Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available. Doc ID 14619 Rev 7 Electrical characteristics 89/113 Electrical characteristics SPC560Bx, SPC560Cx Figure 21. DSPI classic SPI timing - master, CPHA = 0 2 3 PCSx 1 4 SCK Output (CPOL = 0) 4 SCK Output (CPOL = 1) 10 9 SIN First Data Data 12 SOUT First Data Last Data 11 Data Last Data Note: Numbers shown reference Table 43. 90/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Electrical characteristics Figure 22. DSPI classic SPI timing - master, CPHA = 1 PCSx SCK Output (CPOL = 0) 10 SCK Output (CPOL = 1) 9 Data First Data SIN Last Data 12 SOUT 11 Data First Data Last Data Note: Numbers shown reference Table 43. Figure 23. DSPI classic SPI timing - slave, CPHA = 0 3 2 SS 1 4 SCK Input (CPOL = 0) 4 SCK Input (CPOL = 1) 5 SOUT First Data 9 SIN 12 11 Data Last Data Data Last Data 6 10 First Data Note: Numbers shown reference Table 43. Doc ID 14619 Rev 7 91/113 Electrical characteristics SPC560Bx, SPC560Cx Figure 24. DSPI classic SPI timing - slave, CPHA = 1 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) 11 5 6 12 SOUT First Data 9 SIN Data Last Data Data Last Data 10 First Data Note: Numbers shown reference Table 43. Figure 25. DSPI modified transfer format timing - master, CPHA = 0 3 PCSx 4 1 2 SCK Output (CPOL = 0) 4 SCK Output (CPOL = 1) 9 SIN First Data 10 12 SOUT First Data Last Data Data 11 Data Last Data Note: Numbers shown reference Table 43. 92/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Electrical characteristics Figure 26. DSPI modified transfer format timing - master, CPHA = 1 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) 10 9 SIN First Data Last Data Data 12 First Data SOUT 11 Last Data Data Note: Numbers shown reference Table 43. Figure 27. DSPI modified transfer format timing - slave, CPHA = 0 3 2 SS 1 SCK Input (CPOL = 0) 4 4 SCK Input (CPOL = 1) SOUT First Data Data First Data 6 Last Data 10 9 SIN 12 11 5 Data Last Data Note: Numbers shown reference Table 43. Doc ID 14619 Rev 7 93/113 Electrical characteristics SPC560Bx, SPC560Cx Figure 28. DSPI modified transfer format timing - slave, CPHA = 1 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) 11 5 6 12 First Data SOUT 9 Last Data Data Last Data 10 First Data SIN Data Note: Numbers shown reference Table 43. 4.19.3 Nexus characteristics Table 44. Nexus characteristics Value No. Symbol C Parameter Unit Min Typ Max 1 tTCYC CC D TCK cycle time 64 -- -- ns 2 tMCYC CC D MCKO cycle time 32 -- -- ns 3 tMDOV CC D MCKO low to MDO data valid -- -- 8 ns 4 tMSEOV CC D MCKO low to MSEO_b data valid -- -- 8 ns 5 tEVTOV CC D MCKO low to EVTO data valid -- -- 8 ns tNTDIS CC D TDI data setup time 15 -- -- ns tNTMSS CC D TMS data setup time 15 -- -- ns tNTDIH CC D TDI data hold time 5 -- -- ns tNTMSH CC D TMS data hold time 5 -- -- ns 10 11 12 tTDOV CC D TCK low to TDO data valid 35 -- -- ns 13 tTDOI CC D TCK low to TDO data invalid 6 -- -- ns 94/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Electrical characteristics Figure 29. Nexus TDI, TMS, TDO timing TCK 10 11 TMS, TDI 12 TDO Note: Numbers shown reference Table 44. 4.19.4 JTAG characteristics Table 45. JTAG characteristics Value No. Symbol C Parameter Unit Min Typ Max 1 tJCYC CC D TCK cycle time 64 -- -- ns 2 tTDIS CC D TDI setup time 15 -- -- ns 3 tTDIH CC D TDI hold time 5 -- -- ns 4 tTMSS CC D TMS setup time 15 -- -- ns 5 tTMSH CC D TMS hold time 5 -- -- ns 6 tTDOV CC D TCK low to TDO valid -- -- 33 ns 7 tTDOI CC D TCK low to TDO invalid 6 -- -- ns Doc ID 14619 Rev 7 95/113 Electrical characteristics SPC560Bx, SPC560Cx Figure 30. Timing diagram - JTAG boundary scan TCK 2/4 DATA INPUTS 3/5 INPUT DATA VALID 6 DATA OUTPUTS OUTPUT DATA VALID 7 DATA OUTPUTS Note: Numbers shown reference Table 45. 96/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Package characteristics 5 Package characteristics 5.1 ECOPACK(R) In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 5.2 Package mechanical data 5.2.1 LQFP64 Figure 31. LQFP64 package mechanical drawing D ccc C D1 A A2 D3 33 48 32 49 b L1 E3 E1 E L A1 K 64 17 Pin 1 identification 16 1 Table 46. c 5W_ME LQFP64 mechanical data inches(1) mm Symbol Min Typ Max Min Typ Max A -- -- 1.6 -- -- 0.063 A1 0.05 -- 0.15 0.002 -- 0.0059 A2 1.35 1.4 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 -- 0.2 0.0035 -- 0.0079 Doc ID 14619 Rev 7 97/113 Package characteristics Table 46. SPC560Bx, SPC560Cx LQFP64 mechanical data (continued) inches(1) mm Symbol Min Typ Max Min Typ Max D 11.8 12 12.2 0.4646 0.4724 0.4803 D1 9.8 10 10.2 0.3858 0.3937 0.4016 D3 -- 7.5 -- -- 0.2953 -- E 11.8 12 12.2 0.4646 0.4724 0.4803 E1 9.8 10 10.2 0.3858 0.3937 0.4016 E3 -- 7.5 -- -- 0.2953 -- e -- 0.5 -- -- 0.0197 -- L 0.45 0.6 0.75 0.0177 0.0236 0.0295 L1 -- 1 -- -- 0.0394 -- k 0.0 3.5 7.0 0.0 3.5 7.0 ccc -- -- 0.08 -- -- 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 98/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx 5.2.2 Package characteristics LQFP100 Figure 32. LQFP100 package mechanical drawing Table 47. LQFP100 mechanical data inches(1) mm Symbol Min Typ Max Min Typ Max A -- -- 1.600 -- -- 0.0630 A1 0.050 -- 0.150 0.0020 -- 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 -- 0.200 0.0035 -- 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 -- 12.000 -- -- 0.4724 -- E 15.800 16.000 16.200 0.6220 0.6299 0.6378 Doc ID 14619 Rev 7 99/113 Package characteristics Table 47. SPC560Bx, SPC560Cx LQFP100 mechanical data (continued) inches(1) mm Symbol Min Typ Max Min Typ Max E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 -- 12.000 -- -- 0.4724 -- e -- 0.500 -- -- 0.0197 -- L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 -- 1.000 -- -- 0.0394 -- k 0.0 3.5 7.0 0.0 3.5 7.0 Tolerance mm inches ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 5.2.3 LQFP144 Figure 33. LQFP144 package mechanical drawing 100/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Table 48. Package characteristics LQFP144 mechanical data inches(1) mm Symbol Min Typ Max Min Typ Max A -- -- 1.600 -- -- 0.0630 A1 0.050 -- 0.150 0.0020 -- 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 -- 0.200 0.0035 -- 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 -- 17.500 -- -- 0.6890 -- E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 -- 17.500 -- -- 0.6890 -- e -- 0.500 -- -- 0.0197 -- L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 -- 1.000 -- -- 0.0394 -- k 0.0 3.5 7.0 3.5 0.0 7.0 Tolerance mm inches ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 14619 Rev 7 101/113 Package characteristics 5.2.4 SPC560Bx, SPC560Cx LBGA208 Figure 34. LBGA208 package mechanical drawing ddd C Seating plane A A A1 A3 e A F e E1 F T R P N M L K J H G F E D C B A E A4 B A2 D D D1 1 3 2 5 4 7 6 9 8 11 13 15 10 12 14 16 A1 corner index area (See note 1) b (208 balls) eee M C A B fff M C Bottom view 1. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional. Table 49. LBGA208 mechanical data inches(1) mm Symbol 102/113 Notes Min Typ Max Min Typ Max A -- -- 1.70 -- -- 0.0669 (2) A1 0.30 -- -- 0.0118 -- -- -- A2 -- 1.085 -- -- 0.0427 -- -- A3 -- 0.30 -- -- 0.0118 -- -- A4 -- -- 0.80 -- -- 0.0315 -- b 0.50 0.60 0.70 0.0197 0.0236 0.0276 (3) Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Table 49. Package characteristics LBGA208 mechanical data (continued) inches(1) mm Symbol Notes Min Typ Max Min Typ Max D 16.80 17.00 17.20 0.6614 0.6693 0.6772 -- D1 -- 15.00 -- -- 0.5906 -- -- E 16.80 17.00 17.20 0.6614 0.6693 0.6772 -- E1 -- 15.00 -- -- 0.5906 -- -- e -- 1.00 -- -- 0.0394 -- -- F -- 1.00 -- -- 0.0394 -- -- ddd -- -- 0.20 -- -- 0.0079 -- eee -- -- 0.25 -- -- 0.0098 (4) fff -- -- 0.10 -- -- 0.0039 (5) 1. Values in inches are converted from mm and rounded to four decimal digits. 2. LBGA stands for Low profile Ball Grid Array. -- Low profile: The total profile height (Dim A) is measured from the seating plane to the top of the component -- The maximum total package height is calculated by the following methodology: A2 Typ+A1 Typ + (A12+A32+A42 tolerance values) -- Low profile: 1.20 mm < A < 1.70 mm 3. The typical ball diameter before mounting is 0.60 mm. 4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. 5. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones. Doc ID 14619 Rev 7 103/113 Ordering information SPC560Bx, SPC560Cx 6 Ordering information Table 50. Order codes Order code CPU SPC560B40L1C4E0X e200z0h Code Flash / SRAM (Kbytes) Package Max Operating speed temp. (C) (MHz) 256 / 24 LQFP64 -40 to +125 256 / 24 LQFP100 SPC560B40L3B4E0X e200z0h Data Flash Voltage Packing 48 4 x 16KB 3.3/5V Tape&Reel 48 4 x 16KB 3.3/5V Tape&Reel 64 4 x 16KB 3.3/5V Tape&Reel 64 4 x 16KB 3.3/5V Tape&Reel 48 4 x 16KB 3.3/5V Tape&Reel 64 4 x 16KB 3.3/5V Tape&Reel 64 4 x 16KB 3.3/5V Tape&Reel -40 to +105 SPC560B40L3C4E0X e200z0h -40 to +125 SPC560B40L3B6E0X e200z0h -40 to +105 256 / 24 LQFP100 SPC560B40L3C6E0X e200z0h -40 to +125 SPC560B40L5B6E0X e200z0h -40 to +105 256 / 24 LQFP144 SPC560B40L5C6E0X e200z0h -40 to +125 SPC560B44L3B4E0X e200z0h -40 to +105 384 / 28 LQFP100 SPC560B44L3C4E0X e200z0h -40 to +125 SPC560B44L3B6E0X e200z0h -40 to +105 384 / 28 LQFP100 SPC560B44L3C6E0X e200z0h -40 to +125 SPC560B44L5B6E0X e200z0h -40 to +105 384 / 28 LQFP144 SPC560B44L5C6E0X e200z0h -40 to +125 SPC560B50L1C6E0X e200z0h 512 / 32 LQFP64 -40 to +125 64 4 x 16KB 3.3/5V Tape&Reel SPC560B50L1C6E0Y e200z0h 512 / 32 LQFP64 -40 to +125 64 4 x 16KB 3.3/5V Tray 512 / 32 LQFP100 48 4 x 16KB 3.3/5V Tape&Reel 64 4 x 16KB 3.3/5V SPC560B50L3B4E0X e200z0h -40 to +105 SPC560B50L3C4E0X e200z0h -40 to +125 SPC560B50L3B6E0X e200z0h -40 to +105 512 / 32 LQFP100 SPC560B50L3C6E0X e200z0h SPC560B50L3C6E0Y e200z0h Tape&Reel -40 to +125 512 / 32 LQFP100 -40 to +125 512 / 32 LQFP144 SPC560B50L5B6E0X e200z0h Tape&Reel 64 4 x 16KB 3.3/5V Tray 64 4 x 16KB 3.3/5V Tape&Reel -40 to +105 SPC560B50L5C6E0X e200z0h -40 to +125 SPC560B50L5C6E0Y e200z0h 512 / 32 LQFP144 -40 to +125 64 4 x 16KB 3.3/5V Tray SPC560C40L1C6E0X e200z0h 256 / 32 LQFP64 -40 to +125 64 4 x 16KB 3.3/5V Tape&Reel SPC560C40L3C6E0X e200z0h 256 / 32 LQFP100 -40 to +125 64 4 x 16KB 3.3/5V Tape&Reel SPC560C44L3C6E0X e200z0h 384 / 40 LQFP100 -40 to +125 64 4 x 16KB 3.3/5V Tape&Reel SPC560C50L1C6E0X e200z0h 512 / 48 LQFP64 -40 to +125 64 4 x 16KB 3.3/5V Tape&Reel SPC560C50L3C6E0X e200z0h 512 / 48 LQFP100 -40 to +125 64 4 x 16KB 3.3/5V Tape&Reel 104/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Table 51. Ordering information Order Codes for Engineering Samples(1) Order code CPU Code Flash / SRAM (Kbytes) Package Max Operating speed temp. (C) (MHz) SPC560B50L1-ENG e200z0h 512 / 48 LQFP64 -40 to +125 64 4 x 16KB 3.3/5V Tray SPC560B50L3-ENG e200z0h 512 / 48 LQFP100 -40 to +125 64 4 x 16KB 3.3/5V Tray SPC560B50L5-ENG e200z0h 512 / 48 LQFP144 -40 to +125 64 4 x 16KB 3.3/5V Tray -40 to +125 64 4 x 16KB 3.3/5V Tray SPC560B50B2C6E0Y e200z0h 512 / 48 BGA208 (2) Data Flash Voltage Packing 1. Engineering samples are suitable only for evaluation and developement purpose but NOT for qualification and production. Their silicon version and maturity may vary until the product has reached qualification. 2. LBGA208 available only as development package for Nexus2+ Figure 35. Commercial product code structure Example code: SPC56 0 B 50 L3 C 5E0 Y Product identifier Core Family Memory Package Temperature Custom vers. Conditioning Y = Tray X = Tape and Reel 90 4E0 = 48 MHz EEPROM 5V/3V 6E0 = 64 MHz EEPROM 5V/3V B = -40 to 105C C = -40 to 125C L1 = LQFP64 L3 = LQFP100 L5 = LQFP144 B2 = LBGA208 50 = 512 KB 44 = 384 KB 40 = 256 KB B = Body C = Gateway 0 = e200z0 SPC56 = Power Architecture in 90nm Doc ID 14619 Rev 7 105/113 Abbreviations SPC560Bx, SPC560Cx Appendix A Abbreviations Table 52 lists abbreviations used but not defined elsewhere in this document. Table 52. Abbreviations Abbreviation CMOS Complementary metal-oxide-semiconductor CPHA Clock phase CPOL Clock polarity CS 106/113 Meaning Peripheral chip select EVTO Event out MCKO Message clock out MDO Message data out MSEO Message start/end out MTFE Modified timing format enable SCK Serial communications clock SOUT Serial data out TBD To be defined TCK Test clock input TDI Test data input TDO Test data output TMS Test mode select Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Revision history Revision history Table 53. Document revision history Date Revision 04-Apr-2008 1 Initial release. 2 Made minor editing and formatting changes to improve readability Harmonized oscillator naming throughout document Modified document title Updated "Feature" on cover page Replaced LFBGA208 with LBGA208 Updated "Description" Section Updated "SPC560Bx and SPC560Cx device comparison" table Added "Block diagram" section Section 3 "Package pinouts and signal descriptions": - Removed signal descriptions (these are found in the device reference manual) Updated "LQFP 144-pin configuration (top view)" figure: - Replaced VPP with VSS_HV on pin 18 - Added MA[1] as AF3 for PC[10] (pin 28) - Added MA[0] as AF2 for PC[3] (pin 116) - Changed description for pin 120 to PH[10] / GPIO[122] / TMS - Changed description for pin 127 to PH[9] / GPIO[121] / TCK - Replaced NMI[0] with NMI on pin 11 Updated "LQFP 100-pin configuration (top view)" figure: - Replaced VPP with VSS_HV on pin 14 - Added MA[1] as AF3 for PC[10] (pin 22) - Added MA[0] as AF2 for PC[3] (pin 77) - Changed description for pin 81 to PH[10] / GPIO[122] / TMS - Changed description for pin 88 to PH[9] / GPIO[121] / TCK - Removed E1UC[19] from pin 76 - Replaced [11] with WKUP[11] for PB[3] (pin 1) - Replaced NMI[0] with NMI on pin 7 Updated "LBGA208 configuration" figure: - Changed description for ball B8 from TCK to PH[9] - Changed description for ball B9 from TMS to PH[10] - Updated descriptions for balls R9 and T9 Added "Parameter classification" section and tagged parameters in tables where appropriate Added "NVUSRO register" section Updated "Absolute maximum ratings" table "Recommended operating conditions" section : - Added note on RAM data retention to end of section Updated "Recommended operating conditions (3.3 V)" and "Recommended operating conditions (5.0 V)" Added "Package thermal characteristics" section Updated "Power considerations" section Updated I/O input DC electrical characteristics definition" figure 06-Mar-2009 Changes Doc ID 14619 Rev 7 107/113 Revision history SPC560Bx, SPC560Cx Table 53. Document revision history (continued) Date Revision Changes Updated tables: - "I/O input DC electrical characteristics" - "I/O pull-up/pull-down DC electrical characteristics" - "SLOW configuration output buffer electrical characteristics" - "MEDIUM configuration output buffer electrical characteristics" - "FAST configuration output buffer electrical characteristics" Added "Output pin transition times" section Updated "I/O consumption" table Updated "Start-up reset requirements" figure Updated "Reset electrical characteristics" table "Voltage regulator electrical characteristics" section: - Amended description of LV_PLL "Voltage regulator capacitance connection" figure: - Exchanged position of symbols CDEC1 and CDEC2 Updated tables" - "Voltage regulator electrical characteristics" - "Low voltage monitor electrical characteristics" 2 06-Mar-2009 (continued) - "Low voltage power domain electrical characteristics" Added "Low voltage monitor vs reset" figure Updated "Flash memory electrical characteristics" section Added "Electromagnetic compatibility (EMC) characteristics" section Updated "Fast external crystal oscillator (4 to 16 MHz) electrical characteristics" section Updated "Slow external crystal oscillator (32 kHz) electrical characteristics" section Updated tables: - "FMPLL electrical characteristics" - "Fast internal RC oscillator (16 MHz) electrical characteristics" - "Slow internal RC oscillator (128 kHz) electrical characteristics" Added "On-chip peripherals" section Added "ADC input leakage current" table Updated "ADC conversion characteristics" table Updated "ECOPACK(R)" section Corrected inverted column headings for typical and minimum dimensions in "LQFP64 mechanical data" and "LQFP100 mechanical data" tables Added "Abbrevation" appendix 03-Jun-2009 108/113 3 Corrected "Commercial product code structure" figure Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Revision history Table 53. Document revision history (continued) Date 06-Aug-2009 Revision 4 Changes Updated "LBGA208 configuration" figure "Absolute maximum ratings" table: - VDD_ADC, VIN: changed min value for "relative to VDD" condition - ICORELV: added new row "Recommended operating conditions (5.0 V)" table: - TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part, TJ M-Grade Part: added new rows - Changed capacitance value in footnote "Output pin transition times" table: - MEDIUM configuration: added condition for PAD3V5V = 0 Updated "Voltage regulator capacitance connection" "Voltage regulator electrical characteristics" table: - CDEC1: changed min value - IMREG: changed max value - IDD_BV: added max value footnote "Low voltage monitor electrical characteristics" table: - VLVDHV3H, VLVDHV5H: changed max value - VLVDHV3L, VLVDHV5L: added max value Updated "Low voltage power domain electrical characteristics" table "Flash module life" table: - Retention: deleted min value footnote for "Blocks with 100000 P/E cycles" "Fast external crystal oscillator (4 to 16 MHz) electrical characteristics" table: - IFXOSC: added typ value "Slow external crystal oscillator (32 kHz) electrical characteristics" table - VSXOSC: changed typ value - TSXOSCSU: added max value footnote "FMPLL electrical characteristics" table - tLTJIT: added max value Updated "LQFP100 package mechanical drawing" Doc ID 14619 Rev 7 109/113 Revision history SPC560Bx, SPC560Cx Table 53. Document revision history (continued) Date Revision Changes 20-Jan-2010 5 Table: "Absolute maximum ratings" - VDD_BV, VDD_ADC, VIN: changed max value Table: "Recommended operating conditions (3.3 V)" - TVDD: deleted min value Table: "Reset electrical characteristics" - Changed footnotes 2 and 5 Table: "Voltage regulator electrical characteristics" - CREGn: changed max value - CDEC1: split into 2 rows - Updated voltage values in footnote 3 Table: "Low voltage monitor electrical characteristics" - Updated column Conditions - VLVDLVCORL, VLVDLVBKPL: changed min/max value Table: "Program and erase specifications" - Tdwprogram: added initial max value Table: "Flash module life" - Retention: changed min value for blocks with 100K P/E cycles Table: "Flash power supply DC electrical characteristics" - IFREAD, IFMOD: added typ value - Added a footnote Added Section: " NVUSRO[WATCHDOG_EN] field description" Section 4.18: "ADC electrical characteristics" has been moved up in hierarchy (it was Section 4.18.5). Table: " ADC conversion characteristics" - RAD: changed initial max value Table: "On-chip peripherals current consumption" - Removed min/max from the heading - Changed unit of measurement and consequently rounded the values 15-Mar-2010 6 Internal release. 110/113 Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Revision history Table 53. Document revision history (continued) Date 22-Jul-2010 Revision Changes 7 Changes between revisions 5 and 7 Added LQFP64 package information Updated the "Features" section. Section "Introduction" - Relocated a note Table: "SPC560Bx and SPC560Cx device comparison" - Added footnote regarding SCI and CAN Added eDMA block in the "SPC560Bx and SPC560Cx series block diagram" figure Removed alternate function information from "LQFP 100-pin configuration" and "LQFP 100-pin configuration" figures. Added "Functional port pin descriptions" table Deleted the "NVUSRO[WATCHDOG_EN] field description" section Table: "Absolute maximum ratings" - Removed the min value of VIN relative tio VDD Table "Recommended operating conditions (3.3 V)" - TVDD: made single row "Recommended operating conditions (5.0 V)" - deleted TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part, TJ M-Grade Part rows Table: "LQFP thermal characteristics" - Added more rows - Rounded the values Removed table "LBGA208 thermal characteristics" Table "I/O input DC electrical characteristics" - WFI: insered a footnote - WNFI: insered a footnote Table "I/O consuption" - Removed IDYNSEG row - Added "I/O weight " table Replaced "nRSTIN" with "RESET" in the "RESET electrical characteristics" section. Table "Voltage regulator electrical characteristics" - Updated the values - Removed IVREGREF and IVREDLVD12 - Added a note about IDD_BC Table: "Low voltage monitor electrical characteristics" - changed min valueVLVDHV3L, from 2.7 to 2.6 - Inserted max value of VLVDLVCORL - Updated VPORH values - Updated VLVDLVCORL value Table "Low voltage power domain electrical characteristics" - Entirely updated Table "Program and erase specifications" - Inserted Teslat row Table "Flash power supply DC electrical characteristics" - Entirely updated Doc ID 14619 Rev 7 111/113 Revision history SPC560Bx, SPC560Cx Table 53. Document revision history (continued) Date 22-Jul-2010 112/113 Revision Changes Table "Start-up time/Switch-off time" - Entirely updated Figures "Crystal oscillator and resonator connection scheme" - Relocated a note Table "Slow external crystal oscillator (32 kHz) electrical characteristics" - Removed gmSXOSC row - Inserted values of ISXOSCBIAS Table "FMPLL electrical characteristics" - Rounded the values of fVCO Table "Fast internal RC oscillator (16 MHz) electrical characteristics" - Entirely updated. Table "ADC conversion characteristics" 7 (continued) - Updated the description of the conditions of tADC_PU and tADC_S. - Added "IADCPWD" and "IADCRUN" rows Table "DSPI characteristics" - Entirely updated. Updated "Order codes" table. Figure "Commercial product code structure" - Replaced PowerPC with "Power ArchitectureTM" in the product identifier - Removed the note about the condition from "Flash read access timing" table - Removed the notes that assert the values need to be confirmed before validation - Exchanged the order of "LQFP 100-pin configuration" and "LQFP 144-pin configuration" - Exchanged the order of "LQFP 100-pin package mechanical drawing" and "LQFP 144-pin package mechanical drawing" Doc ID 14619 Rev 7 SPC560Bx, SPC560Cx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. 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