SPC560B44L3C4E0X - STMicroelectronics, Inc.

July 2010 Doc ID 14619 Rev 7 1/113

SPC560B40x, SPC560B44x, SPC560B50x

SPC560C40x, SPC560C44x, SPC560C50x

32-bit MCU family built on the Power Architecture® embedded

category for automotive body electronics applications

Features

■High-performance 64 MHz e200z0h CPU

– 32-bit Power Architecture® technology

– Up to 60 DMIPs operation

– Variable length encoding (VLE)

■Memory

– Up to 512 Kbytes Code Flash, with ECC

– 64 Kbytes Data Flash, with ECC

– Up to 48 Kbytes SRAM, with ECC

– 8-entry memory protection unit (MPU)

■Interrupts

– 16 priority levels

– Non-maskable interrupt (NMI)

– Up to 34 ext. int. including 18 wakeup lines

■GPIO: QFP64/45, QFP100/75, QFP144/123

■Timer units

– 6-channel 32-bit periodic interrupt timers

– 4-channel 32-bit system timer module

– System watchdog timer

– Real-time clock timer

■16-bit counter time-triggered I/Os

– Up to 56 channels with PWM/MC/IC/OC

– ADC diagnostic via CTU

■Communications interface

– Up to 6 FlexCAN interfaces (2.0B active)

with 64-message objects each

– Up to 4 LINFlex/UART

– 3 DSPI / I2C

■10-bit A/D converter with up to 36 channels

– Up to 64 channels via external multiplexing

– Individual conversion registers

– Cross triggering unit

■Dedicated diagnostic module for lighting

– Advanced PWM generation

– Time-triggered diagnostic

– PWM-synchronized ADC measurements

■Clock generation

– 4 to 16 MHz fast external crystal oscillator

– 32 KHz slow external crystal oscillator

– 16 MHz fast internal RC oscillator

– 128 kHz slow internal RC oscillator

– Software-controlled FMPLL

– Clock monitoring unit

■Exhaustive debugging capability

– Nexus1 on all devices

– Nexus2+ available on emulation package

■Low power capabilities

– Ultra-low power standby with RTC, SRAM

and CAN monitoring

– Fast wakeup schemes

■Operating temp. range up to -40 to 125 °C

■Single 5 V or 3.3 V supply

LQFP64 (10 x 10 x 1.4 mm)

LQFP144 (20 x 20 x 1.4 mm)

LQFP100 (14 x 14 x 1.4 mm)

Table 1. Device summary

Package 256 Kbyte code Flash 384 Kbyte code Flash 512 Kbyte code Flash

LQFP144 SPC560B40L5 — SPC560B44L5 — SPC560B50L5 —

LQFP100 SPC560B40L3 SPC560C40L3 SPC560B44L3 SPC560C44L3 SPC560B50L3 SPC560C50L3

LQFP64 SPC560B40L1 SPC560C40L1 — — SPC560B50L1 SPC560C50L1

LBGA208(1) — — — — SPC560B50B2 —

1. LBGA208 available only as development package for Nexus2+

www.st.com

Contents SPC560Bx, SPC560Cx
2/113 Doc ID 14619 Rev 7
Contents
Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1 Document overview  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7
2 Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7
Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 13
1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  13
2 Pin muxing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
Electrical characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1 Introduction   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  40
2 Parameter classification  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  40
3 NVUSRO register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  41
3.1 NVUSRO[PAD3V5V] field description  . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . 41
4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  41
5 Recommended operating conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  42
6 Thermal characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  44
6.1 Package thermal characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.2 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7 I/O pad electrical characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  46
7.1 I/O pad types  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2 I/O input DC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.3 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.4 Output pin transition times  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.5 I/O pad current specification   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8 RESET electrical characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  56
9 Power management electrical characteristics   . . . . . . . . . . . . . . . . . . . . .  59
9.1 Voltage regulator electrical characteristics   . . . . . . . . . . . . . . . . . . . . . . 59
9.2 Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 62
10 Low voltage domain power consumption  . . . . . . . . . . . . . . . . . . . . . . . . .  63
11 Flash memory electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . .  64

SPC560Bx, SPC560Cx Contents
Doc ID 14619 Rev 7 3/113
11.1 Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
11.2 Flash power supply DC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . 66
11.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12 Electromagnetic compatibility (EMC) characteristics  . . . . . . . . . . . . . . . .  67
12.1 Designing hardened software to avoid noise problems  . . . . . . . . . . . . . 67
12.2 Electromagnetic interference (EMI)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.3 Absolute maximum ratings (electrical sensitivity)   . . . . . . . . . . . . . . . . . 68
13 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics  . .  69
14 Slow external crystal oscillator (32 kHz) electrical characteristics  . . . . . .  72
15 FMPLL electrical characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  75
16 Fast internal RC oscillator (16 MHz) electrical characteristics  . . . . . . . . .  76
17 Slow internal RC oscillator (128 kHz) electrical characteristics  . . . . . . . .  76
18 ADC electrical characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  77
18.1 Introduction   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
18.2 Input impedance and ADC accuracy  . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
18.3 ADC electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
19 On-chip peripherals  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  86
19.1 Current consumption  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
19.2 DSPI characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
19.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
19.4 JTAG characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Package characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
1 ECOPACK®  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  97
2 Package mechanical data   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  97
2.1 LQFP64  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.2 LQFP100  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2.3 LQFP144  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.4 LBGA208  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Ordering information   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Appendix A Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

List of tables SPC560Bx, SPC560Cx
4/113 Doc ID 14619 Rev 7
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. SPC560Bx and SPC560Cx device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. SPC560Bx and SPC560Cx series block summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Functional port pin descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 6. PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 7. OSCILLATOR_MARGIN field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 9. Recommended operating conditions (3.3 V)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 10. Recommended operating conditions (5.0 V)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 11. LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 12. I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 13. I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 14. SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 15. MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 49
Table 16. FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 17. Output pin transition times  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 18. I/O supply segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 19. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 20. I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 21. Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 22. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 23. Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 24. Low voltage power domain electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 25. Program and erase specifications  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 26. Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 27. Flash read access timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 28. Code Flash power supply DC electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 29. Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 30. EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 31. ESD absolute maximum ratings   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 32. Latch-up results  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 33. Crystal description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 34. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 71
Table 35. Crystal motional characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 36. Slow external crystal oscillator (32 kHz) electrical characteristics  . . . . . . . . . . . . . . . . . . . 75
Table 37. FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 76
Table 39. Slow internal RC oscillator (128 kHz) electrical characteristics  . . . . . . . . . . . . . . . . . . . . . 77
Table 40. ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 41. ADC conversion characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 42. On-chip peripherals current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 43. DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 44. Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 45. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 46. LQFP64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 47. LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 48. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

SPC560Bx, SPC560Cx List of tables

Doc ID 14619 Rev 7 5/113

Table 49. LBGA208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 50. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Table 51. Order Codes for Engineering Samples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 52. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

List of figures SPC560Bx, SPC560Cx
6/113 Doc ID 14619 Rev 7
List of figures
Figure 1. SPC560Bx and SPC560Cx series block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2. LQFP 64-pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. LQFP 100-pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. LQFP 144-pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. LBGA208 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 7. Start-up reset requirements  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 8. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 9. Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 10. Low voltage monitor vs reset  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 11. Crystal oscillator and resonator connection scheme  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 12. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 71
Figure 13. Crystal oscillator and resonator connection scheme  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 14. Equivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 15. Slow external crystal oscillator (32 kHz) electrical characteristics  . . . . . . . . . . . . . . . . . . . 74
Figure 16. ADC characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 17. Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 18. Input equivalent circuit (extended channels)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 19. Transient behavior during sampling phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 20. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 21. DSPI classic SPI timing – master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 22. DSPI classic SPI timing – master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 23. DSPI classic SPI timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 24. DSPI classic SPI timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 25. DSPI modified transfer format timing – master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 26. DSPI modified transfer format timing – master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 27. DSPI modified transfer format timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 28. DSPI modified transfer format timing – slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 29. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 30. Timing diagram – JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 31. LQFP64 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 32. LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 33. LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 34. LBGA208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 35. Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

SPC560Bx, SPC560Cx Introduction

Doc ID 14619 Rev 7 7/113

1 Introduction

1.1 Document overview

This document describes the features of the family and options available within the family

members, and highlights important electrical and physical characteristics of the device. To

ensure a complete understanding of the device functionality, refer also to the device

reference manual and errata sheet.

1.2 Description

This family of 32-bit system-on-chip (SoC) microcontrollers is the latest achievement in

integrated automotive application controllers. It belongs to an expanding family of

automotive-focused products designed to address the next wave of body electronics

applications within the vehicle. The advanced and cost-efficient host processor core of this

automotive controller family complies with the Power Architecture embedded category and

only implements the VLE (variable-length encoding) APU, providing improved code density.

It operates at speeds of up to 64 MHz and offers high performance processing optimized for

low power consumption. It capitalizes on the available development infrastructure of current

Power Architecture devices and is supported with software drivers, operating systems and

configuration code to assist with users implementations.

Introduction SPC560Bx, SPC560Cx

8/113 Doc ID 14619 Rev 7

Table 2. SPC560Bx and SPC560Cx device comparison(1)

Feature

Device

SPC560

B40L1

SPC560

B40L3

SPC560

B40L5

SPC560

C40L1

SPC560

C40L3

SPC560

B44L3

SPC560

B44L5

SPC560

C44L3

SPC560

B50L1

SPC560

B50L3

SPC560

B50L5

SPC560

C50L1

SPC560

C50L3

SPC560

B50B2

CPU e200z0h

Execution

speed(2) Static – up to 64 MHz

Code Flash 256 KB 384 KB 512 KB

Data Flash 64 KB (4 × 16 KB)

RAM 24KB 32KB 28KB 40KB 32KB 48 KB

MPU 8-entry

ADC 12 ch,

10-bit

28 ch,

10-bit

36 ch,

10-bit

8ch,

10-bit

28 ch,

10-bit

28 ch,

10-bit

36 ch,

10-bit

28 ch,

10-bit

12 ch,

10-bit

28 ch,

10-bit

36 ch,

10-bit

8ch,

10-bit

28 ch,

10-bit

36 ch,

10-bit

CTU Ye s

Total timer

I/O(3)

eMIOS

12 ch,

16-bit

28 ch,

16-bit

56 ch,

16-bit

12 ch,

16-bit

28 ch,

16-bit

28 ch,

16-bit

56ch,

16-bit

28 ch,

16-bit

12 ch,

16-bit

28 ch,

16-bit

56 ch,

16-bit

12 ch,

16-bit

28 ch,

16-bit

56 ch,

16-bit

– PWM + MC +

IC/OC(4) 2 ch 5 ch 10 ch 2 ch 5 ch 5 ch 10 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 10 ch

– PWM +

IC/OC(4) 10 ch 20 ch 40 ch 10 ch 20 ch 20 ch 40 ch 20 ch 10 ch 20 ch 40 ch 10 ch 20 ch 40 ch

–IC/OC

(4) 0ch 3ch 6ch 0ch 3ch 3ch 6ch 3ch 0ch 3ch 6ch 0ch 3ch 6ch

SCI (LINFlex) 3(5) 4

SPI (DSPI)232333232 3

CAN

(FlexCAN) 2(6) 56 3

(7) 63

(7) 56

I2C 1

32 kHz

oscillator Ye s

SPC560Bx, SPC560Cx Introduction

Doc ID 14619 Rev 7 9/113

GPIO(8) 45 79 123 45 79 79 123 79 45 79 123 45 79 123

Debug JTAG Nexus2+

Package LQFP

64(9)

LQFP

100

LQFP

144

LQFP

64(9)

LQFP

100

LQFP

100

LQFP

144

LQFP

100

LQFP

64(9)

LQFP

100

LQFP

144

LQFP

64(9)

LQFP

100

LBGA

208(10)

1. Feature set dependent on selected peripheral multiplexing—table shows example implementation

2. Based on 105 °C ambient operating temperature

3. Refer to eMIOS section of device reference manual for information on the channel configuration and functions

4. IC - Input Capture; OC - Output Compare; PWM - Pulse Width Modulation; MC - Modulus counter

5. SCI0, SCI1 and SCI2 are available. SCI3 is not available.

6. CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available.

7. CAN0, CAN1 and CAN2 are available. CAN3, CAN4 and CAN5 are not available.

8. I/O count based on multiplexing with peripherals

9. All LQFP64 information is indicative and must be confirmed during silicon validation.

10. LBGA208 available only as development package for Nexus2+

Table 2. SPC560Bx and SPC560Cx device comparison(1) (continued)

Feature

Device

SPC560

B40L1

SPC560

B40L3

SPC560

B40L5

SPC560

C40L1

SPC560

C40L3

SPC560

B44L3

SPC560

B44L5

SPC560

C44L3

SPC560

B50L1

SPC560

B50L3

SPC560

B50L5

SPC560

C50L1

SPC560

C50L3

SPC560

B50B2

Block diagram SPC560Bx, SPC560Cx

10/113 Doc ID 14619 Rev 7

2 Block diagram

Figure 1 shows a top-level block diagram of the SPC560Bx and SPC560Cx device series.

Figure 1. SPC560Bx and SPC560Cx series block diagram

3 x

DSPI

FMPLL

Nexus 2+

Nexus

SRAM

SIUL

Reset control

48 KB

External

IMUX

GPIO and

JTAG

pad control

JTAG port

Nexus port e200z0h

Interrupt requests

64-bit 2 x 3 Crossbar Switch

6 x

FlexCAN

Peripheral bridge

interrupt

request

Interrupt

request

I/O

Clocks

Instructions

Data

Voltage

regulator

NMI

SWT PIT

STM

NMI

SIUL

. . . . . . . . .

. . .

INTC

I2C

. . .

4 x

LINFlex

2 x

eMIOS

36 Ch.

ADC

MPU

CMU

SRAM Flash

Code Flash

512 KB

Data Flash

64 KB

MC_PCUMC_MEMC_CGMMC_RGM BAM

CTU

RTC SSCM

(Master)

(Slave)

controller

Legend:

ADC Analog-to-Digital Converter

BAM Boot Assist Module

FlexCAN Controller Area Network

CMU Clock Monitor Unit

CTU Cross Triggering Unit

DSPI Deserial Serial Peripheral Interface

eDMA Enhanced Direct Memory Access

eMIOS Enhanced Modular Input Output System

FMPLL Frequency-Modulated Phase-Locked Loop

I2C Inter-integrated Circuit Bus

IMUX Internal Multiplexer

INTC Interrupt Controller

JTAG JTAG controller

LINFlex Serial Communication Interface (LIN support)

ECSM Error Correction Status Module

MC_CGM Clock Generation Module

MC_ME Mode Entry Module

MC_PCU Power Control Unit

MC_RGM Reset Generation Module

MPU Memory Protection Unit

Nexus Nexus Development Interface (NDI) Level

NMI Non-Maskable Interrupt

PIT Periodic Interrupt Timer

RTC Real-Time Clock

SIUL System Integration Unit Lite

SRAM Static Random-Access Memory

SSCM System Status Configuration Module

STM System Timer Module

SWT Software Watchdog Timer

WKPU Wakeup Unit

MPU

ECSM

from peripheral

registers

blocks

WKPU

Interrupt

request with

wakeup

functionality

(Master)

eDMA

SPC560Bx, SPC560Cx Block diagram

Doc ID 14619 Rev 7 11/113

Ta bl e 3 summarizes the functions of all blocks present in the SPC560Bx and SPC560Cx

series of microcontrollers. Please note that the presence and number of blocks varies by

device and package.

Table 3. SPC560Bx and SPC560Cx series block summary

Block Function

Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to digital-converter

Boot assist module (BAM) A block of read-only memory containing VLE code which is executed according

to the boot mode of the device

Clock monitor unit (CMU) Monitors clock source (internal and external) integrity

Cross triggering unit (CTU) Enables synchronization of ADC conversions with a timer event from the eMIOS

or from the PIT

Deserial serial peripheral

interface (DSPI)

Provides a synchronous serial interface for communication with external

devices

Error Correction Status Module

(ECSM)

Provides a myriad of miscellaneous control functions for the device including

program-visible information about configuration and revision levels, a reset

status register, wakeup control for exiting sleep modes, and optional features

such as information on memory errors reported by error-correcting codes

Enhanced Direct Memory Access

(eDMA)

Performs complex data transfers with minimal intervention from a host

processor via “n” programmable channels.

Enhanced modular input output

system (eMIOS) Provides the functionality to generate or measure events

Flash memory Provides non-volatile storage for program code, constants and variables

FlexCAN (controller area

network) Supports the standard CAN communications protocol

FMPLL (frequency-modulated

phase-locked loop)

Generates high-speed system clocks and supports programmable frequency

modulation

Internal multiplexer (IMUX) SIU

subblock Allows flexible mapping of peripheral interface on the different pins of the device

Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of

data exchange between devices

Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests

JTAG controller Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

LINflex controller Manages a high number of LIN (Local Interconnect Network protocol)

messages efficiently with a minimum of CPU load

Clock generation module

(MC_CGM)

Provides logic and control required for the generation of system and peripheral

clocks

Mode entry module (MC_ME)

Provides a mechanism for controlling the device operational mode and mode

transition sequences in all functional states; also manages the power control

unit, reset generation module and clock generation module, and holds the

configuration, control and status registers accessible for applications

Power control unit (MC_PCU)

Reduces the overall power consumption by disconnecting parts of the device

from the power supply via a power switching device; device components are

grouped into sections called “power domains” which are controlled by the PCU

Block diagram SPC560Bx, SPC560Cx

12/113 Doc ID 14619 Rev 7

Reset generation module

(MC_RGM)

Centralizes reset sources and manages the device reset sequence of the

device

Memory protection unit (MPU) Provides hardware access control for all memory references generated in a

device

Nexus development interface

(NDI)

Provides real-time development support capabilities in compliance with the

IEEE-ISTO 5001-2003 standard

Periodic interrupt timer (PIT) Produces periodic interrupts and triggers

Real-time counter (RTC)

A free running counter used for time keeping applications, the RTC can be

configured to generate an interrupt at a predefined interval independent of the

mode of operation (run mode or low-power mode)

System integration unit (SIU)

Provides control over all the electrical pad controls and up 32 ports with 16 bits

of bidirectional, general-purpose input and output signals and supports up to 32

external interrupts with trigger event configuration

Static random-access memory

(SRAM) Provides storage for program code, constants, and variables

System status configuration

module (SSCM)

Provides system configuration and status data (such as memory size and

status, device mode and security status), device identification data, debug

status port enable and selection, and bus and peripheral abort enable/disable

System timer module (STM) Provides a set of output compare events to support AUTOSAR and operating

system tasks

System watchdog timer (SWT) Provides protection from runaway code

Wakeup unit (WKPU)

The wakeup unit supports up to 18 external sources that can generate

interrupts or wakeup events, of which 1 can cause non-maskable interrupt

requests or wakeup events.

Crossbar (XBAR) switch

Supports simultaneous connections between two master ports and three slave

ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus

width

Table 3. SPC560Bx and SPC560Cx series block summary (continued)

Block Function

SPC560Bx, SPC560Cx Package pinouts and signal descriptions

Doc ID 14619 Rev 7 13/113

3 Package pinouts and signal descriptions

3.1 Package pinouts

The available LQFP pinouts and the LBGA208 ballmap are provided in the following figures.

For pin signal descriptions, please refer to the device reference manual (RM0017).

Figure 2. LQFP 64-pin configuration (top view)(a)

a. All LQFP64 information is indicative and must be confirmed during silicon validation.

PB[3]

PC[9]

PA [ 2 ]

PA [ 1 ]

PA [ 0 ]

VPP_TEST

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PC[10]

PB[0]

PB[1]

PC[6]

PA[11]

PA[10]

PA [ 9 ]

PA [ 8 ]

PA [ 7 ]

PA [ 3 ]

PB[15]

PB[14]

PB[13]

PB[12]

PB[11]

PB[7]

PB[6]

PB[5]

VDD_HV_ADC

VSS_HV_ADC

PC[7]

PA[15]

PA[14]

PA[ 4 ]

PA[13]

PA[12]

VDD_LV

VSS_LV

XTAL

VSS_HV

EXTAL

VDD_HV

PB[9]

PB[8]

PB[10]

PB[4]

PB[2]

PC[8]

PC[4]

PC[5]

PH[9]

PC[0]

VSS_LV

VDD_LV

VDD_HV

VSS_HV

PC[1]

PH[10]

PA [ 6 ]

PA [ 5 ]

PC[2]

PC[3]

LQFP64

Package pinouts and signal descriptions SPC560Bx, SPC560Cx

14/113 Doc ID 14619 Rev 7

Figure 3. LQFP 100-pin configuration (top view)

Figure 4. LQFP 144-pin configuration (top view)

100

PB[3]

PC[9]

PC[14]

PC[15]

PA[2]

PE[0]

PA[1]

PE[1]

PE[8]

PE[9]

PE[10]

PA[0]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PC[11]

PC[10]

PB[0]

PB[1]

PC[6]

PA[11]

PA[10]

PA[9]

PA[8]

PA[7]

VDD_HV

VSS_HV

PA[3]

PB[15]

PD[15]

PB[14]

PD[14]

PB[13]

PD[13]

PB[12]

PD[12]

PB[11]

PD[11]

PD[10]

PD[9]

PB[7]

PB[6]

PB[5]

VDD_HV_ADC

VSS_HV_ADC

PC[7]

PA[15]

PA[14]

PA[4]

PA[13]

PA[12]

VDD_LV

VSS_LV

XTAL

VSS_HV

EXTAL

VDD_HV

PB[9]

PB[8]

PB[10]

PD[0]

PD[1]

PD[2]

PD[3]

PD[4]

PD[5]

PD[6]

PD[7]

PD[8]

PB[4]

PB[2]

PC[8]

PC[13]

PC[12]

PE[7]

PE[6]

PE[5]

PE[4]

PC[4]

PC[5]

PE[3]

PE[2]

PH[9]

PC[0]

VSS_LV

VDD_LV

VDD_HV

VSS_HV

PC[1]

PH[10]

PA [ 6 ]

PA [ 5 ]

PC[2]

PC[3]

PE[12]

LQFP100

Note:

Availability of port pin alternate functions depends on product selection.

108

107

106

105

104

103

102

101

100

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

PB[3]

PC[9]

PC[14]

PC[15]

PG[5]

PG[4]

PG[3]

PG[2]

PA[2]

PE[0]

PA[1]

PE[1]

PE[8]

PE[9]

PE[10]

PA[0]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PG[9]

PG[8]

PC[11]

PC[10]

PG[7]

PG[6]

PB[0]

PB[1]

PF[9]

PF[8]

PF[12]

PC[6]

PA [ 1 1 ]

PA [ 1 0 ]

PA [ 9 ]

PA [ 8 ]

PA [ 7 ]

PE[13]

PF[14]

PF[15]

VDD_HV

VSS_HV

PG[0]

PG[1]

PH[3]

PH[2]

PH[1]

PH[0]

PG[12]

PG[13]

PA [ 3 ]

PB[15]

PD[15]

PB[14]

PD[14]

PB[13]

PD[13]

PB[12]

PD[12]

PB[11]

PD[11]

PD[10]

PD[9]

PB[7]

PB[6]

PB[5]

VDD_HV_ADC

VSS_HV_ADC

PC[7]

PF[10]

PF[11]

PA[15]

PF[13]

PA[14]

PA[4]

PA[13]

PA[12]

VDD_LV

VSS_LV

XTAL

VSS_HV

EXTAL

VDD_HV

PB[9]

PB[8]

PB[10]

PF[0]

PF[1]

PF[2]

PF[3]

PF[4]

PF[5]

PF[6]

PF[7]

PD[0]

PD[1]

PD[2]

PD[3]

PD[4]

PD[5]

PD[6]

PD[7]

PD[8]

PB[4]

PB[2]

PC[8]

PC[13]

PC[12]

PE[7]

PE[6]

PH[8]

PH[7]

PH[6]

PH[5]

PH[4]

PE[5]

PE[4]

PC[4]

PC[5]

PE[3]

PE[2]

PH[9]

PC[0]

VSS_LV

VDD_LV

VDD_HV

VSS_HV

PC[1]

PH[10]

PA [ 6 ]

PA [ 5 ]

PC[2]

PC[3]

PG[11]

PG[10]

PE[15]

PE[14]

PG[15]

PG[14]

PE[12]

LQFP144

Note:

Availability of port pin alternate functions depends on product selection.

SPC560Bx, SPC560Cx Package pinouts and signal descriptions

Doc ID 14619 Rev 7 15/113

Figure 5. LBGA208 configuration

12345678910111213141516

APC[8] PC[13] NC NC PH[8] PH[4] PC[5] PC[0] NC NC PC[2] NC PE[15] NC NC NC A

BPC[9] PB[2] NC PC[12] PE[6] PH[5] PC[4] PH[9] PH[10] NC PC[3] PG[11] PG[15] PG[14] PA[11] PA[10] B

CPC[14] VDD_HV PB[3] PE[7] PH[7] PE[5] PE[3] VSS_LV PC[1] NC PA[5] NC PE[14] PE[12] PA[9] PA[8] C

DNC NC PC[15] NC PH[6] PE[4] PE[2] VDD_LV VDD_HV NC PA[6] NC PG[10] PF[14] PE[13] PA[7] D

EPG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[15] VDD_HV E

FPE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2] F

GPE[9] PE[8] PE[10] PA[0] VSS_HV VSS_HV VSS_HV VSS_HV VDD_HV NC NC MSEO G

HVSS_HV PE[11] VDD_HV NC VSS_HV VSS_HV VSS_HV VSS_HV MDO3 MDO2 MDO0 MDO1 H

JRESET VSS_LV NC NC VSS_HV VSS_HV VSS_HV VSS_HV NC NC NC NC J

KEVTI NC VDD_BV VDD_LV VSS_HV VSS_HV VSS_HV VSS_HV NC PG[12] PA[3] PG[13] K

LPG[9] PG[8] NC EVTO PB[15] PD[15] PD[14] PB[14] L

MPG[7] PG[6] PC[10] PC[11] PB[13] PD[13] PD[12] PB[12] M

NPB[1] PF[9] PB[0] NC NC PA[4] VSS_LV EXTAL VDD_HV PF[0] PF[4] NC PB[11] PD[10] PD[9] PD[11] N

PPF[8] NC PC[7] NC NC PA[14] VDD_LV XTAL PB[10] PF[1] PF[5] PD[0] PD[3] VDD_HV

_ADC PB[6] PB[7] P

RPF[12] PC[6] PF[10] PF[11] VDD_HV PA[15] PA[13] NC OSC32K

_XTAL PF[3] PF[7] PD[2] PD[4] PD[7] VSS_HV

_ADC PB[5] R

TNC NC NC MCKO NC PF[13] PA[12] NC OSC32K

_EXTAL PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4] T

12345678910111213141516

Note: LBGA208 available only as development package for Nexus 2+. NC = Not connected

Package pinouts and signal descriptions SPC560Bx, SPC560Cx

16/113 Doc ID 14619 Rev 7

3.2 Pin muxing

Ta b l e 4 defines the pin list and muxing for this device.

Each entry of Ta b l e 4 shows all the possible configurations for each pin, via the alternate functions. The default function assigned

to each pin after reset is indicated by AF0.

Table 4. Functional port pin descriptions

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

PA [ 0 ] P C R [ 0 ]

AF0

AF1

AF2

AF3

—

GPIO[0]

E0UC[0]

CLKOUT

—

WKUP[19](4)

SIUL

eMIOS0

CGL

—

WKPU

I/O

—

M Tristate 5 12 16 G4

PA [ 1 ] P C R [ 1 ]

AF0

AF1

AF2

AF3

—

GPIO[1]

E0UC[1]

—

NMI(5)

WKUP[2](4)

SIUL

eMIOS0

—

WKPU

I/O

—

STristate 4 7 11 F3

PA [ 2 ] P C R [ 2 ]

AF0

AF1

AF2

AF3

—

GPIO[2]

E0UC[2]

—

WKUP[3](4)

SIUL

eMIOS0

—

WKPU

I/O

—

STristate359F2

PA [ 3 ] P C R [ 3 ]

AF0

AF1

AF2

AF3

—

GPIO[3]

E0UC[3]

—

EIRQ[0]

SIUL

eMIOS0

—

SIUL

I/O

—

STristate 43 68 90 K15

SPC560Bx, SPC560Cx Package pinouts and signal descriptions

Doc ID 14619 Rev 7 17/113

PA [ 4 ] P C R [ 4 ]

AF0

AF1

AF2

AF3

—

GPIO[4]

E0UC[4]

—

WKUP[9](4)

SIUL

eMIOS0

—

WKPU

I/O

—

STristate 20 29 43 N6

PA [ 5 ] P C R [ 5 ]

AF0

AF1

AF2

AF3

GPIO[5]

E0UC[5]

—

SIUL

eMIOS0

—

I/O

—

M Tristate 51 79 118 C11

PA [ 6 ] P C R [ 6 ]

AF0

AF1

AF2

AF3

—

GPIO[6]

E0UC[6]

—

EIRQ[1]

SIUL

eMIOS0

—

SIUL

I/O

—

S Tristate 52 80 119 D11

PA [ 7 ] P C R [ 7 ]

AF0

AF1

AF2

AF3

—

GPIO[7]

E0UC[7]

LIN3TX

—

EIRQ[2]

SIUL

eMIOS0

LINFlex_3

—

SIUL

I/O

—

S Tristate 44 71 104 D16

PA [ 8 ] P C R [ 8 ]

AF0

AF1

AF2

AF3

—

N/A(6)

—

GPIO[8]

E0UC[8]

—

EIRQ[3]

ABS[0]

LIN3RX

SIUL

eMIOS0

—

SIUL

BAM

LINFlex_3

I/O

—

Input,

weak

pull-up

45 72 105 C16

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

Package pinouts and signal descriptions SPC560Bx, SPC560Cx

18/113 Doc ID 14619 Rev 7

PA [ 9 ] P C R [ 9 ]

AF0

AF1

AF2

AF3

N/A(6)

GPIO[9]

E0UC[9]

—

FAB

SIUL

eMIOS_0

—

BAM

I/O

—

SPull-

down 46 73 106 C15

PA[10] PCR[10]

AF0

AF1

AF2

AF3

GPIO[10]

E0UC[10]

SDA

—

SIUL

eMIOS_0

I2C_0

—

I/O

—

S Tristate 47 74 107 B16

PA[11] PCR[11]

AF0

AF1

AF2

AF3

GPIO[11]

E0UC[11]

SCL

—

SIUL

eMIOS0

I2C_0

—

I/O

—

S Tristate 48 75 108 B15

PA[12] PCR[12]

AF0

AF1

AF2

AF3

—

GPIO[12]

—

SIN_0

SIUL

—

DSPI0

I/O

—

STristate 22 31 45 T7

PA[13] PCR[13]

AF0

AF1

AF2

AF3

GPIO[13]

SOUT_0

—

SIUL

DSPI_0

—

I/O

—

MTristate 21 30 44 R7

PA[14] PCR[14]

AF0

AF1

AF2

AF3

—

GPIO[14]

SCK_0

CS0_0

—

EIRQ[4]

SIUL

DSPI_0

—

SIUL

I/O

—

MTristate 19 28 42 P6

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

SPC560Bx, SPC560Cx Package pinouts and signal descriptions

Doc ID 14619 Rev 7 19/113

PA[15] PCR[15]

AF0

AF1

AF2

AF3

—

GPIO[15]

CS0_0

SCK_0

—

WKUP[10](4)

SIUL

DSPI_0

—

WKPU

I/O

—

MTristate 18 27 40 R6

PB[0] PCR[16]

AF0

AF1

AF2

AF3

GPIO[16]

CAN0TX

—

SIUL

FlexCAN_0

—

I/O

—

MTristate 14 23 31 N3

PB[1] PCR[17]

AF0

AF1

AF2

AF3

—

GPIO[17]

—

WKUP[4](4)

CAN0RX

SIUL

—

WKPU

FlexCAN_0

I/O

—

STristate 15 24 32 N1

PB[2] PCR[18]

AF0

AF1

AF2

AF3

GPIO[18]

LIN0TX

SDA

—

SIUL

LINFlex_0

I2C_0

—

I/O

—

M Tristate 64 100 144 B2

PB[3] PCR[19]

AF0

AF1

AF2

AF3

—

GPIO[19]

—

SCL

—

WKUP[11](4)

LIN0RX

SIUL

—

I2C_0

—

WKPU

LINFlex_0

I/O

—

I/O

—

STristate111C3

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

Package pinouts and signal descriptions SPC560Bx, SPC560Cx

20/113 Doc ID 14619 Rev 7

PB[4] PCR[20]

AF0

AF1

AF2

AF3

—

GPIO[20]

—

ANP[0]

SIUL

—

ADC

—

I Tristate 32 50 72 T16

PB[5] PCR[21]

AF0

AF1

AF2

AF3

—

GPIO[21]

—

ANP[1]

SIUL

—

ADC

—

ITristate 35 53 75 R16

PB[6] PCR[22]

AF0

AF1

AF2

AF3

—

GPIO[22]

—

ANP[2]

SIUL

—

ADC

—

ITristate 36 54 76 P15

PB[7] PCR[23]

AF0

AF1

AF2

AF3

—

GPIO[23]

—

ANP[3]

SIUL

—

ADC

—

ITristate 37 55 77 P16

PB[8] PCR[24]

AF0

AF1

AF2

AF3

—

GPIO[24]

—

ANS[0]

OSC32K_XTAL(7)

SIUL

—

ADC

SXOSC

—

I/O

ITristate 30 39 53 R9

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

SPC560Bx, SPC560Cx Package pinouts and signal descriptions

Doc ID 14619 Rev 7 21/113

PB[9] PCR[25]

AF0

AF1

AF2

AF3

—

GPIO[25]

—

ANS[1]

OSC32K_EXTAL(7)

SIUL

—

ADC

SXOSC

—

I/O

ITristate 29 38 52 T9

PB[10] PCR[26]

AF0

AF1

AF2

AF3

—

GPIO[26]

—

ANS[2]

WKUP[8](4)

SIUL

—

ADC

WKPU

I/O

—

JTristate 31 40 54 P9

PB[11](8) PCR[27]

AF0

AF1

AF2

AF3

—

GPIO[27]

E0UC[3]

—

CS0_0

ANS[3]

SIUL

eMIOS_0

—

DSPI_0

ADC

I/O

—

I/O

JTristate 38 59 81 N13

PB[12] PCR[28]

AF0

AF1

AF2

AF3

—

GPIO[28]

E0UC[4]

—

CS1_0

ANX[0]

SIUL

eMIOS

—

DSPI_0

ADC

I/O

—

J Tristate 39 61 83 M16

PB[13] PCR[29]

AF0

AF1

AF2

AF3

—

GPIO[29]

E0UC[5]

—

CS2_0

ANX[1]

SIUL

eMIOS_0

—

DSPI_0

ADC

I/O

—

J Tristate 40 63 85 M13

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

Package pinouts and signal descriptions SPC560Bx, SPC560Cx

22/113 Doc ID 14619 Rev 7

PB[14] PCR[30]

AF0

AF1

AF2

AF3

—

GPIO[30]

E0UC[6]

—

CS3_0

ANX[2]

SIUL

eMIOS0

—

DSPI_0

ADC

I/O

—

J Tristate 41 65 87 L16

PB[15] PCR[31]

AF0

AF1

AF2

AF3

—

GPIO[31]

E0UC[7]

—

CS4_0

ANX[3]

SIUL

eMIOS_0

—

DSPI_0

ADC

I/O

—

J Tristate 42 67 89 L13

PC[0](9) PCR[32]

AF0

AF1

AF2

AF3

GPIO[32]

—

TDI

—

SIUL

—

JTAGC

—

I/O

—

Input,

weak

pull-up

59 87 126 A8

PC[1](9) PCR[33]

AF0

AF1

AF2

AF3

GPIO[33]

—

TDO(10)

—

SIUL

—

JTAGC

—

I/O

—

M Tristate 54 82 121 C9

PC[2] PCR[34]

AF0

AF1

AF2

AF3

—

GPIO[34]

SCK_1

CAN4TX(11)

—

EIRQ[5]

SIUL

DSPI_1

LINFlex_4

—

SIUL

I/O

—

M Tristate 50 78 117 A11

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

SPC560Bx, SPC560Cx Package pinouts and signal descriptions

Doc ID 14619 Rev 7 23/113

PC[3] PCR[35]

AF0

AF1

AF2

AF3

—

GPIO[35]

CS0_1

MA[0]

—

CAN1RX

CAN4RX(11)

EIRQ[6]

SIUL

DSPI_1

ADC

—

FlexCAN_1

FlexCAN_4

SIUL

I/O

—

S Tristate 49 77 116 B11

PC[4] PCR[36]

AF0

AF1

AF2

AF3

—

GPIO[36]

—

SIN_1

CAN3RX(11)

SIUL

—

DSPI_1

FlexCAN_3

I/O

—

M Tristate 62 92 131 B7

PC[5] PCR[37]

AF0

AF1

AF2

AF3

—

GPIO[37]

SOUT_1

CAN3TX(11)

—

EIRQ[7]

SIUL

DSPI1

FlexCAN_3

—

SIUL

I/O

—

M Tristate 61 91 130 A7

PC[6] PCR[38]

AF0

AF1

AF2

AF3

GPIO[38]

LIN1TX

—

SIUL

LINFlex_1

—

I/O

—

STristate 16 25 36 R2

PC[7] PCR[39]

AF0

AF1

AF2

AF3

—

GPIO[39]

—

LIN1RX

WKUP[12](4)

SIUL

—

LINFlex_1

WKPU

I/O

—

STristate 17 26 37 P3

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

Package pinouts and signal descriptions SPC560Bx, SPC560Cx

24/113 Doc ID 14619 Rev 7

PC[8] PCR[40]

AF0

AF1

AF2

AF3

GPIO[40]

LIN2TX

—

SIUL

LINFlex_2

—

I/O

—

S Tristate 63 99 143 A1

PC[9] PCR[41]

AF0

AF1

AF2

AF3

—

GPIO[41]

—

LIN2RX

WKUP[13](4)

SIUL

—

LINFlex_2

WKPU

I/O

—

STristate222B1

PC[10] PCR[42]

AF0

AF1

AF2

AF3

GPIO[42]

CAN1TX

CAN4TX(11)

MA[1]

SIUL

FlexCAN_1

FlexCAN_4

ADC

I/O

MTristate 13 22 28 M3

PC[11] PCR[43]

AF0

AF1

AF2

AF3

—

GPIO[43]

—

CAN1RX

CAN4RX(11)

WKUP[5](4)

SIUL

—

FlexCAN_1

FlexCAN_4

WKPU

I/O

—

S Tristate — 21 27 M4

PC[12] PCR[44]

AF0

AF1

AF2

AF3

—

GPIO[44]

E0UC[12]

—

SIN_2

SIUL

eMIOS_0

—

DSPI_2

I/O

—

M Tristate — 97 141 B4

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

SPC560Bx, SPC560Cx Package pinouts and signal descriptions

Doc ID 14619 Rev 7 25/113

PC[13] PCR[45]

AF0

AF1

AF2

AF3

GPIO[45]

E0UC[13]

SOUT_2

—

SIUL

eMIOS_0

DSPI_2

—

I/O

—

S Tristate — 98 142 A2

PC[14] PCR[46]

AF0

AF1

AF2

AF3

—

GPIO[46]

E0UC[14]

SCK_2

—

EIRQ[8]

SIUL

eMIOS_0

DSPI_2

—

SIUL

I/O

—

STristate — 3 3 C1

PC[15] PCR[47]

AF0

AF1

AF2

AF3

GPIO[47]

E0UC[15]

CS0_2

—

SIUL

eMIOS_0

DSPI_2

—

I/O

—

MTristate — 4 4 D3

PD[0] PCR[48]

AF0

AF1

AF2

AF3

—

GPIO[48]

—

ANP[4]

SIUL

—

ADC

—

I Tristate — 41 63 P12

PD[1] PCR[49]

AF0

AF1

AF2

AF3

—

GPIO[49]

—

ANP[5]

SIUL

—

ADC

—

I Tristate — 42 64 T12

PD[2] PCR[50]

AF0

AF1

AF2

AF3

—

GPIO[50]

—

ANP[6]

SIUL

—

ADC

—

I Tristate — 43 65 R12

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

Package pinouts and signal descriptions SPC560Bx, SPC560Cx

26/113 Doc ID 14619 Rev 7

PD[3] PCR[51]

AF0

AF1

AF2

AF3

—

GPIO[51]

—

ANP[7]

SIUL

—

ADC

—

I Tristate — 44 66 P13

PD[4] PCR[52]

AF0

AF1

AF2

AF3

—

GPIO[52]

—

ANP[8]

SIUL

—

ADC

—

I Tristate — 45 67 R13

PD[5] PCR[53]

AF0

AF1

AF2

AF3

—

GPIO[53]

—

ANP[9]

SIUL

—

ADC

—

I Tristate — 46 68 T13

PD[6] PCR[54]

AF0

AF1

AF2

AF3

—

GPIO[54]

—

ANP[10]

SIUL

—

ADC

—

I Tristate — 47 69 T14

PD[7] PCR[55]

AF0

AF1

AF2

AF3

—

GPIO[55]

—

ANP[11]

SIUL

—

ADC

—

I Tristate — 48 70 R14

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

SPC560Bx, SPC560Cx Package pinouts and signal descriptions

Doc ID 14619 Rev 7 27/113

PD[8] PCR[56]

AF0

AF1

AF2

AF3

—

GPIO[56]

—

ANP[12]

SIUL

—

ADC

—

I Tristate — 49 71 T15

PD[9] PCR[57]

AF0

AF1

AF2

AF3

—

GPIO[57]

—

ANP[13]

SIUL

—

ADC

—

I Tristate — 56 78 N15

PD[10] PCR[58]

AF0

AF1

AF2

AF3

—

GPIO[58]

—

ANP[14]

SIUL

—

ADC

—

I Tristate — 57 79 N14

PD[11] PCR[59]

AF0

AF1

AF2

AF3

—

GPIO[59]

—

ANP[15]

SIUL

—

ADC

—

I Tristate — 58 80 N16

PD[12](8) PCR[60]

AF0

AF1

AF2

AF3

—

GPIO[60]

CS5_0

E0UC[24]

—

ANS[4]

SIUL

DSPI_0

eMIOS_0

—

ADC

I/O

—

J Tristate — 60 82 M15

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

Package pinouts and signal descriptions SPC560Bx, SPC560Cx

28/113 Doc ID 14619 Rev 7

PD[13] PCR[61]

AF0

AF1

AF2

AF3

—

GPIO[61]

CS0_1

E0UC[25]

—

ANS[5]

SIUL

DSPI_1

eMIOS_0

—

ADC

I/O

—

J Tristate — 62 84 M14

PD[14] PCR[62]

AF0

AF1

AF2

AF3

—

GPIO[62]

CS1_1

E0UC[26]

—

ANS[6]

SIUL

DSPI_1

eMIOS_0

—

ADC

I/O

—

J Tristate — 64 86 L15

PD[15] PCR[63]

AF0

AF1

AF2

AF3

—

GPIO[63]

CS2_1

E0UC[27]

—

ANS[7]

SIUL

DSPI_1

eMIOS_0

—

ADC

I/O

—

J Tristate — 66 88 L14

PE[0] PCR[64]

AF0

AF1

AF2

AF3

—

GPIO[64]

E0UC[16]

—

CAN5RX(11)

WKUP[6](4)

SIUL

eMIOS_0

—

FlexCAN_5

WKPU

I/O

—

STristate — 6 10 F1

PE[1] PCR[65]

AF0

AF1

AF2

AF3

GPIO[65]

E0UC[17]

CAN5TX(11)

—

SIUL

eMIOS_0

FlexCAN_5

—

I/O

—

MTristate — 8 12 F4

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

SPC560Bx, SPC560Cx Package pinouts and signal descriptions

Doc ID 14619 Rev 7 29/113

PE[2] PCR[66]

AF0

AF1

AF2

AF3

—

GPIO[66]

E0UC[18]

—

SIN_1

SIUL

eMIOS0

—

DSPI_1

I/O

—

M Tristate — 89 128 D7

PE[3] PCR[67]

AF0

AF1

AF2

AF3

GPIO[67]

E0UC[19]

SOUT_1

—

SIUL

eMIOS0

DSPI_1

—

I/O

—

M Tristate — 90 129 C7

PE[4] PCR[68]

AF0

AF1

AF2

AF3

—

GPIO[68]

E0UC[20]

SCK_1

—

EIRQ[9]

SIUL

eMIOS0

DSPI_1

—

SIUL

I/O

—

M Tristate — 93 132 D6

PE[5] PCR[69]

AF0

AF1

AF2

AF3

GPIO[69]

E0UC[21]

CS0_1

MA[2]

SIUL

eMIOS_0

DSPI_1

ADC

I/O

M Tristate — 94 133 C6

PE[6] PCR[70]

AF0

AF1

AF2

AF3

GPIO[70]

E0UC[22]

CS3_0

MA[1]

SIUL

eMIOS_0

DSPI_0

ADC

I/O

M Tristate — 95 139 B5

PE[7] PCR[71]

AF0

AF1

AF2

AF3

GPIO[71]

E0UC[23]

CS2_0

MA[0]

SIUL

eMIOS_0

DSPI_0

ADC

I/O

M Tristate — 96 140 C4

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

Package pinouts and signal descriptions SPC560Bx, SPC560Cx

30/113 Doc ID 14619 Rev 7

PE[8] PCR[72]

AF0

AF1

AF2

AF3

GPIO[72]

CAN2TX(12)

E0UC[22]

CAN3TX(11)

SIUL

FlexCAN_2

I/O

FlexCAN_3

I/O

eMIOS0

MTristate — 9 13 G2

PE[9] PCR[73]

AF0

AF1

AF2

AF3

—

GPIO[73]

—

E0UC[23]

—

WKUP[7](4)

CAN2RX(12)

CAN3RX(11)

SIUL

—

eMIOS_0

—

WKPU

FlexCAN_2

FlexCAN_3

I/O

—

I/O

—

S Tristate — 10 14 G1

PE[10] PCR[74]

AF0

AF1

AF2

AF3

—

GPIO[74]

LIN3TX

CS3_1

—

EIRQ[10]

SIUL

LINFlex_3

DSPI_1

—

SIUL

I/O

—

S Tristate — 11 15 G3

PE[11] PCR[75]

AF0

AF1

AF2

AF3

—

GPIO[75]

—

CS4_1

—

LIN3RX

WKUP[14](4)

SIUL

—

DSPI_1

—

LINFlex_3

WKPU

I/O

—

S Tristate — 13 17 H2

PE[12] PCR[76]

AF0

AF1

AF2

AF3

—

GPIO[76]

—

E1UC[19](13)

—

SIN_2

EIRQ[11]

SIUL

—

eMIOS_1

—

DSPI_2

SIUL

I/O

—

I/O

—

S Tristate — 76 109 C14

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

SPC560Bx, SPC560Cx Package pinouts and signal descriptions

Doc ID 14619 Rev 7 31/113

PE[13] PCR[77]

AF0

AF1

AF2

AF3

GPIO[77]

SOUT2

E1UC[20]

—

SIUL

DSPI_2

eMIOS_1

—

I/O

—

S Tristate — — 103 D15

PE[14] PCR[78]

AF0

AF1

AF2

AF3

—

GPIO[78]

SCK_2

E1UC[21]

—

EIRQ[12]

SIUL

DSPI_2

eMIOS_1

—

SIUL

I/O

—

S Tristate — — 112 C13

PE[15] PCR[79]

AF0

AF1

AF2

AF3

GPIO[79]

CS0_2

E1UC[22]

—

SIUL

DSPI_2

eMIOS_1

—

I/O

—

M Tristate — — 113 A13

PF[0] PCR[80]

AF0

AF1

AF2

AF3

—

GPIO[80]

E0UC[10]

CS3_1

—

ANS[8]

SIUL

eMIOS_0

DSPI_1

—

ADC

I/O

—

JTristate — — 55 N10

PF[1] PCR[81]

AF0

AF1

AF2

AF3

—

GPIO[81]

E0UC[11]

CS4_1

—

ANS[9]

SIUL

eMIOS_0

DSPI_1

—

I/O

—

JTristate — — 56 P10

PF[2] PCR[82]

AF0

AF1

AF2

AF3

—

GPIO[82]

E0UC[12]

CS0_2

—

ANS[10]

SIUL

eMIOS_0

DSPI_2

—

ADC

I/O

—

J Tristate — — 57 T10

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

Package pinouts and signal descriptions SPC560Bx, SPC560Cx

32/113 Doc ID 14619 Rev 7

PF[3] PCR[83]

AF0

AF1

AF2

AF3

—

GPIO[83]

E0UC[13]

CS1_2

—

ANS[11]

SIUL

eMIOS_0

DSPI_2

—

ADC

I/O

—

JTristate — — 58 R10

PF[4] PCR[84]

AF0

AF1

AF2

AF3

—

GPIO[84]

E0UC[14]

CS2_2

—

ANS[12]

SIUL

eMIOS_0

DSPI_2

—

ADC

I/O

—

JTristate — — 59 N11

PF[5] PCR[85]

AF0

AF1

AF2

AF3

—

GPIO[85]

E0UC[22]

CS3_2

—

ANS[13]

SIUL

eMIOS_0

DSPI_2

—

ADC

I/O

—

JTristate — — 60 P11

PF[6] PCR[86]

AF0

AF1

AF2

AF3

—

GPIO[86]

E0UC[23]

—

ANS[14]

SIUL

eMIOS_0

—

ADC

I/O

—

J Tristate — — 61 T11

PF[7] PCR[87]

AF0

AF1

AF2

AF3

—

GPIO[87]

—

ANS[15]

SIUL

—

ADC

I/O

—

JTristate — — 62 R11

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

SPC560Bx, SPC560Cx Package pinouts and signal descriptions

Doc ID 14619 Rev 7 33/113

PF[8] PCR[88]

AF0

AF1

AF2

AF3

GPIO[88]

CAN3TX(14)

CS4_0

CAN2TX(15)

SIUL

FlexCAN_3

DSPI_0

FlexCAN_2

I/O

MTristate — — 34 P1

PF[9] PCR[89]

AF0

AF1

AF2

AF3

—

GPIO[89]

—

CS5_0

—

CAN2RX(15)

CAN3RX(14)

SIUL

—

DSPI_0

—

FlexCAN_2

FlexCAN_3

I/O

—

STristate — — 33 N2

PF[10] PCR[90]

AF0

AF1

AF2

AF3

GPIO[90]

—

SIUL

—

I/O

—

MTristate — — 38 R3

PF[11] PCR[91]

AF0

AF1

AF2

AF3

—

GPIO[91]

—

WKUP[15](4)

SIUL

—

WKPU

I/O

—

STristate — — 39 R4

PF[12] PCR[92]

AF0

AF1

AF2

AF3

GPIO[92]

E1UC[25]

—

SIUL

eMIOS_1

—

I/O

—

MTristate — — 35 R1

PF[13] PCR[93]

AF0

AF1

AF2

AF3

—

GPIO[93]

E1UC[26]

—

WKUP[16](4)

SIUL

eMIOS_1

—

WKPU

I/O

—

STristate — — 41 T6

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

Package pinouts and signal descriptions SPC560Bx, SPC560Cx

34/113 Doc ID 14619 Rev 7

PF[14] PCR[94]

AF0

AF1

AF2

AF3

GPIO[94]

CAN4TX(11)

E1UC[27]

CAN1TX

SIUL

FlexCAN_4

eMIOS_1

FlexCAN_4

I/O

M Tristate — — 102 D14

PF[15] PCR[95]

AF0

AF1

AF2

AF3

—

GPIO[95]

—

CAN1RX

CAN4RX(11)

EIRQ[13]

SIUL

—

FlexCAN_1

FlexCAN_4

SIUL

I/O

—

S Tristate — — 101 E15

PG[0] PCR[96]

AF0

AF1

AF2

AF3

GPIO[96]

CAN5TX(11)

E1UC[23]

—

SIUL

FlexCAN_5

eMIOS_1

—

I/O

—

MTristate — — 98 E14

PG[1] PCR[97]

AF0

AF1

AF2

AF3

—

GPIO[97]

—

E1UC[24]

—

CAN5RX(11)

EIRQ[14]

SIUL

—

eMIOS_1

—

FlexCAN_5

SIUL

I/O

—

I/O

—

STristate — — 97 E13

PG[2] PCR[98]

AF0

AF1

AF2

AF3

GPIO[98]

E1UC[11]

—

SIUL

eMIOS_1

—

I/O

—

MTristate — — 8 E4

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

SPC560Bx, SPC560Cx Package pinouts and signal descriptions

Doc ID 14619 Rev 7 35/113

PG[3] PCR[99]

AF0

AF1

AF2

AF3

—

GPIO[99]

E1UC[12]

—

WKUP[17](4)

SIUL

eMIOS_1

—

WKPU

I/O

—

STristate — — 7 E3

PG[4] PCR[100]

AF0

AF1

AF2

AF3

GPIO[100]

E1UC[13]

—

SIUL

eMIOS_1

—

I/O

—

MTristate — — 6 E1

PG[5] PCR[101]

AF0

AF1

AF2

AF3

—

GPIO[101]

E1UC[14]

—

WKUP[18](4)

SIUL

eMIOS_1

—

WKPU

I/O

—

STristate — — 5 E2

PG[6] PCR[102]

AF0

AF1

AF2

AF3

GPIO[102]

E1UC[15]

—

SIUL

eMIOS_1

—

I/O

—

MTristate — — 30 M2

PG[7] PCR[103]

AF0

AF1

AF2

AF3

GPIO[103]

E1UC[16]

—

SIUL

eMIOS_1

—

I/O

—

MTristate — — 29 M1

PG[8] PCR[104]

AF0

AF1

AF2

AF3

—

GPIO[104]

E1UC[17]

—

CS0_2

EIRQ[15]

SIUL

eMIOS_1

—

DSPI_2

SIUL

I/O

—

I/O

STristate — — 26 L2

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

Package pinouts and signal descriptions SPC560Bx, SPC560Cx

36/113 Doc ID 14619 Rev 7

PG[9] PCR[105]

AF0

AF1

AF2

AF3

GPIO[105]

E1UC[18]

—

SCK_2

SIUL

eMIOS1

—

DSPI_2

I/O

—

I/O

STristate — — 25 L1

PG[10] PCR[106]

AF0

AF1

AF2

AF3

GPIO[106]

E0UC[24]

—

SIUL

eMIOS_0

—

I/O

—

S Tristate — — 114 D13

PG[11] PCR[107]

AF0

AF1

AF2

AF3

GPIO[107]

E0UC[25]

—

SIUL

eMIOS_0

—

I/O

—

M Tristate — — 115 B12

PG[12] PCR[108]

AF0

AF1

AF2

AF3

GPIO[108]

E0UC[26]

—

SIUL

eMIOS_0

—

I/O

—

MTristate — — 92 K14

PG[13] PCR[109]

AF0

AF1

AF2

AF3

GPIO[109]

E0UC[27]

—

SIUL

eMIOS_0

—

I/O

—

MTristate — — 91 K16

PG[14] PCR[110]

AF0

AF1

AF2

AF3

GPIO[110]

E1UC[0]

—

SIUL

eMIOS_1

—

I/O

—

S Tristate — — 110 B14

PG[15] PCR[111]

AF0

AF1

AF2

AF3

GPIO[111]

E1UC[1]

—

SIUL

eMIOS_1

—

I/O

—

M Tristate — — 111 B13

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

SPC560Bx, SPC560Cx Package pinouts and signal descriptions

Doc ID 14619 Rev 7 37/113

PH[0] PCR[112]

AF0

AF1

AF2

AF3

—

GPIO[112]

E1UC[2]

—

SIN1

SIUL

eMIOS_1

—

DSPI_1

I/O

—

M Tristate — — 93 F13

PH[1] PCR[113]

AF0

AF1

AF2

AF3

GPIO[113]

E1UC[3]

SOUT1

—

SIUL

eMIOS_1

DSPI_1

—

I/O

—

M Tristate — — 94 F14

PH[2] PCR[114]

AF0

AF1

AF2

AF3

GPIO[114]

E1UC[4]

SCK_1

—

SIUL

eMIOS_1

DSPI_1

—

I/O

—

M Tristate — — 95 F16

PH[3] PCR[115]

AF0

AF1

AF2

AF3

GPIO[115]

E1UC[5]

CS0_1

—

SIUL

eMIOS_1

DSPI_1

—

I/O

—

M Tristate — — 96 F15

PH[4] PCR[116]

AF0

AF1

AF2

AF3

GPIO[116]

E1UC[6]

—

SIUL

eMIOS_1

—

I/O

—

M Tristate — — 134 A6

PH[5] PCR[117]

AF0

AF1

AF2

AF3

GPIO[117]

E1UC[7]

—

SIUL

eMIOS_1

—

I/O

—

S Tristate — — 135 B6

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

Package pinouts and signal descriptions SPC560Bx, SPC560Cx

38/113 Doc ID 14619 Rev 7

PH[6] PCR[118]

AF0

AF1

AF2

AF3

GPIO[118]

E1UC[8]

—

MA[2]

SIUL

eMIOS_1

—

ADC

I/O

—

M Tristate — — 136 D5

PH[7] PCR[119]

AF0

AF1

AF2

AF3

GPIO[119]

E1UC[9]

CS3_2

MA[1]

SIUL

eMIOS_1

DSPI_2

ADC

I/O

M Tristate — — 137 C5

PH[8] PCR[120]

AF0

AF1

AF2

AF3

GPIO[120]

E1UC[10]

CS2_2

MA[0]

SIUL

eMIOS_1

DSPI_2

ADC

I/O

M Tristate — — 138 A5

PH[9](9) PCR[121]

AF0

AF1

AF2

AF3

GPIO[121]

—

TCK

—

SIUL

—

JTAGC

—

I/O

—

Input,

weak

pull-up

— 88 127 B8

PH[10](9) PCR[122]

AF0

AF1

AF2

AF3

GPIO[122]

—

TMS

—

SIUL

—

JTAGC

—

I/O

—

Input,

weak

pull-up

— 81 120 B9

1. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00 -> AF0; PCR.PA = 01->AF1; PCR.PA=10->AF2;

PCR.PA = 11 -> AF3. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values

selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “—”.

2. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx bitfields inside

the SIUL module.

3. LBGA208 available only as development package for Nexus2+

4. All WKUP pins also support external interrupt capability. See wakeup unit chapter for further details.

5. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.

6. “Not applicable” because these functions are available only while the device is booting. Refer to BAM chapter of the reference manual for details.

Table 4. Functional port pin descriptions (continued)

Port

PCR

Alternate

function(1) Function Peripheral I/O

direction(2)

Pad

type

RESET

config.

Pin No.

LQFP

100

LQFP

144

LBGA

208(3)

SPC560Bx, SPC560Cx Package pinouts and signal descriptions

Doc ID 14619 Rev 7 39/113

7. Value of PCR.IBE bit must be 0

8. This pad is used on SPC560B64L3 and SPC560B64L5 to provide supply for the second ADC. Therefore it is recommended not using it to keep the compatibility with the

family devices.

9. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.

PC[0:1] are available as JTAG pins (TDI and TDO respectively).

PH[9:10] are available as JTAG pins (TCK and TMS respectively).

It is up to the user to configure these pins as GPIO when needed, in this case SPC560Bx and SPC560Cx get incompliance with IEEE 1149.1-2001.

10. The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in STANDBY mode. However, no pull-resistor is active on the

TDO pad while in STANDBY mode. At this time the pad is configured as an input. When no debugger is connected the TDO pad is floating causing additional current

consumption. To avoid the extra consumption TDO must be connected. An external pull-up resistor in the range of 47–100 kOhms should be added between the TDO pin

and VDD. Only in case the TDO pin is used as application pin and a pull-up cannot be used then a pull-down resistor with the same value should be used between TDO pin

and GND instead.

11. Available only on SPC560Cx versions and SPC560B50B2 devices

12. Not available on SPC560B40L3 and SPC560B40L5 devices

13. Not available in LQFP100 package

14. Available only on SPC560B50B2 devices

15. Not available on SPC560B44L3 devices

Electrical characteristics SPC560Bx, SPC560Cx

40/113 Doc ID 14619 Rev 7

4 Electrical characteristics

4.1 Introduction

This section contains electrical characteristics of the device as well as temperature and

power considerations.

This product contains devices to protect the inputs against damage due to high static

voltages. However, it is advisable to take precautions to avoid application of any voltage

higher than the specified maximum rated voltages.

To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD

or VSS). This could be done by the internal pull-up and pull-down, which is provided by the

product for most general purpose pins.

The parameters listed in the following tables represent the characteristics of the device and

its demands on the system.

In the tables where the device logic provides signals with their respective timing

characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol

column.

In the tables where the external system must provide signals with their respective timing

characteristics to the device, the symbol “SR” for System Requirement is included in the

Symbol column.

Caution: All LQFP64 information is indicative and must be confirmed during silicon validation.

4.2 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To

give the customer a better understanding, the classifications listed in Ta bl e 5 are used and

the parameters are tagged accordingly in the tables where appropriate.

Note: The classification is shown in the column labeled “C” in the parameter tables where

appropriate.

Table 5. Parameter classifications

Classification tag Tag description

P Those parameters are guaranteed during production testing on each individual device.

CThose parameters are achieved by the design characterization by measuring a statistically

relevant sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical

devices under typical conditions unless otherwise noted. All values shown in the typical

column are within this category.

D Those parameters are derived mainly from simulations.

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 41/113

4.3 NVUSRO register

Portions of the device configuration, such as high voltage supply, oscillator margin, and

watchdog enable/disable after reset are controlled via bit values in the Non-Volatile User

Options Register (NVUSRO) register.

4.3.1 NVUSRO[PAD3V5V] field description

Ta bl e 6 shows how NVUSRO[PAD3V5V] controls the device configuration.

The DC electrical characteristics are dependent on the PAD3V5V bit value.

4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description

Ta bl e 7 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.

The fast external crystal oscillator consumption is dependent on the

OSCILLATOR_MARGIN bit value.

For a detailed description of the NVUSRO register, please refer to the SPC560Bx and

SPC560Cx Reference Manual.

4.4 Absolute maximum ratings

Table 6. PAD3V5V field description(1)

1. See the device reference manual for more information on the NVUSRO register.

Value(2)

2. '1' is delivery value. It is part of shadow Flash, thus programmable by customer.

Description

0 High voltage supply is 5.0 V

1 High voltage supply is 3.3 V

Table 7. OSCILLATOR_MARGIN field description(1)

1. See the device reference manual for more information on the NVUSRO register.

Value(2)

2. '1' is delivery value. It is part of shadow Flash, thus programmable by customer.

Description

0 Low consumption configuration (4 MHz/8 MHz)

1 High margin configuration (4 MHz/16 MHz)

Table 8. Absolute maximum ratings

Symbol Parameter Conditions

Value

Unit

Min Max

VSS SR Digital ground on VSS_HV pins — 0 0 V

VDD SR Voltage on VDD_HV pins with respect to ground

(VSS)—0.3 6.0 V

Electrical characteristics SPC560Bx, SPC560Cx

42/113 Doc ID 14619 Rev 7

Note: Stresses exceeding the recommended absolute maximum ratings may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification are not implied. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability. During overload conditions (VIN >V

DD or VIN <V

SS),

the voltage on pins with respect to ground (VSS) must not exceed the recommended values.

4.5 Recommended operating conditions

VSS_LV SR Voltage on VSS_LV (low voltage digital supply)

pins with respect to ground (VSS)—V

SS0.1 VSS+0.1 V

VDD_BV SR Voltage on VDD_BV pin (regulator supply) with

respect to ground (VSS)

—0.3 6.0 V

Relative to VDD 0.3 VDD+0.3

VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin

with respect to ground (VSS)—V

SS0.1 VSS+0.1 V

VDD_ADC SR Voltage on VDD_HV_ADC pin (ADC reference)

with respect to ground (VSS)

—0.3 6.0 V

Relative to VDD VDD 0.3 VDD+0.3

VIN SR Voltage on any GPIO pin with respect to ground

(VSS)

—0.3 6.0 V

Relative to VDD —V

DD+0.3

IINJPAD SR Injected input current on any pin during overload

condition —10 10

IINJSUM SR Absolute sum of all injected input currents during

overload condition —50 50

IAVGSEG SR Sum of all the static I/O current within a supply

segment

VDD = 5.0 V ± 10%,

PAD3V5V = 0 —70

VDD = 3.3 V ± 10%,

PAD3V5V = 1 —64

ICORELV SR Low voltage static current sink through VDD_BV — — 150 mA

TSTORAGE SR Storage temperature — 55 150 °C

Table 9. Recommended operating conditions (3.3 V)

Symbol Parameter Conditions

Value

Unit

Min Max

VSS SR Digital ground on VSS_HV pins — 0 0 V

VDD(1) SR Voltage on VDD_HV pins with respect to ground

(VSS)—3.03.6V

VSS_LV(2) SR Voltage on VSS_LV (low voltage digital supply)

pins with respect to ground (VSS)—V

SS0.1 VSS+0.1 V

Table 8. Absolute maximum ratings (continued)

Symbol Parameter Conditions

Value

Unit

Min Max

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 43/113

VDD_BV(3) SR Voltage on VDD_BV pin (regulator supply) with

respect to ground (VSS)

—3.03.6

Relative to VDD VDD0.1 VDD+0.1

VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin

with respect to ground (VSS)—V

SS0.1 VSS+0.1 V

VDD_ADC(4) SR Voltage on VDD_HV_ADC pin (ADC reference)

with respect to ground (VSS)

—3.0

(5) 3.6 V

Relative to VDD VDD0.1 VDD+0.1

VIN SR Voltage on any GPIO pin with respect to ground

(VSS)

—V

SS0.1 — V

Relative to VDD —V

DD+0.1

IINJPAD SR Injected input current on any pin during overload

condition —55

IINJSUM SR Absolute sum of all injected input currents during

overload condition —50 50

TVDD SR VDD slope to ensure correct power up(6) — — 0.25 V/µs

1. 100 nF capacitance needs to be provided between each VDD/VSS pair

2. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.

3. 400 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed

depending on external regulator characteristics).

4. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.

5. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical

characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is

reset.

6. Guaranteed by device validation

Table 10. Recommended operating conditions (5.0 V)

Symbol Parameter Conditions

Value

Unit

Min Max

VSS SR Digital ground on VSS_HV pins — 0 0 V

VDD(1) SR Voltage on VDD_HV pins with respect to ground

(VSS)

—4.55.5

Voltage drop(2) 3.0 5.5

VSS_LV(3) SR Voltage on VSS_LV (low voltage digital supply) pins

with respect to ground (VSS)—V

SS0.1 VSS+0.1 V

VDD_BV(4) SR Voltage on VDD_BV pin (regulator supply) with

respect to ground (VSS)

—4.55.5

VVoltage drop(2) 3.0 5.5

Relative to VDD VDD0.1 VDD+0.1

VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin with

respect to ground (VSS

—V

SS0.1 VSS+0.1 V

Table 9. Recommended operating conditions (3.3 V) (continued)

Symbol Parameter Conditions

Value

Unit

Min Max

Electrical characteristics SPC560Bx, SPC560Cx

44/113 Doc ID 14619 Rev 7

Note: RAM data retention is guaranteed with VDD_LV not below 1.08 V.

4.6 Thermal characteristics

4.6.1 Package thermal characteristics

VDD_ADC(5) SR Voltage on VDD_HV_ADC pin (ADC reference) with

respect to ground (VSS)

—4.55.5

VVoltage drop(2) 3.0 5.5

Relative to VDD VDD0.1 VDD+0.1

VIN SR Voltage on any GPIO pin with respect to ground

(VSS)

—V

SS0.1 — V

Relative to VDD —V

DD+0.1

IINJPAD SR Injected input current on any pin during overload

condition —55

IINJSUM SR Absolute sum of all injected input currents during

overload condition —50 50

TVDD SR VDD slope to ensure correct power up(6) — — 0.25 V/µs

1. 100 nF capacitance needs to be provided between each VDD/VSS pair.

2. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain analog

electrical characteristics will not be guaranteed to stay within the stated limits.

3. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.

4. 100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed

depending on external regulator characteristics).

5. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.

6. Guaranteed by device validation

Table 11. LQFP thermal characteristics(1)

Symbol C Parameter Conditions(2) Pin count Value Unit

RJA CC D Thermal resistance, junction-to-

ambient natural convection(3)

Single-layer board - 1s

64 TBD

°C/W

100 64

144 64

Four-layer board - 2s2p

64 TBD

100 51

144 49

Table 10. Recommended operating conditions (5.0 V) (continued)

Symbol Parameter Conditions

Value

Unit

Min Max

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 45/113

4.6.2 Power considerations

The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using

Equation 1:

Equation 1 TJ = TA + (PD x RJA)

RJB CC D Thermal resistance, junction-to-

board(4)

Single-layer board - 1s

64 TBD

°C/W

100 36

144 37

Four-layer board - 2s2p

64 TBD

100 34

144 35

RJC CC D Thermal resistance, junction-to-

case(5)

Single-layer board - 1s

64 TBD

°C/W

100 22

144 22

Four-layer board - 2s2p

64 TBD

100 22

144 22

JB CC D

Junction-to-board thermal

characterization parameter, natural

convection

Single-layer board - 1s

64 TBD

°C/W

100 33

144 34

Four-layer board - 2s2p

64 TBD

100 34

144 35

JC CC D

Junction-to-case thermal

characterization parameter, natural

convection

Single-layer board - 1s

64 TBD

°C/W

100 9

144 10

Four-layer board - 2s2p

64 TBD

100 9

144 10

1. Thermal characteristics are based on simulation.

2. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C

3. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets

JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA.

4. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for

the specified package. When Greek letters are not available, the symbols are typed as RthJB.

5. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is

used for the case temperature. Reported value includes the thermal resistance of the interface layer. When Greek letters

are not available, the symbols are typed as RthJC.

Table 11. LQFP thermal characteristics(1) (continued)

Symbol C Parameter Conditions(2) Pin count Value Unit

Electrical characteristics SPC560Bx, SPC560Cx

46/113 Doc ID 14619 Rev 7

Where:

TA is the ambient temperature in °C.

RJA is the package junction-to-ambient thermal resistance, in °C/W.

PD is the sum of PINT and PI/O (PD = PINT + PI/O).

PINT is the product of IDD and VDD, expressed in watts. This is the chip internal

power.

PI/O represents the power dissipation on input and output pins; user determined.

Most of the time for the applications, PI/O< PINT and may be neglected. On the other hand,

PI/O may be significant, if the device is configured to continuously drive external modules

and/or memories.

An approximate relationship between PD and TJ (if PI/O is neglected) is given by:

Equation 2 PD = K / (TJ + 273 °C)

Therefore, solving equations 1 and 2:

Equation 3 K = PD x (TA + 273 °C) + RJA x PD2

Where:

K is a constant for the particular part, which may be determined from Equation 3

by measuring PD (at equilibrium) for a known TA. Using this value of K, the values

of PD and TJ may be obtained by solving equations 1 and 2 iteratively for any value

of TA.

4.7 I/O pad electrical characteristics

4.7.1 I/O pad types

The device provides four main I/O pad types depending on the associated alternate

functions:

●Slow pads—These pads are the most common pads, providing a good compromise

between transition time and low electromagnetic emission.

●Medium pads—These pads provide transition fast enough for the serial communication

channels with controlled current to reduce electromagnetic emission.

●Fast pads—These pads provide maximum speed. There are used for improved Nexus

debugging capability.

●Input only pads—These pads are associated to ADC channels and the external 32 kHz

crystal oscillator (SXOSC) providing low input leakage.

Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at

the cost of reducing AC performance.

4.7.2 I/O input DC characteristics

Ta bl e 1 2 provides input DC electrical characteristics as described in Figure 6.

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 47/113

Figure 6. I/O input DC electrical characteristics definition

Table 12. I/O input DC electrical characteristics

Symbol C Parameter Conditions(1)

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value

Unit

Min Typ Max

VIH SR P Input high level CMOS (Schmitt

Trigger) —0.65V

DD —V

DD+0.4

VVIL SR P Input low level CMOS (Schmitt

Trigger) —0.4 — 0.35VDD

VHYS CC C Input hysteresis CMOS (Schmitt

Trigger) —0.1V

DD ——

ILKG CC

Digital input leakage No injection on

adjacent pin

TA=40 °C — 2 —

A= 25 °C — 2 —

A=105 °C — 12 500

A= 125 °C — 70 1000

WFI(2)

2. In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage.

SR P Wakeup input filtered pulse — — — 40 ns

WNFI(

2) SR P Wakeup input not filtered pulse — 1000 — — ns

VIL

VIN

VIH

PDIx = ‘1’

VDD

VHYS

(GPDI register of SIUL)

PDIx = ‘0’

Electrical characteristics SPC560Bx, SPC560Cx

48/113 Doc ID 14619 Rev 7

4.7.3 I/O output DC characteristics

The following tables provide DC characteristics for bidirectional pads:

●Ta b le 1 3 provides weak pull figures. Both pull-up and pull-down resistances are

supported.

●Ta b le 1 4 provides output driver characteristics for I/O pads when in SLOW

configuration.

●Ta b le 1 5 provides output driver characteristics for I/O pads when in MEDIUM

configuration.

●Ta b le 1 6 provides output driver characteristics for I/O pads when in FAST configuration.

Table 13. I/O pull-up/pull-down DC electrical characteristics

Symbol C Parameter Conditions(1)

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.

Value

Unit

Min Typ Max

|IWPU|CC

Weak pull-up current

absolute value

VIN = VIL, VDD = 5.0 V ± 10% PA D 3 V 5 V = 0 1 0 — 1 5 0

µAC PAD3V5V = 1(2)

2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and

Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

10 — 250

IN = VIL, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150

|IWPD|CC

Weak pull-down current

absolute value

VIN = VIH, VDD = 5.0 V ± 10% PAD 3 V5 V = 0 1 0 — 1 5 0

µAC PAD3V5V = 1 10 — 250

IN = VIH, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150

Table 14. SLOW configuration output buffer electrical characteristics

Symbol C Parameter Conditions(1)

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value

Unit

Min Typ Max

VOH CC

Output high level

SLOW configuration Push Pull

IOH = 2mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0

(recommended)

0.8VDD ——

VC IOH = 2mA,

VDD = 5.0 V ± 10%, PAD3V5V = 1(2) 0.8VDD ——

IOH = 1mA,

VDD = 3.3 V ± 10%, PAD3V5V = 1

(recommended)

VDD0.8 — —

VOL CC

Output low level

SLOW configuration Push Pull

IOL = 2 mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0

(recommended)

— — 0.1VDD

VC IOL = 2 mA,

VDD = 5.0 V ± 10%, PAD3V5V = 1(2) — — 0.1VDD

IOL = 1 mA,

VDD = 3.3 V ± 10%, PAD3V5V = 1

(recommended)

——0.5

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 49/113

2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and

Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 15. MEDIUM configuration output buffer electrical characteristics

Symbol C Parameter Conditions(1)

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value

Unit

Min Typ Max

VOH CC

Output high level

MEDIUM

configuration

Push

Pull

IOH = 3.8 mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD ——

IOH = 2mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0

(recommended)

0.8VDD ——

CIOH = 1mA,

VDD = 5.0 V ± 10%, PAD3V5V = 1(2)

2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and

Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

0.8VDD ——

IOH = 1mA,

VDD = 3.3 V ± 10%, PAD3V5V = 1

(recommended)

VDD0.8 — —

CIOH = 100 µA,

VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD ——

VOL CC

Output low level

MEDIUM

configuration

Push

Pull

IOL = 3.8 mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.2VDD

IOL = 2 mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0

(recommended)

— — 0.1VDD

CIOL = 1 mA,

VDD = 5.0 V ± 10%, PAD3V5V = 1(2) — — 0.1VDD

IOL = 1 mA,

VDD = 3.3 V ± 10%, PAD3V5V = 1

(recommended)

——0.5

CIOH = 100 µA,

VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.1VDD

Electrical characteristics SPC560Bx, SPC560Cx

50/113 Doc ID 14619 Rev 7

4.7.4 Output pin transition times

Table 16. FAST configuration output buffer electrical characteristics

Symbol C Parameter Conditions(1)

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value

Unit

Min Typ Max

VOH CC

Output high level

FAST configuration

Push

Pull

IOH = 14mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0

(recommended)

0.8VDD ——

VC IOH = 7mA,

VDD = 5.0 V ± 10%, PAD3V5V = 1(2)

2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and

Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

0.8VDD ——

IOH = 11mA,

VDD = 3.3 V ± 10%, PAD3V5V = 1

(recommended)

VDD

0.8 ——

VOL CC

Output low level

FAST configuration

Push

Pull

IOL = 14mA,

VDD = 5.0 V ± 10%, PAD3V5V = 0

(recommended)

— — 0.1VDD

VC IOL = 7mA,

VDD = 5.0 V ± 10%, PAD3V5V = 1(2) — — 0.1VDD

IOL = 11mA,

VDD = 3.3 V ± 10%, PAD3V5V = 1

(recommended)

——0.5

Table 17. Output pin transition times

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

Ttr CC

Output transition time

output pin(2)

SLOW configuration

CL = 25 pF

VDD = 5.0 V ± 10%,

PAD3V5V = 0

——50

L = 50 pF — — 100

L = 100 pF — — 125

L = 25 pF

VDD = 3.3 V ± 10%, PAD3V5V = 1

——50

L = 50 pF — — 100

L = 100 pF — — 125

Ttr CC

Output transition time

output pin(2)

MEDIUM configuration

CL = 25 pF

VDD = 5.0 V ± 10%, PAD3V5V = 0

SIUL.PCRx.SRC = 1

——10

L = 50 pF — — 20

L = 100 pF — — 40

L = 25 pF

VDD = 3.3 V ± 10%, PAD3V5V = 1

SIUL.PCRx.SRC = 1

——12

L = 50 pF — — 25

L = 100 pF — — 40

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 51/113

4.7.5 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is

associated to a VDD/VSS supply pair as described in Ta b le 1 8 .

Ta bl e 1 9 provides I/O consumption figures.

In order to ensure device reliability, the average current of the I/O on a single segment

should remain below the IAVGSEG maximum value.

In order to ensure device functionality, the sum of the dynamic and static current of the I/O

on a single segment should remain below the IDYNSEG maximum value.

Ttr CC D

Output transition time

output pin(2)

FAST configuration

CL = 25 pF

VDD = 5.0 V ± 10%, PAD3V5V = 0

—— 4

CL = 50 pF — — 6

CL = 100 pF — — 12

CL = 25 pF

VDD = 3.3 V ± 10%, PAD3V5V = 1

—— 4

CL = 50 pF — — 7

CL = 100 pF — — 12

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

2. CL includes device and package capacitances (CPKG < 5 pF).

Table 17. Output pin transition times (continued)

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

Table 18. I/O supply segment

Package

Supply segment

123456

LBGA208(1) Equivalent to LQFP144 segment pad distribution MCKO MDOn/MSEO

LQFP144 pin20–pin49 pin51–pin99 pin100–pin122 pin 123–pin19 — —

LQFP100 pin16–pin35 pin37–pin69 pin70–pin83 pin 84–pin15 — —

LQFP64(2) pin8–pin26 pin28–pin55 pin56–pin7 — — —

1. LBGA208 available only as development package for Nexus2+

2. All LQFP64 information is indicative and must be confirmed during silicon validation.

Table 19. I/O consumption

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

ISWTSLW(2) CCDDynamic I/O current for

SLOW configuration CL = 25 pF

VDD = 5.0 V ± 10%,

PAD3V5V = 0 ——20

VDD = 3.3 V ± 10%,

PAD3V5V = 1 ——16

Electrical characteristics SPC560Bx, SPC560Cx

52/113 Doc ID 14619 Rev 7

Ta bl e 2 0 provides the weight of concurrent switching I/Os.

In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on

a single segment should remain below the 100%.

ISWTMED(2

)CCDDynamic I/O current for

MEDIUM configuration CL = 25 pF

VDD = 5.0 V ± 10%,

PAD3V5V = 0 ——29

VDD = 3.3 V ± 10%,

PAD3V5V = 1 ——17

ISWTFST(2) CCDDynamic I/O current for

FAST configuration CL = 25 pF

VDD = 5.0 V ± 10%,

PAD3V5V = 0 ——110

VDD = 3.3 V ± 10%,

PAD3V5V = 1 ——50

IRMSSLW CC D

Root medium square I/O

current for SLOW

configuration

CL = 25 pF, 2 MHz

VDD = 5.0 V ± 10%,

PAD3V5V = 0

——2.3

CL = 25 pF, 4 MHz — — 3.2

CL = 100 pF, 2 MHz — — 6.6

CL = 25 pF, 2 MHz VDD = 3.3 V ± 10%,

PAD3V5V = 1

——1.6

CL = 25 pF, 4 MHz — — 2.3

CL = 100 pF, 2 MHz — — 4.7

IRMSMED CC D

Root medium square I/O

current for MEDIUM

configuration

CL = 25 pF, 13 MHz VDD = 5.0 V ± 10%,

PAD3V5V = 0

——6.6

CL = 25 pF, 40 MHz — — 13.4

CL = 100 pF, 13 MHz — — 18.3

CL = 25 pF, 13 MHz

VDD = 3.3 V ± 10%,

PAD3V5V = 1

—— 5

CL = 25 pF, 40 MHz — — 8.5

CL = 100 pF, 13 MHz — — 11

IRMSFST CC D

Root medium square I/O

current for FAST

configuration

CL = 25 pF, 40 MHz

VDD = 5.0 V ± 10%,

PAD3V5V = 0

——22

CL = 25 pF, 64 MHz — — 33

CL = 100 pF, 40 MHz — — 56

CL = 25 pF, 40 MHz VDD = 3.3 V ± 10%,

PAD3V5V = 1

——14

CL = 25 pF, 64 MHz — — 20

CL = 100 pF, 40 MHz — — 35

IAVGSEG SR D

Sum of all the static I/O

current within a supply

segment

VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 70

VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 65

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to125 °C, unless otherwise specified

2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.

Table 19. I/O consumption (continued)

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 53/113

Table 20. I/O weight(1)

PAD

LQFP144/LQFP100 LQFP64(2)

Weight

SRE=0

Weight

SRE=1

Weight

3.3V

SRE=0

Weight

3.3V

SRE=1

Weight

SRE=0

Weight

SRE=1

Weight

3.3V

SRE=0

Weight

3.3V

SRE=1

PB[3] 10% — 12% — 10% — 12% —

PC[9] 10% — 12% — 10% — 12% —

PC[14] 9% — 11% — 9% — 11% —

PC[15] 9% 13% 11% 12% 9% 13% 11% 12%

PG[5] 9% — 11% — 9% — 11% —

PG[4] 9% 12% 10% 11% 9% 12% 10% 11%

PG[3] 9% — 10% — 9% — 10% —

PG[2] 8% 12% 10% 10% 8% 12% 10% 10%

PA[2] 8% — 9% — 8% — 9% —

PE[0] 8% — 9% — 8% — 9% —

PA[1] 7% — 9% — 7% — 9% —

PE[1] 7% 10% 8% 9% 7% 10% 8% 9%

PE[8] 7% 9% 8% 8% 7% 9% 8% 8%

PE[9] 6% — 7% — 6% — 7% —

PE[10] 6% — 7% — 6% — 7% —

PA[0]5%8%6%7%5%8%6%7%

PE[11] 5% — 6% — 5% — 6% —

PG[9] 9% — 10% — 9% — 10% —

PG[8] 9% — 11% — 9% — 11% —

PC[11] 9% — 11% — 9% — 11% —

PC[10] 9% 13% 11% 12% 9% 13% 11% 12%

PG[7] 10% 14% 11% 12% 10% 14% 11% 12%

PG[6] 10% 14% 12% 12% 10% 14% 12% 12%

PB[0] 10% 14% 12% 12% 10% 14% 12% 12%

PB[1] 10% — 12% — 10% — 12% —

PF[9] 10% — 12% — 10% — 12% —

PF[8] 10% 15% 12% 13% 10% 15% 12% 13%

PF[12] 10% 15% 12% 13% 10% 15% 12% 13%

PC[6] 10% — 12% — 10% — 12% —

PC[7] 10% — 12% — 10% — 12% —

PF[10] 10% 14% 12% 12% 10% 14% 12% 12%

PF[11] 10% — 11% — 10% — 11% —

Electrical characteristics SPC560Bx, SPC560Cx

54/113 Doc ID 14619 Rev 7

PA[15] 9% 12% 10% 11% 9% 12% 10% 11%

PF[13] 8% — 10% — 8% — 10% —

PA[14] 8% 11% 9% 10% 8% 11% 9% 10%

PA[4] 8% — 9% — 8% — 9% —

PA[13] 7% 10% 9% 9% 7% 10% 9% 9%

PA[12] 7% — 8% — 7% — 8% —

PB[9] 1% — 1% — 1% — 1% —

PB[8] 1% — 1% — 1% — 1% —

PB[10] 6% — 7% — 6% — 7% —

PF[0] 6% — 7% — 6% — 7% —

PF[1] 7% — 8% — 7% — 8% —

PF[2] 7% — 8% — 7% — 8% —

PF[3] 7% — 9% — 8% — 9% —

PF[4] 8% — 9% — 8% — 9% —

PF[5] 8% — 10% — 8% — 10% —

PF[6] 8% — 10% — 9% — 10% —

PF[7] 9% — 10% — 9% — 11% —

PD[0] 1% — 1% — 1% — 1% —

PD[1] 1% — 1% — 1% — 1% —

PD[2] 1% — 1% — 1% — 1% —

PD[3] 1% — 1% — 1% — 1% —

PD[4] 1% — 1% — 1% — 1% —

PD[5] 1% — 1% — 1% — 1% —

PD[6] 1% — 1% — 1% — 1% —

PD[7] 1% — 1% — 1% — 1% —

PD[8] 1% — 1% — 1% — 1% —

PB[4] 1% — 1% — 1% — 1% —

PB[5] 1% — 1% — 1% — 2% —

PB[6] 1% — 1% — 1% — 2% —

PB[7] 1% — 1% — 1% — 2% —

PD[9] 1% — 1% — 1% — 2% —

PD[10] 1% — 1% — 1% — 2% —

Table 20. I/O weight(1)

PAD

LQFP144/LQFP100 LQFP64(2)

Weight

SRE=0

Weight

SRE=1

Weight

3.3V

SRE=0

Weight

3.3V

SRE=1

Weight

SRE=0

Weight

SRE=1

Weight

3.3V

SRE=0

Weight

3.3V

SRE=1

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 55/113

PD[11] 1% — 1% — 1% — 2% —

PB[11] 11% — 13% — 17% — 21% —

PD[12] 11% — 13% — 18% — 21% —

PB[12] 11% — 13% — 18% — 21% —

PD[13] 10% — 12% — 18% — 21% —

PB[13] 10% — 12% — 18% — 21% —

PD[14] 10% — 12% — 18% — 21% —

PB[14] 10% — 12% — 18% — 21% —

PD[15] 10% — 11% — 18% — 21% —

PB[15] 9% — 11% — 18% — 21% —

PA[3] 9% — 11% — 18% — 21% —

PG[13] 9% 13% 10% 11% 18% 26% 21% 23%

PG[12] 9% 12% 10% 11% 18% 26% 21% 23%

PH[0] 5% 8% 6% 7% 18% 26% 21% 23%

PH[1] 5% 7% 6% 6% 18% 26% 21% 23%

PH[2] 5% 6% 5% 6% 18% 25% 21% 22%

PH[3] 4% 6% 5% 5% 18% 25% 21% 22%

PG[1] 4% — 4% — 18% — 21% —

PG[0] 3% 4% 4% 4% 17% 25% 21% 22%

PF[15] 3% — 4% — 17% — 20% —

PF[14] 4% 5% 5% 5% 16% 23% 20% 21%

PE[13] 4% — 5% — 16% — 19% —

PA[7] 5% — 6% — 16% — 19% —

PA[8] 5% — 6% — 16% — 19% —

PA[9] 5% — 6% — 15% — 18% —

PA[10] 6% — 7% — 15% — 18% —

PA[11] 6% — 8% — 14% — 17% —

PE[12] 7% — 8% — 11% — 14% —

PG[14] 7% — 8% — 10% — 12% —

PG[15] 7% 10% 8% 9% 10% 14% 12% 12%

PE[14] 7% — 8% — 9% — 11% —

PE[15] 7% 9% 8% 8% 9% 12% 10% 11%

Table 20. I/O weight(1)

PAD

LQFP144/LQFP100 LQFP64(2)

Weight

SRE=0

Weight

SRE=1

Weight

3.3V

SRE=0

Weight

3.3V

SRE=1

Weight

SRE=0

Weight

SRE=1

Weight

3.3V

SRE=0

Weight

3.3V

SRE=1

Electrical characteristics SPC560Bx, SPC560Cx

56/113 Doc ID 14619 Rev 7

4.8 RESET electrical characteristics

The device implements a dedicated bidirectional RESET pin.

PG[10] 6% — 8% — 8% — 10% —

PG[11] 6% 9% 7% 8% 8% 11% 9% 10%

PC[3] 6% — 7% — 7% — 9% —

PC[2]6%8%7%7%6%9%8%8%

PA[5]5%7%6%6%6%8%7%7%

PA[6] 5% — 6% — 5% — 6% —

PC[1] 5% — 5% — 5% — 5% —

PC[0]6%9%7%8%6%9%7%8%

PE[2] 7% 10% 9% 9% 7% 10% 9% 9%

PE[3] 8% 11% 9% 9% 8% 11% 9% 9%

PC[5] 8% 11% 9% 10% 8% 11% 9% 10%

PC[4] 8% 12% 10% 10% 8% 12% 10% 10%

PE[4] 8% 12% 10% 11% 8% 12% 10% 11%

PE[5] 9% 12% 10% 11% 9% 12% 10% 11%

PH[4] 9% 13% 11% 11% 9% 13% 11% 11%

PH[5] 9% — 11% — 9% — 11% —

PH[6] 9% 13% 11% 12% 9% 13% 11% 12%

PH[7] 9% 13% 11% 12% 9% 13% 11% 12%

PH[8] 10% 14% 11% 12% 10% 14% 11% 12%

PE[6] 10% 14% 12% 12% 10% 14% 12% 12%

PE[7] 10% 14% 12% 12% 10% 14% 12% 12%

PC[12] 10% 14% 12% 13% 10% 14% 12% 13%

PC[13] 10% — 12% — 10% — 12% —

PC[8] 10% — 12% — 10% — 12% —

PB[2] 10% 15% 12% 13% 10% 15% 12% 13%

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to125 °C, unless otherwise specified

2. All LQFP64 information is indicative and must be confirmed during silicon validation.

Table 20. I/O weight(1)

PAD

LQFP144/LQFP100 LQFP64(2)

Weight

SRE=0

Weight

SRE=1

Weight

3.3V

SRE=0

Weight

3.3V

SRE=1

Weight

SRE=0

Weight

SRE=1

Weight

3.3V

SRE=0

Weight

3.3V

SRE=1

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 57/113

Figure 7. Start-up reset requirements

Figure 8. Noise filtering on reset signal

Table 21. Reset electrical characteristics

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

VIH SR P Input High Level CMOS

(Schmitt Trigger) — 0.65VDD —V

DD+0.4 V

VIL SR P Input low Level CMOS

(Schmitt Trigger) —0.4 — 0.35VDD V

VIL

VDD

device reset forced by RESET

VDDMIN

RESET

VIH

device start-up phase

VRESET

VIL

VIH

VDD

filtered by

hysteresis

filtered by

lowpass filter

WFRST

WNFRST

hw_rst

‘1’

‘0’

filtered by

lowpass filter

WFRST

unknown reset

state device under hardware reset

Electrical characteristics SPC560Bx, SPC560Cx

58/113 Doc ID 14619 Rev 7

VHYS CC C Input hysteresis CMOS

(Schmitt Trigger) —0.1V

DD ——V

VOL CC P Output low level

Push Pull, IOL = 2mA,

VDD = 5.0 V ± 10%,

PA D 3 V 5 V = 0

(recommended)

— — 0.1VDD

Push Pull, IOL = 1mA,

VDD = 5.0 V ± 10%,

PA D 3 V 5 V = 1 (2)

— — 0.1VDD

Push Pull, IOL = 1mA,

VDD = 3.3 V ± 10%,

PA D 3 V 5 V = 1

(recommended)

——0.5

Ttr CC D Output transition time

output pin(3)

CL = 25pF,

VDD = 5.0 V ± 10%,

PA D 3 V 5 V = 0

——10

CL = 50pF,

VDD = 5.0 V ± 10%,

PA D 3 V 5 V = 0

——20

CL = 100pF,

VDD = 5.0 V ± 10%,

PA D 3 V 5 V = 0

——40

CL = 25pF,

VDD = 3.3 V ± 10%,

PA D 3 V 5 V = 1

——12

CL = 50pF,

VDD = 3.3 V ± 10%,

PA D 3 V 5 V = 1

——25

CL = 100pF,

VDD = 3.3 V ± 10%,

PA D 3 V 5 V = 1

——40

WFRST SR P RESET input filtered pulse — — — 40 ns

WNFRST SR P RESET input not filtered

pulse — 1000 — — ns

|IWPU|CCP

Weak pull-up current

absolute value

VDD = 3.3 V ± 10%,

PA D 3 V 5 V = 1 10 — 150

µA

VDD = 5.0 V ± 10%,

PA D 3 V 5 V = 0 10 — 150

VDD = 5.0 V ± 10%,

PA D 3 V 5 V = 1 (2) 10 — 250

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

2. This transient configuration does not occurs when device is used in the VDD = 3.3 V ± 10% range.

3. CL includes device and package capacitance (CPKG <5pF).

Table 21. Reset electrical characteristics (continued)

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 59/113

4.9 Power management electrical characteristics

4.9.1 Voltage regulator electrical characteristics

The device implements an internal voltage regulator to generate the low voltage core supply

VDD_LV from the high voltage ballast supply VDD_BV

. The regulator itself is supplied by the

common I/O supply VDD. The following supplies are involved:

●HV—High voltage external power supply for voltage regulator module. This must be

provided externally through VDD power pin.

●BV—High voltage external power supply for internal ballast module. This must be

provided externally through VDD_BV power pin. Voltage values should be aligned with

VDD.

●LV—Low voltage internal power supply for core, FMPLL and flash digital logic. This is

generated by the internal voltage regulator but provided outside to connect stability

capacitor. It is further split into four main domains to ensure noise isolation between

critical LV modules within the device:

– LV_COR—Low voltage supply for the core. It is also used to provide supply for

FMPLL through double bonding.

– LV_CFLA—Low voltage supply for code flash module. It is supplied with dedicated

ballast and shorted to LV_COR through double bonding.

– LV_DFLA—Low voltage supply for data flash module. It is supplied with dedicated

ballast and shorted to LV_COR through double bonding.

– LV_PLL—Low voltage supply for FMPLL. It is shorted to LV_COR through double

bonding.

Electrical characteristics SPC560Bx, SPC560Cx

60/113 Doc ID 14619 Rev 7

Figure 9. Voltage regulator capacitance connection

The internal voltage regulator requires external capacitance (CREGn) to be connected to the

device in order to provide a stable low voltage digital supply to the device. Capacitances

should be placed on the board as near as possible to the associated pins. Care should also

be taken to limit the serial inductance of the board to less than 5 nH.

Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply

pairs to ensure stable voltage (see Section 4.5 Recommended operating conditions).

CREG1 (LV_COR/LV_DFLA)

DEVICE

VSS_LV

VDD_BV

VDD_LV

CDEC1 (Ballast decoupling)

VSS_LV VDD_LV VDD

VSS_LV VDD_LV

CREG2 (LV_COR/LV_CFLA)

CREG3 (LV_COR/LV_PLL) CDEC2 (supply/IO decoupling)

DEVICE

VDD_BV

VDD_LVn

VREF

VDD

Voltage Regulator

VSS

VSS_LVn

GND

GND GND

GND

Table 22. Voltage regulator electrical characteristics

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

CREGn SR — Internal voltage regulator external

capacitance — 200 — 500 nF

RREG SR — Stability capacitor equivalent

serial resistance ———0.2W

CDEC1 SR — Decoupling capacitance(2) ballast

VDD_BV/VSS_LV pair: VDD_BV

= 4.5 V to 5.5 V 100(3)

470(4)

—

VDD_BV/VSS_LV pair: VDD_BV

= 3V to 3.6V 400 —

CDEC2 SR — Decoupling capacitance regulator

supply VDD/VSS pair 10 100 — nF

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 61/113

VMREG CC TMain regulator output voltage Before exting from reset — 1.32 — V

P After trimming 1.15 1.28 1.32

IMREG SR — Main regulator current provided to

VDD_LV domain ———150mA

IMREGINT CC D Main regulator module current

consumption

IMREG = 200 mA — — 2 mA

IMREG = 0 mA — — 1

VLPREG CC P Low power regulator output

voltage After trimming 1.15 1.23 1.32 V

ILPREG SR — Low power regulator current

provided to VDD_LV domain ———15mA

ILPREGINT CC

DLow power regulator module

current consumption

ILPREG = 15 mA;

TA = 55 °C ——600

µA

—ILPREG = 0 mA;

TA = 55 °C —5—

VULPREG CC P Ultra low power regulator output

voltage After trimming 1.15 1.23 1.32 V

IULPREG SR — Ultra low power regulator current

provided to VDD_LV domain ———5mA

IULPREGINT CC D Ultra low power regulator module

current consumption

IULPREG = 5 mA;

TA = 55 °C ——100

µA

IULPREG = 0 mA;

TA = 55 °C —2—

IDD_BV CC D In-rush current on VDD_BV during

power-up(5) ———400

(6) mA

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

2. This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical

value is in the range of 470 nF.

3. This value is acceptable to guarantee operation from 4.5 V to 5.5 V

4. External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in

operating range.

5. In-rush current is seen only for short time during power-up and on standby exit (max 20 µs, depending on external LV

capacitances to be load)

6. The duration of the in-rush current depends on the capacitance placed on LV pins. BV decaps must be sized accordingly.

Refer to IMREG value for minimum amount of current to be provided in cc.

Table 22. Voltage regulator electrical characteristics (continued)

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

Electrical characteristics SPC560Bx, SPC560Cx

62/113 Doc ID 14619 Rev 7

4.9.2 Voltage monitor electrical characteristics

The device implements a Power-on Reset (POR) module to ensure correct power-up

initialization, as well as four low voltage detectors (LVDs) to monitor the VDD and the VDD_LV

voltage while device is supplied:

●POR monitors VDD during the power-up phase to ensure device is maintained in a safe

reset state

●LVDHV3 monitors VDD to ensure device reset below minimum functional supply

●LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range

●LVDLVCOR monitors power domain No. 1

●LVDLVBKP monitors power domain No. 0

Note: When enabled, power domain No. 2 is monitored through LVD_DIGBKP.

Figure 10. Low voltage monitor vs reset

VDD

VLVDHVxH

RESET

VLVDHVxL

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 63/113

4.10 Low voltage domain power consumption

Ta bl e 2 4 provides DC electrical characteristics for significant application modes. These

values are indicative values; actual consumption depends on the application.

Table 23. Low voltage monitor electrical characteristics

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

VPORUP SR P Supply for functional POR module — 1.0 — 5.5

VPORH CC PPower-on reset threshold

TA = 25 °C,

after trimming 1.5 — 2.6

T — 1.5 — 2.6

VLVDH V3H CC T LVDHV3 low voltage detector high threshold

—

— — 2.95

VLVDH V3L CC P LVDHV3 low voltage detector low threshold 2.6 — 2.9

VLVDH V5H CC T LVDHV5 low voltage detector high threshold — — 4.5

VLVDH V5L CC P LVDHV5 low voltage detector low threshold 3.8 — 4.4

VLVDLV COR L CC P LVDLVCOR low voltage detector low threshold 1.08 — 1.5

VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold 1.08 — 1.14

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Table 24. Low voltage power domain electrical characteristics

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

IDDMAX(2) CC D RUN mode maximum

average current — — 115 140(3) mA

IDDRUN(4) CC

RUN mode typical

average current(5)

fCPU = 8 MHz — 7 —

CPU = 16 MHz — 18 —

CPU = 32 MHz — 29 —

CPU = 48 MHz — 40 —

CPU = 64 MHz — 51 —

IDDHALT CC

HALT mode current(6)

Slow internal RC

oscillator (128 kHz)

running

TA=25°C — 8 15

A= 125 °C — 14 25

IDDSTOP CC

STOP mode current(7)

Slow internal RC

oscillator (128 kHz)

running

TA= 25 °C — 180 700(8)

µA

A= 55 °C — 500 —

A=85°C — 1 —

mADT

A= 105 °C — 2 —

A=125°C — 4.5 12

(8)

Electrical characteristics SPC560Bx, SPC560Cx

64/113 Doc ID 14619 Rev 7

4.11 Flash memory electrical characteristics

4.11.1 Program/Erase characteristics

Ta bl e 2 5 shows the program and erase characteristics.

IDDSTDBY2 CC

STANDBY2 mode

current(9)

Slow internal RC

oscillator (128 kHz)

running

TA= 25 °C — 30 100

µA

A=55°C — 75 —

A= 85 °C — 180 —

A= 105 °C — 315 —

A= 125 °C — 560 1700

IDDSTDBY1 CC

STANDBY1 mode

current(10)

Slow internal RC

oscillator (128 kHz)

running

TA=25°C — 20 60

µA

A=55°C — 45 —

A= 85 °C — 100 —

A= 105 °C — 165 —

A= 125 °C — 280 900

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

2. Running consumption is given on voltage regulator supply (VDDREG). IDDMAX is composed of three components: IDDMAX =

IDD(vdd_bv) + IDD(vdd_hv) + IDD(Vdd_hv_adc). It does not include a fourth component linked to I/Os toggling which is

highly dependent on the application. The given value is thought to be a worst case value with all peripherals running, and

code fetched from code flash while modify operation on-going on data flash. It is to be noticed that this value can be

significantly reduced by application: switch-off not used peripherals (default), reduce peripheral frequency through internal

prescaler, fetch from RAM most used functions, use low power mode when possible.

3. Higher current may be sinked by device during power-up and standby exit. please refer to in rush current on Table 22.

4. RUN current measured with typical application with accesses on both flash and RAM.

5. Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and LIN in

loop back mode, DSPi as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at

max frequency, periodic SW/WDG timer reset enabled.

6. Data Flash Power Down. Code Flash in Low Power. RC-osc128kHz & RC-OSC 16MHz on. 10MHz XTAL clock. FlexCAN:

instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex: instances: 0, 1, 2

ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON (16 channels on PA[0]-

PA[11] and PC[12]-PC[15]) with PWM 20kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication).

RTC/API ON.PIT ON. STM ON. ADC ON but not conversion except 2 analogue watchdog

7. Only for the “P” classification: No clock, RC 16MHz off, RC128kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All

possible peripherals off and clock gated. Flash in power down mode.

8. When going from RUN to STOP mode and the core consumption is > 6 mA , it is normal operation for the main regulator

module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures

exceeding 125 °C and under these circumstances , it is possible for the current to initially exceed the maximum STOP

specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and

the main regulator will be automatically switched off when the load current is below 6 mA.

9. Only for the “P” classification: ULPreg on, HP/LPVreg off, 32kB RAM on, device configured for minimum consumption, all

possible modules switched-off.

10. ULPreg on, HP/LPVreg off, 8kB RAM on, device configured for minimum consumption, all possible modules switched-off.

Table 24. Low voltage power domain electrical characteristics (continued)

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 65/113

Table 25. Program and erase specifications

Symbol C Parameter

Value

Unit

Min Typ(1)

1. Typical program and erase times assume nominal supply values and operation at 25 °C.

Initial max(2)

2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

Max(3)

3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values

are characterized but not guaranteed.

Tdwprogram

CC C

Double word (64 bits) program time(4)

4. Actual hardware programming times. This does not include software overhead.

—22 50 500µs

T16Kpperase 16 KB block pre-program and erase time — 300 500 5000 ms

T32Kpperase 32 KB block pre-program and erase time — 400 600 5000 ms

T128Kpperase 128 KB block pre-program and erase time — 800 1300 7500 ms

Teslat CC D Erase Suspend Latency — — 30 30 µs

Table 26. Flash module life

Symbol C Parameter Conditions

Value

Unit

Min Typ Max

P/E CC C

Number of program/erase cycles per

block for 16 Kbyte blocks over the

operating temperature range (TJ)

— 100000 — — cycles

P/E CC C

Number of program/erase cycles per

block for 32 Kbyte blocks over the

operating temperature range (TJ)

— 10000 100000 — cycles

P/E CC C

Number of program/erase cycles per

block for 128 Kbyte blocks over the

operating temperature range (TJ)

— 1000 100000 — cycles

Retention CC C Minimum data retention at 85 °C

average ambient temperature(1)

1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature

range.

ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability

results. Some units will experience single bit corrections throughout the life of the product with no impact

to product reliability.

Blocks with 0–1000

P/E cycles 20 — — years

Blocks with 1001–

10000 P/E cycles 10 — — years

Blocks with 10001–

100000 P/E cycles 5——years

Electrical characteristics SPC560Bx, SPC560Cx

66/113 Doc ID 14619 Rev 7

4.11.2 Flash power supply DC characteristics

Ta bl e 2 8 shows the power supply DC characteristics on external supply.

Table 27. Flash read access timing

Symbol C Parameter Conditions(1)

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Max Unit

fREAD CC

Maximum frequency for Flash reading

2 wait states 64

MHzC 1 wait state 40

C 0 wait states 20

Table 28. Code Flash power supply DC electrical characteristics

Symbol C Parameter Conditions(1)

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value

Unit

Min Typ Max

IFREAD(2)

2. This value is only relative to the actual duration of the read cycle

CC D

Sum of the current

consumption on VDDHV and

VDDBV on read access

Code Flash module read

fCPU =64 MHz

(3)

3. fCPU 64 MHz can be achieved only at up to 105 °C

—1533

Data Flash module read

fCPU =64 MHz

(3) —1533

IFMOD(2) CC D

Sum of the current

consumption on VDDHV and

VDDBV on matrix modification

(program/erase)

Program/Erase on-going while reading

Code Flash registers fCPU = 64 MHz(3) —1533

Program/Erase on-going while reading

Data Flash registers fCPU =64 MHz

(3) —1533

IFLPW CC D

Sum of the current

consumption on VDDHV and

VDDBV

during Code Flash low-power mode — — 900

µA

during Data Flash low-power mode — — 900

IFPWD CC D

Sum of the current

consumption on VDDHV and

VDDBV

during Code Flash powe-down mode — — 150

µA

during Data Flash powe-down mode — — 150

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 67/113

4.11.3 Start-up/Switch-off timings

4.12 Electromagnetic compatibility (EMC) characteristics

Susceptibility tests are performed on a sample basis during product characterization.

4.12.1 Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical

application environment and simplified MCU software. It should be noted that good EMC

performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user apply EMC software optimization and

prequalification tests in relation with the EMC level requested for his application.

●Software recommendations:The software flowchart must include the management of

runaway conditions such as:

– Corrupted program counter

– Unexpected reset

– Critical data corruption (control registers...)

●Prequalification trials:Most of the common failures (unexpected reset and program

counter corruption) can be reproduced by manually forcing a low state on the reset pin

or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device. When

unexpected behavior is detected, the software can be hardened to prevent

unrecoverable errors occurring (see application note Software Techniques For

Improving Microcontroller EMC Performance (AN1015)).

Table 29. Start-up time/Switch-off time

Symbol C Parameter Conditions(1)

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value

Unit

Min Typ Max

TFLARSTEXIT CC TDelay for Flash module to exit reset mode Code Flash — — 125

µs

T Data Flash — — 125

TFLALPEXIT CC TDelay for Flash module to exit low-power

mode

Code Flash — — 0.5

T Data Flash — — 0.5

TFLAPDEXIT CC TDelay for Flash module to exit power-down

mode

Code Flash — — 30

T Data Flash — — 30

TFLALPENTRY CC TDelay for Flash module to enter low-power

mode

Code Flash — — 0.5

T Data Flash — — 0.5

TFLAPDENTRY CC TDelay for Flash module to enter power-

down mode

Code Flash — — 1.5

T Data Flash — — 1.5

Electrical characteristics SPC560Bx, SPC560Cx

68/113 Doc ID 14619 Rev 7

4.12.2 Electromagnetic interference (EMI)

The product is monitored in terms of emission based on a typical application. This emission

test conforms to the IEC 61967-1 standard, which specifies the general conditions for EMI

measurements.

4.12.3 Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the

product is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test

conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the

application note Electrostatic Discharge Sensitivity Measurement (AN1181).

Table 30. EMI radiated emission measurement(1)(2)

1. EMI testing and I/O port waveforms per IEC 61967-1, -2, -4

2. For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local

marketing representative.

Symbol C Parameter Conditions

Value

Unit

Min Typ Max

— SR — Scan range — 0.150 — 1000 MHz

fCPU SR — Operating frequency — — 64 — MHz

VDD_LV SR — LV operating voltages — — 1.28 — V

SEMI CC T Peak level

VDD = 5V, T

A=25°C,

LQFP144 package

Test conforming to IEC

61967-2,

fOSC = 8 MHz/fCPU = 64

MHz

No PLL frequency

modulation — — 18 dBµV

± 2% PLL frequency

modulation — — 14 dBµV

Table 31. ESD absolute maximum ratings(1) (2)

Symbol C Ratings Conditions Class Max value Unit

VESD(HBM) CC T Electrostatic discharge voltage

(Human Body Model)

TA = 25 °C

conforming to AEC-Q100-002 H1C 2000

VESD(MM) CC T Electrostatic discharge voltage

(Machine Model)

TA = 25 °C

conforming to AEC-Q100-003 M2 200

VESD(CDM) CC T Electrostatic discharge voltage

(Charged Device Model)

TA = 25 °C

conforming to AEC-Q100-011 C3A 500

750 (corners)

1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification

requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at

room temperature followed by hot temperature, unless specified otherwise in the device specification.

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 69/113

Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up

performance:

●A supply overvoltage is applied to each power supply pin.

●A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with the EIA/JESD 78 IC latch-up standard.

4.13 Fast external crystal oscillator (4 to 16 MHz) electrical

characteristics

The device provides an oscillator/resonator driver. Figure 11 describes a simple model of

the internal oscillator driver and provides an example of a connection for an oscillator or a

resonator.

Ta bl e 3 3 provides the parameter description of 4 MHz to 16 MHz crystals used for the

design simulations.

Table 32. Latch-up results

Symbol C Parameter Conditions Class

LU CC T Static latch-up class TA = 125 °C

conforming to JESD 78 II level A

Electrical characteristics SPC560Bx, SPC560Cx

70/113 Doc ID 14619 Rev 7

Figure 11. Crystal oscillator and resonator connection scheme

Table 33. Crystal description

Nominal

frequency

(MHz)

NDK crystal

reference

Crystal

equivalent

series

resistance

ESR 

Crystal

motional

capacitance

(Cm) fF

Crystal

motional

inductance

(Lm) mH

Load on

xtalin/xtalout

C1 = C2

(pF)(1)

1. The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all

the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.

Shunt

capacitance

between

xtalout

and xtalin

C0(2) (pF)

2. The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package,

etc.).

4 NX8045GB 300 2.68 591.0 21 2.93

NX5032GA

300 2.46 160.7 17 3.01

10 150 2.93 86.6 15 2.91

12 120 3.11 56.5 15 2.93

16 120 3.90 25.3 10 3.00

Crystal

XTAL

EXTAL

Resonator

XTAL

EXTAL

DEVICE

XTAL

EXTAL

VDD

Note: XTAL/EXTAL must not be directly used to drive external circuits.

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 71/113

Figure 12. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics

VFXOSCOP

TFXOSCSU

VXTAL

VFXOSC

valid internal clock

90%

10%

1/fFXOSC

S_MTRANS bit (ME_GS register)

‘1’

‘0’

Table 34. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

fFXOSC SR — Fast external crystal oscillator

frequency —4.0—16.0MHz

gmFXOSC

CC C

Fast external crystal oscillator

transconductance

VDD = 3.3 V ± 10%,

PAD3V5V = 1

OSCILLATOR_MARGIN = 0

2.2 — 8.2

mA/V

CC P

VDD = 5.0 V ± 10%,

PAD3V5V = 0

OSCILLATOR_MARGIN = 0

2.0 — 7.4

CC C

VDD = 3.3 V ± 10%,

PAD3V5V = 1

OSCILLATOR_MARGIN = 1

2.7 — 9.7

CC C

VDD = 5.0 V ± 10%,

PAD3V5V = 0

OSCILLATOR_MARGIN = 1

2.5 — 9.2

VFXOSC CC T Oscillation amplitude at

EXTAL

fOSC = 4 MHz,

OSCILLATOR_MARGIN = 0 1.3 — —

fOSC = 16 MHz,

OSCILLATOR_MARGIN = 1 1.3 — —

VFXOSCOP CC P Oscillation operating point — — 0.95 V

IFXOSC(2) CC T Fast external crystal oscillator

consumption ——23mA

TFXOSCSU CC T Fast external crystal oscillator

start-up time

fOSC = 4 MHz,

OSCILLATOR_MARGIN = 0 —— 6

fOSC = 16 MHz,

OSCILLATOR_MARGIN = 1 ——1.8

Electrical characteristics SPC560Bx, SPC560Cx

72/113 Doc ID 14619 Rev 7

4.14 Slow external crystal oscillator (32 kHz) electrical

characteristics

The device provides a low power oscillator/resonator driver.

Figure 13. Crystal oscillator and resonator connection scheme

VIH SR P Input high level CMOS

(Schmitt Trigger) Oscillator bypass mode 0.65VDD —V

DD+0.4 V

VIL SR P Input low level CMOS

(Schmitt Trigger) Oscillator bypass mode 0.4 — 0.35VDD V

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

2. Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled

peripherals)

Table 34. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued)

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

OSC32K_XTAL

OSC32K_EXTAL

DEVICE

Crystal

OSC32K_XTAL

OSC32K_EXTAL

Resonator

DEVICE

Note: OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 73/113

Figure 14. Equivalent circuit of a quartz crystal

C2C1

Crystal

Electrical characteristics SPC560Bx, SPC560Cx

74/113 Doc ID 14619 Rev 7

Figure 15. Slow external crystal oscillator (32 kHz) electrical characteristics

Table 35. Crystal motional characteristics(1)

1. The crystal used is Epson Toyocom MC306.

Symbol Parameter Conditions

Value

Unit

Min Typ Max

LmMotional inductance — — 11.796 — KH

CmMotional capacitance — — 2 — fF

C1/C2

Load capacitance at OSC32K_XTAL

and OSC32K_EXTAL with respect to

ground(2)

2. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It

includes all the parasitics due to board traces, crystal and package.

— 18 — 28 pF

Rm(3)

3. Maximum ESR (Rm) of the crystal is 50 k

Motional resistance

AC coupled @ C0 = 2.85 pF(4)

4. C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins

——65

AC coupled @ C0 = 4.9 pF(4) ——50

AC coupled @ C0 = 7.0 pF(4) ——35

AC coupled @ C0 = 9.0 pF(4) ——30

OSCON bit (OSC_CTL register)

TSXOSCSU

VOSC32K_XTAL

VSXOSC

valid internal clock

90%

10%

1/fSXOSC

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 75/113

4.15 FMPLL electrical characteristics

The device provides a frequency-modulated phase-locked loop (FMPLL) module to

generate a fast system clock from the main oscillator driver.

Table 36. Slow external crystal oscillator (32 kHz) electrical characteristics

Symbol C Parameter Conditions(1)

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified

Value

Unit

Min Typ Max

fSXOSC SR — Slow external crystal oscillator

frequency — 32 32.768 40 kHz

VSXOSC CC T Oscillation amplitude — — 2.1 — V

ISXOSCBIAS CC T Oscillation bias current — — 2.5 — µA

ISXOSC CC T Slow external crystal oscillator

consumption ———8µA

TSXOSCSU CC T Slow external crystal oscillator

start-up time ———2

(2)

2. Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal

Table 37. FMPLL electrical characteristics

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

fPLLIN SR — FMPLL reference clock(2) —4—64MHz

PLLIN SR — FMPLL reference clock duty

cycle(2) —40—60%

fPLLOUT CC D FMPLL output clock

frequency —16—64MHz

fVCO(3) CC

PVCO frequency without

frequency modulation —256—512

MHz

PVCO frequency with

frequency modulation —245—533

fCPU SR — System clock frequency — — — 64 MHz

fFREE CC P Free-running frequency — 20 — 150 MHz

tLOCK CC P FMPLL lock time Stable oscillator (fPLLIN = 16 MHz) 40 100 µs

tLTJIT CC — FMPLL long term jitter fPLLIN = 16 MHz (resonator),

fPLLCLK @ 64 MHz, 4000 cycles — — 10 ns

IPLL CC C FMPLL consumption TA = 25 °C — — 4 mA

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.

2. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional

mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN.

3. Frequency modulation is considered ± 4%

Electrical characteristics SPC560Bx, SPC560Cx

76/113 Doc ID 14619 Rev 7

4.16 Fast internal RC oscillator (16 MHz) electrical characteristics

The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at

the power-up of the device.

4.17 Slow internal RC oscillator (128 kHz) electrical

characteristics

The device provides a 128 kHz slow internal RC oscillator. This can be used as the

reference clock for the RTC module.

Table 38. Fast internal RC oscillator (16 MHz) electrical characteristics

Symbol C Parameter Conditions(1)

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.

Value

Unit

Min Typ Max

fFIRC

CC P Fast internal RC oscillator high

frequency

TA = 25 °C, trimmed — 16 — MHz

SR — — 12 20

IFIRCRUN(2)

2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.

CC T

Fast internal RC oscillator high

frequency current in running

mode

TA = 25 °C, trimmed — — 200 µA

IFIRCPWD CC D

Fast internal RC oscillator high

frequency current in power

down mode

TA = 125 °C — — 10 µA

IFIRCSTOP CC T

Fast internal RC oscillator high

frequency and system clock

current in stop mode

TA = 25 °C

sysclk = off — 500 —

µA

sysclk = 2 MHz — 600 —

sysclk = 4 MHz — 700 —

sysclk = 8 MHz — 900 —

sysclk = 16 MHz — 1250 —

TFIRCSU CC C Fast internal RC oscillator start-

up time VDD = 5.0 V ± 10% — 1.1 2.0 µs

FIRCPRE CC T

Fast internal RC oscillator

precision after software

trimming of fFIRC

TA = 25 °C 1—+1%

FIRCTRIM CC T Fast internal RC oscillator

trimming step TA = 25 °C — 1.6 %

FIRCVAR CC P

Fast internal RC oscillator

variation in overtemperature

and supply with respect to fFIRC

at TA= 25 °C in high-frequency

configuration

—5—+5%

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 77/113

4.18 ADC electrical characteristics

4.18.1 Introduction

The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital

converter.

Table 39. Slow internal RC oscillator (128 kHz) electrical characteristics

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

fSIRC

CC P Slow internal RC oscillator low

frequency

TA = 25 °C, trimmed — 128 — kHz

SR — — 100 — 150

ISIRC(2) CC C Slow internal RC oscillator low

frequency current TA = 25 °C, trimmed — — 5 µA

TSIRCSU CC P Slow internal RC oscillator start-up

time TA = 25 °C, VDD = 5.0 V ± 10% — 8 12 µs

SIRCPRE CC C

Slow internal RC oscillator

precision after software trimming of

fSIRC

TA = 25 °C 2—+2

SIRCTRIM CC C Slow internal RC oscillator trimming

step ——2.7—

SIRCVAR CC C

Slow internal RC oscillator variation

in temperature and supply with

respect to fSIRC at TA= 55 °C in

high frequency configuration

High frequency configuration 10 — +10 %

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.

2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.

Electrical characteristics SPC560Bx, SPC560Cx

78/113 Doc ID 14619 Rev 7

Figure 16. ADC characteristic and error definitions

4.18.2 Input impedance and ADC accuracy

In the following analysis, the input circuit corresponding to the precise channels is

considered.

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have

low AC impedance. Placing a capacitor with good high frequency characteristics at the input

pin of the device can be effective: the capacitor should be as large as possible, ideally

infinite. This capacitor contributes to attenuating the noise present on the input pin;

furthermore, it sources charge during the sampling phase, when the analog signal source is

a high-impedance source.

A real filter can typically be obtained by using a series resistance with a capacitor on the

input pin (simple RC filter). The RC filtering may be limited according to the value of source

(2)

(1)

(3)

(4)

(5)

Offset Error OSE

Gain Error GE

1 LSB (ideal)

Vin(A) (LSBideal)

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer curve

code out

1023

1022

1021

1020

1019

1018

1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023

1 LSB ideal = VDD_ADC / 1024

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 79/113

impedance of the transducer or circuit supplying the analog signal to be measured. The filter

at the input pins must be designed taking into account the dynamic characteristics of the

input signal (bandwidth) and the equivalent input impedance of the ADC itself.

In fact a current sink contributor is represented by the charge sharing effects with the

sampling capacitance: CS being substantially a switched capacitance, with a frequency

equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For

instance, assuming a conversion rate of 1 MHz, with CS equal to 3 pF, a resistance of

330 k is obtained (REQ = 1 / (fc*CS), where fc represents the conversion rate at the

considered channel). To minimize the error induced by the voltage partitioning between this

resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external

circuit must be designed to respect the Equation 4:

Equation 4

Equation 4 generates a constraint for external network design, in particular on a resistive

path. Internal switch resistances (RSW and RAD) can be neglected with respect to external

resistances.

Figure 17. Input equivalent circuit (precise channels)

RSRFRLRSW RAD

+++ +

REQ

---------------------------------------------------------------------------

1

---LSB



SW1

Sampling

Source Filter Current Limiter

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

Channel

Selection

RS Source Impedance

RF Filter Resistance

CF Filter Capacitance

RL Current Limiter Resistance

RSW1 Channel Selection Switch Impedance

RAD Sampling Switch Impedance

CP Pin Capacitance (two contributions, CP1 and CP2)

CS Sampling Capacitance

Electrical characteristics SPC560Bx, SPC560Cx

80/113 Doc ID 14619 Rev 7

Figure 18. Input equivalent circuit (extended channels)

A second aspect involving the capacitance network shall be considered. Assuming the three

capacitances CF

, CP1 and CP2 are initially charged at the source voltage VA (refer to the

equivalent circuit in Figure 17): A charge sharing phenomenon is installed when the

sampling phase is started (A/D switch close).

Figure 19. Transient behavior during sampling phase

In particular two different transient periods can be distinguished:

1. A first and quick charge transfer from the internal capacitance CP1 and CP2 to the

sampling capacitance CS occurs (CS is supposed initially completely discharged):

considering a worst case (since the time constant in reality would be faster) in which

SW1

Sampling

Source Filter Current Limiter

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

Channel

Selection

Extended

SW2

Switch

RS Source Impedance

RF Filter Resistance

CF Filter Capacitance

RL Current Limiter Resistance

RSW Channel Selection Switch Impedance (two contributions RSW1 and RSW2)

RAD Sampling Switch Impedance

CP Pin Capacitance (three contributions, CP1, CP2 and CP3)

CS Sampling Capacitance

VA1

VA2

VCS Voltage transient on CS

V <0.5 LSB

1 < (RSW + RAD) CS << TS



= R

+ C

)

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 81/113

CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and

CS are in series, and the time constant is

Equation 5

Equation 5 can again be simplified considering only CS as an additional worst

condition. In reality, the transient is faster, but the A/D converter circuitry has been

designed to be robust also in the very worst case: the sampling time TS is always much

longer than the internal time constant:

Equation 6

The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the

voltage VA1 on the capacitance according to Equation 7:

Equation 7

2. A second charge transfer involves also CF (that is typically bigger than the on-chip

capacitance) through the resistance RL: again considering the worst case in which CP2

and CS were in parallel to CP1 (since the time constant in reality would be faster), the

time constant is:

Equation 8

In this case, the time constant depends on the external circuit: in particular imposing

that the transient is completed well before the end of sampling time TS, a constraints on

RL sizing is obtained:

Equation 9

Of course, RL shall be sized also according to the current limitation constraints, in

combination with RS (source impedance) and RF (filter resistance). Being CF

definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the

charge transfer transient) will be much higher than VA1. Equation 10 must be respected

(charge balance assuming now CS already charged at VA1):

Equation 10

The two transients above are not influenced by the voltage source that, due to the presence

of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on

CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with

respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.

1RSW RAD

+=

CPCS



CPCS

----------------------



1RSW RAD

+CSTS

«

VA1 CSCP1 CP2

++VACP1 CP2

+=

2RL

CSCP1 CP2

++

10 2

10 RLCSCP1 CP2

++=T



VA2 CSCP1 CP2 CF

+++VACF

VA1

P1 CP2

+=

Electrical characteristics SPC560Bx, SPC560Cx

82/113 Doc ID 14619 Rev 7

Figure 20. Spectral representation of input signal

Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of

the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at

least 2f0; it means that the constant time of the filter is greater than or at least equal to twice

the conversion period (TC). Again the conversion period TC is longer than the sampling time

TS, which is just a portion of it, even when fixed channel continuous conversion mode is

selected (fastest conversion rate at a specific channel): in conclusion it is evident that the

time constant of the filter RFCF is definitively much higher than the sampling time TS, so the

charge level on CS cannot be modified by the analog signal source during the time in which

the sampling switch is closed.

The considerations above lead to impose new constraints on the external circuit, to reduce

the accuracy error due to the voltage drop on CS; from the two charge balance equations

above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS:

Equation 11

From this formula, in the worst case (when VA is maximum, that is for instance 5 V),

assuming to accept a maximum error of half a count, a constraint is evident on CF value:

Equation 12

f0f

Analog source bandwidth (VA)

f0f

Sampled signal spectrum (fC = conversion rate)

Anti-aliasing filter (fF = RC filter pole)

2 f0<fC (Nyquist)

fF = f0 (anti-aliasing filtering condition)

TC<2 RFCF (conversion rate vs. filter pole)

Noise

VA2

------------

CP1 CP2

FCS

--------------------------------------------------------=

CF2048 CS



SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 83/113

4.18.3 ADC electrical characteristics

Table 40. ADC input leakage current

Symbol C Parameter Conditions

Value

Unit

Min Typ Max

ILKG CC

Input leakage current

TA=40 °C

No current injection on adjacent pin

—1—

A= 25 °C — 1 —

A= 105 °C — 8 200

A= 125 °C — 45 400

Table 41. ADC conversion characteristics

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

VSS_ADC SR —

Voltage on VSS_HV_ADC (ADC

reference) pin with respect to ground

(VSS)(2)

—0.1 — 0.1 V

VDD_ADC SR —

Voltage on VDD_HV_ADC pin (ADC

reference) with respect to ground

(VSS)

—V

DD0.1 — VDD+0.1 V

VAINx SR — Analog input voltage(3) —V

SS_ADC0.1 — VDD_ADC+0.1 V

fADC SR —ADC analog frequency —6—32 + 4% MHz

ADC_SYS SR —ADC digital clock duty cycle (ipg_clk) ADCLKSEL = 1(4) 45 — 55 %

IADCPWD SR —ADC0 consumption in power down

mode ———

50 µs

IADCRUN SR —ADC0 consumption in running mode — — — 4ms

tADC_PU SR —ADC power up delay ———1.5 µs

Electrical characteristics SPC560Bx, SPC560Cx

84/113 Doc ID 14619 Rev 7

tADC_S CC T Sample time(5)

fADC = 32 MHz,

INPSAMP = 17 0.5 —

µs

fADC = 6 MHz,

INPSAMP = 255 ——42

tADC_C CC P Conversion time(6) fADC = 32 MHz,

INPCMP = 2 0.625 — µs

CSCC DADC input sampling capacitance — — — 3pF

CP1 CC DADC input pin capacitance 1 — — — 3pF

CP2 CC DADC input pin capacitance 2 ———1pF

CP3 CC DADC input pin capacitance 3 — — — 1pF

RSW1 CC DInternal resistance of analog source — — — 3 k

RSW2 CC DInternal resistance of analog source — — — 2 k

RAD CC DInternal resistance of analog source — — — 2 k

IINJ SR —Input current Injection

Current

injection on

one ADC

input,

different from

the

converted

one

VDD =

3.3 V ± 10% 5— 5

VDD =

5.0 V ± 10% 5 — 5

| INL | CC TAbsolute value for integral non-

linearity No overload — 0.5 1.5 LSB

| DNL | CC TAbsolute differential non-linearity No overload —0.5 1.0 LSB

| OFS | CC TAbsolute offset error — — 0.5 — LSB

| GNE | CC TAbsolute gain error ——0.6 —LSB

Table 41. ADC conversion characteristics (continued)

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 85/113

TUEp CC PTotal unadjusted error(7) for precise

channels, input only pins

Without current injection 20.6 2LSB

TWith current injection 3 3

TUEx CC TTotal unadjusted error(7) for extended

channel

Without current injection 3 1 3 LSB

TWith current injection 4 4

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.

2. Analog and digital VSS must be common (to be tied together externally).

3. VAINx may exceed VSS_ADC and VDD_ADC limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to

0x000 or 0x3FF.

4. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal divider by 2.

5. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must

allow the capacitance to reach its final voltage level within tADC_S. After the end of the sample time tADC_S, changes of the analog input voltage have no

effect on the conversion result. Values for the sample clock tADC_S depend on programming.

6. This parameter does not include the sample time tADC_S, but only the time for determining the digital result and the time to load the result’s register with the

conversion result.

7. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a combination of Offset, Gain and Integral

Linearity errors.

Table 41. ADC conversion characteristics (continued)

Symbol C Parameter Conditions(1) Value

Unit

Min Typ Max

Electrical characteristics SPC560Bx, SPC560Cx

86/113 Doc ID 14619 Rev 7

4.19 On-chip peripherals

4.19.1 Current consumption

Table 42. On-chip peripherals current consumption(1)

Symbol C Parameter Conditions

Value

Unit

Typ

IDD_BV(CAN) CC T CAN (FlexCAN) supply current on

VDD_BV

500

Kbps

Total (static + dynamic)

consumption:

– FlexCAN in loop-back mode

– XTAL@ 8MHz used as CAN

engine clock source

– Message sending period is 580

µs

8 * fperiph + 85

µA

125

Kbps 8 * fperiph + 27

IDD_BV(eMIOS) CC T eMIOS supply current on VDD_BV

Static consumption:

– eMIOS channel OFF

– Global prescaler enabled

29 * fperiph

Dynamic consumption:

– It does not change varying the frequency

(0.003 mA)

IDD_BV(SCI) CC T SCI (LINFlex) supply current on

VDD_BV

Total (static + dynamic) consumption:

– LIN mode

– Baudrate: 20 Kbps

5 * fperiph + 31

IDD_BV(SPI) CC T SPI (DSPI) supply current on

VDD_BV

Ballast static consumption (only clocked) 1

Ballast dynamic consumption (continuus

communication):

– Baudrate: 2 Mbit

– Trasmission every 8 µs

– Frame: 16 bits

16 * fperiph

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 87/113

4.19.2 DSPI characteristics

IDD_BV(ADC) CC T ADC supply current on VDD_BV

VDD =

5.5 V

Ballast static consumption (no

conversion) 41 * fperiph

µA

VDD =

5.5 V

Ballast dynamic consumption

(continuus conversion) 5 * fperiph

IDD_HV_ADC(ADC) CC T ADC supply current on

VDD_HV_ADC

VDD =

5.5 V

Analog static consumption (no

conversion) 2 * fperiph

VDD =

5.5 V

Analog dynamic consumption

(continuus conversion) 75 * fperiph + 32

IDD_HV(FLASH) CC T CFlash + DFlash supply current

on VDD_HV_ADC

VDD =

5.5 V —8.21mA

IDD_HV(PLL) CC T PLL supply current on VDD_HV

VDD =

5.5 V —3 * f

periph µA

1. Operating conditions: TA = 25 °C, fperiph = 8 MHz to 64 MHz

Table 42. On-chip peripherals current consumption(1) (continued)

Symbol C Parameter Conditions

Value

Unit

Typ

Table 43. DSPI characteristics(1)

No. Symbol C Parameter

DSPI0/DSPI1 DSPI2

Unit

Min Typ Max Min Typ Max

SCK SR

SCK cycle time

Master mode

(MTFE = 0) 125 — — 333 — —

DSlave mode

(MTFE = 0) 125 — — 333 — —

DMaster mode

(MTFE = 1) 83——125——

DSlave mode

(MTFE = 1) 83——125——

Electrical characteristics SPC560Bx, SPC560Cx

88/113 Doc ID 14619 Rev 7

—f

DSPI SR D DSPI digital controller frequency — — fCPU ——f

CPU MHz

—tCSC CC D

Internal delay between pad associated

to SCK and pad associated to CSn in

master mode for CSn1->0

Master mode — — 130(2) ——15

(3) ns

—tASC CC D

Internal delay between pad associated

to SCK and pad associated to CSn in

master mode for CSn1->1

Master mode — — 130(3) ——130

(3) ns

CSCext(4) SR D CS to SCK delay Slave mode 32 — — 32 — — ns

ASCext(5) SR D After SCK delay Slave mode 1/fDSPI +

5——

1/fDSPI +

5——ns

SDC

CC D SCK duty cycle Master mode — tSCK/2 — — tSCK/2 — ns

SR D Slave mode tSCK/2 — — tSCK/2 — —

ASR D Slave access time Slave mode — — 1/fDSPI +

70 ——

1/fDSPI +

130 ns

DI SR D Slave SOUT disable time Slave mode 7 — — 7 — — ns

SUI SR D Data setup time for inputs Master mode 43 — — 145 — — ns

Slave mode 5 — — 5 — —

10 tHI SR D Data hold time for inputs Master mode 0 — — 0 — — ns

Slave mode 2(6) ——2

(6) ——

11 tSUO(7) CC D Data valid after SCK edge Master mode — — 32 — — 50 ns

Slave mode — — 52 — — 160

12 tHO(7) CC D Data hold time for outputs Master mode 0 — — 0 — — ns

Slave mode 8 — — 13 — —

1. Operating conditions: Cout = 10 to 50 pF, SlewIN = 3.5 to 15 ns.

2. Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK starts before CSn is

asserted. DSPI2 has only SLOW SCK available.

Table 43. DSPI characteristics(1) (continued)

No. Symbol C Parameter

DSPI0/DSPI1 DSPI2

Unit

Min Typ Max Min Typ Max

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 89/113

3. Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is deasserted before

SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.

4. The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS

and internal SCK must be higher than tCSC to ensure positive tCSCext.

5. The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between internal CS and

internal SCK must be higher than tASC to ensure positive tASCext.

6. This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.

7. SCK and SOUT configured as MEDIUM pad

Electrical characteristics SPC560Bx, SPC560Cx

90/113 Doc ID 14619 Rev 7

Figure 21. DSPI classic SPI timing – master, CPHA = 0

Data Last Data

First Data

First Data Data Last Data

SIN

SOUT

PCSx

SCK Output

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Ta b le 4 3 .

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 91/113

Figure 22. DSPI classic SPI timing – master, CPHA = 1

Figure 23. DSPI classic SPI timing – slave, CPHA = 0

Data Last Data

First Data

SIN

SOUT

12 11

Last Data

Data

First Data

SCK Output

PCSx

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Ta bl e 4 3 .

Last Data

First Data

Data

SIN

SOUT

5 6

SCK Input

First Data Last Data

SCK Input

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Ta bl e 4 3 .

Electrical characteristics SPC560Bx, SPC560Cx

92/113 Doc ID 14619 Rev 7

Figure 24. DSPI classic SPI timing – slave, CPHA = 1

Figure 25. DSPI modified transfer format timing – master, CPHA = 0

5 6

Last Data

SIN

SOUT

First Data

Data

SCK Input

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Ta b l e 4 3 .

PCSx

12 11

SCK Output

SIN

SOUT

First Data Data Last Data

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Ta b l e 4 3 .

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 93/113

Figure 26. DSPI modified transfer format timing – master, CPHA = 1

Figure 27. DSPI modified transfer format timing – slave, CPHA = 0

PCSx

12 11

SCK Output

SIN

SOUT

First Data Data Last Data

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Ta b l e 4 3 .

Last Data

First Data

Data

SIN

SOUT

5 6

SCK Input

First Data Last Data

SCK Input

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Table 43 .

Electrical characteristics SPC560Bx, SPC560Cx

94/113 Doc ID 14619 Rev 7

Figure 28. DSPI modified transfer format timing – slave, CPHA = 1

4.19.3 Nexus characteristics

5 6

Last Data

SIN

SOUT

First Data

Data

SCK Input

(CPOL = 0)

(CPOL = 1)

Note: Numbers shown reference Ta bl e 4 3 .

Table 44. Nexus characteristics

No. Symbol C Parameter

Value

Unit

Min Typ Max

TCYC CC D TCK cycle time 64 — — ns

MCYC CC D MCKO cycle time 32 — — ns

MDOV CC D MCKO low to MDO data valid — — 8 ns

MSEOV CC D MCKO low to MSEO_b data valid — — 8 ns

EVTOV CC D MCKO low to EVTO data valid — — 8 ns

10 tNTDIS CC D TDI data setup time 15 — — ns

tNTMSS CC D TMS data setup time 15 — — ns

11 tNTDIH CC D TDI data hold time 5 — — ns

tNTMSH CC D TMS data hold time 5 — — ns

12 tTDOV CC D TCK low to TDO data valid 35 — — ns

13 tTDOI CC D TCK low to TDO data invalid 6 — — ns

SPC560Bx, SPC560Cx Electrical characteristics

Doc ID 14619 Rev 7 95/113

Figure 29. Nexus TDI, TMS, TDO timing

4.19.4 JTAG characteristics

TCK

TMS, TDI

TDO

Note: Numbers shown reference Ta b l e 4 4 .

Table 45. JTAG characteristics

No. Symbol C Parameter

Value

Unit

Min Typ Max

JCYC CC D TCK cycle time 64 — — ns

TDIS CC D TDI setup time 15 — — ns

TDIH CC D TDI hold time 5 — — ns

TMSS CC D TMS setup time 15 — — ns

TMSH CC D TMS hold time 5 — — ns

TDOV CC D TCK low to TDO valid — — 33 ns

TDOI CC D TCK low to TDO invalid 6 — — ns

Electrical characteristics SPC560Bx, SPC560Cx

96/113 Doc ID 14619 Rev 7

Figure 30. Timing diagram – JTAG boundary scan

INPUT DATA VALID

OUTPUT DATA VALID

DATA INPUTS

DATA OUTPUTS

TCK

Note: Numbers shown reference Ta bl e 4 5 .

3/5

2/4

SPC560Bx, SPC560Cx Package characteristics

Doc ID 14619 Rev 7 97/113

5 Package characteristics

5.1 ECOPACK®

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

5.2 Package mechanical data

5.2.1 LQFP64

Figure 31. LQFP64 package mechanical drawing

5W_ME

A1 K

ccc C

E3 E1 E

Pin 1

identification 16

Table 46. LQFP64 mechanical data

Symbol

mm inches(1)

Min Typ Max Min Typ Max

A — — 1.6 — — 0.063

A1 0.05 — 0.15 0.002 — 0.0059

A2 1.35 1.4 1.45 0.0531 0.0551 0.0571

b 0.17 0.22 0.27 0.0067 0.0087 0.0106

c 0.09 — 0.2 0.0035 — 0.0079

Package characteristics SPC560Bx, SPC560Cx

98/113 Doc ID 14619 Rev 7

D 11.8 12 12.2 0.4646 0.4724 0.4803

D1 9.8 10 10.2 0.3858 0.3937 0.4016

D3 — 7.5 — — 0.2953 —

E 11.8 12 12.2 0.4646 0.4724 0.4803

E1 9.8 10 10.2 0.3858 0.3937 0.4016

E3 — 7.5 — — 0.2953 —

e — 0.5 — — 0.0197 —

L 0.45 0.6 0.75 0.0177 0.0236 0.0295

L1 — 1 — — 0.0394 —

k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°

ccc — — 0.08 — — 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 46. LQFP64 mechanical data (continued)

Symbol

mm inches(1)

Min Typ Max Min Typ Max

SPC560Bx, SPC560Cx Package characteristics

Doc ID 14619 Rev 7 99/113

5.2.2 LQFP100

Figure 32. LQFP100 package mechanical drawing

Table 47. LQFP100 mechanical data

Symbol

mm inches(1)

Min Typ Max Min Typ Max

A — — 1.600 — — 0.0630

A1 0.050 — 0.150 0.0020 — 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 — 0.200 0.0035 — 0.0079

D 15.800 16.000 16.200 0.6220 0.6299 0.6378

D1 13.800 14.000 14.200 0.5433 0.5512 0.5591

D3 — 12.000 — — 0.4724 —

E 15.800 16.000 16.200 0.6220 0.6299 0.6378

Package characteristics SPC560Bx, SPC560Cx

100/113 Doc ID 14619 Rev 7

5.2.3 LQFP144

Figure 33. LQFP144 package mechanical drawing

E1 13.800 14.000 14.200 0.5433 0.5512 0.5591

E3 — 12.000 — — 0.4724 —

e — 0.500 — — 0.0197 —

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 — 1.000 — — 0.0394 —

k 0.0 ° 3.5 ° 7.0 ° 0.0 ° 3.5 ° 7.0 °

Tolerance mm inches

ccc 0.080 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 47. LQFP100 mechanical data (continued)

Symbol

mm inches(1)

Min Typ Max Min Typ Max

SPC560Bx, SPC560Cx Package characteristics

Doc ID 14619 Rev 7 101/113

Table 48. LQFP144 mechanical data

Symbol

mm inches(1)

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Min Typ Max Min Typ Max

A — — 1.600 — — 0.0630

A1 0.050 — 0.150 0.0020 — 0.0059

A2 1.350 1.400 1.450 0.0531 0.0551 0.0571

b 0.170 0.220 0.270 0.0067 0.0087 0.0106

c 0.090 — 0.200 0.0035 — 0.0079

D 21.800 22.000 22.200 0.8583 0.8661 0.8740

D1 19.800 20.000 20.200 0.7795 0.7874 0.7953

D3 — 17.500 — — 0.6890 —

E 21.800 22.000 22.200 0.8583 0.8661 0.8740

E1 19.800 20.000 20.200 0.7795 0.7874 0.7953

E3 — 17.500 — — 0.6890 —

e — 0.500 — — 0.0197 —

L 0.450 0.600 0.750 0.0177 0.0236 0.0295

L1 — 1.000 — — 0.0394 —

k 0.0 ° 3.5 ° 7.0° 3.5 ° 0.0 ° 7.0 °

Tolerance mm inches

ccc 0.080 0.0031

Package characteristics SPC560Bx, SPC560Cx

102/113 Doc ID 14619 Rev 7

5.2.4 LBGA208

Figure 34. LBGA208 package mechanical drawing

1. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized

markings, or other feature of package body or integral heatslug.

A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1

corner. Exact shape of each corner is optional.

Table 49. LBGA208 mechanical data

Symbol

mm inches(1)

Notes

Min Typ Max Min Typ Max

A — — 1.70 — — 0.0669 (2)

A1 0.30 — — 0.0118 — — —

A2 — 1.085 — — 0.0427 — —

A3 — 0.30 — — 0.0118 — —

A4 — — 0.80 — — 0.0315 —

b 0.50 0.60 0.70 0.0197 0.0236 0.0276 (3)

1 3 5 7 9 111315

2 4 6 8 10 12 14 16

A1 corner index area

(See note 1)

Bottom view

b (208 balls)

eee

fff

CAB

Seating

plane

ddd

SPC560Bx, SPC560Cx Package characteristics

Doc ID 14619 Rev 7 103/113

D 16.80 17.00 17.20 0.6614 0.6693 0.6772 —

D1 — 15.00 — — 0.5906 — —

E 16.80 17.00 17.20 0.6614 0.6693 0.6772 —

E1 — 15.00 — — 0.5906 — —

e — 1.00 — — 0.0394 — —

F — 1.00 — — 0.0394 — —

ddd — — 0.20 — — 0.0079 —

eee — — 0.25 — — 0.0098 (4)

fff — — 0.10 — — 0.0039 (5)

1. Values in inches are converted from mm and rounded to four decimal digits.

2. LBGA stands for Low profile Ball Grid Array.

— Low profile: The total profile height (Dim A) is measured from the seating plane to the top of the

component

— The maximum total package height is calculated by the following methodology:

A2 Typ+A1 Typ + (A12+A32+A42 tolerance values)

— Low profile: 1.20 mm < A < 1.70 mm

3. The typical ball diameter before mounting is 0.60 mm.

4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.

For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true

position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball

must lie within this tolerance zone.

5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.

For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position

as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.

Each tolerance zone in the array is contained entirely in the respective zone eee above.

The axis of each ball must lie simultaneously in both tolerance zones.

Table 49. LBGA208 mechanical data (continued)

Symbol

mm inches(1)

Notes

Min Typ Max Min Typ Max

Ordering information SPC560Bx, SPC560Cx

104/113 Doc ID 14619 Rev 7

6 Ordering information

Table 50. Order codes

Order code CPU

Code Flash /

SRAM

(Kbytes)

Package Operating

temp. (°C)

Max

speed

(MHz)

Data

Flash Voltage Packing

SPC560B40L1C4E0X e200z0h 256 / 24 LQFP64 -40 to +125 48 4 x 16KB 3.3/5V Tape&Reel

SPC560B40L3B4E0X e200z0h 256 / 24 LQFP100 -40 to +105 48 4 x 16KB 3.3/5V Tape&Reel

SPC560B40L3C4E0X e200z0h -40 to +125

SPC560B40L3B6E0X e200z0h 256 / 24 LQFP100 -40 to +105 64 4 x 16KB 3.3/5V Tape&Reel

SPC560B40L3C6E0X e200z0h -40 to +125

SPC560B40L5B6E0X e200z0h 256 / 24 LQFP144 -40 to +105 64 4 x 16KB 3.3/5V Tape&Reel

SPC560B40L5C6E0X e200z0h -40 to +125

SPC560B44L3B4E0X e200z0h 384 / 28 LQFP100 -40 to +105 48 4 x 16KB 3.3/5V Tape&Reel

SPC560B44L3C4E0X e200z0h -40 to +125

SPC560B44L3B6E0X e200z0h 384 / 28 LQFP100 -40 to +105 64 4 x 16KB 3.3/5V Tape&Reel

SPC560B44L3C6E0X e200z0h -40 to +125

SPC560B44L5B6E0X e200z0h 384 / 28 LQFP144 -40 to +105 64 4 x 16KB 3.3/5V Tape&Reel

SPC560B44L5C6E0X e200z0h -40 to +125

SPC560B50L1C6E0X e200z0h 512 / 32 LQFP64 -40 to +125 64 4 x 16KB 3.3/5V Tape&Reel

SPC560B50L1C6E0Y e200z0h 512 / 32 LQFP64 -40 to +125 64 4 x 16KB 3.3/5V Tray

SPC560B50L3B4E0X e200z0h 512 / 32 LQFP100 -40 to +105 48 4 x 16KB 3.3/5V Tape&Reel

SPC560B50L3C4E0X e200z0h -40 to +125

SPC560B50L3B6E0X e200z0h 512 / 32 LQFP100 -40 to +105 64 4 x 16KB 3.3/5V Tape&Reel

SPC560B50L3C6E0X e200z0h -40 to +125 Tape&Reel

SPC560B50L3C6E0Y e200z0h 512 / 32 LQFP100 -40 to +125 64 4 x 16KB 3.3/5V Tray

SPC560B50L5B6E0X e200z0h 512 / 32 LQFP144 -40 to +105 64 4 x 16KB 3.3/5V Tape&Reel

SPC560B50L5C6E0X e200z0h -40 to +125

SPC560B50L5C6E0Y e200z0h 512 / 32 LQFP144 -40 to +125 64 4 x 16KB 3.3/5V Tray

SPC560C40L1C6E0X e200z0h 256 / 32 LQFP64 -40 to +125 64 4 x 16KB 3.3/5V Tape&Reel

SPC560C40L3C6E0X e200z0h 256 / 32 LQFP100 -40 to +125 64 4 x 16KB 3.3/5V Tape&Reel

SPC560C44L3C6E0X e200z0h 384 / 40 LQFP100 -40 to +125 64 4 x 16KB 3.3/5V Tape&Reel

SPC560C50L1C6E0X e200z0h 512 / 48 LQFP64 -40 to +125 64 4 x 16KB 3.3/5V Tape&Reel

SPC560C50L3C6E0X e200z0h 512 / 48 LQFP100 -40 to +125 64 4 x 16KB 3.3/5V Tape&Reel

SPC560Bx, SPC560Cx Ordering information

Doc ID 14619 Rev 7 105/113

Figure 35. Commercial product code structure

Table 51. Order Codes for Engineering Samples(1)

Order code CPU

Code Flash /

SRAM

(Kbytes)

Package Operating

temp. (°C)

Max

speed

(MHz)

Data

Flash Voltage Packing

SPC560B50L1-ENG e200z0h 512 / 48 LQFP64 -40 to +125 64 4 x 16KB 3.3/5V Tray

SPC560B50L3-ENG e200z0h 512 / 48 LQFP100 -40 to +125 64 4 x 16KB 3.3/5V Tray

SPC560B50L5-ENG e200z0h 512 / 48 LQFP144 -40 to +125 64 4 x 16KB 3.3/5V Tray

SPC560B50B2C6E0Y e200z0h 512 / 48 BGA208(2) -40 to +125 64 4 x 16KB 3.3/5V Tray

1. Engineering samples are suitable only for evaluation and developement purpose but NOT for qualification and production.

Their silicon version and maturity may vary until the product has reached qualification.

2. LBGA208 available only as development package for Nexus2+

Memory ConditioningCore Family

Y = Tray

X = Tape and Reel 90°

4E0 = 48 MHz EEPROM 5V/3V

6E0 = 64 MHz EEPROM 5V/3V

B = -40 to 105°C

C = -40 to 125°C

L1 = LQFP64

L3 = LQFP100

L5 = LQFP144

B2 = LBGA208

50 = 512 KB

44 = 384 KB

40 = 256 KB

B=Body

C = Gateway

0 = e200z0

SPC56 = Power Architecture in

90nm

TemperaturePackage Custom vers.

SPC56 50 Y0B CL3 5E0

Example code:

Product identifier

Abbreviations SPC560Bx, SPC560Cx

106/113 Doc ID 14619 Rev 7

Appendix A Abbreviations

Ta bl e 5 2 lists abbreviations used but not defined elsewhere in this document.

Table 52. Abbreviations

Abbreviation Meaning

CMOS Complementary metal–oxide–semiconductor

CPHA Clock phase

CPOL Clock polarity

CS Peripheral chip select

EVTO Event out

MCKO Message clock out

MDO Message data out

MSEO Message start/end out

MTFE Modified timing format enable

SCK Serial communications clock

SOUT Serial data out

TBD To be defined

TCK Test clock input

TDI Test data input

TDO Test data output

TMS Test mode select

SPC560Bx, SPC560Cx Revision history

Doc ID 14619 Rev 7 107/113

Revision history

Table 53. Document revision history

Date Revision Changes

04-Apr-2008 1 Initial release.

06-Mar-2009 2

Made minor editing and formatting changes to improve readability

Harmonized oscillator naming throughout document

Modified document title

Updated “Feature” on cover page

Replaced LFBGA208 with LBGA208

Updated “Description” Section

Updated “SPC560Bx and SPC560Cx device comparison” table

Added “Block diagram” section

Section 3 “Package pinouts and signal descriptions”:

– Removed signal descriptions (these are found in the device reference manual)

Updated “LQFP 144-pin configuration (top view)” figure:

– Replaced VPP with VSS_HV on pin 18

– Added MA[1] as AF3 for PC[10] (pin 28)

– Added MA[0] as AF2 for PC[3] (pin 116)

– Changed description for pin 120 to PH[10] / GPIO[122] / TMS

– Changed description for pin 127 to PH[9] / GPIO[121] / TCK

– Replaced NMI[0] with NMI on pin 11

Updated “LQFP 100-pin configuration (top view)” figure:

– Replaced VPP with VSS_HV on pin 14

– Added MA[1] as AF3 for PC[10] (pin 22)

– Added MA[0] as AF2 for PC[3] (pin 77)

– Changed description for pin 81 to PH[10] / GPIO[122] / TMS

– Changed description for pin 88 to PH[9] / GPIO[121] / TCK

– Removed E1UC[19] from pin 76

– Replaced [11] with WKUP[11] for PB[3] (pin 1)

– Replaced NMI[0] with NMI on pin 7

Updated “LBGA208 configuration” figure:

– Changed description for ball B8 from TCK to PH[9]

– Changed description for ball B9 from TMS to PH[10]

– Updated descriptions for balls R9 and T9

Added “Parameter classification” section and tagged parameters in tables where

appropriate

Added “NVUSRO register” section

Updated “Absolute maximum ratings” table

“Recommended operating conditions” section :

– Added note on RAM data retention to end of section

Updated “Recommended operating conditions (3.3 V)” and “Recommended operating

conditions (5.0 V)”

Added “Package thermal characteristics” section

Updated “Power considerations” section

Updated I/O input DC electrical characteristics definition” figure

Revision history SPC560Bx, SPC560Cx

108/113 Doc ID 14619 Rev 7

06-Mar-2009 2

(continued)

Updated tables:

– “I/O input DC electrical characteristics”

– “I/O pull-up/pull-down DC electrical characteristics”

– “SLOW configuration output buffer electrical characteristics”

– “MEDIUM configuration output buffer electrical characteristics”

– “FAST configuration output buffer electrical characteristics”

Added “Output pin transition times” section

Updated “I/O consumption” table

Updated “Start-up reset requirements” figure

Updated “Reset electrical characteristics” table

“Voltage regulator electrical characteristics” section:

– Amended description of LV_PLL

“Voltage regulator capacitance connection” figure:

– Exchanged position of symbols CDEC1 and CDEC2

Updated tables”

– “Voltage regulator electrical characteristics”

– “Low voltage monitor electrical characteristics”

– “Low voltage power domain electrical characteristics”

Added “Low voltage monitor vs reset” figure

Updated “Flash memory electrical characteristics” section

Added “Electromagnetic compatibility (EMC) characteristics” section

Updated “Fast external crystal oscillator (4 to 16 MHz) electrical characteristics”

section

Updated “Slow external crystal oscillator (32 kHz) electrical characteristics” section

Updated tables:

– “FMPLL electrical characteristics”

– “Fast internal RC oscillator (16 MHz) electrical characteristics”

– “Slow internal RC oscillator (128 kHz) electrical characteristics”

Added “On-chip peripherals” section

Added “ADC input leakage current” table

Updated “ADC conversion characteristics” table

Updated “ECOPACK®” section

Corrected inverted column headings for typical and minimum dimensions in “LQFP64

mechanical data” and “LQFP100 mechanical data” tables

Added “Abbrevation” appendix

03-Jun-2009 3 Corrected “Commercial product code structure” figure

Table 53. Document revision history (continued)

Date Revision Changes

SPC560Bx, SPC560Cx Revision history

Doc ID 14619 Rev 7 109/113

06-Aug-2009 4

Updated “LBGA208 configuration” figure

“Absolute maximum ratings” table:

–V

DD_ADC, VIN: changed min value for “relative to VDD” condition

–I

CORELV: added new row

“Recommended operating conditions (5.0 V)” table:

–T

A C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part,

TJ M-Grade Part: added new rows

– Changed capacitance value in footnote

“Output pin transition times” table:

– MEDIUM configuration: added condition for PAD3V5V = 0

Updated “Voltage regulator capacitance connection”

“Voltage regulator electrical characteristics” table:

–C

DEC1: changed min value

–I

MREG: changed max value

–I

DD_BV: added max value footnote

“Low voltage monitor electrical characteristics” table:

–V

LVDH V3H , VLVDHV5H: changed max value

–V

LVDH V3L , VLVD HV 5L : added max value

Updated “Low voltage power domain electrical characteristics” table

“Flash module life” table:

– Retention: deleted min value footnote for “Blocks with 100000 P/E cycles“

“Fast external crystal oscillator (4 to 16 MHz) electrical characteristics” table:

–I

FXOSC: added typ value

“Slow external crystal oscillator (32 kHz) electrical characteristics” table

–V

SXOSC: changed typ value

–T

SXOSCSU: added max value footnote

“FMPLL electrical characteristics” table

–tLTJIT: added max value

Updated “LQFP100 package mechanical drawing”

Table 53. Document revision history (continued)

Date Revision Changes

Revision history SPC560Bx, SPC560Cx

110/113 Doc ID 14619 Rev 7

20-Jan-2010 5

Table: “Absolute maximum ratings”

–V

DD_BV

, VDD_ADC, VIN: changed max value

Table: ”Recommended operating conditions (3.3 V)”

–TV

DD: deleted min value

Table: “Reset electrical characteristics“

– Changed footnotes 2 and 5

Table: “Voltage regulator electrical characteristics“

–C

REGn: changed max value

–C

DEC1: split into 2 rows

– Updated voltage values in footnote 3

Table: “Low voltage monitor electrical characteristics“

– Updated column Conditions

–V

LVDLV C OR L, VLVDLVBKPL: changed min/max value

Table: “Program and erase specifications“

–T

dwprogram: added initial max value

Table: “Flash module life“

– Retention: changed min value for blocks with 100K P/E cycles

Table: “Flash power supply DC electrical characteristics“

–I

FREAD, IFMOD: added typ value

– Added a footnote

Added Section: “ NVUSRO[WATCHDOG_EN] field description“

Section 4.18: “ADC electrical characteristics“ has been moved up in hierarchy (it was

Section 4.18.5).

Table: “ ADC conversion characteristics“

–R

AD: changed initial max value

Table: “On-chip peripherals current consumption“

– Removed min/max from the heading

– Changed unit of measurement and consequently rounded the values

15-Mar-2010 6 Internal release.

Table 53. Document revision history (continued)

Date Revision Changes

SPC560Bx, SPC560Cx Revision history

Doc ID 14619 Rev 7 111/113

22-Jul-2010 7

Changes between revisions 5 and 7

Added LQFP64 package information

Updated the “Features“ section.

Section “Introduction”

– Relocated a note

Table: “SPC560Bx and SPC560Cx device comparison“

– Added footnote regarding SCI and CAN

Added eDMA block in the “SPC560Bx and SPC560Cx series block diagram” figure

Removed alternate function information from “LQFP 100-pin configuration” and “LQFP

100-pin configuration” figures.

Added “Functional port pin descriptions” table

Deleted the “NVUSRO[WATCHDOG_EN] field description“ section

Table: “Absolute maximum ratings“

– Removed the min value of VIN relative tio VDD

Table ”Recommended operating conditions (3.3 V)”

–TV

DD: made single row

”Recommended operating conditions (5.0 V)”

– deleted TA C-Grade Part, TJ C-Grade Part, TA V-Grade Part, TJ V-Grade Part, TA M-Grade Part, TJ

M-Grade Part rows

Table: “LQFP thermal characteristics”

– Added more rows

– Rounded the values

Removed table “LBGA208 thermal characteristics”

Table “I/O input DC electrical characteristics”

–W

FI: insered a footnote

–W

NFI: insered a footnote

Table “I/O consuption“

–Removed I

DYNSEG row

– Added “I/O weight “ table

Replaced “nRSTIN” with “RESET” in the “RESET electrical characteristics” section.

Table “Voltage regulator electrical characteristics“

– Updated the values

–Removed I

VREGREF and IVREDLVD12

– Added a note about IDD_BC

Table: “Low voltage monitor electrical characteristics“

– changed min valueVLVDH V3 L, from 2.7 to 2.6

– Inserted max value of VLV DLVC ORL

– Updated VPORH values

– Updated VLVDLV COR L value

Table “Low voltage power domain electrical characteristics“

– Entirely updated

Table “Program and erase specifications“

– Inserted Teslat row

Table “Flash power supply DC electrical characteristics“

– Entirely updated

Table 53. Document revision history (continued)

Date Revision Changes

Revision history SPC560Bx, SPC560Cx

112/113 Doc ID 14619 Rev 7

22-Jul-2010 7

(continued)

Table “Start-up time/Switch-off time“

– Entirely updated

Figures “Crystal oscillator and resonator connection scheme“

– Relocated a note

Table ”Slow external crystal oscillator (32 kHz) electrical characteristics”

–Removed g

mSXOSC row

– Inserted values of ISXOSCBIAS

Table ”FMPLL electrical characteristics”

– Rounded the values of fVCO

Table “Fast internal RC oscillator (16 MHz) electrical characteristics“

– Entirely updated.

Table “ADC conversion characteristics”

– Updated the description of the conditions of tADC_PU and tADC_S.

– Added “IADCPWD” and “IADCRUN” rows

Table “DSPI characteristics“

– Entirely updated.

Updated “Order codes” table.

Figure “Commercial product code structure”

– Replaced PowerPC with “Power Architecture™“ in the product identifier

– Removed the note about the condition from “Flash read access timing“ table

– Removed the notes that assert the values need to be confirmed before validation

– Exchanged the order of “LQFP 100-pin configuration” and “LQFP 144-pin

configuration”

– Exchanged the order of “LQFP 100-pin package mechanical drawing” and “LQFP

144-pin package mechanical drawing”

Table 53. Document revision history (continued)

Date Revision Changes

SPC560Bx, SPC560Cx

Doc ID 14619 Rev 7 113/113

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

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