Cover 88PG8237, 88PG8227, 88PG8226, 88PG8216, 88PG8204 Field Programmable DSP SwitcherTM Family 1MHz, Dual Step-down Regulator with AnyVoltageTM Technology Datasheet Doc. No. MV-S103563-00, Rev. C April 23, 2008 Marvell. Moving Forward Faster Document Classification: Proprietary Information 88PG82XX Datasheet Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: 2.00 Technical Publication: 0.xx For more information, visit our website at: www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these types of equipment or applications. With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees: 1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2; 2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are controlled for national security reasons by the EAR; and, 3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant, not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons by the EAR, or is subject to controls under the U.S. Munitions List ("USML"). At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright (c) 2008. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas, Link Street, NetGX, PHYAdvantage, Prestera, Raising The Technology Bar, The Technology Within, Virtual Cable Tester, and Yukon are registered trademarks of Marvell. Ants, AnyVoltage, Discovery, DSP Switcher, Feroceon, GalNet, GalTis, Horizon, Marvell Makes It All Possible, RADLAN, UniMAC, and VCT are trademarks of Marvell. All other trademarks are the property of their respective owners. Doc. No. MV-S103563-00 Rev. C Page 2 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 88PG82XX Field Programmable DSP SwitcherTM Family Datasheet PRODUCT OVERVIEW The 88PG82XX family integrates the dual synchronous Step-Down (Buck) switching regulators housed in a 3 X 4mm QFN-20 package. Internally self-compensated, the step-down regulator requires no external compensation and works with low-ESR output capacitors to simplify the design, minimize the board space, and reduce the amount of external components. The switching frequency for the step-down regulator is 1MHz, allowing the use of low profile surface mount inductors and low value capacitors. Each step-down regulator includes programmable output voltage to allow the user to easily set the output voltage with external resistors, logic control, or serial data interface. The output voltage range is 0.72V to 3.63V. The 88PG82XX family operates from an input voltage range of 2.75V to 5.5V, making the device well suited for portable applications. Other key features of the 88PG82XX family include soft start, an internal current limit, an under-voltage lockout, thermal shutdown, over voltage protection, and power-on-reset signals. Applications Features Dual switching regulators 1MHz switching frequency Low quiescent current of 2.1 mA (typ.) Stable with low-ESR ceramic output capacitors No external compensation required Up to 95% efficiency Input voltage range: 2.75V to 5.5V Programmable output voltage range: 0.72V to 3.63V Serial / Logic Programmability Any VoltageTM Technology provides 64 output voltage selections to provide up most flexibility Built-in undervoltage lockout Over voltage protection Thermal shutdown protection Output short circuit protection Output voltage margining capability Lead-free packages Portable and handheld computing Point-of-load power supplies DSP power supplies Disk drive power supplies Tiny 3 X 4 mm QFN-20 package Figure 1: Typical Application Circuit: Output 1.8V/1.5A and 1.2V/1.5A R1 10 ohm 3 17 SVIN PVIN2 C1 0.1uF R4 100k R3 100k R2 100k 4 11 16 POR 1 POR 2 6 SDI 1 EN 13 12 14 15 R7 160k R8 0 R5 51k SGND 10 PVIN1 SW1 SW1 POR1 POR2 88PG8226 SFB1 SDI PGND1 EN SW2 VSET1 SW2 SFB2 PSET2 PGND2 C5 22uF/6.3V 22uF/6.3V 7 L1 9 3.3uH Vout1 2.5V/1.5A 22uF/6.3V 8 18 L2 20 3.3uH C4 Vout2 1.5V/1.5A 2 22uF/6.3V 19 R6 0 Copyright (c) 2008 Marvell April 23, 2008, 2.00 C3 5 PSET1 VSET2 Vin 2.75V - 5.5V C2 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 3 88PG82XX Datasheet Caution: This is a very high frequency device, proper PCB layout is required. Refer to page 47 for further details. : Table 1: DC Loading Current Ratings Buck 2 Buck 1 0 .7 5 A 1 .0 A 1 .5 A 2 .0 A 0.75A 1 88PG8204 88PG8214 1.0A 1 .5 A 88PG8205 88PG8206 2 .0 A 88PG8207 1 88PG8217 88PG8215 88PG8216 88PG8224 88PG8225 88PG82261 88PG82271 88PG8234 88PG8235 88PG8236 88PG82371 1. The part numbers in Bold are released to production. The other parts are available upon request. Contact Marvell(R) marketing for availability. The devices shown in Table 1 have the same input and output voltage range for step-down registers. Doc. No. MV-S103563-00 Rev. C Page 4 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Table of Contents Table of Contents Product Overview ....................................................................................................................................... 3 Table of Contents ....................................................................................................................................... 5 List of Tables .............................................................................................................................................. 7 List of Figures............................................................................................................................................. 9 1 Signal Description ....................................................................................................................... 11 1.1 Pin Configuration.............................................................................................................................................11 1.2 Pin Description ................................................................................................................................................12 1.2.1 Pin Types ..........................................................................................................................................12 2 Electrical Specifications ............................................................................................................. 15 2.1 Absolute Maximum Ratings ............................................................................................................................15 2.2 Recommended Operating Conditions .............................................................................................................15 2.3 Electrical Characteristics .................................................................................................................................16 2.4 Switching Step-down Regulator ......................................................................................................................17 3 Functional Description................................................................................................................ 19 3.1 Regulation and Start-up ..................................................................................................................................19 3.1.1 Soft Start and Sequencing ................................................................................................................20 3.2 Output Voltage Settings ..................................................................................................................................22 3.2.1 Logic Programmability ......................................................................................................................22 3.2.2 Serial Programmability......................................................................................................................23 3.2.3 Output Voltage - AnyVoltageTM Technology ....................................................................................25 3.3 Undervoltage Lockout (UVLO) ........................................................................................................................28 3.4 Over Voltage Protection (OVP) .......................................................................................................................28 3.5 Power-On Reset (POR) ..................................................................................................................................28 3.6 Thermal Shutdown ..........................................................................................................................................29 3.7 Adaptive Transient Response .........................................................................................................................29 4 Functional Characteristics ......................................................................................................... 31 4.1 Start-Up Waveforms........................................................................................................................................31 4.2 Short-Circuit Waveforms .................................................................................................................................32 4.3 Switching Waveforms......................................................................................................................................33 4.4 Load Transient Waveforms .............................................................................................................................34 4.4.1 Step-Down Regulator .......................................................................................................................34 4.4.2 Cross-Talk Waveforms .....................................................................................................................36 4.5 Output Voltage Transient Waveforms .............................................................................................................37 4.5.1 Step-Down Regulator .......................................................................................................................37 Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 5 88PG82XX Datasheet 4.6 Line Transient Waveforms ..............................................................................................................................38 5 Typical Characteristics ............................................................................................................... 39 5.1 Efficiency Graphs ............................................................................................................................................39 5.1.1 Efficiency Graphs in Log Scale .........................................................................................................39 5.2 Load Regulation ..............................................................................................................................................40 5.3 Dropout Voltage ..............................................................................................................................................40 5.4 RDS (ON) Resistance .....................................................................................................................................40 5.5 IC Case and Inductor Temperature.................................................................................................................41 5.6 Input Voltage Graphs ......................................................................................................................................43 5.6.1 Step-Down Regulator .......................................................................................................................44 5.7 Temperature Graphs .......................................................................................................................................45 5.7.1 Step-Down regulator .........................................................................................................................46 6 Applications Information ............................................................................................................ 47 6.1 PC Board Layout Considerations and Guidelines ...........................................................................................47 6.1.1 PC Board Layout Examples for 88PG82XX .....................................................................................50 6.1.2 Bill of Materials (BOM) ......................................................................................................................52 7 Mechanical Drawing .................................................................................................................... 55 7.1 88PG82XX Mechanical Drawing .....................................................................................................................55 7.2 Dimensions .....................................................................................................................................................56 7.3 Typical Pad Layout Dimensions ......................................................................................................................57 7.3.1 Recommeded Solder Pad Layout .....................................................................................................57 8 Ordering Information................................................................................................................... 59 8.1 Ordering Part Numbers and Package Markings..............................................................................................59 8.2 Sample Ordering Part Number........................................................................................................................59 8.3 Package Marking ............................................................................................................................................60 8.3.1 88PG82XX Package Marking and Pin 1 Locations ..........................................................................60 Doc. No. MV-S103563-00 Rev. C Page 6 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 List of Tables List of Tables Table 1: 1 2 3 DC Loading Current Ratings...............................................................................................................4 Signal Description ............................................................................................................................ 11 Table 2: Pin Type Definitions ..........................................................................................................................12 Table 3: Pin Descriptions ................................................................................................................................12 Electrical Specifications .................................................................................................................. 15 Table 4: Absolute Maximum Ratings ..............................................................................................................15 Table 5: Recommended Operating Conditions...............................................................................................15 Table 6: Electrical Characteristics Table ........................................................................................................16 Table 7: Switching Step-down Regulator Table..............................................................................................17 Functional Description..................................................................................................................... 19 Table 8: Logic Programmability Table ............................................................................................................22 Table 9: Default Value of Data Field ...............................................................................................................24 Table 10: Voltage and Percentage Set .............................................................................................................24 Table 11: Output Voltage Selection ..................................................................................................................24 Table 12: AnyVoltageTM Programming Table for 1% Resistors ........................................................................25 Table 13: AnyVoltageTM Programming Table for 5% Resistors ........................................................................26 Table 14: Output Voltage Option Steps ............................................................................................................27 4 Functional Characteristics............................................................................................................... 31 5 Typical Characteristics .................................................................................................................... 39 6 Applications Information ................................................................................................................. 47 7 Table 15: BOM for 88PG82XX .........................................................................................................................52 Table 16: Ceramic Capacitor Cross Reference ................................................................................................54 Mechanical Drawing ......................................................................................................................... 55 Table 17: 8 Ordering Information........................................................................................................................ 59 Table 18: A Package Dimensions ........................................................................................................................56 88PG82XX Ordering Part Numbers..................................................................................................59 Revision History ............................................................................................................................... 61 Table 19: Revision History ................................................................................................................................61 Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 7 88PG82XX Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103563-00 Rev. C Page 8 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 List of Figures List of Figures Figure 1: 1 Typical Application Circuit: Output 1.8V/1.5A and 1.2V/1.5A .............................................................3 Signal Description ........................................................................................................................... 11 Figure 2: 88PG82XX Family 3X4mm QFN-20 Package--Top View................................................................11 2 Electrical Specifications ................................................................................................................. 15 3 Functional Description.................................................................................................................... 19 4 Figure 3: 88PG82XX Block Diagram ...............................................................................................................19 Figure 4: Output Voltage Window ....................................................................................................................20 Figure 5: Startup without Sequencing ..............................................................................................................20 Figure 6: Startup with Sequencing and Soft Start (COUT= 22 F) ...................................................................20 Figure 7: Fast Startup (0.8V, 1.2V, 1.8V, 2.5V, 3.3V) Figure 8: Soft Start up (0.8V, 1.2V, 1.8V, 2.5V, 3.3V) .....................................................................................21 .................................................................................21 Figure 9: Inrush Current with COUT = 100 F ..................................................................................................21 Figure 10: Serial Programmability......................................................................................................................23 Figure 11: Startup Sequence ............................................................................................................................27 Figure 12: VSET = 2.5V and PSET = -5% .........................................................................................................27 Figure 13: UVLO and OVP Waveforms .............................................................................................................28 Figure 14: Power-On Reset Waveforms ............................................................................................................28 Figure 15: Adaptive Transient Response ..........................................................................................................29 Functional Characteristics.............................................................................................................. 31 Figure 16: Startup Using the Enable Pin ...........................................................................................................31 Figure 17: Turn Off Using the Enable Pin ..........................................................................................................31 Figure 18: Startup Sequence ............................................................................................................................31 Figure 19: Hot Plug ............................................................................................................................................31 Figure 20: UVLO and OVP Thresholds..............................................................................................................32 Figure 21: Input Soft Start and Start up Sequence ............................................................................................32 Figure 22: Step-Down Short-Circuit Response .................................................................................................32 Figure 23: Switching Waveforms - PWM mode ................................................................................................33 Figure 24: Switching Waveforms - PWM mode .................................................................................................33 Figure 25: Switching Waveforms - DCM Mode .................................................................................................33 Figure 26: Switching Waveforms - DCM Mode-Zoom........................................................................................33 Figure 27: PWM Output Ripple Voltage ............................................................................................................34 Figure 28: Fast Load Rise Time ........................................................................................................................34 Figure 29: Slow Load Rise Time ........................................................................................................................34 Figure 30: Fast Load Fall Time .........................................................................................................................35 Figure 31: Slow Load Fall Time .........................................................................................................................35 Figure 32: Load Transient Response ................................................................................................................35 Figure 33: Double-Pulsed Load Response ........................................................................................................35 Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 9 88PG82XX Datasheet Figure 34: Load Transient Response ................................................................................................................36 Figure 35: Double-Pulsed Load Response ........................................................................................................36 Figure 36: Cross-talk Continuous Mode ...........................................................................................................36 Figure 37: Cross-talk Discontinuous Mode ........................................................................................................36 Figure 38: VOUT = 1.0V to 1.2V with No Load ...................................................................................................37 Figure 39: VOUT = 1.0V to 1.5V with No Load....................................................................................................37 Figure 40: VOUT = 1.0V to 1.2V with ILOAD = 1.5A.............................................................................................37 Figure 41: VOUT = 1.0V to 1.5V with ILOAD = 1.5A.............................................................................................37 Figure 42: VOUT = 1.2V to 1.0V with ILOAD = 1.5A.............................................................................................38 Figure 43: VOUT = 1.5V to 1.0V with ILOAD = 1.5A.............................................................................................38 Figure 44: Line Transient @ VIN = 3.6V.............................................................................................................38 Figure 45: Line Transient @ VIN = 4.5V.............................................................................................................38 5 Typical Characteristics ................................................................................................................... 39 6 Applications Information ................................................................................................................ 47 Figure 46: Simpified Schematic .........................................................................................................................48 Figure 47: PC Board Schematic ........................................................................................................................49 Figure 48: Top Silk-Screen, Top Traces, Vias, and Top Copper (Not to Scales) ..............................................50 Figure 49: Bottom Silk Screen, Bottom Trace, Vias, and Bottom Copper (Not to Scale)...................................51 7 Mechanical Drawing ........................................................................................................................ 55 8 Ordering Information....................................................................................................................... 59 A Figure 50: Sample Part Number ........................................................................................................................59 Figure 51: 88PG8227 Package Marking and Pin 1 Location .............................................................................60 Revision History ............................................................................................................................... 61 Doc. No. MV-S103563-00 Rev. C Page 10 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Signal Description Pin Configuration 1 Signal Description 1.1 Pin Configuration Figure 2: 88PG82XX Family 3X4mm QFN-20 Package--Top View SW2 PGND2 SW2 PVIN2 20 19 18 17 EN 1 16 POR 2 SFB2 2 15 PSET 2 SVIN 3 14 VSET 2 SGND 4 13 VSET 1 SFB1 5 12 PSET 1 SDI/ ENSEQ 6 11 POR1 7 8 9 10 SW1 PGND1 SW1 PVIN1 Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 11 88PG82XX Datasheet 1.2 Pin Description 1.2.1 Pin Types Table 2: Pin Type Definitions Pi n Typ e D e f in it io n I Input Only O Output Only S Supply NC Not Connected GND Ground Table 3 provides pin descriptions for the 88PG82XX. Table 3: Pin Descriptions Pi n # P in N a m e Pi n Typ e P i n D es c r ip t i o n 1 EN I Enable. Logic high (> 2.0V) enables both switching regulators. Logic low (<0.8V) disables the regulators. When disabled, the switch nodes SW1 and SW2 are Hi-Z. The feedback nodes SFB1 and SFB2 are pulled down by 20K resistors, and the power on reset nodes POR1 and POR2 are pulled down by internal open drain NFETs. The low signal has to be at least 20 s to disable both regulators. If this pin is left floating, an internal 10 A current source pulls this pin high to SVIN, enabling the regulator. 2 SFB2 I Switching Regulator Feedback. Senses the output voltage of the switching regulator 2. 3 SVIN S Signal Input Voltage. The input voltage is 2.75V to 5.5V for internal circuitry. Connect a 0.1 F decoupling capacitor between SVIN and SGND and position it as close as possible to the IC. 4 SGND GND Ground. Connect to a ground plane. 5 SFB1 I Switching Regulator Feedback. Senses the output voltage of the switching regulator 1. Doc. No. MV-S103563-00 Rev. C Page 12 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Signal Description Pin Description Table 3: Pin Descriptions Pi n # P in N a m e Pi n Typ e P i n D es c r ip t i o n 6 SDI/ENSEQ I Multi-purpose logic input. Logic high (> 2.0V) enables soft start and sequence. Buck 1 starts followed by Buck 2, once VOUT1 is within a specified tolerance. The soft start rise time is typically 5 ms and is dependent on output, but independent of capacitance and load current. If a short circuit is detected on Buck1, then Buck 2 will be disabled. Logic low (< 0.8V) disables the start up sequence. Buck 1 and Buck 2 will start up together without any soft start. Serial Data Input. The input data into this pin is used to program the output voltage (See "Output Voltage Settings" on page 22). The power-good signal has to be high before the serial data interface can be used. To implement soft start a 10K pull-up resistor must be connected to SVIN. This pin is internally pulled down by a 10 A current source. 7, 9 SW1 O Switch Node for regulator 1. Internal power MOSFET drain. Connects to an external inductor. 8 PGND1 GND Power Ground. The power ground must be connected to the negative terminal of the input and output capacitors. 10 PVIN1 S Power Input Voltage. Internal power MOSFET source. Connect the 10F decoupling capacitor between PVIN and PGND and position it as close as possible to the IC. NOTE: PVIN and PVIN2 must be connected together and should not be separated. 11 POR1 O Power-On Reset 1. This pin is an open drain output to indicate the status of the output voltage. The output pin goes high 40 ms after the output voltage is within the specified tolerance. POR2 and POR1 can be connected to the same external pull-up resistor to indicate "both outputs good". 12 PSET1 I Percent Set for Regulator 1. 1. Resistor Programming: Connect an external resistor to ground to set the output voltage of the switching regulator. See the "Electrical Characteristics" for resistor values and Output Voltage Settings. Use resistor values with a tolerance of 5% or better. The total capacitance across this pin and GND should be equal to 25 pF or less. If the pin is not used, it must be connected to GND. 2. Logic Programming: Four output voltage levels (1.8V, 2.5V, 3.0V, 3.3V) can be set by connecting the VSET and PSET pins to either GND or SVIN. 13 VSET1 I Voltage Set for Regulator 1. 1. Resistor Programming: Connect an external resistor to ground to set the output voltage of the switching regulator. See the "Electrical Characteristics" for resistor values and Output Voltage Settings. Use resistor values with a tolerance of 5% or better. The total capacitance across this pin and GND should be equal to 25 pF or less. 2. Logic Programming: Four output voltage levels (1.8V, 2.5V, 3.0V, 3.3V) can be set by connecting the VSET and PSET pins to either GND or SVIN. Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 13 88PG82XX Datasheet Table 3: Pin Descriptions Pi n # P in N a m e Pi n Typ e P i n D es c r ip t i o n 14 VSET2 I Voltage Set for Regulator 2. 1. Resistor Programming: Connect an external resistor to ground to set the output voltage of the switching regulator. See the "Electrical Characteristics" for resistor values and Output Voltage Settings. Use resistor values with a tolerance of 5% or better. The total capacitance across this pin and GND should be equal to 25 pF or less. 2. Logic Programming: Four output voltage levels (0.8V, 1.0V, 1.2V, and 1.5V) can be set by connecting the VSET and PSET pins to either GND or SVIN. 15 PSET2 I Percent Set for Regulator 2. 1. Resistor Programming: Connect an external resistor to ground to set the output voltage of the switching regulator. See the "Electrical Characteristics" for resistor values and Output Voltage Settings. Use resistor values with a tolerance of 5% or better. The total capacitance across this pin and GND should be equal to 25 pF or less. If the pin is not used, it must be connected to GND. 2. Logic Programming: Four output voltage levels (0.8V, 1.0V, 1.2V, and 1.5V) can be set by connecting the VSET and PSET pins to either GND or SVIN. 16 POR2 O Power-On Reset 2. This pin is an open drain output to indicate the status of the output voltage. The output pin goes high 40 ms after the output voltage is within the specified tolerance. POR2 and POR1 can be connected to the same external pull up resistor to indicate "both output good". 17 PVIN2 S Power Input Voltage for regulator 2: Internal power MOSFET source. Connect the 10 F decoupling capacitor between PVIN2 and PGND2 and position it as close as possible to the IC. NOTE: PVIN and PVIN2 must be connected together and should not be separated. 19 PGND2 GND Power Ground for regulator 2: The power ground must be connected to the negative terminal of the input and output capacitors. 18, 20 SW2 O Switch Node for regulator 2: Internal power MOSFET drain. Connects to an external inductor. Doc. No. MV-S103563-00 Rev. C Page 14 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Electrical Specifications Absolute Maximum Ratings 2 Electrical Specifications 2.1 Absolute Maximum Ratings Table 4: Absolute Maximum Ratings1 Parameter S y m bo l R a ng e U n i ts Signal Input Voltage SVIN -0.3 to 6.0 V Power Input Voltage PVIN1, PVIN2 -0.3 to 6.0 V VSW1, VSW2 -0.6 to (SVIN +0.3) V Switching Regulator Feedback Voltage VSFB1, VSFB2 -0.6 to (SVIN +0.3) V Voltage Set VVSET1, VVSET2 -0.6 to (SVIN +0.3) V Percentage Set Voltage VPSET1, VPSET2 -0.6 to (SVIN +0.3) V Enable VEN -0.6 to (SVIN +0.3) V POR Voltage VPOR -0.6 to (SVIN +0.3) V VSDI -0.6 to (SVIN +0.3) V TOP -40 to 85 C Maximum Junction Temperature TJMAX 125 C Storage Temperature Range TSTOR -65 to 150 C 2 kV Switch Voltage 2 SDI Voltage Operating Temperature Range ESD Rating 3 4 1. Exceeding the absolute maximum rating may damage the device 2. -10V to (VIN +0.3)V for less than 50s 3. Specifications over the -40C to 85C operating temperature ranges are assured by design, characterization and correction with statistical process controls 4. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF 2.2 Table 5: Recommended Operating Conditions Recommended Operating Conditions1 Parameter S y m bo l r a n ge U ni ts Single Input Voltage SVIN 2.75 to 5.5 V Power Input Voltage PVIN1, PVIN2 2.75 to 5.5 V JA 70 C/W JC 19 C/W Package Thermal Resistance2 1. This device is not gauranteed to function outside the specified operating range 2. Test on 4-layer (JESD51-7) and vias (JESD51-5) board Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 15 88PG82XX Datasheet 2.3 Electrical Characteristics The following applies unless otherwise noted: SVIN = PVIN1= PVIN2, VVSET1 = VPSET = 0, VOUT1 = 1.8V, VVSET2 = SVIN, VPSET2 = 0, VOUT2 = 1.2V, VEN = SVIN, L (BUCK1) = 2.2 H, COUT (BUCK1) = 22F (Ceramic), L (BUCK2) = 2.2 H, COUT (BUCK2) = 22 F (Ceramic), TA = 25 C. Bold values indicate -40 C < TA < 85 C. Table 6: Electrical Characteristics Table Parameter S y m b ol C o nd i ti on s Min Signal Input Voltage Range SVIN SVIN = PVIN Power Input Voltage Range PVIN Total Quiescent Current Ty p Max U n i ts 2.75 5.5 V 2.75 5.5 V No load 2.1 mA Shutdown Supply Current ISVIN VEN = 0V 1 50 A Undervoltage Lockout VUVLO High threshold, SVIN increasing 2.65 2.70 V Low threshold, SVIN decreasing Over-voltage Protection EN Threshold Voltage EN Pin Input Current Over-temperature Thermal Shutdown VOVP VEN IEN TOTS 2.44 High threshold, SVIN increasing 5.7 Low threshold, SVIN decreasing 5.6 Enable regulators V V 1.70 Disable regulators 0.7 VEN = 5.0V 1 VEN = 0V 10 TJ increasing (Disable regulators) 150 TJ decreasing (Enable regulators) 105 Doc. No. MV-S103563-00 Rev. C Page 16 2.55 20 V A C Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Electrical Specifications Switching Step-down Regulator 2.4 Switching Step-down Regulator The following applies unless otherwise noted: SVIN = PVIN1 = PVIN2, VVSET1 = VPSET = 0, VOUT1 = 1.8V, VVSET2 = SVIN, VPSET2 = 0, VOUT2 = 1.2V, VEN = SVIN, L (BUCK1) = 2.2 H, COUT (BUCK1) = 22 F (Ceramic), L (BUCK2) = 2.2 H, COUT (BUCK2) = 22 F (Ceramic), TA = 25 C. Bold values indicate -40 C < TA < 85 C. Table 7: Switching Step-down Regulator Table Parameter S y m b ol C o nd i ti on s Minimum Peak Switch Current Limit ILIM 88PG8204 = VOUT1 1.12 88PG8204 = VOUT2 1.12 88PG8216 = VOUT1 1.5 88PG8216 = VOUT2 2.25 88PG8226 = VOUT1 2.25 88PG8226 = VOUT2 2.25 88PG8227 = VOUT1 2.25 88PG8227 = VOUT2 3.0 88PG8237 = VOUT1 3.0 88PG8237 = VOUT2 3.0 88PG8204 = VOUT1, L1 = 4.7 H 0.75 88PG8204 = VOUT2, L2 = 4.7 H 0.75 88PG8216 = VOUT1, L1 = 4.7 H 1.0 88PG8216 = VOUT2, L2 = 3.3 H 1.5 88PG8226 = VOUT1, L1 = 3.3 H 1.5 88PG8226 = VOUT2, L2 = 3.3 H 1.5 88PG8227 = VOUT1, L3 = 3.3 H 1.5 88PG8227 = VOUT2, L4 = 2.0 H 2.0 88PG8237 = VOUT1, L1 = 2.0 H 2.0 88PG8237 = VOUT2, L2 = 2.0 H 2.0 RVSET = 11K 0.8 RVSET = 18K 1.0 RVSET = 30K 1.2 RVSET = 51K 1.5 RVSET = 100K 1.8 RVSET = 160K 2.5 RVSET = 270K 3.0 RVSET = 470K 3.3 VVSET1 = 0V, VPSET1 = 0V 1.8 VVSET1 = 0V, VPSET1 = SVIN 2.5 VVSET1 = SVIN, VPSET1 = 0V 3.0 VVSET1 = SVIN, VPSET1 = SVIN 3.3 Maximum Output Current Output Voltage Output Voltage 1, Logic Programmability IOUT VOUT VOUT1 Copyright (c) 2008 Marvell April 23, 2008, 2.00 Min Ty p Max U n i ts A A V V Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 17 88PG82XX Datasheet Parameter S y m b ol C o nd i ti on s Output Voltage 2, Logic Programmability VOUT2 VVSET2 = 0V, VPSET2 = 0V 0.8 VVSET2 = 0V, VPSET2 = SVIN 1.0 VVSET2 = SVIN, VPSET2 = 0V 1.2 VVSET2 = SVIN, VPSET2 = SVIN 1.5 RVSET = 11K -10 RVSET = 18K -7.5 Percentage Set Min Ty p RVSET = 30K -5 RVSET = 51K -2.5 RVSET = 0K 0 RVSET = 100K 2.5 RVSET = 160K 5 RVSET = 270K 7.5 RVSET = 470K 10 SVIN = PVIN = 3.0V to 5.0V VOUT = 1.5V ILOAD = IOUT(MAX)/4 0.05 Max U n i ts V % Output Voltage Line Regulation VLNREG Output Voltage Load Regulation VLDREG SVIN = PVIN = 5.0V VOUT = 1.5V ILOAD = IOUT(MAX)/4 to IOUT(MAX) 0.05 % Switching Frequency fSW ILOAD = IOUT(MAX)/2 1 MHz Switch Leakage Current ILSW SVIN = PVIN = 5V, VEN = 0V VSW = PVIN 1 50 SVIN = PVIN, VEN = 0V VSW = SGND = PGND 1 50 VOUT > 1.35V VOUT* 90% Power-On Reset Threshold Voltage for Buck1 VPORTH Power-On Reset Threshold Voltage for Buck2 VPORTH Power-On Reset Output Low Voltage VPORL ISINK = 2 mA, VEN = SVIN Power-On Reset Leakage Current IPOR VEN = 5V Power-On Reset Delay tRESET A VOUT < 1.32V VOUT-13 0 mV VOUT > 1.35V VOUT* 90% VOUT < 1.32V Doc. No. MV-S103563-00 Rev. C Page 18 % V V VOUT-13 0 mV 0.4 V 1 A 40 ms Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Functional Description Regulation and Start-up 3 Functional Description Figure 3: 88PG82XX Block Diagram R1 C5 C1 Vin 2.75V to 5.5V C2 SVIN PVIN2 PVIN1 + OSCILLATOR 10 A Current Sense INTERNAL CIRCUITRY POWER SUPPLY DSP 1 EN Current Sense + EN 1 A/D 1 SW1 SW2 Vout 1 C3 PGND1 PWM CONTROL DSP 1 ON SFB1 OFF EN 2 SDI 10 A A/D 2 A/D 1 PGood 1 PVIN2 PWM CONTROL DSP 2 SFB1 SW2 A/D 2 L2 Vout 2 C4 Serial Data Interface PGND2 SFB1 THERMAL SHUTDOWN 150 C RESISTOR NETWORK RESISTOR NETWORK PGood1 SFB2 Vin PGood 2 R3 BAND-GAP VOLTAGE REFERENCE UNDERVOLTAGE LOCKOUT SGND 40us /40ms 40us /40ms FAULT POR1 RESISTOR SENSING CIRCUITRY VSET1 R7 3.1 L1 DSP 2 PSET1 R8 RESISTOR SENSING CIRCUITRY VSET2 R5 VPOR POR2 PSET2 R6 Regulation and Start-up The step-down switching regulator uses Pulse Width Modulation (PWM) and Pulse Frequency Modulation (PFM) modes to regulate the output voltage using digital control. The mode of operation depends on the level of output current and the output voltage. In steady states, the step-down switching regulator monitors the current flowing through the inductor to determine if the regulator is handling heavy or light load applications. For heavy load applications, the step-down regulator operates in the PWM mode (B and C) to minimize the ripple current for optimum efficiency and to minimize the ripple output voltage. The step-down regulator operates in the PFM and Discontinuous Conduction Mode (DCM) (A and D) to limit the switching actions for optimum efficiency in light load applications. In this mode, the average output voltage is slightly higher than the average output voltage for heavy transient load applications. Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 19 88PG82XX Datasheet Figure 4: Output Voltage Window Typical VOUT 3.1.1 PFM Mode A B C D PWM Mode PFM Mode Soft Start and Sequencing The 88PG82XX device's outputs can either be sequenced to start up together or have VOUT1 start followed by VOUT2. When the SDI pin is low, the VOUT1 and VOUT2 will start up together with a start up time in the order of 100 s, as shown in Figure 5. If the SDI pin is high, then VOUT1 will start first and VOUT2 will start as soon as VOUT1 is within its specified tolerance (see Figure 6). Both outputs will have a soft start ramp. The POR2 output will go high 40 ms after VOUT2 is within its regulation limits. Soft start is a highly desirable property in "Hot-Plug" applications. The 88PG82XX starts up in less then 100 s when soft-start is disabled (Figure 7). However in soft-start mode, the 88PG82XX controls the rise time of the output voltage, thereby dramatically reducing the inrush current. The 88PG82XX rise time is roughly 0.25V/ms and it is independent of output capacitance and load current (see Figure 8). Figure 9 shows the output voltage rise time with a 100 F output capacitor. Although there is a difference in output capacitance between Figure 6 and Figure 9, the output voltage rise time difference is less than 0.1 ms. Figure 5: Startup without Sequencing Figure 6: Startup with Sequencing and Soft Start (COUT= 22 F) 2V/DIV 5V/DIV VIN VEN 1.0V/DIV 1V/DIV VOUT1 VOUT1 1V/DIV 1V/DIV VOUT2 VOUT2 2.0 ms/DIV 1.0 ms/DIV Doc. No. MV-S103563-00 Rev. C Page 20 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Functional Description Regulation and Start-up Figure 7: Fast Startup (0.8V, 1.2V, 1.8V, 2.5V, 3.3V) Figure 8: Soft Start up (0.8V, 1.2V, 1.8V, 2.5V, 3.3V) 500mV/DIV VOUT VOUT 20 s/DIV 500mV/DIV 2.0 ms/DIV Figure 9: Inrush Current with COUT = 100 F 500 mV/DIV VOUT IIN 100 mA/DIV 5.0 ms/DIV Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 21 88PG82XX Datasheet 3.2 Output Voltage Settings 3.2.1 Logic Programmability The output voltage of the step-down switching regulator can be programmed by connecting VSET and PSET pins to SGND and/or SVIN. This can be very useful for standard output voltages. Table 8: Logic Programmability Table V V S E T1 V PS E T 1 V OUT 1 V V S E T2 V P SE T 2 V O U T2 SGND SGND 1.8V SGND SGND 0.8V SGND SVIN 2.5V SGND SVIN 1.0V SVIN SGND 3.0V SVIN SGND 1.2V SVIN SVIN 3.3V SVIN SVIN 1.5V SGND 11KRPSET2475K Hi-Z SGND 11KRPSET2475K Hi-Z Doc. No. MV-S103563-00 Rev. C Page 22 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Functional Description Output Voltage Settings 3.2.2 Serial Programmability The output voltage of the step-down switching regulator can also program by using 18-bit serial data into the SDI pin. Figure 10: Serial Programmability WRITE MODE Stop Start Chip Select "1" Pulse Registor Address "1" "0" "0" pulse Pulse pulse "1" Pulse DATA FIELD "0" "0" "1" "0" pulse pulse Pulse pulse The period of a pulse is 1 s +/- 200 ns VHIGH > 1.4V VLow < 0.8V "1" Pulse D7 D6 D5 D4 D3 D2 D1 D0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 "1" pulse The write operation : V HIGH VLOW 1) 2) 3) be Each write sequence needs 18 pulses to complete. During a non -write operation , the input needs to be at V LOW (<0.8V). In between two successive write operations , the SDI input needs to at VLOW (<0.8V) for a minimum of 10 s For "1" pulse, the high is 0.75 s +/- 150 ns and the low period is 0.25 s+/-50 ns "0" pulse 1st Write sequence VLOW Low for at least 10 s nd 2 Write sequence VHIGH For "0" pulse, the high is 0.25 s +/- 50 ns and the low period is 0.75 s+/-150 ns Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 23 88PG82XX Datasheet The first 4 bits (MSB-bits) of the data field are used to select the output voltage where the second 4 bits (LSB-bits) of the data field are used to trim the output voltage (percent of output voltage). The default value for the data field is as follows. Table 9: Default Value of Data Field D a ta F i e ld D e s c r i p t io n Voltage Set Percent Set B i ts 7 6 5 4 3 2 1 0 D e f au l t Va l u e 0 0 1 0 0 1 0 0 On power up, the output voltage is set according to RPSET and RVSET. The output voltage can then be field programmed by setting bit 3 and bit 7 to "1". The output voltage and percent set are selected according to Table 6. Table 10: Voltage and Percentage Set D a ta F i e l d V OUT (V ) D a ta F i e l d Percent Set B i ts 7 6 5 4 3 2 1 0 Va lu e 1 0 0 0 0.8 1 0 0 0 -7.5% 1 0 0 1 1.0 1 0 0 1 -10% 1 0 1 0 1.2 1 0 1 0 -5.0% 1 0 1 1 1.5 1 0 1 1 -2.5% 1 1 0 0 1.8 1 1 0 0 +2.5% 1 1 0 1 2.5 1 1 0 1 +5.0% 1 1 1 0 3.0 1 1 1 0 +7.5% 1 1 1 1 3.3 1 1 1 1 +10% All combinations of the VSET (Table 8) can be used with all combinations of the PSET (Table 8) to provide maximum flexibility in output voltage selection (Table 6). To select the output voltage, use the value from Table 7 to program the address bits. Table 11: Output Voltage Selection D e s c r i p t io n R e g is t e r A d d r e s s B i ts O u t p u t Vol ta g e S e le c t io n 3 2 1 0 Va lu e 0 0 0 0 VOUT1 0 0 1 0 VOUT2 Doc. No. MV-S103563-00 Rev. C Page 24 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Functional Description Output Voltage Settings 3.2.3 Output Voltage - AnyVoltageTM Technology The output voltage of the step-down switching regulator is programmed by using Table 8 or Table 9 to select resistor values for VSET and PSET pin. The VSET pin sets the output voltage and the PSET pin trims the set voltage to a percentage value. For example, to program 2.25V output, a 165 k resistor is selected for the VSET pin, and an 11 k resistor is selected for the PSET pin. The 165 k resistor sets the output voltage to 2.5V and the 11 k resistor trims the set voltage by -10%. Using the VSET resistor's value greater than 619 k or less than 7.68 k disables the step-down switching regulator and sets the SW pin to high impedance. If the VSET resistor's value is outside the 5% tolerance, the output can be either higher or lower than the set voltage. Using resistor values greater than 619 k or less than 7.68 k for the PSET pin does not affect the set voltage. When the PSET pin is not used, it must be connected to ground. Like the VSET resistor, the percent value can be either higher or lower if the PSET resistor's value is outside the 5% tolerance. Table 12: AnyVoltageTM Programming Table for 1% Resistors VSET P SE T -10.0% -7.5% -5.0% -2.5% 0% 2 . 5% 5.0% 7.5% 1 0 .0 % 11 k 1 8. 7 k 31.6k 5 3 .6 k GND 97.6k 165k 280k 475k 11 k 0.720 0.740 0.760 0.780 0.800 0.820 0.840 0.860 0.880 1 8 .7 k 0.900 0.925 0.950 0.975 1.000 1.025 1.050 1.075 1.100 3 1 .6 k 1.080 1.110 1.140 1.170 1.200 1.230 1.260 1.290 1.320 5 3 .6 k 1.350 1.388 1.425 1.463 1.500 1.538 1.575 1.613 1.650 9 7 .6 k 1.620 1.665 1.710 1.755 1.800 1.845 1.890 1.935 1.980 1 6 5k 2.250 2.313 2.375 2.438 2.500 2.563 2.625 2.688 2.750 2 8 0k 2.700 2.775 2.850 2.925 3.000 3.075 3.150 3.225 3.300 4 7 5k 2.970 3.053 3.135 3.218 3.300 3.383 3.465 3.548 3.630 Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 25 88PG82XX Datasheet . Table 13: AnyVoltageTM Programming Table for 5% Resistors VSET P SE T -10.0% -7.5% -5.0% -2.5% 0% 2 . 5% 5.0% 7.5% 1 0 .0 % 11 k 18k 3 0k 51k GND 100k 160k 270k 470k 11 k 0.720 0.740 0.760 0.780 0.800 0.820 0.840 0.860 0.880 18k 0.900 0.925 0.950 0.975 1.000 1.025 1.050 1.075 1.100 30k 1.080 1.110 1.140 1.170 1.200 1.230 1.260 1.290 1.320 51k 1.350 1.388 1.425 1.463 1.500 1.538 1.575 1.613 1.650 1 0 0k 1.620 1.665 1.710 1.755 1.800 1.845 1.890 1.935 1.980 1 6 0k 2.250 2.313 2.375 2.438 2.500 2.563 2.625 2.688 2.750 2 7 0k 2.700 2.775 2.850 2.925 3.000 3.075 3.150 3.225 3.300 4 7 0k 2.970 3.053 3.135 3.218 3.300 3.383 3.465 3.548 3.630 The VSET and PSET resistors are read once during start-up before the output voltage is turned on. After the output voltage is turned on, the output voltage can change to different values using serial programming interface. Otherwise to configure the output to a different voltage, power has to recycle or the 88PG82XX has to turn OFF and back ON using the shutdown pin. Figure 11 shows the startup waveforms of the 88PG82XX. Once the input voltage (VIN) is above the under voltage lockout (UVLO) upper threshold (UTH), the VSET and PSET pin become active. Current is first sourced out of PSET pin and then the VSET pin, in exponentially increasing steps. After each step there is a blanking time before the VSET voltage is compared to an internal 1.2V reference. If the VSET voltage is below internal reference voltage, the current source proceeds to the next step. Once the VSET voltage is above the internal reference voltage the sequence stops and the output voltage (VOUT) is allowed to turn on. The Figure 12 shows the VSET waveform for VSET = 2.5V and PSET = -5% output. The 88PG82XX keeps track of how many steps are required to determine the appropriate output voltage. Table 10 provides the number of steps necessary for each output voltage option. Using a VSET resistor of 165 k requires the current source to step 4 times, and a PSET resistor of 31.6 k requires 7 steps. Doc. No. MV-S103563-00 Rev. C Page 26 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Functional Description Output Voltage Settings Figure 11: Startup Sequence Figure 12: VSET = 2.5V and PSET = -5% VIN 2V/DIV VOUT 1V/DIV VVSET 1V/DIV VPSET 1V/DIV VVSET 500mV/DIV VPSET 500mV/DIV 200 s/DIV 2.0 ms/DIV Table 14: Output Voltage Option Steps Ste p V O U T (V ) RV S ET (K ) Step P S ET (% ) R S PS E T (k ) 1 0 0 1 0 0 2 3.3 475 2 +10 475 3 3.0 280 3 +7.5 280 4 2.5 165 4 +5.0 165 5 1.8 97.6 5 +2.5 97.6 6 1.5 53.6 6 -2.5 53.6 7 1.2 31.6 7 -5.0 31.6 8 1.0 18.7 8 -7.5 18.7 9 0.8 11 9 -10 11 The 88PG82XX provides an innovative technique to set the output voltage. During start-up it reads the value of external resistors, which are located outside the regulator's feedback loop to program the output voltage. By placing the output voltage programming resistor outside the regulator's feedback loop, its tolerance does not affect the accuracy of the output voltage. Normally, adjustable regulators use 1% resistors to set the output voltage. However, these resistors are located inside the feedback loop, introducing as much as 2% of initial accuracy error to the output voltage, resulting in an overall initial accuracy of 3%. Whereas, the 88PG82XX initial accuracy is 2% for any of the eight output voltages. The VSET and PSET pins are sensitive to excessive leakage currents and stray capacitance. The output voltage can potentially be programmed to the lower output voltage if there is contamination, which introduces excessive leakage current on the VSET and PSET pin, especially for a RVSET and RPSET of 470k. The parasitic resistance on these nodes must be greater than 3 M and the stray capacitance must be less than 25 pF; otherwise, a 3.3V output can potentially end up at 3V. Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 27 88PG82XX Datasheet 3.3 Undervoltage Lockout (UVLO) This feature ensures that the internal MOSFETs have adequate voltage levels to operate properly. When the input voltage drops below 2.55V (typical), both MOSFETs are off until the input rises above the upper threshold of 2.65V (typical). 3.4 Over Voltage Protection (OVP) An over voltage comparator guards against transient overshoots, as well as other serious conditions, that may damage the IC. When the input voltage is rises above 5.7V (typical), both internal MOSFETs are turned off until the input voltage drops below the lower threshold of 5.6V (typical) Figure 13: UVLO and OVP Waveforms VOVP_HTH VOVP-LTH VUVLO-HTH VUVLO-LTH VIN BUCK 1 Output Enable Undefined BUCK 1 Output Disable Buck 2 Output Enable Undefined Buck 2 Output Disable 3.5 Power-On Reset (POR) The Power-On Reset (POR) pin is an active-high, open-drain output pin. This output is held low when the output voltage of the step-down regulator is below the threshold. When the output voltage is above the threshold, the Power-On Reset pin goes high 40 ms later. Setting the output voltage greater than 1.35V, the threshold voltage is 0.9% * VOUT (typical). Setting the output voltage less than 1.32V, the threshold voltage is VOUT - 130 mV (typical). A built-in 25 s (tDELAY) delay is incorporated to prevent nuisance tripping. Figure 14: Power-On Reset Waveforms V POOD_TH VOUT <t DELAY 0V > t V POR DELAY VPORH VPORL 40 ms Doc. No. MV-S103563-00 Rev. C Page 28 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Functional Description Thermal Shutdown 3.6 Thermal Shutdown When the junction temperature of the 88PG82XX exceeds 150 C (typical), the thermal shutdown circuitry disables the step-down regulator. The step-down switching regulator is enabled when the junction temperature is decreased to 105 C (typical). 3.7 Adaptive Transient Response The 88PG82XX device's Smart Technology allows the step-down switching regulator to quickly respond to the multiple step loads and maintain stability over a wide range of applications. Figure 15 shows an example of a second step-load applied while the output voltage of the step-down switching regulator increased due to the inductive kick from the first step-load. Condition: VIN = 5.0V, RSVIN = 10, CSVIN = 0.1 F, CPVIN = 22 F, L = 3.3 H, COUT = 22 F, VOUT = 1.2V, ILOAD = 500 mA to 1.5A. Figure 15: Adaptive Transient Response VOUT 100mV/DIV ILOAD 1A/DIV 20 s/DIV The worst case overshoot (VSOAR) during a full-load to light-load transient due to stored inductor energy (Figure 15) can be calculated as: 2 I LOAD ( MAX ) * L V SOAR = --------------------------------------------2 * C OUT * V OUT Although the VSOAR cannot be eliminated, its amplitude can be controlled based on the COUT capacitor value. The appropriate COUT value can easily be calculated for the acceptable VSOAR level for each specific application. 2 I LOAD ( MAX ) * L C OUT = --------------------------------------------2 * V SOAR * V OUT Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 29 88PG82XX Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103563-00 Rev. C Page 30 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Functional Characteristics Start-Up Waveforms 4 Functional Characteristics The following applies unless otherwise noted: TA = 25C, RSVIN = 10, CSVIN = 0.1 F, CPVIN = 2 x 22 F, L1 = L2 = 3.3 H, COUT (BUCK1) = 22 F (ceramic), COUT (BUCK2) = 22 F (ceramic). 4.1 Start-Up Waveforms NOTE: When the input voltage rises above the UVLO's upper threshold, there is a delay (4 ms typ) before the step-down regulator's output voltage turns on. Figure 16: Startup Using the Enable Pin Figure 17: Turn Off Using the Enable Pin 2V/DIV VEN 2V/DIV VEN VBUCK1 1V/DIV VBUCK1 1V/DIV 1V/DIV VBUCK2 VBUCK2 1V/DIV 1 ms/DIV 1 ms/DIV VIN = 5.0V ILOAD = No Load VIN = 5.0V VBUCK1= 1.2V tDLY= 4.0 ms VBUCK1= 1.2V VBUCK2= 1.2V SDI = 0V VBUCK2= 1.2V Figure 18: Startup Sequence ILOAD = 50 mA Figure 19: Hot Plug 5V/DIV 5V/DIV VIN VIN 2V/DIV VBUCK1 2V/DIV VBUCK1 2V/DIV VBUCK2 2V/DIV VBUCK2 5V/DIV VPOR1 5V/DIV VPOR1 5V/DIV 5V/DIV VPOR2 VPOR2 10 ms/DIV 10 ms/DIV VIN = 5.0V VBUCK2= 1.2V VIN = 5.0V VBUCK2= 1.2V VBUCK1= 1.2V ILOAD = No Load VBUCK1= 1.2V ILOAD = No Load SDI = 0V SDI = 0V Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 31 88PG82XX Datasheet Figure 20: UVLO and OVP Thresholds Figure 21: Input Soft Start and Start up Sequence 5V/DIV VIN VIN 2V/DIV 1V/DIV VBUCK1 VBUCK1 1V/DIV 1V/DIV VBUCK2 1V/DIV VBUCK2 100 ms/DIV 2.0 ms/DIV VIN = 0 to 6.0V VUVLO(HTH) = 2.608V VIN = 5V VBUCK1= 1.0V VUVLO(LTH)= 2.531V VBUCK1= 1.2V VBUCK2= 1.0V VOVP(HTH) = 5.64V VBUCK2= 1.2V ILOAD1 = 10 mA VOVP(LTH) = 5.32V ILOAD = No Load ILOAD2 = 10 mA 4.2 SDI = SVIN Short-Circuit Waveforms Figure 22: Step-Down Short-Circuit Response VSW 5V/DIV VBUCK Short Circuit 500 mV/DIV 2nd Peak Current Limit 2A/DIV IIND 1st Peak Current Limit 200 s/DIV Doc. No. MV-S103563-00 Rev. C Page 32 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Functional Characteristics Switching Waveforms 4.3 Switching Waveforms NOTE: For repeatability of measuring output ripple (VBUCK (P-P)) for the BUCK regulator, the standard test procedure limits the scope bandwidth to 20 MHz and uses a coax cable with very short leads terminated into 50. The coax leads must be routed away from the switching node as much as possible. Figure 23: Switching Waveforms PWM mode Figure 24: Switching Waveforms PWM mode VSW VSW 5V/DIV 1A/DIV IIND VBUCK 10 mV/DIV VIN 100 mV/DIV 5V/DIV 1A/DIV IIND VBUCK 10 mV/DIV VIN 50 mV/DIV 500 ns/DIV 500 ns/DIV CIN = 22 F VIN(P-P) = 77.3 mV CIN = 2 x 22 F VIN(P-P) = 58.9 mV VIN = 5.0V IIND(P-P) = 412.3 mA VIN = 5.0V IIND(P-P) = 446.8 mA VBUCK= 1.2V IIND(PK) = 1.73A VBUCK= 1.2V IIND(PK) = 1.76A IOUT = 1.5A Freq = 940 kHz IOUT = 1.5A Freq = 940 kHz VOUT(P-P) = 5.4 mV (Note) VOUT(P-P) = 5 mV (Note) Figure 25: Switching Waveforms DCM Mode VSW Figure 26: Switching Waveforms - DCM Mode-Zoom 5V/DIV VBUCK 20 mV/DIV VSW 5V/DIV VBUCK 20 mV/DIV IIND IIND 200 mA/DIV 200 mA/DIV 5 s/DIV 500 ns/DIV VIN = 5.0V IIND(PK) = 440 mA VIN = 5.0V VBUCK= 1.2V Freq = 187 kHz VBUCK= 1.2V IOUT = 29 mA IOUT = 29 mA VOUT(P-P) =22 mV (Note) Ringing Freq = 6.5 MHz Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 33 88PG82XX Datasheet Figure 27: PWM Output Ripple Voltage VBUCK1 10 mV/DIV VBUCK2 10 mV/DIV 100 ms/DIV VIN = 5.0V IOUT2 = 1.5A VBUCK1= 1.2V VBUCK1(P-P) = 7.3 mV (Note) VBUCK2= 1.2V VBUCK2(P-P) = 8.2 mV (Note) IOUT1 = 1.5A 4.4 Load Transient Waveforms 4.4.1 Step-Down Regulator Figure 28: Fast Load Rise Time Figure 29: Slow Load Rise Time VSW 5V/DIV VBUCK 100 mV/DIV VSW 5V/DIV VBUCK 100 mV/DIV ILOAD IIND 1A/DIV 1A/DIV ILOAD IIND 2 s/DIV 1A/DIV 1A/DIV 2 s/DIV VIN = 5.0V COUT = 22 F VIN = 5.0V COUT = 2 F VBUCK= 1.2V tRISE = 13.1 A/s VBUCK= 1.2V tRISE = 1.2 A/s IOUT = 500 mA to 1.5A IOUT = 500 mA to 1.5A Doc. No. MV-S103563-00 Rev. C Page 34 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Functional Characteristics Load Transient Waveforms Figure 30: Fast Load Fall Time Figure 31: Slow Load Fall Time 5V/DIV VSW VSW 5V/DIV VBUCK VBUCK 100 mV/DIV ILOAD IIND 1A/DIV 1A/DIV 100 mV/DIV ILOAD IIND 1A/DIV 1A/DIV 2 s/DIV 2 s/DIV VIN = 5.0V COUT = 22 F VIN = 5.0V COUT = 22 F VBUCK= 1.2V tFALL = 88 A/s VBUCK= 1.2V tFALL = 1.2 A/s IOUT = 500 mA to 1.5A IOUT = 500 mA to 1.5A Figure 32: Load Transient Response VBUCK Figure 33: Double-Pulsed Load Response 100 mV/DIV VBUCK 100 mV/DIV ILOAD 1A/DIV 1A/DIV ILOAD 20 s/DIV 20 s/DIV VIN = 5.0V ILOAD = 500 mA to 1.5A VIN = 5.0V ILOAD = 500 mA to 1.5A VBUCK= 1.2V tRISE = 13.8 A/s VBUCK= 1.2V tRISE = 11.2 A/s COUT = 22 F tFALL = 121 A/s COUT = 22 F tFALL = 95.3 A/s Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 35 88PG82XX Datasheet Figure 34: Load Transient Response VBUCK Figure 35: Double-Pulsed Load Response 100 mV/DIV 100 mV/DIV VBUCK ILOAD ILOAD 1A/DIV 1A/DIV 20 s/DIV 20 s/DIV VIN = 5.0V ILOAD = 500 mA to 1.5A VIN = 5.0V ILOAD = 500 mA to 1.5A VBUCK= 1.2V tRISE = 15 A/s VBUCK= 1.2V tRISE = 13.2 A/s COUT = 2 x 22 F tFALL = 95.2 A/s COUT = 2 x 22 F tFALL = 91 A/s 4.4.2 Cross-Talk Waveforms Figure 36: Cross-talk Continuous Mode Figure 37: Cross-talk Discontinuous Mode VOUT1 20 mV/DIV VOUT1 20 mV/DIV VOUT2 200 mV/DIV VOUT2 200 mV/DIV IOUT_2 2A/DIV IOUT_2 2A/DIV 20 s/DIV 20 s/DIV IOUT1 = 30 mA VOUT1 = 1.5V IOUT1 = 500 mA VOUT1 = 1.5V IOUT2 = 0.5A to 2.0A VOUT2 = 1.5V IOUT2 = 0.5A to 2.0A VOUT2 = 1.5V Doc. No. MV-S103563-00 Rev. C Page 36 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Functional Characteristics Output Voltage Transient Waveforms 4.5 Output Voltage Transient Waveforms The following graphs show the effect of changing the step-down regulator's output voltage using the serial interface. Depending on the change in the step-size of the output voltage, the output load, and the output capacitance, the power-on reset pin de-asserts when the changes of the output voltage occur beyond the 25 s (typical) delay. 4.5.1 Step-Down Regulator Figure 38: VOUT = 1.0V to 1.2V with No Load VBUCK Figure 39: VOUT = 1.0V to 1.5V with No Load 500 mV/DIV 500 mV/DIV VBUCK 5V/DIV VPOR VPOR 5V/DIV 5V/DIV SDI 5V/DIV SDI 100 s/DIV 100 s/DIV VIN = 5.0V VIN = 5.0V COUT= (2 x 22) + 1000 F COUT= (2 x 22) +1000 F Figure 40: VOUT = 1.0V to 1.2V with ILOAD = 1.5A Figure 41: VOUT = 1.0V to 1.5V with ILOAD = 1.5A 500 mV/DIV VBUCK 500 mV/DIV 5V/DIV VPOR VBUCK VPOR 5V/DIV 5V/DIV SDI SDI 5V/DIV 100 s/DIV 100 s/DIV VIN = 5.0V VIN = 5.0V COUT= (2 x 22) + 1000 F COUT= (2 x 22) +1000 F Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 37 88PG82XX Datasheet Figure 42: VOUT = 1.2V to 1.0V with ILOAD = 1.5A Figure 43: VOUT = 1.5V to 1.0V with ILOAD = 1.5A VBUCK VBUCK 500 mV/DIV 500 mV/DIV VPOR 5V/DIV VPOR 5V/DIV SDI 5V/DIV SDI 5V/DIV 100 s/DIV 100 s/DIV VIN = 5.0V VIN = 5.0V COUT= (2 x 22)+1000 F COUT= (2 x 22)+1000 F 4.6 Line Transient Waveforms Figure 44: Line Transient @ VIN = 3.6V VIN Figure 45: Line Transient @ VIN = 4.5V 1V/DIV 3.2V 1V/DIV VIN 3.6V VBUCK 4.1V 4.5V 20 mV/DIV VBUCK 20 mV/DIV 2 ms/DIV 2 ms/DIV VIN = 3.6V VBUCK = 1.2V VIN = 4.5V VBUCK = 1.2V CIN= 22 F ILOAD = 1.5A CIN= 22 F ILOAD = 1.5A Doc. No. MV-S103563-00 Rev. C Page 38 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Typical Characteristics Efficiency Graphs 5 Typical Characteristics 5.1 Efficiency Graphs Efficiency vs. Output Current Vin = 3.3V 100 100 90 90 Efficiency (%) Efficiency (%) Efficiency vs. Output Current Vin = 5.0V 80 3.3V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 70 60 80 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 70 60 50 50 0 0.5 1 5.1.1 0 1.5 1 1.5 26 G2 26 G1 Efficiency Graphs in Log Scale Efficiency vs. Output Current Vin = 5.0V Efficiency vs. Output Current Vin = 3.3V 100 100 90 90 Efficiency (%) Efficiency (%) 0.5 Output Current (A) Output Current (A) 80 3.3V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 70 60 50 0.01 0.1 1 Output Current (A) 80 70 10 50 0.01 26 G3 Copyright (c) 2008 Marvell April 23, 2008, 2.00 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 60 0.1 1 Output Current (A) 10 26 G4 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 39 88PG82XX Datasheet 5.2 Load Regulation Output Voltage vs. Output Current Vout = 1.5V Output Voltage (V) 1.60 1.55 1.50 1.45 3.3V 5.0V 1.40 0 0.2 5.3 0.4 0.6 0.8 1 Output Current (A) 1.2 1.4 1.6 26 G5 Dropout Voltage 88PG8226 Buck Dropout vs. Load Current Vin = 3.2, Vout = 3.3V 0.4 Buck Dropout (V) 0.35 85C 25C -40C 0.3 0.25 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 Load Current(A) 26 G6 5.4 RDS (ON) Resistance TOP Switch Resistance vs. Temperature BOT Switch Resistance vs. Temperature 0.070 Vin = 3.0V 0.120 Resistance (ohm) Resistance (ohm) 0.130 Vin = 4.0V 0.110 Vin = 5.0V 0.100 0.090 0.080 Vin = 3.0V 0.060 Vin = 4.0V Vin = 5.0V 0.050 0.040 0.030 0.020 0.070 -40 -20 0 20 40 Temperature (C) 60 80 -40 0 20 40 60 80 Temperature (C) 26 G7 Doc. No. MV-S103563-00 Rev. C Page 40 -20 26 G8 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Typical Characteristics IC Case and Inductor Temperature BOT Switch Resistance vs. Input Voltage TOP Switch Resistance vs. Input Voltage 0.070 Resistance (ohm) Resistance (ohm) 0.130 85C 0.120 25C 0.110 - 40C 0.100 0.090 0.080 85C 0.060 25C - 40C 0.050 0.040 0.030 0.020 0.070 3 3 3.5 5.5 4 4.5 Input Voltage(V) 3.5 5 4 4.5 5 Input Voltage (V) 26 G10 26 G9 IC Case and Inductor Temperature The following data was taken using a 1.4 square inch PCB 1 oz. copper and L = 1.2 H. Actual results depend upon the size of the PCB proximity to other heat emitting components. Input Current vs. Output Current Vin = 5V, Ta = 25C Input Current vs. Output Current Vin = 3.3V, Ta = 25C 2.0 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 1.5 1.0 Input Current (A) Input Current (A) 2.0 0.5 2.5V 1.5 1.8V 1.5V 1.2V 1.0V 1.0 0.8V 0.5 0.0 0.0 0 0.5 1 1.5 0 2 0.5 1 1.5 Output Current (A) Output Current (A) IC Case Temperature vs. Output Current Vin = 5V, Ta = 25C 2 26 G12 26 G11 IC Case Temperature vs. Output Current Vin = 3.3V, Ta = 25C 60 50 45 40 35 30 50 45 40 35 30 25 25 0 0.5 1 1.5 2 Output Current (A) 0 0.5 1 1.5 2 Output Current (A) 26 G13 Copyright (c) 2008 Marvell April 23, 2008, 2.00 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 55 Temperature (C) Temperature (C) 60 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 55 26 G14 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 41 88PG82XX Datasheet Inductor Temperature vs. Output Current Vin = 5V, Ta = 25C Inductor Temperature vs. Output Current Vin = 3.3V, Ta = 25C 50 50 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 40 35 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 45 Temperature (C) Temperature(C) 45 30 40 35 30 25 25 0 0.5 1 1.5 0 2 0.5 1 1.5 2 Output Current (A) Output Current (A) 26 G16 26 G15 Inductor Temperature vs. Output Current 2 Output Current 1 = 2A Vin = 3.3V, Ta = 25C IC Case Temperature vs. Output Current 2 Output Current 1 = 2A Vin = 3.3V, T = 25C 65 80 75 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 55 50 45 40 Temperature (C) Temperature (C) 60 35 30 25 0 0.5 1 1.5 Output Current 2 (A) 60 55 50 45 40 2 26 G17 Doc. No. MV-S103563-00 Rev. C Page 42 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 70 65 0 0.5 1 1.5 Output Current 2 (A) 2 26 G18 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Typical Characteristics Input Voltage Graphs 5.6 Input Voltage Graphs The 88PG8237 part was used to determine the following graph data. Supply Current vs. Input Voltage Shutdow n Supply Current vs. Input Voltage See Test Conditions 4.0 Shutdown Current (uA) Supply Current (mA) 8 3.0 2.0 1.0 0.0 6 4 2 0 2.5 3 3.5 4 4.5 5 2.5 Input Voltage (V) 3 3.5 4 4.5 5 5.5 6 Input Voltage (V) 26 G19 Load = No Load VEN = GND Enable Threshold Vout 1 vs. Input Voltage 3.0 Enable Threshold (V) 2.5 UTH-Enable LTH-Disable 2.0 1.5 1.0 0.5 0.0 2.5 3 3.5 4 4.5 5 Input Voltage (V) 26 G21 Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 43 88PG82XX Datasheet 5.6.1 Step-Down Regulator Output Voltage vs. Input Voltage Efficiency vs. Input Voltage 1.53 100% 95% Efficiency Output Voltage (V) 1.515 1.5 Vout1 1.485 90% Vout1 85% Vout2 Vout2 80% 1.47 3 3.5 4 4.5 3 5 3.5 4 4.5 5 Input Voltage (V) Input Voltage (V) 26 G23 26 G22 IOUT(BUCK) = 375 mA VOUT(BUCK) = 1.5V IOUT(BUCK) = 0.75A Frequency vs. Input Voltage 1000 0.10% 950 Frequency (kHz) Load Regulation Load Regulation vs. Input Voltage 0.20% 0.00% Vout1 Vout1 Vout2 900 850 -0.10% Vout2 800 -0.20% 3 3 3.5 4 Input Voltage (V) 4.5 5 3.5 4 4.5 5 Input Voltage (V) 26 G24 26 G25 VOUT(BUCK) = 1.5V VOUT(BUCK) = 1.5V IOUT(BUCK) = 0.375A - 1.5A IOUT(BUCK) = 0.75A Average Output Current Limit vs. Input Voltage 5.0 Current Limit (A) 4.0 3.0 2.0 Vout1 Vout2 1.0 0.0 3 3.5 4 4.5 5 Input Voltage (V) 26 G26 Doc. No. MV-S103563-00 Rev. C Page 44 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Typical Characteristics Temperature Graphs 5.7 Temperature Graphs The 88PG8237 part was used to determine the following graph data. Shutdown Supply Current vs.Temperature Supply Current vs. Temperature 5 120.0 100.0 Shutdown Current(uA) Supply Current (mA) 4 3 2 1 80.0 60.0 40.0 20.0 0 0.0 -40 -20 0 20 40 60 80 -40 -20 0 Temperature (C) 20 40 60 80 Temperature (C) 26 G27 26 G28 IOUT(BUCK1) = No Load VIN = 5V IOUT(BUCK2) = No Load VEN = GND Enable Threshold Vout 1 vs. Temperature UVLO vs. Temperature 2.7 3.0 UTH - Enable Enable Treshold (V) 2.5 UVLO (V) 2.6 2.5 UTH LTH - Disable 2.0 1.5 1.0 0.5 LTH 0.0 2.4 -40 -20 0 20 40 60 -40 80 -20 20 40 60 80 26 G30 26 G29 VIN= 5V VIN = 5V IOUT(BUCK) = 10mA IOUT(BUCK) = 10mA Copyright (c) 2008 Marvell April 23, 2008, 2.00 0 Temperature (C) Temperature (C) Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 45 88PG82XX Datasheet 5.7.1 Step-Down regulator Output Voltage vs. Temperature Buck Efficiency vs. Temperature 1.515 95% Efficiency 100% Output Voltage (V) 1.53 1.5 1.485 90% 85% Vout1 Vout1 Vout2 Vout2 80% 1.47 -40 -20 0 20 40 60 -40 80 -20 0 20 40 60 80 Temperature (C) Temperature (C) 26 G31 26 G32 VIN = 5.0V VIN = 5.0V IOUT(BUCK) = 750 mA VOUT(BUCK) = 1.5V IOUT(BUCK) = 1.5A Buck Line Regulation vs. Temperature Buck Load Regulation vs. Temperature 0.20% 0.20% Vout1 0.10% Line Regulation Load Regulation 0.10% 0.00% -0.10% Vout2 0.00% -0.10% Vout1 Vout2 -0.20% -0.20% -40 -20 0 20 40 60 -40 80 -20 0 20 40 60 80 Temperature (C) Temperature (C) 26 G33 26 G34 VIN = 5.0V VIN = 3.0V - 5.0V VOUT(BUCK) = 1.5V VOUT(BUCK) = 1.5V IOUT(BUCK) = 750 mA - 3A IOUT(BUCK) = 1.5A Frequency vs. Temperature Buck Current Limit vs. Temperature 1000 5 950 Frequency (kHz) Current Limit (A) 4 3 2 Vout1 Vout2 1 Vout1 Vout2 900 850 800 0 -40 -20 0 20 40 60 -40 80 Temperature (C) -20 0 20 40 60 80 Temperature (C) 26 G36 26 G35 VIN = 5.0V IOUT(BUCK) = 1.5A Doc. No. MV-S103563-00 Rev. C Page 46 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Applications Information PC Board Layout Considerations and Guidelines 6 Applications Information 6.1 PC Board Layout Considerations and Guidelines The PC board layout is very critical in any switching converter. An improper layout can contribute to system instability, excessive EMI (Electro-magnetic interference), and high switching loss. Follow these basic guidelines for good PC layout: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. This is a 2-layer board with 1 ground plane and 1 routing layer. Copy the layout input Figure 48 and Figure 49 as much as possible and use the recommended BOM in Table 15. Contact the factory where substitutions are made. Review the recommended solder pad layout and notes on page 50. Do not replace the Ceramic input capacitor with any other type of capacitor. Any type of capacitor can be placed in parallel with the input capacitor as long as the Ceramic input capacitor is placed next to the IC. If Tantalum input capacitor is used, it must be rated for switching regulator applications and the operating voltage must be derated by 50%. Any type of capacitor can be placed in parallel with the output capacitor. Low-ESR capacitors like the POSCAP from Sanyo can replace the Ceramic output capacitors as long as the capacitor value is the same or greater. Note that the Ceramic capacitors provide the lowest noise and smallest foot print solution. Use planes for the ground, input and output power to maintain good voltage filtering, and to keep power losses low. If there is not enough space for a power plane for the input supply, then the input supply trace must be at least 3/8 inch wide. If there is not enough space for a power plane for the output supplies, then place the output as close to the load as possible with a trace at least 3/8 inch wide. Do not lay out the inductor first. The input capacitor placement is the most critical for proper operation. The AC current circulating through the input capacitor and loop 1 (LP1) are square wave with rise and fall times of 8 ns and slew rates as high as 300 A/s (see Figure 46). At these fast slew rates, stray PCB inductance can generate a voltage spike as high as 3V per inch of PCB trace, VIND = L * di/dt. Therefore, the ceramic input capacitor (C2 and C5) must be placed as close as possible to the PVIN and PGND pins with a short and wide trace as possible. Also, the PVIN and PGND traces must be placed on the top layer. This will isolate the fast AC currents from interfering with the analog ground plane. The 88PG82XX has two internal grounds, analog (SGND) and power (PGND). The analog ground ties to all the noise sensitive signals (PSET, VSET, and SVIN) while the power ground ties to the higher current power paths. Noise on an analog ground can cause problems with the IC's internal control and bias signals. For this reason, separate analog and power ground traces are recommended. The signal ground is connected to the power ground at one point, which is the (-) terminal of the output capacitor. Keep loop 2 (LP2) as small as possible and connect the (-) terminal of the output capacitor as close to the (-) terminal of the input capacitor. A back-to-back placing of bypass capacitors, as shown in Figure 48, is recommended for best results. Keep the switching node (SW) away from the SFB pin and all sensitive signal nodes, minimizing capacitive coupling effects. If the SFB trace must cross the SW node, cross it at a right angle. Try not to route analog or digital lines in close proximity to the power supply especially the VSW node. If this can't be avoided, shield these lines with a power plane placed between the VSW node and the signal lines. Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 47 88PG82XX Datasheet 15. PVIN1 and PVIN2 must be connected together and should not be separated. 16. The type of solder paste recommended for QFN packages is "No clean", due to the difficulty of cleaning flux residues from beneath the QFN package. Figure 46: Simpified Schematic I Cin I Cout LP2 LP1 C4 Vout 2 1.5V/2.0A C5 Vin 2.75V - 5.5V LP2 L2 10 ohm C1 0.1 uF 4 5 6 17 PVIN2 18 SW2 VSE T2 88PG82XX SG ND VSE T1 SFB 1 PSE T1 SD I 7 L1 19 PSE T2 SVI N SW1 SD I SFB 2 PO R1 R3 100 k PO R 1 16 PO R 2 15 14 13 12 11 R8 0 PVIN1 3 R2 100 k R7 16 0k R5 51k R6 0 10 R1 Vin SW1 2 PO R2 9 R4 100 k EN PG ND1 1 8 EN PG ND2 SW2 20 LP1 LP1 LP2 Vin C2 Vout1 2.5V/1.5A C3 Doc. No. MV-S103563-00 Rev. C Page 48 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Applications Information PC Board Layout Considerations and Guidelines Figure 47: PC Board Schematic C4 22uF/6.3V C5 22uF/6.3V Vout 2 1.5V/1.5A Vin 2.75V - 5.5V C1 0.1uF 4 5 6 17 18 PVIN2 SW2 19 SVIN VSET2 88PG8226 SGND VSET1 SFB1 PSET1 SDI 7 SW1 SDI PSET2 POR1 L1 3.3uH Vout 1 2.5V/1.5A POR 1 POR 2 15 14 13 12 11 R8 0 R7 160k R5 51k R6 0 Vin 22uF/6.3V C2 22uF/6.3V C3 Copyright (c) 2008 Marvell April 23, 2008, 2.00 R3 100k 16 PVIN1 3 10 ohm R2 100k 10 R1 Vin SFB2 SW1 2 POR2 9 R4 100k EN PGND1 1 8 EN PGND2 SW2 20 L2 3.3uH Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 49 88PG82XX Datasheet 6.1.1 PC Board Layout Examples for 88PG82XX Actual board size = 570 mil x 630 mil; Area = 0.359 Sq. Inches. Total copper layers = 2 (Top and Bottom) All the components are on the top layer Figure 48: Top Silk-Screen, Top Traces, Vias, and Top Copper (Not to Scales) Actual board size = 711 mil x 1060 mil Total copper layer = 2 Connect the BUCK2 output voltage at this point Connect to the ground plane of the board Connect to the ground plane of the board Connect the BUCK1 output voltage at this point Connect to the ground plane of the board Doc. No. MV-S103563-00 Rev. C Page 50 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Applications Information PC Board Layout Considerations and Guidelines Figure 49: Bottom Silk Screen, Bottom Trace, Vias, and Bottom Copper (Not to Scale) Connect the POR 2 signal at this trace. Connect to the input voltage plane of the board. Connect to the input voltage plane of the board. Connect to the ground plane of the board. Connect the POR 2 signal at this trace. Copyright (c) 2008 Marvell April 23, 2008, 2.00 Connect to the input voltage plane of the board. Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 51 88PG82XX Datasheet 6.1.2 Bill of Materials (BOM) The following tables list the components used with the 88PG82XX. Table 15: BOM for 88PG82XX Ite m Q t y. R ef . M a n u f a ct ur e r P a r t # M an u fa ctu r e r De sc r i pt io n 1 1 U1 88PG8204 Marvell Semiconductor 1MHz, Dual (0.75A/0.75A) Step-Down Regulator 2 1 C1 ECJ-1VB1C104K Pansonic - ECG 0.1F,10%,X7R,16V,0603 Case Size, Ceramic 3 4 C2,C3, C4,C5 C2012X5R0J106MT TDK 10F,20%,X5R,6.3V,0805 Case Size, Ceramic 4 2 L1,L2 1117AS-4R7M Toko 4.7H, 0.91A, 170m, H=1mm, L=2.8mm, W=3.0mm 5 1 R1 ERJ-2RKF10R0X Pansonic - ECG 10.0, 1/16W, 1%, 0402 Case Size 6 1 R2,R3, R4 ERJ-3GEYJ104V Pansonic - ECG 100, 1/10W, 5%, 0603 Case Size 7 4 R5,R6, R7,R8 Pansonic - ECG See AnyVoltage Programming Table 1/16W, 1%, 0402 Case Size Ite m Q t y. R ef . M a n u f a ct ur e r P a r t # M an u fa ctu r e r De sc r i pt io n 1 1 U1 88PG8216 Marvell Semiconductor 1MHz, Dual (1.0A/1.5A) Step-Down Regulator 2 1 C1 ECJ-1VB1C104K Pansonic - ECG 0.1F,10%,X7R,16V,0603 Case Size, Ceramic 3 1 C3 C2012X5R0J106MT TDK 10F,20%,X5R,6.3V,0805 Case Size, Ceramic 4 3 C2,C4, C5 C2012X5R0J226MT TDK 22F,20%,X5R,6.3V,0805 Case Size, Ceramic 5 1 L1 A918CY-4R7M=P3 Toko 4.7H, 0.91A, 170m, H=1mm, L=2.8mm, W=3.0mm 6 1 L2 A918CY-2R0M=P3 Toko 3.3H, 1.99A, 39m, H=2mm, L=6.2mm, W=6.3mm 7 1 R1 ERJ-2RKF10R0X Pansonic - ECG 10.0, 1/16W, 1%, 0402 Case Size 8 3 R2,R3, R4 ERJ-3GEYJ104V Pansonic - ECG 100, 1/10W, 5%, 0603 Case Size 9 4 R5,R6, R7,R8 Pansonic - ECG See AnyVoltage Programming Table 1/16W, 1%, 0402 Case Size Q t y. R ef . M a n u f a ct ur e r P a r t # M an u fa ctu r e r De sc r i pt io n 1 1 U1 88PG8227 Marvell Semiconductor 1MHz, Dual (1.5A/2.0A) Step-Down Regulator 2 1 C1 ECJ-1VB1C104K Pansonic - ECG 0.1F,10%,X7R,16V,0603 Case Size, Ceramic 3 2 C2,C5 C2012X5R0J226MT TDK 22F,20%,X5R,6.3V,0805 Case Size, Ceramic 4 2 C3,C4 C2012X5R0J226MT TDK 22F,20%,X5R,6.3V,0805 Case Size, Ceramic 5 1 L1 A918CY-3R3M=P3 Toko 3.3H, 1.99A, 39m, H=2mm, L=6.2mm, W=6.3mm 6 1 L2 A918CY-2R0M=P3 Toko 2.0H, 2.47A, 24m, H=2mm, L=6.2mm, W=6.3mm 7 1 R1 ERJ-2RKF10R0X Pansonic - ECG 10.0, 1/16W, 1%, 0402 Case Size 8 3 R2,R3, R4 ERJ-3GEYJ104V Pansonic - ECG 100, 1/10W, 5%, 0603 Case Size Ite m Doc. No. MV-S103563-00 Rev. C Page 52 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Applications Information PC Board Layout Considerations and Guidelines Table 15: BOM for 88PG82XX Ite m 9 Ite m Q t y. R ef . 4 R5,R6, R7,R8 M a n u f a ct ur e r P a r t # M an u fa ctu r e r De sc r i pt io n Pansonic - ECG See AnyVoltage Programming Table 1/16W, 1%, 0402 Case Size Q t y. R ef . M a n u f a ct ur e r P a r t # M an u fa ctu r e r De sc r i pt io n 1 1 U1 88PG8226 Marvell Semiconductor 1MHz, Dual (1.5A/1.5A) Step-Down Regulator 2 1 C1 ECJ-1VB1C104K Pansonic - ECG 0.1F, 10%, X7R, 16V, 0603 Case Size, Ceramic 3 2 C2,C5 C2012X5R0J226MT TDK 22F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 4 2 C3,C4 C2012X5R0J226MT TDK 22F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 5 2 L1,L2 A918CY-3R3M=P3 Toko 3.3H, 1.99A, 39m, H=2mm, L=6.2mm, W=6.3mm 6 1 R1 ERJ-2RKF10R0X Pansonic - ECG 10.0, 1/16W, 1%, 0402 Case Size 7 3 R2,R3, R4 ERJ-3GEYJ104V Pansonic - ECG 100, 1/10W, 5%, 0603 Case Size 8 4 R5,R6, R7,R8 Pansonic - ECG See AnyVoltage Programming Table 1/16W, 1%, 0402 Case Size Q t y. R ef . M a n u f a ct ur e r P a r t # M an u fa ctu r e r De sc r i pt io n 1 1 U1 88PG8237 Marvell Semiconductor 1MHz, Dual (2.0A/2.0A) Step-Down Regulator 2 1 C1 ECJ-1VB1C104K Pansonic - ECG 0.1F, 10%, X7R, 16V, 0603 Case Size, Ceramic 3 2 C2,C5 C2012X5R0J226MT TDK 22F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 4 2 C3,C4 C2012X5R0J226MT TDK 22F, 20%, X5R, 6.3V, 0805 Case Size, Ceramic 5 2 L1,L2 A918CY-2R0M=P3 Toko 2.0H, 2.47A, 24m, H=2mm, L=6.2mm, W=6.3mm 6 1 R1 ERJ-2RKF10R0X Pansonic - ECG 10.0, 1/16W, 1%, 0402 Case Size 7 3 R2,R3, R4 ERJ-3GEYJ104V Pansonic - ECG 100, 1/10W, 5%, 0603 Case Size 8 4 R5,R6, R7,R8 Pansonic - ECG See AnyVoltage Programming Table 1/16W, 1%, 0402 Case Size Ite m Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 53 88PG82XX Datasheet Table 16: Ceramic Capacitor Cross Reference Manufacturer M a n u fa c tu r e r Pa r t # D e s c r i p t io n Taiyo-Yuden CE JMK212BJ226MG-T 22F TDK C2012X5R0J226MT Murata GRM21BR60J226ME39L Taiyo-Yuden CE JMK212BJ106MG-T TDK C2012X5R0J106MT Murata GRM219R60J106KE190 Taiyo-Yuden RM LMK105BJ104KV-F TDK C1005X5R1A104K Doc. No. MV-S103563-00 Rev. C Page 54 10F 0.1F Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Mechanical Drawing 88PG82XX Mechanical Drawing 7 Mechanical Drawing 7.1 88PG82XX Mechanical Drawing Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 55 88PG82XX Datasheet 7.2 Dimensions Table 17: Package Dimensions S y m b ol D im e n s io n i n m m MIN NOM MAX A 0.80 0.85 1.00 A1 0.00 0.02 0.05 A3 b 0.20 REF 0.20 D 0.25 0.30 3.00 BSC E 4.00 BSC e 0.50 BSC L 0.45 R 0.10 0.50 0.55 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 Notes: 1. CONTROLLING DIMENSION: MILLIMETER 2. SPECIAL CHARACTERISTICS C CLASS: ccc Doc. No. MV-S103563-00 Rev. C Page 56 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Mechanical Drawing Typical Pad Layout Dimensions 7.3 Typical Pad Layout Dimensions 7.3.1 Recommeded Solder Pad Layout Package Outline 0.50 3.00 4.30 0.65 0.25 4x3 QFN-20 Land Pattern (mm) 0.25 mm 9.84 mils 0.25 mm 9.84 mils Pad SM Pad SM Pad 0.148 mm 5.84 mils 0.051 mm 2.0 mils QFN Lead with Non-Solder Mask Defined Terminal (Not to Scale) Notes: 1. TOP VIEW 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE IN MILLIMETERS 4. OVERSIZE SOLDER MASK BY 4 MILS OVER PAD SIZE (2 MIL ANNULAR RING) 5. 0.148mm SOLDER MASK (SM) BETWEEN PADS 6. TOLERANCE 0.05mm Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 57 88PG82XX Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S103563-00 Rev. C Page 58 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 Ordering Information Ordering Part Numbers and Package Markings 8 Ordering Information 8.1 Ordering Part Numbers and Package Markings Figure 50 shows the ordering part numbering scheme for the 88PG82XX devices. Contact Marvell(R) FAEs or sales representatives for complete ordering information. Figure 50: Sample Part Number 88PG82XX XX - XXX 1 C000 - T Part Number Custom (Optional) 88PG8204 88PG8216 88PG8226 88PG8227 88PG8237 Custom Code Custom Code Environmental 1 = RoHS 6/6 compliant "-" = RoHS 5/6 compliant Package Code NFE = 20-pin QFN 8.2 Sample Ordering Part Number The standard ordering part numbers for the respective solutions are as follows: Table 18: 88PG82XX Ordering Part Numbers1 B o o k in g P a r t Number Marking Current V OUT 1 V O U T2 Ambient Te m p er a t u r e Range2 Package3 88PG8204A0-NFE1C000 G204 0.75A 0.75A -40 C to 85 C 3 X 4 QFN-20 88PG8216A1-NFE1C000 G216 1.0A 1.5A -40 C to 85 C 3 X 4 QFN-20 88PG8226A1-NFE1C000 G226 1.5A 1.5A -40 C to 85 C 3 X 4 QFN-20 88PG8227A1-NFE1C000 G227 1.5A 2.0A -40 C to 85 C 3 X 4 QFN-20 88PG8237A1-NFE1C000 G237 2.0A 2.0A -40 C to 85 C 3 X 4 QFN-20 1. Contact Marvell for details. 2. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. 3. Package dimensions are in mm. Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 59 88PG82XX Datasheet 8.3 Package Marking 8.3.1 88PG82XX Package Marking and Pin 1 Locations Figure 51 is an example of the package marking and pin 1 location for the 88PG847 part. Markings for the other variants are similar. Figure 51: 88PG8227 Package Marking and Pin 1 Location MRVL M arv el l Se m ic on d u ct or G227 Marking YWW# Year, Work week, Assembly code Y WW # = Last digit of year = Work week = Assembly code Pin 1 location Note: The above example is not drawn to scale. Locations of markings are approximate. Doc. No. MV-S103563-00 Rev. C Page 60 Copyright (c) 2008 Marvell Document Classification: Proprietary Information April 23, 2008, 2.00 A Revision History Table 19: Revision History D o c u m e n t Ty p e D o c u m en t R ev i s io n Release Rev. C * * * * Document brought into new template. "Confidential" removed. Functional Characteristic Graphs edited. Replaced Mechanical Drawing Copyright (c) 2008 Marvell April 23, 2008, 2.00 Doc. No. MV-S103563-00 Rev. C Document Classification: Proprietary Information Page 61 Back Cover Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Marvell. Moving Forward Faster