LH28F128SPHTD-PTLZ5 - Sharp Microelectronics of the Americas

PRODUCT SPECIFICATION

Integrated Circuits Group

LH28F128SPHTD-PTLZ5

Flash Memory

128Mbit (8Mbitx16 / 16Mbitx8)

(Model Number: LHF12PZ5)

Spec. Issue Date: December 15, 2004

Spec No: EL16Y377

LHF12PZ5

• Handle this document carefully for it contains material protected by international copyright law. Any reproduction,

full or in part, of this material is prohibited without the express wri tten permission of the company.

• When using the products covered herein, please observe the conditions written herein and the precautions outlined in

the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly

adhere to these conditions and precautions.

(1) The products covered herein are designed and manufactured for the following application areas. When using the

products covered herein for the equi pm ent l is ted in Paragrap h ( 2), even fo r t he fol lowi ng ap pl icat ion ar eas, be su re

to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph

(3).

• Office electronics

• Instrumentat i on and measu ri ng equipment

• Machine tools

• Audiovisual equipment

• Home appliance

• Communication equipment other than for trunk lines

(2) Those contemplating using the products covered herein for the following equipment which demands high

reliability, should first contact a sales representative of the company and then accept responsibility for

incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring

reliability and safety of the equipment and the overall system.

• Control and safety devices for airplanes, trains, automobiles, and other transportation equipment

• Mainframe computers

• Traffic control systems

• Gas leak detectors and automatic cutoff devices

• Rescue and security equipment

• Other safety devices and safety equipment, etc.

(3) Do not use the products covered herein for the following equipment which demands extremely high performance

in terms of functionality, reliability, or accuracy.

• Aerospace equipment

• Communications equipment for trunk lines

• Control equip ment for the nuclear power industry

• Medical equipment related to life support, etc.

(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales

representative of the company.

• Please direct all queries regarding the products covered herein to a sales representative of the company.

Rev. 0.06

                                                                       LHF12PZ5                                                                  1
CONTENTS
PAGE
56-Lead TSOP (Normal Bend) Pinout.......................  3
Pin Descriptions..........................................................  4
CE0, CE1, BS Truth Table............ ...... ...... ................ ..  5
Memory Map..............................................................  6
Identifier Codes Address............................................  8
OTP Block Address Map............................................  9
Bus Operation.......................... ..... ................. ...... .....  10
Command Definitions ............................................... 11
Functions of Block Lock.............. ...... ...... ................  13
Status Register Definition.........................................  14
Extended St atus Regist er Definition ........................  15
STS Configuration Definition ..................................  16
PAGE
1 Electrical Specifications........................................  17
1.1 Absolute Maximum Ratings...........................  17
1.2 Operating Conditions .....................................  17
1.2.1 Capacitance........ ................. ...... ...............  18
1.2.2 AC Input/Output Test Conditions............  18
1.2.3 DC Characteristics...................................  19
1.2.4 AC Characteristics - 
Read-Only Operations..............................  21
1.2.5 AC Characteristics - Write Operations....  25
1.2.6 Reset Operations.................................. ....  27
1.2.7 Block Erase, (Page Buffer) Program 
and Block Lock Configuration 
Performance..............................................  28
2 Related Document Information.............................  29
3 Package and packing specification........................  30
Rev. 0.06

LHF12PZ5 2

LH28F128SPHTD-PTLZ5

128Mbit (8Mbit×16/16Mbit×8)

Page Mode Flash MEMORY

 128-Mbit Density

• Bit Organization ×8/×16

 High Performance Page Mode Reads

for Memory Array

• 120/25ns 4-Word/ 8-Byte Page Mode

 VCC=2.7V-3.6V Operation

• VCCQ for Input/Output Power Supply Isolation

• Automatic Power Savings Mode reduces ICCR

in Static Mode

 OTP (One Time Program) Block

• 4-Word/ 8-Byte Factory-Programmed Area

• 3963-Word/ 7926-Byte User-Programmable Area

 High Performa nce Program wit h Pag e Buffer

• 16-Word/ 32- Byte Page Bu ffer

• Page Buffer Program Time 12.5µs/byte (Typ.)

 Operating Temperature -40°C to +85°C

 Symmetrically-Blocked Architecture

• One-hundred and twenty-eight

64-KWord/ 128-KByte Blocks

 Enhanced Data Protection Features

• Individual Block Lock

• Absolute Protection with VPEN≤VPENLK

• Block Erase, (Page Buffer) Program Lockout during

Power Transitions

 Automated Erase/Program Algorithms

• Program Time 210µs (Typ.)

• Block Erase Time 1s (Typ.)

 Cross-Compatib le Command Support

• Basic Command Set

• Common Flash Interface (CFI)

 Extended Cycling Capability

• Minimum 100,000 Block Erase Cycles

 56-Lead TSOP (Normal Bend)

 CMOS Process (P-type silicon substrate)

 ETOXTM* Flash Technology

 Not designed or rated as radiation hardened

The product, which is Page Mode Flash memory, is a high density, low cost, nonvolatile read/write storage solution for a

wide range of applications. The product can operate at VCC=2.7V-3.6V and VPEN=2.7V-3.6V

The product supports high performance page mode. It allows code execution directly from Flash, thus eliminating time

consuming wait states.

Fast program capability is provided through the use of high speed Page Buffer Program.

The block locking scheme is available for memory array and this scheme provides maximum flexibility for safe nonvolatile

code and data storage.

OTP (One Ti me Program) block provides an area to store security code and to protect its code.

* ETOX is a trademark of Intel Corporation.

Rev. 0.06

LHF12PZ5 3

56-LEAD TSOP

STANDARD PINOUT

14mm x 20mm

TOP VIEW

PEN

RP#

GND

WE#

OE#

STS

CCQ

GND

BYTE#

GND

Figure 1. 56-Lead TSOP (Normal Bend) Pinout

Rev. 0.06

LHF12PZ5 4

Table 1. Pin Descriptions

Symbol Type Name and Funct i on

A0INPUT ADDRESS INPUTS: Lowest address input in byte mode (BYTE#=VIL : ×8 bit).

Address is internally latched during an erase or a program cycle. This pin is not used in

word mode (BYTE#=VIH : ×16 bit)

A22-A1INPUT ADDRESS INPUTS: Inputs for addresses during read, erase and program operations.

Addresses are internally latched during an erase or a program cycle.

BS INPUT BANK SELECT: Bank 0 is selected by BS=VIL. Bank 1 is selected by BS=VIH.

DQ15-DQ0INPUT/

OUTPUT

DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User

Interface) write cycles, outputs data during memory array, status register, query code,

identifier code reads. Data pins float to high-impedance (High Z) when the chip or

outputs are deselected. Data is internally latched during an erase or program cycle.

DQ15-DQ8 pins are not used in byte mode (BYTE#=VIL : ×8 bit).

CE0, CE1INPUT

CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense

amplifiers. When the device is de-selected, power consumption reduces to standby

levels. Refer to Table 2 to determine whether the device is selected or de-selected

depending on th e state of CE0, CE1 and BS.

RP# INPUT

RESET : When low (VIL), RP# resets internal automation and inhib its erase and prog ram

operations, which provides data protection. RP#-high (VIH) enables normal operation.

After power-up or reset mode, the device is automatically set to read array mode.

RP# must be low during power-up/down.

OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.

WE# INPUT

WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are

latched on the first edge of CE0 or CE1 that disables the device or the rising edge of

WE# (whichever occurs first). BS transitions must not occur when CE0=CE1=VIL and

WE#=VIL.

STS OPEN DRAIN

OUTPUT

STATUS: Indicates the status of the internal WSM (Write State Machine). When

configured in level mode (default mode), STS acts as a RY/BY# pin (STS is VOL when

the WSM is executing internal erase or program algorithms). When configured in one of

its pulse modes, STS can pulse to indicate erase/program completion. Refer to Table 9

for STS configu rat ion.

BYTE# INPUT

BYTE ENABLE: BYTE# VIL places the device in byte mode (×8). In this mode, DQ15-

DQ8 is floated (High Z) and A0 is the lowest address input. BYTE# VIH places the

device in word mode (×16) and A1 is the lowest address input.

VPEN INPUT MONITORING POWER SUPPLY VOLTAGE: V PEN is not used for power supply pin.

With VPEN≤VPENLK, block erase, (page buffer) program, block lock configuration and

OTP program cannot be executed and should not be attempted.

VCC SUPPLY DEVICE POWER SUPPLY (2.7V-3.6V): With VCC≤VLKO, all write attempts to the

flash memory are inhibited. Device operations at invalid VCC voltage (refer to DC

Characteristics) produce spurious resu lts and should not be attempted.

VCCQ SUPPLY INPUT/OUTPUT POWER SUPPLY (2.7V-3.6V): Power supply for all input/output

pins.

GND SUPPLY GROUND: Do not float any ground pins.

NC NO CONNECT: Lead is not internally connected; it may be driven or floated.

Rev. 0.06

LHF12PZ5 5

NOTE:

1. For single-chip applications, CE1 can be connected to GND.

2. BS transitions must not occur when CE0=CE1=VIL and WE#=VIL.

Table 2. CE0, CE1, BS Truth Table (1), (2)

BS CE1CE0Device

VIL

VIL VIL Bank 0 Enabled

VIL VIH Disabled

VIH VIL Disabled

VIH VIH Disabled

VIH

VIL VIL Bank 1 Enabled

VIL VIH Disabled

VIH VIL Disabled

VIH VIH Disabled

Rev. 0.06

LHF12PZ5 6

64-Kword/128-Kbyte Block 63

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[A22-A1]

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[A22-A0]

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6C0000

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Rev. 0.06

Figure 2.1. Memory Map (Memory Area selected by BS=VIL)

Selected by BS=VIL (Bank 0)

LHF12PZ5 7

Rev. 0.06

Figure 2.2. Memory Map (Memory Area selected by BS=VIH)

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[A22-A1]

[A22-A1][A22-A0]

[A22-A0]

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020000

03FFFF

01FFFF

040000

05FFFF

060000

07FFFF

080000

09FFFF

0A0000

0BFFFF

0C0000

0DFFFF

0E0000

0FFFFF

100000

11FFFF

120000

13FFFF

140000

15FFFF

160000

17FFFF

180000

19FFFF

1A0000

1BFFFF

1C0000

1DFFFF

1E0000

1FFFFF

200000

21FFFF

220000

23FFFF

240000

25FFFF

260000

27FFFF

280000

29FFFF

2A0000

2BFFFF

2E0000

2FFFFF

300000

31FFFF

320000

33FFFF

340000

35FFFF

360000

37FFFF

380000

39FFFF

3A0000

3BFFFF

3C0000

3DFFFF

3E0000

3FFFFF

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2DFFFF

000000

010000

01FFFF

00FFFF

020000

02FFFF

030000

03FFFF

040000

04FFFF

050000

05FFFF

060000

06FFFF

070000

07FFFF

080000

08FFFF

090000

09FFFF

0A0000

0AFFFF

0B0000

0BFFFF

0C0000

0CFFFF

0D0000

0DFFFF

0E0000

0EFFFF

0F0000

0FFFFF

100000

10FFFF

110000

11FFFF

120000

12FFFF

130000

13FFFF

140000

14FFFF

150000

15FFFF

170000

17FFFF

180000

18FFFF

190000

19FFFF

1A0000

1AFFFF

1B0000

1BFFFF

1C0000

1CFFFF

1D0000

1DFFFF

1E0000

1EFFFF

1F0000

1FFFFF

160000

16FFFF

200000

210000

21FFFF

20FFFF

220000

22FFFF

230000

23FFFF

240000

24FFFF

250000

25FFFF

260000

26FFFF

270000

27FFFF

280000

28FFFF

290000

29FFFF

2A0000

2AFFFF

2B0000

2BFFFF

2C0000

2CFFFF

2D0000

2DFFFF

2E0000

2EFFFF

2F0000

2FFFFF

300000

30FFFF

310000

31FFFF

320000

32FFFF

330000

33FFFF

340000

34FFFF

350000

35FFFF

370000

37FFFF

380000

38FFFF

390000

39FFFF

3A0000

3AFFFF

3B0000

3BFFFF

3C0000

3CFFFF

3D0000

3DFFFF

3E0000

3EFFFF

3F0000

3FFFFF

360000

36FFFF

400000

420000

43FFFF

41FFFF

440000

45FFFF

460000

47FFFF

480000

49FFFF

4A0000

4BFFFF

4C0000

4DFFFF

4E0000

4FFFFF

500000

51FFFF

520000

53FFFF

540000

55FFFF

560000

57FFFF

580000

59FFFF

5A0000

5BFFFF

5C0000

5DFFFF

5E0000

5FFFFF

600000

61FFFF

620000

63FFFF

640000

65FFFF

660000

67FFFF

680000

69FFFF

6A0000

6BFFFF

6E0000

6FFFFF

700000

71FFFF

720000

73FFFF

740000

75FFFF

760000

77FFFF

780000

79FFFF

7A0000

7BFFFF

7C0000

7DFFFF

7E0000

7FFFFF

6C0000

6DFFFF

Selected by BS=VIH (Bank 1)

LHF12PZ5 8

NOTES:

1. The address A0 and BS don't care.

2. "00H" is presented on DQ15-DQ8 in word mode (BYTE#=VIH : ×16 bit) .

3. Block Address = The beginning location of a block address. DQ15-DQ1 are reserved for future implementation.

Table 3. Identifier Codes Address

Code Address

[A22-A1] (1) Data

[DQ7-DQ0]Notes

Manufacturer Code Manufacturer Code 000000H B0H 2

Device Code Device Code 000001H 18H 2

Block Lock Configuration

Code Block is Unlocked Block

Address

+ 2

DQ0 = 0 3

Block is Locked DQ0 = 1 3

Rev. 0.06

LHF12PZ5 9

Rev. 0.06

Customer Programmable Area Lock Bit (DQ

)

Factory Programmed Area Lock Bit (DQ

)

Customer Programmable Area

Factory Programmed Area

Reserved for Future Implementation

000080H

000081H

000084H

000085H

000FFFH

[A22-A1]

(DQ

-DQ

000100H

000102H

000109H

00010AH

001FFFH

[A22-A0]

Figure 3. OTP Block Address Map

(The area not specified in the above figure cannot be used.)

NOTE:

1. BS must be VIL, when using OTP block.

LHF12PZ5 10

Rev. 0.06

NOTES:

1. Refer to DC Characteristics. When VPEN≤VPENLK, memory contents can be read, but cannot be altered.

2. X can be VIL or VIH for control pins and addresses, and VPENLK or VPENH for V PEN.

Refer to DC Characteristics for VPENLK and VPENH voltages.

3. Refer to Table 2 to determine whether the device is selected or de-selected depending on the state of CE0, CE1 and BS.

4. DQ refers to DQ15-DQ0 in word mode (BYTE#=VIH : ×16 bit) and DQ7-DQ0 in byte mode (BYTE#=VIL : ×8 bit).

5. RP# at GND±0.2V ensures the lowest power consumption.

6. Command writes involving block erase, (page buffer) program, block lock configuration or OTP program are reliably

executed when VPEN=VPENH and VCC=2.7V-3.6V.

7. Refer to Table 5 for valid DIN during a write oper ation. B S transit ions mus t not occu r when CE0=CE1=VIL an d WE#=VIL.

8. Never hold OE# low and WE# low at the same timing.

9. Refer to Appendix of LH28F640SP series for more information about query code.

10. STS is VOL when the WSM (Write State Machine) is executing internal block erase, (page buffer) program or OTP

program algori thms . It is High Z dur i ng when th e WSM is not bus y, in block erase s us pend mode (with prog ram and p age

buffer program inactive), (page buffer) program suspend mode, or reset mode.

Table 4. Bus Operation(1, 2)

Mode Notes RP# CE0,1 (3) OE# WE# Address VPEN DQ (4) STS (10)

Read Array 8VIH Enabled VIL VIH XX

DOUT X

Output Disable VIH Enabled VIH VIH XXHigh ZX

Standby VIH Disabled X X X X High Z X

Reset 5VIL XXXXXHigh ZHigh Z

Read Identifier

Codes/OTP 8VIH Enabled VIL VIH Refer to

Table 3 XRefer to

Table 3 X

Read Query 8,9 VIH Enabled VIL VIH See

Appendix XSee

Appendix X

Write 6,7,8 VIH Enabled VIH VIL XX

DIN X

LHF12PZ5 11

NOTES:

1. Bus operations are defined in Table 4. Each command is valid for the bank to which the command is written.

BS transitions must not occur when CE0=CE1=VIL and WE#=VIL.

2. Bnk=Any valid address within the bank selected by BS.

IA=Identifier codes address (Refer to Table 3).

QA=Query codes address. Refer to Appendix of LH28F640SP series for details.

BA=Address within the block for block erase, page buffer program or set block lock bit.

WA=Address of memory location for the Program command.

OA=Address of OTP block to be read or programmed (Refer to Figure 3).

3. The upper byte of the data bus (DQ15-DQ8) during command writes is ignored in word mode (BYTE#=VIH : ×16 bit).

ID=Data to be read from identifier codes. (Refer to Table 3).

QD=Data to be read from query database. Refer to Appendix of LH28F640SP series for details.

SRD=Data to be read from status register. Refer to Table 7 for a description of the status register bits.

WD=Data to be programmed at location WA. Data is latched on the first edge of CE0 or CE1 that disa bles

the device or the rising edge of WE# (whichever occurs first) during command write cycles.

N-1=N is the number of the words /bytes to be loaded into a page buffer.

OD=Data within OTP block. Data is latched on the first edge of CE 0 or CE1 that disabl es

the device or the rising edge of WE# (whichever occurs first) during command write cycles.

CC=

STS configuration

code (Refer to Table 9). STS configuration must be set for every bank.

4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock

configuration code and the data within OTP block (Refer to Table 3).

The Read Query command is available for reading CFI (Common Flash Interface) information.

5. Block erase or (page buf fe r) program cannot be executed when the selected block is locked. Unlocked block can be erased

or programmed when RP# is VIH.

6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.

7. Following the third bus cycle, write the program sequential address and data of "N" times. Finally, write the any valid

address within the block to be programmed and the confirm command (D0H).

Refer to Appendix of LH28F640SP series for details.

Table 5. Command Definitions (10)

Command Bus

Cycles

Req’d Notes First Bus Cycle Second Bus Cycle

Oper(1) Addr(2) Data(3) Oper(1) Addr(2) Data(3)

Read Array 1 Write Bnk FFH

Read Identifier Codes/OTP ≥ 2 4 Write Bnk 90H Read IA or OA ID or OD

Read Query ≥ 2 4 Write Bnk 98H Read QA QD

Read Status Register 2 Write Bnk 70H Read Bnk SRD

Clear Status Register 1 Write Bnk 50H

Block Erase 2 5 Write BA 20H Write BA D0H

Program 2 5,6 Write WA 40H or

10H Write WA WD

Page Buffer Program ≥ 4 5,7 Write BA E8H Write BA N-1

Block Erase and (Page Buffer)

Program Suspend 1 8 Write Bnk B0H

Block Erase and (Page Buffer)

Program Resume 1 8 Write Bnk D0H

STS Configuration

2 Write Bnk B8H Write Bnk CC

Set Block Lock Bit 2 Write BA 60H Write BA 01H

Clear Block Lock Bits 2 9 Write Bnk 60H Write Bnk D0H

OTP Program 2 Write OA C0H Write OA OD

Rev. 0.06

LHF12PZ5 12

8. If both block erase operation and (page buffer) program operation are suspended, the suspended (page buffer) program

operation is resumed when writing the Block Erase and (Page Buffer) Program Resume (D0H) command.

9. Following the Clear Block Lock Bits command, all the blocks within the bank to which the command is written are

unlocked at a time.

10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be

used.

Rev. 0.06

LHF12PZ5 13

NOTES:

1. Selected block is locked by the Set Block Lock Bit command. Following the Clear Block

Lock Bits command, all the blocks within the bank to which the command is written are

unlocked at a time.

2. Locked and unlocked states remain unchanged even after power-up/down and device reset.

3. After writin g the Read Iden tif ier Codes /OTP command , read oper a tion out p uts the bl ock lock bit

sta tus on D Q0 (refer to Table 3).

4. Erase and program are general terms, respectively, to express: block erase and

(page buf fer) pro gram oper a tio ns.

Table 6. Functions of Block Lock (1), (2)

DQ0(3) State Name Erase/Program Allowed (4)

0 Unlocked Yes

1Locked No

Rev. 0.06

LHF12PZ5 14

Rev. 0.06

Table 7. Status Register Definition

RRRRRRRR

15 14 13 12 11 10 9 8

WSMS BESS BECBLS PBPOPSBLS VPENS PBPSS DPS R

76543210

SR.15 - SR.8 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

0 = Busy

SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)

1 = Block Erase Suspended

0 = Block Erase in Progress/Completed

SR.5 = BLOCK ERASE AND CLEAR BLOCK LOCK

BITS STATUS (BECBLS)

1 = Error in Block Erase or Clear Block Lock Bits

0 = Successful Block Erase or Clear Block Lock Bits

SR.4 = (PAGE BUFFER) PROGRAM, OTP PROGRAM

AND SET BLOCK LOCK BIT STATUS (PBPOPSBLS)

1 = Error in (Page Buffer) Program, OTP Program or Set

Block Lock Bit

0 = Successful (Page Buffer) Program, OTP Program or

Set Block Lock Bit

SR.3 = VPEN STATUS (VPENS)

1 = VPEN LOW Detect, Operation Abort

0 = VPEN OK

SR.2 = (PAGE BUFFER) PROGRAM SUS PEND STATUS

(PBPSS)

1 = (Page Buffer) Program Suspended

0 = (Page Buffer) Program in Progress/Completed

SR.1 = DEVICE PROTECT STATUS (DPS)

1 = Erase or Program Attempted on a

Locked Block, Operation Abort

0 = Unlocked

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTES:

Check SR.7 or STS to determine block erase, (page buffer)

program, block lock configuration or OTP program

completion. SR.6 - SR.1 are invalid while SR.7="0".

If both SR.5 and SR.4 are "1"s after a block erase, page

buffer program, block lock configuration, STS configuration

attempt, an improper command sequence was entered.

SR.3 does not provide a continuous indication of VPEN level.

The WSM interrogates and indicates the VPEN level only

after Block Erase, (Page Buffer) Program, Set Block Lock

Bit, Clear Block Lock Bits or OTP Program command

sequences . SR.3 is not guaranteed to report accur ate feedback

when VPEN≠VPENH or VPENLK.

SR.1 does not provide a continuous indication of block lock

bit. The WSM interrogates the block lock bit only after Block

Erase, (Page Buffer) Program or OTP Program command

seque nces. It inf orms t he sy stem, depending on the att empt ed

operation, if the block lock bit is set . Reading the block lock

configuration codes after writing the Read Identifier Codes/

OTP command indicates block lock bit status.

SR.15 - SR.8 and SR.0 are reserved for future use and should

be masked out when polling the status register.

LHF12PZ5 15

Table 8. Extended Status Register Definition

RRRRRRRR

15 14 13 12 11 10 9 8

SMSRRRRRRR

76543210

XSR.15-8 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

XSR.7 = STATE MACHINE STATUS (SMS)

1 = Page Buffer Program available

0 = Page Buffer Program not available

XSR.6-0 =RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTES:

After issue a Page Buffer Program command (E8H),

XSR.7="1" indicates that the entered command is accepted.

If XSR.7 is "0 ", the co mmand is n ot accepted and a next Page

Buffer Program command (E8H) should be issued again to

check if page buffer is available or not.

XSR.15-8 and XSR.6-0 are reserved for future use and

should be masked out when polling the extended status

Rev. 0.06

LHF12PZ5 16

Rev. 0.06

NOTE:

1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250ns.

2. STS configuration must be set for every bank.

Table 9. STS Configuration Definition (1), (2)

RRRRRRRR

15 14 13 12 11 10 9 8

RRRRRRCCCC

76543210

DQ15-DQ2 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

DQ1-DQ0 = STS CONFIGURATION CODE (CC)

00 = level mode: RY/BY# indication. (Default)

01 = pulse mode on erase complete.

10 = pulse mode on pr ogram complete.

11 = pulse mode on erase or program complete.

In STS configuration = "00", STS is VOL when the WSM is

executing internal erase or program algorithms.

STS configuration codes "01", "10" and "11" are all pulse

modes such that the STS pin pulses low then high when the

operation indicated by the configuration code is completed.

NOTES:

After power-up or device reset, STS configuration is set to

"00".

STS configuration 00

The output of the STS pin is the control signal to prevent

accessing a flash memory while the internal WSM is busy

(SR.7="0").

STS configuration 01

The output of the STS pin is the control signal to indicate

that the erase operation is completed and the flash memory

is available for the next operation.

STS configuration 10

The output of the STS pin is the control signal to indicate

that the program operation is completed and the flash

memory is available for the next operation.

STS configuration 11

The output of the STS pin is the control signal to indicate

that the erase or program operation is completed and the

flash memory is available for the next operation.

LHF12PZ5 17

1 Electrical Specifications

1.1 Absolute Maximum Ratings*

Operating Temperature

During Read, Erase and Program...-40°C to +85°C (1)

Storage Temperature

During under Bias............................... -40°C to +85°C

During non Bias.............................. .. -65°C to +125°C

Voltage On Any Pin (except VCC, VCCQ and VPEN)

...................................................-0.5V to VCCQ+0.5V (2)

VCC and VCCQ Supply Voltage.......... -0.2V to +3.9V (2)

VPEN Supply Voltage.......................... -0.2V to +3.9V (2)

Output Short Circuit Current...........................100mA (3)

*WARNING: Stressing the device beyond the "Absolute

Maximum Ratings" may cause permanent

damage. These are stress ratings only. Operation

beyond the "Operating Conditions" is not

recommended and ex ten ded ex pos ur e beyon d t he

"Operating Conditions" may affect device

reliability.

NOTES:

1. Operating temperature is for extended temperature

product defined by this specification.

2. All specified voltages are with respect to GND.

Minimum DC voltage is -0.5V on input/output pins and

-0.2V on VCC, VCCQ and VPEN pins. During

transitions, this level may undershoot to -2.0V for

periods <20ns. Maximum DC voltage on input/output

pins is VCC+0.5V which, during transitions, may

overshoot to VCC+2.0V for periods <20n s.

3. Output shorted for no more than one second. No more

than one output shorted at a time.

Rev. 0.06

1.2 Operating Conditions

NOTES:

1. Refer to DC Characteristics tables for voltage range-specific specification.

2. VCC and VCCQ should be the same voltage.

Symbol Parameter Notes Min. Typ. Max. Unit Test Conditions

TAOperating Temperature -40 +25 +85 °CAmbient

Temperature

VCC VCC Supply Voltage 1, 2 2.7 3.0 3.6 V

VCCQ I/O Supply Voltage 1, 2 2.7 3.0 3.6 V

VPENH VPEN Voltage 1 2.7 3.0 3.6 V

Block Erase Cycling: VPEN=VPENH 100,000 Cycles

LHF12PZ5 18

TEST POINTSV

CCQ

/2 V

CCQ

/2INPUT

CCQ

0.0

OUTPUT

AC test inputs are driven at V

CCQ

(min) for a Logic "1" and 0.0V for a Logic "0".

Input timing begins, and output timing ends at V

CCQ

/2. Input rise and fall times (10% to 90%) < 5ns.

Worst case speed conditions are when V

(min).

DEVICE

UNDER

TEST

RL=3.3kΩ

VCCQ(min)/2

OUT

CL Includes Jig

Capacitances.

1N914

Figure 5. Transient Equivalent Testing Load Circuit

Rev. 0.06

Table 10. Configuration Capacitance Loading Value

Test Configuration CL (pF)

VCC=2.7V-3.6V 30

1.2.2 AC Input/Output Test Conditions

1.2.1 Capacitance (1) (TA=+25°C, f=1MHz)

NOTE:

1. Sampled, not 100% tested.

Symbol Parameter Min. Typ. Max. Unit Condition

CIN Input Capacit ance 12 16 pF VIN=0.0V

COUT Output Capacitance 16 24 pF VOUT=0.0V

Figure 4. Transient Input/Output Reference Waveform for VCC=2.7V-3.6V

LHF12PZ5 19

Rev. 0.06

1.2.3 DC Characteristics VCC=2.7V-3.6V

Symbol Parameter Notes Min. Typ. Max. Unit Test Cond itions

ILI Input Load Current 1 -2 +2 µAVCC=VCCMax.,

VCCQ=VCCQMax.,

VIN/VOUT=VCCQ or

GND

ILO Output Leakage Current 1 -10 +10 µA

ICCS VCC Standby Current 1, 2, 8

50 120 µA

CMOS Inputs,

VCC=VCCMax.,

VCCQ=VCCQMax.,

Device is disabled

(refer to Table 2),

RP#=VCCQ±0.2V

0.71 2 mA

TTL Inputs,

VCC=VCCMax.,

VCCQ=VCCQMax.,

Device is disabled

(refer to Table 2),

RP#=VIH

ICCAS VCC Automatic Power Savings Current 1, 2, 5 50 120 µA

CMOS Inputs,

VCC=VCCMax.,

VCCQ=VCCQMax.,

Device is enabled

(refer to Table 2)

ICCD VCC Reset Current 150120µARP#=GND±0.2V

IOUT (STS)=0mA

ICCR

Average VCC Page

Mode Read Current 4 word/ 8 byte

read

1, 2 15 20 mA

CMOS Inputs,

VCC=VCCMax.,

VCCQ=VCCQMax.,

Device is enabled

(refer to Table 2),

f=5MHz, IOUT=0mA

1, 2 24 29 mA

CMOS Inputs,

VCC=VCCMax.,

VCCQ=VCCQMax.,

Device is enabled

(refer to Table 2),

f=33MHz, IOUT=0mA

Average VCC Read

Current 1 word/ 1 byte

read 1, 2 40 50 mA

CMOS Inputs,

VCC=VCCMax.,

VCCQ=VCCQMax.,

Device is enabled

(refer to Table 2),

f=5MHz, IOUT=0mA

ICCW VCC (Page Buffer) Program, Set Block

Lock Bit Current

1, 2, 6 35 60 mA CMOS Inputs,

VPEN=VPENH

1, 2, 6 40 70 mA TTL Inputs,

VPEN=VPENH

LHF12PZ5 20

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC=3.0V, VCCQ=3.0V and

TA=+25°C unless VCC is specified.

2. CMOS inputs are either VCCQ±0.2V or GND±0.2V. TTL inputs are either VIL or VIH.

3. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program is executed while in block

erase suspend mode, the device’s current draw is the sum of ICCES and ICCR or ICCW. If read is executed while in (page

buffer) program suspend mode, the device’s current draw is the sum of ICCWS and ICCR.

4. Block erase, (page buffer) program, block lock configuration and OTP program operations are inhibited when

VPEN≤VPENLK or VCC≤VLKO. These operations are not guaranteed outside the specified voltage (VCC=2.7V-3.6V and

VPEN=2.7V-3.6V).

5. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle

completion. Standard address access timings (tAVQV) provide new data when addresses are changed.

6. Sampled, not 100% tested.

7. VPEN is no t us ed for power s upp ly pin. Wi t h V PEN≤VPENLK, block erase, (page buf fer ) p rog ram, block lock configur atio n

and OTP program operations are inhibited.

8. Includes STS.

ICCE VCC Block Erase, Clear Block Lock

Bits Current

1, 2, 6 35 70 mA CMOS Inputs,

VPEN=VPENH

1, 2, 6 40 80 mA TTL Inputs,

VPEN=VPENH

ICCWS

ICCES

VCC (Page Buffer) Program or

Block Erase Suspend Current 1, 3 10 mA Device is disabled

(refer to Table 2).

VIL Input Low Voltage 6 -0.5 0.8 V

VIH Input High Voltage 6 2.0 VCCQ

+ 0.5 V

VOL Output Low Vo ltage 6, 8

0.4 V

VCC=VCCMin.,

VCCQ=VCCQMin.,

IOL=2mA

0.2 V

VCC=VCCMin.,

VCCQ=VCCQMin.,

IOL=100µA

VOH Output High Voltage 6, 8

0.85×

VCCQ V

VCC=VCCMin.,

VCCQ=VCCQMin.,

IOH=-1.5mA

VCCQ

-0.2 V

VCC=VCCMin.,

VCCQ=VCCQMin.,

IOH=-100µA

VPENLK VPEN Lockout Voltage during Normal

Operations 4, 6, 7 1.0 V

VPENH

VPEN Voltage during Block Erase,

(Page Buffer) Program, Set Block Lock

Bit, Clear Block Lock Bits or OTP

Program Operations

4, 7 2.7 3.0 3.6 V

VLKO VCC Lockout Voltage 42.0 V

VCC=2.7V-3.6V

Symbol Parameter Notes Min. Typ. Max. Unit Test Cond itions

Rev. 0.06

DC Characteristics (Continued)

LHF12PZ5 21

1.2.4 AC Characteristics - Read-Only Operations (1)

NOTES:

1. Refer to AC input/output reference waveform for timing measurements and maximum allowable input slew rate.

2. Sampled, not 100% tested.

3. OE# may be delayed up to tELQV ⎯ tGLQV after the first edge of CE0, CE1 or BS that enables the device

(refer to Table 2) without impact to tELQV.

4. The timing is defined from the first edge of CE0, CE1 or BS that enables the device.

5. The timing is defined from the first edge of CE0, CE1 or BS that disables the device.

TA=-40°C to +85°C

VCC 3.0V-3.6V 2.7V-3.6V

VCCQ 3.0V-3.6V 2.7V-3.6V

Symbol Parameter

Notes

Min. Max. Min. Max. Unit

tAVAV Read Cycle Time 120 120 ns

tAVQ V Address to Output Delay 120 120 ns

tELQV CEX to Output Delay 3, 4 120 120 ns

tAPA Page Address Access Time 25 30 ns

tGLQV OE# to Output Delay 3 25 30 ns

tPHQV RP# High to Output Delay 180 180 ns

tELQX CEX to Output in Low Z 2, 4 0 0 ns

tGLQX OE# to Output in Low Z 2 0 0 ns

tEHQZ CEX to Output in High Z 2, 5 35 35 ns

tGHQZ OE# to Output in High Z 2 15 15 ns

tOH Output Hold from First Occurring Address, CEX or OE#

change 2, 5 0 0 ns

tELFL/tELFH CEx Setup to BYTE# Going Low or High 2, 4 10 10 ns

tFLQV/tFHQV BYTE# to Output Delay 1000 1000 ns

tFLQZ/tFHQZ BYTE# to Output in High Z 2 1000 1000 ns

Rev. 0.06

LHF12PZ5 22

tAVQV

tEHQZ

tGHQZ

tELQV

tPHQV

tGLQV

tOH

VIH

VIL

Disabled (VIH)

Enabled (VIL)

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

(P)

(D/Q)

(W)

(G)

(E)

(A)BS

DQ15-0

CEX

OE#

WE#

RP#

High Z

tELQX

VALID

OUTPUT

VALID

INPUT

tGLQX

VIH

VIL

(F)

BYTE#

tAVAV

tFLQZ/tFHQZ

tFLQV/tFHQV

tELFL/tELFH

VIH

VIL

(A)A22-0 VALID

ADDRESS

Figure 6. AC Waveform for 1-Word/ 1-Byte Read Operations

(Status Register, Identifier Codes, OTP Block or Query Code)

Rev. 0.06

NOTE:

1. Status register, identifier codes, OTP block and query code can only be read in 1 word/ 1 byte

read operations .

LHF12PZ5 23

tAVQV

tELQV tEHQZ

tGHQZ

tOH

tAPA

tGLQV

tPHQV

High Z

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

(P)

(W)

(G)

VIH

VIL

(A)A2-1

(D/Q)

DQ15-0

OE#

WE#

RP#

tGLQX

tELQX

VALID

ADDRESS VALID

ADDRESS

VALID

OUTPUT VALID

OUTPUT

VALID

ADDRESS

VIH

VIL

(A)A22-3 VALID

ADDRESS

Disabled (VIH)

Enabled (VIL)

(E)

CEX

VIH

VIL

(F)

BYTE#

tFHQZ

tFHQV

tELFH

VIH

VIL

(A)BS VALID

INPUT

Figure 7. AC Waveform for 4-Word Page Mode Read Operations

(Memory Array)

Rev. 0.06

NOTE:

1. Memory array supports page mode read operations.

LHF12PZ5 24

Figure 8. AC Waveform for 8-Byte Page Mode Read Operations

(Memory Array)

Rev. 0.06

tAVQV

tELQV

tEHQZ

tGHQZ

tOH

tAPA

tPHQV

High Z

VIH

VIL

VIH

VIL

VOH

VOL

VIH

VIL

(P)

(W)

(G)

VIH

VIL

(A)A2-0

(D/Q)

DQ7-0

OE#

WE#

RP#

tGLQX

tELQX

VALID

ADDRESS

VIH

VIL

(A)A22-3 VALID

ADDRESS

Disabled (VIH)

Enabled (VIL)

(E)

CEX

VIH

VIL

(F)

BYTE#

tFLQZ

tELFL

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

tFLQV

tGLQV

VIH

VIL

(A)BS VALID

INPUT

NOTE:

1. Memory array supports page mode read operations.

LHF12PZ5 25

Rev. 0.06

1.2.5 AC Characteristics - Write Operations (1), (2)

NOTES:

1. The timing characteristics for reading the status register during block erase, (page buffer) program, block lock

configuration and OTP program operations are the same as during read-only operations. Refer to AC Characteristics for

read-only operations.

2. A write operation can be initiated and terminated with either CE0, CE1 or WE#.

BS transitions must not occur when CE0=CE1=VIL and WE#=VIL.

3. Sampled, not 100% tested.

4. Write pulse width low (tWP) is defined from the first edge of CE0 or CE1 that enables the device or the falling edge of

WE# (whichever oc curs last) to the firs t edge of CE0 or CE1 that disables the device or the rising edge of WE # (whichever

occurs first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH.

5. Write pulse width high (tWPH) is defined from the first edge of CE0 or CE1 that disables the device or the rising edge of

WE# (whichever occurs first) to the first edge of CE0 or CE1 that enables the device or the falling edge of WE#

(whichever occurs last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL.

6. VPEN should be held at VPEN=VPENH until determination of block erase, (page buffer) program, block lock configuration

or OTP program success (SR.1/3/4/5=0).

7. Refer to Table 5 for valid address and data for block erase, (page buffer) program, block lock configuration and OTP

program.

8. The output delay time tAVQV or tELQV is required in addition to tWHGL (tEHGL) for read operations after command writes.

9. The timing is defined from the first edge of CE0 or CE1 that enables the device.

10. The timing is defined from the first edge of CE0 or CE1 that disables the device.

11. STS timings depend on STS configuration.

VCC=2.7V-3.6V, TA=-40°C to +85°C

Symbol Parameter Notes Min. Max. Unit

tAVAV Write Cycle Time 120 ns

tPHWL (tPHEL)

RP# High Recovery to WE# (

CEX

) Going Low

3, 9 1 µs

tELWL (tWLEL)CE

X (WE#) Setup to WE# (CEX) Going Low 90 ns

tWLWH (tELEH)WE# (CE

X) Pulse Width Low 4, 9, 10 70 ns

tDVWH (tDVEH) Data Setup to WE# (CEX) Going High 7, 10 50 ns

tAVWH (tAVEH) Address Setup to WE# (CEX) Going High 7, 10 55 ns

tWHEH (tEHWH)CE

X (WE#) Hold from WE# (CEX) High 10 0 ns

tWHDX (tEHDX) Data Hold from WE# (CEX) High 10 0 ns

tWHAX (tEHAX) Address Hold from WE# (CEX) High 10 0 ns

tWHWL (tEHEL)WE# (CE

X) Pulse Width High 5, 9, 10 30 ns

tVVWH (tVVEH)V

PEN Setup to WE# (CEX) Going High 3, 10 0 ns

tWHGL (tEHGL)Write R ecovery before Read 8 35 ns

tWHR0 (tEHR0)

tWHRL (tEHRL)WE# (CEX) High to SR.7 Going "0", STS Going Low 10, 11 500 ns

tQVVL VPEN Hold from Valid SRD, STS Hig h Z 3, 6, 1 1 0 ns

tFLWH/tFHWH

(tFLEH/tFHEH)BYTE# Setup to WE# (CEX) Going High 10 50 ns

tWHFL/tWHFH

(tEHFL/tEHFH)BYTE# Hold from WE# (CEX) High 10 90 ns

LHF12PZ5 26

tWHAX

(tEHAX)

tELWL (tWLEL)

tPHWL (tPHEL)

tWLWH

tWHWL (tEHEL)

tWHDX (tEHDX)tDVWH (tDVEH)

tVVWH (tVVEH)

tWHQV1,2,3,4,5,6

(tEHQV1,2,3,4,5,6)

tQVVL

tWHEH (tEHWH)t

WHGL (tEHGL)

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

(D/Q)

(W)

(G)

(A)BS

DQ15-0

(V)

VPEN

VIH

VPENH

VPENLK

VIL

(P)

RP#

OE#

WE#

VIH

VIL

(F)BYTE#

(tELEH )

VALID

INPUT VALID

INPUT

DATA IN DATA IN VALID

SRD

("1")

VOL

(R)

STS

(SR.7)

High Z

("0")

(tWHR0 (tEHR0))

tWHRL (tEHRL)

Disabled (VIH)

Enabled (VIL)

(E)

CEX

tFLWH/tFHWH

(tFLEH/tFHEH)tWHFL/tWHFH

(tEHFL/tEHFH)

NOTE 4

NOTES 5, 6

NOTES:

1. VCC power-up and standby.

2. Write each first cycle command.

3. Write each second cycle command or valid address and data.

4. Automated erase or program delay. This waveform illustrates the case when STS is in level mode (RY/BY#).

5. Read status register data.

6. For read operation, OE# and CEX must be driven active, and WE# de-asserted.

tAVAV tAVWH (tAVEH)

VIH

VIL

(A)A22-0 VALID

ADDRESS VALID

ADDRESS

NOTE 1 NOTE 2 NOTE 3

Figure 9. AC Waveform for Write Operations

Rev. 0.06

LHF12PZ5 27

tPLPH

t2VPH

tPLRH tPHQV

tPHQV

(A) Reset during Read Array Mode

(B) Reset during Erase or Program Mode

RP#

VIL

VIH

VIL

VIH

VCC GND

VCC(min)

RP# VIL

VIH

SR.7="1"

VOH

VOL

(D/Q)

DQ15-0 VALID

OUTPUT

High Z

(P)

VOH

VOL

(D/Q)

DQ15-0 VALID

OUTPUT

High Z

VOH

VOL

(D/Q)

DQ15-0 VALID

OUTPUT

High Z

tPHQV

tVHQV

ABORT

COMPLETE

NOTES:

1. A reset time, tPHQV, is required from the later of SR.7 (STS) going "1" (High Z) or RP# going high until outputs are valid.

Refer to AC Characteristics - Read-Only Operations for tPHQV.

2. The device may reset if tPLPH is <100ns, but this is not guaranteed.

3. Sampled, not 100% tested.

4. If RP# asserted while a block erase, (page buffer) program, block lock configuration or OTP program operation is not

executing, the reset will complete within 100ns.

5. When the dev ice powe r-up, hol d in g RP # low mini mu m 100 ns is requi r e d afte r VCC has been in predefined range and also

has been in stable there.

Reset AC Specifications (VCC=2.7V-3.6V, TA=-40°C to +85°C)

Symbol Parameter Notes Min. Max. Unit

tPLPH RP# Low to Reset during Read

(RP# must be low during power-up.) 1, 2, 3 100 n s

tPLRH RP# Low to Reset during Erase or Program 1, 3, 4 30 µs

t2VPH VCC 2.7V to RP# High 1, 3, 5 100 n s

tVHQV VCC 2.7V to Output Delay 31ms

Figure 10. AC Waveform for Reset Operations

Rev. 0.06

1.2.6 Reset Operations

LHF12PZ5 28

Rev. 0.06

1.2.7 Block Erase, (Page Buffer) Program and Block Lock Configuration Performance(3)

NOTES:

1. Typical values measured at VCC=3.0 V, VPEN=3.0V and TA=+25°C. Assumes corresponding lock bits

are not set. Subject to change based on device characterization.

2. Excludes external system-level overhead.

3. Sampled, but not 100% tested.

4. A latency time is required from writing suspend command (the first edge of CE0 or CE1 that disables

the device or the rising edge of WE#) until SR.7 going "1" or STS going High Z.

5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter

than tERES and its sequence is repeated, the block erase operation may not be finished.

6. These values are valid when the page buffer is full, and the start address is aligned on a 16-word/ 32-byte boundary.

7. Program time per byte (tWHQV1/ tEHQV1) is 12.5µs/byte (typical).

Program time per word (tWHQV2/ tEHQV2) is 25.0µs/word (typical).

VCC=2.7V-3.6V, TA=-40°C to +85°C

Symbol Parameter Notes VPEN=VPENH Unit

Min. Typ.(1)

Max.

Page Buffer Program Time

(Time to Program 16 words/ 32 bytes) 2, 6,

7400 1200 µs

tWHQV3/

tEHQV3 Program Time 2 210 630 µs

Block Pr ogr am Time

(Using Page Buffer Program Command) 21.64.8s

tWHQV4/

tEHQV4 Block Erase Time 2 1 5 s

tWHQV5/

tEHQV5 Set Block Lock Bit Time 2 64 85 µs

tWHQV6/

tEHQV6 Clear Block Lock Bits Time 2 0.5 0.7 s

tWHRH1/

tEHRH1

(Page Buffer) Program Suspend

Latency Time to Read 42590µs

tWHRH2/

tEHRH2

Block Erase Suspend

Latency Time to Read 42640µs

tERES

Lat ency Time from B lock E rase

Resume Command to Block

Erase Suspend Command 5 600 µs

LHF12PZ5 29

Rev. 0.06

2 Related Document Information(1)

NOTE:

1. International customers should contact their local SHARP or distribution sales offices.

Document No. Document Name

FUM03201 LH28F640SP series Appendix

030313

A-1 RECOMMENDED OPERATING COND ITIONS

A-1.1 At Device Power-Up

AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.

If the timing in the figure is ignored, the device may not operate correctly.

Figure A-1. AC Timing at Device Power-Up

For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“

described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in

the next page.

t2VPH

GND

VCC(min)

RP#

VIL

VIH

(P)

tPHQV

VPEN *1

GND

VPENH

(V)

WE#

VIL

VIH

(W)

OE#

VIL

VIH

(G)

VOH

VOL

(D/Q)

DATA High Z Valid

Output

tVR

tFtELQV

tFtGLQV

(A)ADDRESS Valid

(RST#)

(VPP)

tR or tF

Address

VIL

VIH

tAVQV tR or tF

*1 To prevent the unwanted writes, system designers should consider the design, which applies VPEN (VPP)

to 0V during read operations and VPENH (VPPH) during write or erase operations.

(VPPH)

See the application note AP-007-SW-E for details.

Disabled (VIH)

Enabled (VIL)

(E)

CEX

VCC

VCCQ

030313

A-1.1.1 Rise a nd F a ll Time

NOTES:

1. Sampled, not 100% tested.

2. This specification is applied for not only the device power-up but also the normal operations.

Symbol Parameter Notes Min. Max. Unit

tVR VCC Rise Time 1 0.5 30000 µs/V

tRInput Signal Rise Time 1, 2 1 µs/V

tFInput Signal Fall Time 1, 2 1 µs/V

030313

iii

A-1.2 Glitch Noises

Do n ot input th e g li tch no is es whic h are bel ow V IH (M in.) o r a bov e VIL ( M ax.) on add res s, data, reset , a nd c ont rol s ign als,

as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).

Figure A-2. Waveform for Glitch Noises

See the “DC CHARACTERISTICS“ described in specifications for VIH (Min.) and VIL (Max.).

(a) Acceptable Glitch Noises

Input Signal

VIH (Min.)

Input Signal

VIH (Min.)

Input Signal

VIL (Max.)

Input Signal

VIL (Max.)

(b)

NOT

Acceptable Glitch Noises

030313

A-2 RELATED DOCUMENT INFORMATION(1)

NOTE:

1. International customers should contact their local SHARP or distribution sales office.

Document No. Document Name

AP-001-SD-E Flash Memory Family Software Drivers

AP-006-PT-E Data Protection Method of SHARP Flash Memory

AP-007-SW-E RP#, VPP Electric Potential Switc hing Circuit

SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited 

Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. 

ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND 

FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,

for any incidental or consequential economic or property damage.

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