PRELIMINARY PRODUCT SPECIFICATION 1 Z86E30/E31/E40 1 Z8 4K OTP MICROCONTROLLER FEATURES Device ROM (KB) RAM* (Bytes) I/O Lines Speed (MHz) Z86E30 Z86E31 Z86E40 4 2 4 237 125 236 24 24 32 16 16 16 Programmable OTP Options: RC Oscillator EPROM Protect Auto Latch Disable Permanently Enabled WDT Crystal Oscillator Feedback Resistor Disable RAM Protect Low-Power Consumption: 60 mW Fast Instruction Pointer: 0.75 s Note: *General-Purpose Standard Temperature (VCC = 3.5V to 5.5V) Extended Temperature (VCC = 4.5V to 5.5V) Available Packages: 28-Pin DIP/SOIC/PLCC OTP (Z86E30/31 only) 40-Pin DIP OTP (Z86E40 only) PLCC/LQFP OTP (Z86E40 only) 44-Pin PLCC/QFP OTP (Z86E40 only) Two Standby Modes: STOP and HALT Digital Inputs CMOS Levels, Schmitt-Triggered Software Programmable Low EMI Mode Software Enabled Watch-Dog Timer (WDT) Push-Pull/Open-Drain Programmable on Port 0, Port 1, and Port 2 Two Programmable 8-Bit Counter/Timers Each with a 6-Bit Programmable Prescaler Six Vectored, Priority Interrupts from Six Different Sources Two Comparators On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive 24/32 Input/Output Lines Auto Latches Auto Power-On Reset (POR) GENERAL DESCRIPTION The Z86E30/E31/E40 8-Bit One-Time Programmable (OTP) Microcontrollers are members of Zilog's single-chip Z8(R) MCU family featuring enhanced wake-up circuitry, programmable Watch-Dog Timers, Low Noise EMI options, and easy hardware/software system expansion capability. Four basic address spaces support a wide range of memory configurations. The designer has access to three additional control registers that allow easy access to register mapped peripheral and I/O circuits. DS97Z8X0502 For applications demanding powerful I/O capabilities, the Z86E30/E31 have 24 pins, and the Z86E40 has 32 pins of dedicated input and output. These lines are grouped into four ports, eight lines per port, and are configurable under software control to provide timing, status signals, and parallel I/O with or without handshake, and address/data bus for interfacing external memory. Notes: All signals with a preceding front slash, "/", are active Low. For example, B/W (WORD is active Low); B/W (BYTE is active Low, only). PRELIMINARY 1 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Power connections follow conventional descriptions below: Connection Circuit Device Power VCC VDD Ground GND VSS (E40 Only) Output Input VCC GND XTAL AS DS R/W RESET Machine Timing & Instruction Control Port 3 Counter/ Timers (2) RESET WDT, POR ALU FLAGS Interrupt Control OTP Two Analog Comparators Register Pointer Register File Program Counter Port 0 Port 1 Port 2 4 I/O (Bit Programmable) 4 Address or I/O (Nibble Programmable) 8 Address/Data or I/O (Byte Programmable) (E40 Only) Figure 1. Z86E30/E31/E40 Functional Block Diagram 2 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog D7 - 0 1 AD 11- 0 Z8 MCU MSN Port 3 AD 11- 0 Address MUX D7 - 0 AD 11- 0 EPROM TEST ROM Z8 Port 0 Data MUX D7 - 0 Z8 Port 2 OTP Options PGM + Test Mode Logic VPP P33 EPM P32 OE P31 PGM P30 CE XT1 Figure 2. EPROM Programming Block Diagram DS97Z8X0502 PRELIMINARY 3 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog PIN IDENTIFICATION Table 1. 40-Pin DIP Pin Identification Standard Mode R/W P25 P26 P27 P04 P05 P06 P14 P15 P07 VCC P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 AS 1 40 40-Pin DIP 20 21 DS P24 P23 P22 P21 P20 P03 P13 P12 GND P02 P11 P10 P01 P00 P30 P36 P37 P35 RESET Figure 3. 40-Pin DIP Pin Configuration Standard Mode 4 Pin # Symbol Function Direction 1 2-4 5-7 8-9 10 11 R/W P25-P27 P04-P06 P14-P15 P07 VCC Read/Write Port 2, Pins 5,6,7 Port 0, Pins 4,5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply Output In/Output In/Output In/Output In/Output 12-13 14 15 16-18 19 20 21 22 23 24 25 26-27 28-29 30 31 32-33 34 35-39 40 P16-P17 XTAL2 XTAL1 P31-P33 P34 AS RESET P35 P37 P36 P30 P00-P01 P10-P11 P02 GND P12-P13 P03 P20-P24 DS Port 1, Pins 6,7 Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Ground Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe In/Output Output Input Input Output Output Input Output Output Output Input In/Output In/Output In/Output PRELIMINARY In/Output In/Output In/Output Output DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog P20 P03 P13 P12 GND GND P02 P11 P10 P01 P00 1 6 1 40 39 7 44-Pin PLCC 17 29 28 18 P30 P36 P37 P35 RESET R/RL AS P34 P33 P32 P31 P05 P06 P14 P15 P07 VCC VCC P16 P17 XTAL2 XTAL1 P21 P22 P23 P24 DS NC R/W P25 P26 P27 P04 Figure 4. 44-Pin PLCC Pin Configuration Standard Mode Table 2. 44-Pin PLCC Pin Identification Pin # Symbol Function 1-2 3-4 5 6-10 11 12 13 14-16 17-19 20-21 22 23-24 GND P12-P13 P03 P20-P24 DS NC R/W P25-P27 P04-P06 P14-P15 P07 VCC Ground Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe No Connection Read/Write Port 2, Pins 5,6,7 Port 0, Pins 4,5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply 25-26 27 28 29-31 32 P16-P17 XTAL2 XTAL1 P31-P33 P34 Port 1, Pins 6,7 Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pin 4 DS97Z8X0502 Direction In/Output In/Output In/Output Output Output In/Output In/Output In/Output In/Output Table 2. 44-Pin PLCC Pin Identification Pin # Symbol Function Direction 33 34 35 36 37 38 39 40-41 42-43 44 AS R/RL RESET P35 P37 P36 P30 P00-P01 P10-P11 P02 Address Strobe ROM/ROMless select Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1 Port 1, Pins 0,1 Port 0, Pin 2 Output Input Input Output Output Output Input In/Output In/Output In/Output In/Output Output Input Input Output PRELIMINARY 5 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog P20 P03 P13 P12 GND GND P02 P11 P10 P01 P00 PIN IDENTIFICATION (Continued) 33 23 22 34 P21 P22 P23 P24 DS NC R/W P25 P26 P27 P04 44-Pin 44-PinLQFP QFP 12 11 44 P05 P06 P14 P15 P07 VCC VCC P16 P17 XTAL2 XTAL1 1 P30 P36 P37 P35 RESET R/RL AS P34 P33 P32 P31 Figure 5.5.44-Pin LQFP Configuration Figure 44-Pin QFPPin Pin Configuration Standard ModeMode Standard Table LQFP Pin Identification Table3.3.44-Pin 44-Pin QFP Pin Identification Table LQFP PinPin Identification Table3.3.44-Pin 44-Pin QFP Identification Pin # Symbol Function Direction Pin # Symbol Function Direction 1-2 3-4 5 6-7 P05-P06 P14-P15 P07 VCC Port 0, Pins 5,6 Port 1, Pins 4,5 Port 0, Pin 7 Power Supply In/Output In/Output In/Output P16-P17 XTAL2 XTAL1 P31-P33 P34 AS R/RL RESET P35 P37 P36 P30 P00-P01 P10-P11 Port 1, Pins 6,7 Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pin 4 Address Strobe ROM/ROMless select Reset Port 3, Pin 5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pin 0,1 Port 1, Pins 0,1 In/Output Output Input Input Output Output Input Input Output Output Output Input In/Output In/Output P02 GND P12-P13 P03 P20-4 DS NC R/W P25-P27 P04 Port 0, Pin 2 Ground Port 1, Pins 2,3 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 Data Strobe No Connection Read/Write Port 2, Pins 5,6,7 Port 0, Pin 4 In/Output 8-9 10 11 12-14 15 16 17 18 19 20 21 22 23-24 25-26 27 28-29 30-31 32 33-37 38 39 40 41-43 44 6 PRELIMINARY In/Output In/Output In/Output Output Output In/Output In/Output DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Table 4. 40-Pin DIP Package Pin Identification EPROM Mode NC D5 D6 D7 A4 A5 A6 NC NC A7 VCC NC NC NC CE OE EPM VPP A8 NC 1 40 40-Pin DIP 20 21 NC D4 D3 D2 D1 D0 A3 NC NC GND A2 NC NC A1 A0 PGM A10 A11 A9 NC Figure 6. 40-Pin DIP Pin Configuration EPROM Mode DS97Z8X0502 Pin # Symbol Function 1 2-4 5-7 8-9 10 11 NC D5-D7 A4-A6 NC A7 VCC No Connection Data 5,6,7 Address 4,5,6 No Connection Address 7 Power Supply 12-14 15 16 17 18 NC CE OE EPM VPP No Connection Chip Select Output Enable EPROM Prog. Mode Prog. Voltage 19 20-21 22 23 24 25 26-27 28-29 30 31 32-33 34 35-39 40 A8 NC A9 A11 A10 PGM A0-A1 NC A2 GND NC A3 D0-D4 NC Address 8 No Connection Address 9 Address 11 Address 10 Prog. Mode Address 0,1 No Connection Address 2 Ground No Connection Address 3 Data 0,1,2,3,4 No Connection PRELIMINARY 1 Direction In/Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input In/Output 7 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog D0 A3 NC NC GND GND A2 NC NC A1 A0 PIN IDENTIFICATION (Continued) 6 1 40 39 7 44-Pin PLCC 17 29 28 18 PGM A10 A11 A9 NC NC NC A8 VPP EPM OE A5 A6 NC NC A7 VCC VCC NC NC NC CE D1 D2 D3 D4 NC NC NC D5 D6 D7 A4 Figure 7. 44-Pin PLCC Pin Configuration EPROM Programming Mode Table 5. 44-Pin PLCC Pin Configuration EPROM Programming Mode Pin # Symbol Function 1-2 3-4 5 6-10 11-13 14-16 17-19 20-21 22 23-24 GND NC A3 D0-D4 NC D5-D7 A4-A6 NC A7 VCC Ground No Connection Address 3 Data 0,1,2,3,4 No Connection Data 5,6,7 Address 4,5,6 No Connection Address 7 Power Supply 25-27 28 29 30 NC CE OE EPM No Connection Chip Select Output Enable EPROM Prog. Mode 8 Direction Input In/Output In/Output Input Input Table 5. 44-Pin PLCC Pin Configuration EPROM Programming Mode Pin # Symbol Function Direction 31 VPP Prog. Voltage Input 32 33-35 36 37 38 39 40-41 42-43 44 A8 NC A9 A11 A10 PGM A0,A1 NC A2 Address 8 No Connection Address 9 Address 11 Address 10 Prog. Mode Address 0,1 No Connection Address 2 Input Input Input Input Input Input Input Input Input Input PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog D0 A3 NC NC GND GND A2 NC NC A1 A0 1 33 D1 D2 D3 D4 NC NC NC D5 D6 D7 A4 23 22 34 44-Pin LQFP 44 -Pin QFP 12 11 44 A5 A6 NC NC NC A7 VCC VCC NC NC CE 1 PGM A10 A11 A9 NC NC NC A8 VPP EPM OE Figure Figure8.8.44-Pin 44-PinLQFP QFP Pin Pin Configuration Configuration EPROM Programming Mode EPROM Programming Mode Table Pin Identification Configuration Table 6. 6. 44-Pin 44-PinLQFP QFP Pin EPROM EPROMProgramming ProgrammingMode Mode Table Pin Identification Configuration Table 6. 6. 44-Pin 44-PinLQFP QFP Pin EPROM Programming EPROM ProgrammingMode Mode Pin # Symbol Function Direction Pin # Symbol Function Direction 1-2 3-4 5 6-7 A5-A6 NC A7 VCC Address 5,6 No Connection Address 7 Power Supply Input NC CE OE EPM 14 VPP No Connection Chip Select Output Enable EPROM Prog. Mode Prog. Voltage A0,A1 NC A2 GND NC A3 D0-D4 NC D5-D7 A4 Address 0,1 No Connection Address 2 Ground No Connection Address 3 Data 0,1,2,3,4 No Connection Data 5,6,7 Address 4 Input 8-10 11 12 13 23-24 25-26 27 28-29 30-31 32 33-37 38-40 41-43 44 15 16-18 19 20 21 22 A8 NC A9 A11 A10 PGM Address 8 No Connection Address 9 Address 11 Address 10 Prog. Mode DS97Z8X0502 Input Input Input Input Input Input Input In/Output In/Output Input Input Input Input Input Input PRELIMINARY 9 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog PIN IDENTIFICATION (Continued) P25 P26 P27 P04 P05 P06 P07 VCC XTAL2 XTAL1 P31 P32 P33 P34 1 28 28-Pin DIP 14 15 P24 P23 P22 P21 P20 P03 VSS P02 P01 P00 P30 P36 P37 P35 D5 D6 D7 A4 A5 A6 A7 VCC NC CE OE EPM VPP A8 Figure 9. Standard Mode 28-Pin DIP/SOIC Pin Configuration 1 28 28-Pin DIP 14 15 D4 D3 D2 D1 D0 A3 VSS A2 A1 A0 PGM A10 A11 A9 Figure 10. EPROM Programming Mode 28-Pin DIP/SOIC Pin Configuration Table 7. 28-Pin DIP/SOIC/PLCC Pin Identification* Function Direction 1-3 4-7 8 P25-P27 P04-P07 VCC Port 2, Pins 5,6, In/Output Port 0, Pins 4,5,6,7 In/Output Power Supply 9 10 11-13 14-15 16 17 18 19-21 22 XTAL2 XTAL1 P31-P33 P34-P35 P37 P36 P30 P00-P02 VSS Crystal Oscillator Crystal Oscillator Port 3, Pins 1,2,3 Port 3, Pins 4,5 Port 3, Pin 7 Port 3, Pin 6 Port 3, Pin 0 Port 0, Pins 0,1,2 Ground Output Input Input Output Output Output Input In/Output 23 24-28 P03 P20-P24 Port 0, Pin 3 Port 2, Pins 0,1,2,3,4 In/Output In/Output P04 P27 P26 P25 P24 P23 P22 Symbol 4 XXX P05 P06 XXX P07 XXX VCC XXX XXX XT2 XXX XT1 XXX P31 1 5 26 25 28-Pin PLCC 11 12 19 18 P21 XXX XXX P20 XXX P03 XXX V SS XXX P02 XXX P01 XXX P00 P32 P33 P34 P35 P37 P36 P30 Pin # Figure 11. Standard Mode 28-Pin PLCC Pin Configuration 10 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog A4 D7 D6 D5 D4 D3 D2 Table 8. 28-Pin EPROM Pin Identification 4 1 5 26 25 28-Pin PLCC 19 18 D1 XXX XXX D0 XXX A3 XXX V SS XXX A2 XXX A1 XXX A0 A8 A9 A11 A10 PGM 11 12 EPM VPP XXX A5 XXX A6 XXX A7 VCC XXX XXX NC XXX CE XXX OE Figure 12. EPROM Programming Mode 28-Pin PLCC Pin Configuration DS97Z8X0502 Pin # Symbol Function Direction 1-3 4-7 8 D5-D7 A4-A7 VCC Data 5,6,7 Address 4,5,6,7 Power Supply In/Output Input 9 10 11 12 NC CE OE EPM 13 VPP No connection Chip Select Output Enable EPROM Prog. Mode Prog. Voltage 14-15 16 17 18 19-21 22 A8-A9 A11 A10 PGM A0-A2 VSS Address 8,9 Address 11 Address 10 Prog. Mode Address 0,1,2 Ground Input Input Input Input Input 23 24-28 A3 D0-D4 Address 3 Data 0,1,2,3,4 Input In/Output PRELIMINARY 1 Input Input Input Input 11 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog ABSOLUTE MAXIMUM RATINGS Parameter Min Max Units Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS [Note 1] -40 -65 -0.6 +105 +150 +7 C C V Voltage on VDD Pin with Respect to VSS -0.3 +7 V Voltage on XTAL1 and RESET Pins with Respect to VSS [Note 2] -0.6 VDD+1 V Total Power Dissipation Maximum Allowable Current out of VSS 1.21 220 W mA Maximum Allowable Current into VDD 180 mA +600 +600 25 25 3 mA A A mA mA Maximum Allowable Current into an Input Pin [Note 3] Maximum Allowable Current into an Open-Drain Pin [Note 4] Maximum Allowable Output Current Sinked by Any I/O Pin Maximum Allowable Output Current Sourced by Any I/O Pin Maximum Allowable Output Current Sinked by RESET Pin -600 -600 Notes: 1. This applies to all pins except XTAL pins and where otherwise noted. 2. There is no input protection diode from pin to VDD. 3. This excludes XTAL pins. 4. Device pin is not at an output Low state. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Total power dissipation should not exceed 1.2 W for the package. Power dissipation is calculated as follows: Total Power Dissipation = VDD x [ IDD - (sum of IOH) ] + sum of [ (VDD - VOH) x IOH ] + sum of (V0L x I0L) STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Test Load). From Output Under Test 150 pF Figure 13. Test Load Diagram 12 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog CAPACITANCE TA = 25C, VCC = GND = 0V, f = 1.0 MHz; unmeasured pins returned to GND. Parameter Min Max 0 0 0 12 pF 12 pF 12 pF Input capacitance Output capacitance I/O capacitance 1 DC ELECTRICAL CHARACTERISTICS TA= 0 C to +70 C Sym Parameter VCC Note [3] Min Max Typical @ 25C Units Conditions Notes VCH Clock Input High Voltage 3.5V 5.5V 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 1.8 2.5 V V Driven by External Clock Generator VCL Clock Input Low Voltage 3.5V 4.5V GND -0.3 GND -0.3 0.2 VCC 0.2 VCC 0.9 1.5 V V Driven by External Clock Generator VIH Input High Voltage 3.5V 5.5V 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 2.5 2.5 V V VIL Input Low Voltage 3.5V 5.5V GND -0.3 GND -0.3 0.2 VCC 0.2 VCC 1.5 1.5 V V VOH Output High Voltage Low EMI Mode 3.5V 5.5V VCC -0.4 VCC -0.4 3.3 4.8 V V IOH = - 0.5 mA VOH1 Output High Voltage 3.5V 5.5V VCC -0.4 VCC -0.4 3.3 4.8 V V IOH = -2.0 mA IOH = -2.0 mA VOL Output Low Voltage Low EMI Mode 3.5V 4.5V 0.4 0.4 0.2 0.2 V V IOL = 1.0 mA IOL = 1.0 mA VOL1 Output Low Voltage 3.5V 4.5V 0.4 0.4 0.1 0.1 V V IOL = + 4.0 mA IOL = + 4.0 mA 8 8 VOL2 Output Low Voltage 3.5V 4.5V 1.2 1.2 0.5 0.5 V V IOL = + 12 mA IOL = + 12 mA 8 8 VRH Reset Input High Voltage 3.5V 5.5V .8 VCC .8 VCC VCC VCC 1.7 2.1 V V VRL Reset Input Low Voltage 3.5V 5.5V GND -0.3 GND -0.3 0.2 VCC 0.2 VCC 1.3 1.7 V V VOLR Reset Output Low Voltage 3.5V 5.5V 0.6 0.6 0.3 0.2 V V VOFFSET Comparator Input Offset Voltage Input Common Mode Voltage Range 3.5V 4.5V 3.5V 5.5V 10 10 0 0 25 25 VCC -1.0V VCC -1.0V mV mV V V IIL Input Leakage 3.5V 4.5V -1 -1 2 2 0.032 0.032 A A VIN = 0V, VCC VIN = 0V, VCC IOL Output Leakage 3.5V 4.5V -1 -1 2 2 0.032 0.032 A A VIN = 0V, VCC VIN = 0V, VCC IIR Reset Input Current 3.5V 4.5V -20 -20 -130 -180 -65 -112 A A VICR DS97Z8X0502 PRELIMINARY 13 IOL = 1.0 mA IOL = 1.0 mA 10 10 13 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog DC ELECTRICAL CHARACTERISTICS (Continued) TA= 0 C to +70 C Sym Parameter ICC Supply Current ICC1 Standby Current Halt Mode VCC Note [3] Max Typical @ 25C Units 3.5V 5.5V 3.5V 5.5V 20 25 8 8 7 20 3.7 3.7 mA mA mA mA 7.0 7.0 10 10 800 800 2.9 2.9 2 3 600 600 mA mA A A A A Min Conditions @ 16 MHz @ 16 MHz VIN = 0V, VCC @ 16 MHz Clock Divide by 16 @ 16 MHz VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC Notes 4,5 4,5 4,5 4,5 ICC2 Standby Current Stop Mode 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V IALL Auto Latch Low Current 3.5V 5.5V 0.7 1.4 8 15 2.4 4.7 A A 0V <VIN<VCC 0V <VIN<VCC 4,5 4,5 6,11 6,11 6,11,1 4 6,11,1 4 9 9 IALH Auto Latch High Current 3.5V 5.5V -0.6 -1 -5 -8 -1.8 -3.8 A A 0V<VIN<VCC 0V<VIN<VCC 9 9 TPOR Power On Reset 3.5V 5.5V VLV Auto Reset Voltage 3.0 2.0 2.3 24 13 3.1 7 4 2.9 ms ms V 1,7 Notes: 1. Device does function down to the Auto Reset voltage. 2. GND=0V 3. The VCC voltage specification of 5.5V guarantees 5.0V 0.5V and the VCC voltage specification of 3.5V guarantees only 3.5V. 4. All outputs unloaded, I/O pins floating, inputs at rail. 5. CL1= CL2 = 22 pF 6. Same as note [4] except inputs at VCC. 7. Max. temperature is 70C. 8. STD Mode (not Low EMI Mode) 9. Auto Latch (mask option) selected 10. For analog comparator inputs when analog comparators are enabled. 11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating. 12. Typicals are at VCC = 5.0V and VCC = 3.5V 13. Z86E40 only 14. WDT running 14 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog TA=-40 C to +105 C Sym Parameter VCC Note [3] Min Max Typical @ 25C Units Conditions VCH Clock Input High Voltage 4.5V 5.5V 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 2.5 2.5 V V Driven by External Clock Generator VCL Clock Input Low Voltage 4.5V 5.5V GND-0.3 GND-0.3 0.2 VCC 0.2 VCC 1.5 1.5 V V Driven by External Clock Generator VIH Input High Voltage 4.5V 5.5V 0.7 VCC 0.7 VCC VCC+0.3 VCC+0.3 2.5 2.5 V V VIL Input Low Voltage 4.5V 5.5V GND-0.3 GND-0.3 0.2 VCC 0.2 VCC 1.5 1.5 V V VOH Output High Voltage Low EMI Mode Output High Voltage 4.5V 5.5V VCC -0.4 VCC -0.4 4.8 4.8 V V IOH = - 0.5 mA IOH = - 0.5 mA 8 8 4.5V 4.5V VCC -0.4 VCC -0.4 4.8 4.8 V V IOH = -2.0 mA IOH = -2.0 mA 8 8 VOL Output Low Voltage Low EMI Mode 4.5V 5.5V 0.4 0.4 0.2 0.2 V V IOL = 1.0 mA IOL = 1.0 mA VOL1 Output Low Voltage 4.5V 5.5V 0.4 0.4 0.1 0.1 V V IOL = + 4.0 mA IOL = +4.0 mA 8 8 VOL2 Output Low Voltage 4.5V 5.5V 1.2 1.2 0.5 0.5 V V IOL = + 12 mA IOL = + 12 mA 8 8 VRH Reset Input High Voltage 3.5V 5.5V VCC VCC 1.7 2.1 V V VOLR Reset Output Low Voltage 3.5V 5.5V 0.6 0.6 0.3 0.2 V V VOFFSET Comparator Input Offset Voltage VICR Input Common Mode Voltage Range Input Leakage IIL 4.5V 5.5V 4.5V 5.5V 0 0 25 25 VCC-1.5V VCC-1.5V 4.5V 5.5V 4.5V 5.5V -1 -1 -1 -1 2 2 2 2 <1 <1 <1 <1 A A A A 4.5V 5.5V 4.5V 5.5V 4.5V -18 -18 -180 -180 25 25 8 -112 -112 20 20 3.7 A A mA mA mA 5.5V 8 3.7 mA 10 10 2 3 20 20 4.7 4.7 VOH1 IOL Output Leakage IIR Reset Input Current ICC Supply Current ICC1 Standby Current Halt Mode ICC2 Standby Current (Stop Mode) 4.5V 5.5V IALL Auto Latch Low Current 4.5V 5.5V DS97Z8X0502 .8 VCC .8 VCC 1.4 1.4 10 10 PRELIMINARY 1 Notes 13 13 IOL = 1.0 mA IOL = 1.0 mA mV mV V V 13 13 10 10 VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC A A @ 16 MHz @ 16 MHz VIN = 0V, VCC @ 16 MHz VIN = 0V, VCC @ 16 MHz VIN = 0V, VCC VIN = 0V, VCC 4,5 4,5 4,5 6,11,14 6,11,14 A A 0V < VIN < VCC 0V < VIN < VCC 9 9 4,5 15 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog DC ELECTRICAL CHARACTERISTICS (Continued) TA=-40 C to +105 C Sym Parameter VCC Note [3] Min Max Typical @ 25C Units IALH Auto Latch High Current 4.5V 5.5V -1.0 -1.0 -10 -10 -3.8 -3.8 A A TPOR Power On Reset 4.5V 5.5V VLV Auto Reset Voltage 2.0 2.0 2.0 14 14 3.3 4 4 2.9 mS mS V 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 16 Conditions 0V < VIN < VCC 0V < VIN < VCC Notes 9 9 1 Device does function down to the Auto Reset voltage. GND=0V The VCC voltage specification of 5.5V guarantees 5.0V 0.5V. All outputs unloaded, I/O pins floating, inputs at rail. CL1= CL2 = 22 pF Same as note [4] except inputs at VCC. Maximum temperature is 70C STD Mode (not Low EMI Mode) Auto Latch (mask option) selected For analog comparator inputs when analog comparators are enabled. Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating. Typicals are at VCC = 5.0V Z86E40 only WDT is not running. PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog R/W , DM 1 13 12 19 Port 0 16 18 Port 1 20 3 A7 - A0 1 D7 - D0 IN 2 9 AS 8 11 4 5 DS (Read) 6 17 10 Port1 A7 - A0 D7 - D0 OUT 14 15 7 DS (W rite) Figure 14. External I/O or Memory Read/Write Timing Z86E40 Only DS97Z8X0502 PRELIMINARY 17 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog DC ELECTRICAL CHARACTERISTICS (Continued) TA = 0C to 70C 16 MHz No Symbol Note [3] VCC Parameter 1 TdA(AS) 2 TdAS(A) 3 TdAS(DR) 4 TwAS Address Valid to AS Rise Delay AS Rise to Address Float Delay AS Rise to Read Data Req'd Valid AS Low Width 5 TdAS(DS) Address Float to DS Fall 6 TwDSR DS (Read) Low Width 7 TwDSW DS (Write) Low Width 8 TdDSR(DR) 9 ThDR(DS) 10 TdDS(A) 11 TdDS(AS) DS Fall to Read Data Req'd Valid Read Data to DS Rise Hold Time DS Rise to Address Active Delay DS Rise to AS Fall Delay 12 TdR/W(AS) R/W Valid to AS Rise Delay 13 TdDS(R/W) DS Rise to R/W Not Valid 14 TdDW(DSW) 15 TdDS(DW) 16 TdA(DR) 17 TdAS(DS) Write Data Valid to DS Fall (Write) Delay DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req'd Valid AS Rise to DS Fall Delay 18 TdDM(AS) DM Valid to AS Fall Delay 20 ThDS(AS) DS Valid to Address Valid Hold Time 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V Min Max 25 25 35 35 180 180 40 40 0 0 135 135 80 80 75 75 0 0 50 50 35 35 25 25 35 35 55 55 35 35 25 25 230 230 45 45 30 30 35 35 Units Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 2 1,2 2 1,2 1,2 1,2 2 2 2 2 2 2 2 1,2 2 2 Notes: 1. When using extended memory timing, add 2 TpC. 2. Timing numbers given are for minimum TpC. 3. The VCC voltage specification of 5.5V guarantees 5.0V 0.5V and the VCC voltage specification of 3.5V guarantees only 3.5V Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0. 18 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog No Symbol TA = -40C to 105C 16 MHz Note [3] VCC Min Max Parameter 1 TdA(AS) 2 TdAS(A) 3 TdAS(DR) 4 TwAS Address Valid to AS Rise Delay ASAS Rise to Address Float Delay AS Rise to Read Data Req'd Valid AS Low Width 5 TdAS(DS) Address Float to DS Fall 6 TwDSR DS (Read) Low Width 7 TwDSW DS (Write) Low Width 8 TdDSR(DR) 9 ThDR(DS) 10 TdDS(A) 11 TdDS(AS) DS Fall to Read Data Req'd Valid Read Data to DS Rise Hold Time DS Rise to Address Active Delay DS Rise to AS Fall Delay 12 TdR/W(AS) R/W Valid to AS Rise Delay 13 TdDS(R/W) DS Rise to R/W Not Valid 14 TdDW(DSW) 15 TdDS(DW) 16 TdA(DR) 17 TdAS(DS) Write Data Valid to DS Fall (Write) Delay DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req'd Valid AS Rise to DS Fall Delay 18 TdDM(AS) /DM Valid to AS Fall Delay 20 ThDS(AS) DS Valid to Address Valid Hold Time 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 25 25 35 35 180 180 40 40 0 0 135 135 80 80 75 75 0 0 50 50 35 35 25 25 35 35 55 55 35 35 25 25 230 230 45 45 30 30 35 35 1 Units Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 2 1,2 2 1,2 1,2 1,2 2 2 2 2 2 2 2 1,2 2 2 Notes: 1. When using extended memory timing, add 2 TpC. 2. Timing numbers given are for minimum TpC. 3. The VCC voltage specification of 5.5V guarantees 5.0V 0.5V and the VCC voltage specification of 3.5V guarantees only 3.5V Standard Test Load All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. For Standard Mode (not Low-EMI Mode for outputs) with SMR, D1 = 0, D0 = 0. DS97Z8X0502 PRELIMINARY 19 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog DC ELECTRICAL CHARACTERISTICS (Continued) 3 1 Clock 2 7 2 3 7 TIN 4 5 6 IRQN 8 9 Clock Setup 11 Stop Mode Recovery Source 10 Figure 15. Additional Timing Diagram 20 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Additional Timing Table (Divide-By-One Mode) TA = 0 C to +70 C 4 MHz No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC 3 TwC Clock Input Rise & Fall Times Input Clock Width 4 TwTinL 5 TwTinH 6 TpTin 7 TrTin, TfTin Timer Input Rise & Fall Timer TwIL Int. Request Low Time TwIL Int. Request Low Time TwIH Int. Request Input High Time Twsm STOP Mode Recovery Width Spec Tost Oscillator Startup Time 8A 8B 9 10 11 Timer Input Low Width Timer Input High Width Timer Input Period VCC Note [6] 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V TA = -40 C to +105 C 1 4 MHz Min Max Min Max Units Notes 250 250 DC DC 25 25 250 250 DC DC 25 25 ns ns ns ns ns ns ns ns 100 100 ns ns ns ns 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,2,7,8 1,2,7,8 1,3,7,8 1,3,7,8 1,2,7,8 1,2,7,8 4,8 4,8 100 100 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 8TpC 8TpC 100 100 100 70 5TpC 5TpC 5TpC 5TpC 12 12 3.5V 5.5V 100 70 5TpC 5TpC 5TpC 5TpC 12 12 5TpC 5TpC ns ns 5TpC 4,8,9 Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request via Port 3 (P31-P33). 3. Interrupt request via Port 3 (P30). 4. SMR-D5 = 1, POR STOP Mode Delay is on. 5. Reg. WDTMR. 6. The VCC voltage specification of 5.5V guarantees 5.0V 0.5V and the VCC voltage specification of 3.5V guarantees 3.5V only. 7. SMR D1 = 0. 8. Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. 9. For RC and LC oscillator, and for oscillator driven by clock driver. DS97Z8X0502 PRELIMINARY 21 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog DC ELECTRICAL CHARACTERISTICS (Continued) Handshake Timing Diagrams Data In Valid Data In Next Data In Valid 1 2 3 DA V (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Figure 16. Input Handshake Timing Data Out Data Out Valid Next Data Out Valid 7 DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed RDY Figure 17. Output Handshake Timing 22 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Additional Timing Table TA = -40 C to +105 C 1 16 MHz No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC 3 TwC Clock Input Rise & Fall Times Input Clock Width 4 TwTinL 5 TwTinH 6 TpTin 7 TrTin, TfTin Timer Input Rise & Fall Timer TwIL Int. Request Low Time TwIL Int. Request Low Time TwIH Int. Request Input High Time Twsm STOP Mode Recovery Width Spec Tost Oscillator Startup Time Twdt Watch-Dog Timer Delay Time Before Timeout 8A 8B 9 10 11 12 Timer Input Low Width Timer Input High Width Timer Input Period VCC Note [6] 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V 3.5V 5.5V Min Max Units 62.5 62.5 DC DC 15 15 ns ns ns ns ns ns ns ns 100 100 ns ns ns ns 31 31 70 70 5TpC 5TpC 8TpC 8TpC 70 70 5TpC 5TpC 5TpC 12 12 Conditions 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,7,8 1,2,7,8 1,2,7,8 1,3,7,8 1,3,7,8 1,2,7,8 ns ns 4,8 4,8 ms ms ms ms ms ms ms ms 4,8 4,8 5,11 5,11 5,11 5,11 5,11 5,11 5,11 5,11 5TpC 5TpC 10 5 20 10 40 20 160 80 Notes D0 = 0 D1 = 0 D0 = 1 D1 = 0 D0 = 0 D1 = 1 D0 = 1 D1 = 1 Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request via Port 3 (P31-P33) 3. Interrupt request via Port 3 (P30) 4. SMR-D5 = 1, POR STOP Mode Delay is on 5. Reg. WDTMR 6. The VCC voltage spec. of 5.5V guarantees 5.0V 0.5V. 7. SMR D1 = 0 8. Maximum frequency for internal system clock is 4 MHz when using XTAL divide-by-one mode. 9. For RC and LC oscillator, and for oscillator driven by clock driver. 10. Standard Mode (not Low EMI output ports) 11. Using internal RC DS97Z8X0502 PRELIMINARY 23 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog PIN FUNCTIONS EPROM Programming Mode D7-D0 Data Bus. The data can be read from or written to external memory through the data bus. A11-A0 Address Bus. During programming, the EPROM address is written to the address bus. VCC Power Supply. This pin must supply 5V during the EPROM read mode and 6V during other modes. CE Chip Enable (active Low). This pin is active during EPROM Read Mode, Program Mode, and Program Verify Mode. OE Output Enable (active Low). This pin drives the direction of the Data Bus. When this pin is Low, the Data Bus is output, when High, the Data Bus is input. EPM EPROM Program Mode. This pin controls the different EPROM Program Mode by applying different voltages. VPP Program Voltage. This pin supplies the program voltage. PGM Program Mode (active Low). When this pin is Low, the data is programmed to the EPROM through the Data Bus. Application Precaution The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above VCC occur on pins XTAL1 and RESET. In addition, processor operation of Z8 OTP devices may be affected by excessive noise surges on the VPP, CE, EPM, OE pins while the microcontroller is in Standard Mode. Recommendations for dampening voltage surges in both test and OTP mode include the following: Using a clamping diode to VCC Adding a capacitor to the affected pin R/W Read/Write (output, write Low). The R/W signal is Low when the CCP is writing to the external program or data memory (Z86E40 only). RESET Reset (input, active Low). Reset will initialize the MCU. Reset is accomplished either through Power-On, Watch-Dog Timer reset, STOP-Mode Recovery, or external reset. During Power-On Reset and Watch-Dog Timer Reset, the internally generated reset drives the reset pin low for the POR time. Any devices driving the reset line must be open-drain in order to avoid damage from a possible conflict during reset conditions. Pull-up is provided internally. After the POR time, RESET is a Schmitt-triggered input. To avoid asynchronous and noisy reset problems, the Z86E40 is equipped with a reset filter of four external clocks (4TpC). If the external reset signal is less than 4TpC in duration, no reset occurs. On the fifth clock after the reset is detected, an internal RST signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external reset, whichever is longer. During the reset cycle, DS is held active Low while AS cycles at a rate of TpC/2. Program execution begins at location 000CH, 5-10 TpC cycles after RESET is released. For Power-On Reset, the reset output time is 5 ms. The Z86E40 does not reset WDTMR, SMR, P2M, and P3M registers on a STOP-Mode Recovery operation. ROMless (input, active Low). This pin, when connected to GND, disables the internal ROM and forces the device to function as a Z86C90/C89 ROMless Z8. (Note that, when left unconnected or pulled High to VCC, the device functions normally as a Z8 ROM version). Note: When using in ROM Mode in High EMI (noisy) environment, the ROMless pins should be connected directly to VCC. Standard Mode XTAL Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic resonator, LC, RC network, or external single-phase clock to the on-chip oscillator input. XTAL2 Crystal 2 (time-based output). This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network to the on-chip oscillator output. 24 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOScompatible I/O port. These eight I/O lines can be configured under software control as a nibble I/O port, or as an address port for interfacing external memory. The input buffers are Schmitt-triggered and nibble programmed. Either nibble output that can be globally programmed as push-pull or open-drain. Low EMI output buffers can be globally programmed by the software. Port 0 can be placed under handshake control. In Handshake Mode, Port 3 lines P32 and P35 are used as handshake control lines. The handshake direction is determined by the configuration (input or output) assigned to Port 0's upper nibble. The lower nibble must have the same direction as the upper nibble. nibble) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 mode register. In ROMless mode, after a hardware reset, Port 0 is configured as address lines A15-A8, and extended timing is set to accommodate slow memory access. The initialization routine can include reconfiguration to eliminate this extended timing mode. In ROM mode, Port 0 is defined as input after reset. Port 0 can be set in the High-Impedance Mode if selected as an address output state, along with Port 1 and the control signals AS, DS, and R/W (Figure 18). For external memory references, Port 0 provides address bits A11-A8 (lower nibble) or A15-A8 (lower and upper 4 Port 0 (I/O) 4 Handshake Controls /DAV0 and RDY0 (P32 and P35) Open-Drain OEN PAD Out 1.5 2.3V Hysteresis In Auto Latch R 500 k Figure 18. Port 0 Configuration DS97Z8X0502 PRELIMINARY 25 1 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog PIN FUNCTIONS (Continued) Port 1 (P17-P10). Port 1 is an 8-bit, bidirectional, CMOScompatible port with multiplexed Address (A7-A0) and Data (D7-D0) ports. These eight I/O lines can be programmed as inputs or outputs or can be configured under software control as an Address/Data port for interfacing external memory. The input buffers are Schmitt-triggered and the output buffers can be globally programmed as either push-pull or open-drain. Low EMI output buffers can be globally programmed by the software. Port 1 can be placed under handshake control. In this configuration, Port 3, lines P33 and P34 are used as the handshake controls RDY1 and /DAV1 (Ready and Data Available). To interface external memory, Port 1 must be programmed for the multiplexed Address/Data mode. If more than 256 external locations are required, Port 0 outputs the additional lines (Figure 19). Port 1 can be placed in the high-impedance state along with Port 0, AS, DS, and R/W, allowing the Z86E40 to share common resources in multiprocessor and DMA applications. Port 2 (I/O) MCU Handshake Controls DAV1 and RDY1 (P33 and P34) Open-Drain OEN PAD Out 1.5 2.3V Hysteresis In Auto Latch R 500 k Figure 19. Port 1 Configuration (Z86E40 Only) 26 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOScompatible I/O port. These eight I/O lines can be configured under software control as an input or output, independently. All input buffers are Schmitt-triggered. Bits programmed as outputs can be globally programmed as either push-pull or open-drain. Low EMI output buffers can be globally programmed by the software. When used as an I/O port, Port 2 can be placed under handshake control. In Handshake Mode, Port 3 lines P31 and P36 are used as handshake control lines. The handshake direction is determined by the configuration (input or output) assigned to bit 7 of Port 2 (Figure 20). Port 2 (I/O) Z86E40 MCU Handshake Controls DAV2 and RDY2 (P31 and P36) Open-Drain OEN PAD Out TTL Level Shifter In Auto Latch R 500 K Figure 20. Port 2 Configuration DS97Z8X0502 PRELIMINARY 27 1 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog PIN FUNCTIONS (Continued) Port 3 (P37-P30). Port 3 is an 8-bit, CMOS-compatible port with four fixed inputs (P33-P30) and four fixed outputs (P37-P34). These eight lines can be configured by software for interrupt and handshake control functions. Port 3, Pin 0 is Schmitt- triggered. P31, P32, and P33 are standard CMOS inputs with single trip point (no Auto Latches) and P34, P35, P36, and P37 are push-pull output lines. Low EMI output buffers can be globally programmed by the software. Two on-board comparators can process analog signals on P31 and P32 with reference to the voltage on P33. The analog function is enabled by setting the D1 of Port 3 Mode Register (P3M). The comparator output can be outputted from P34 and P37, respectively, by setting PCON register Bit D0 to 1 state. For the interrupt function, P30 and P33 are falling edge triggered interrupt inputs. P31 and P32 can be programmed as falling, rising or both edges triggered interrupt inputs (Figure 21). Access to Counter/Timer 1 is made through P31 (TIN) and P36 (TOUT). Handshake lines for Port 0, Port 1, and Port 2 are also available on Port 3 (Table 9). 28 Note: When enabling/ or disabling analog mode, the following is recommended: 1. Allow two NOP delays before reading this comparator output. 2. Disable global interrupts, switch to analog mode, clear interrupts, and then re-enable interrupts. 3. IRQ register bits 3 to 0 must be cleared after enabling analog mode. Note: P33-P30 differs from the Z86C30/C31/C40 in that there is no clamping diode to VCC due to the EPROM highvoltage circuits. Exceeding the VIH maximum specification during standard operating mode may cause the device to enter EPROM mode. PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog 1 Z86E40 MCU Port 3 (I/O or Control) Auto Latch R 500 K P30 P30 Data Latch IRQ3 R247 = P3M D1 1 = Analog 0 = Digital DIG. P31 (AN1) IRQ2, Tin, P31 Data Latch + AN. - P32 (AN2) IRQ0, P32 Data Latch + P33 (REF) - IRQ1, P33 Data Latch From Stop Mode Recovery Source Figure 21. Port 3 Configuration Table 9. Port 3 Pin Assignments Pin I/O CTC1 Analog Interrupt P30 P31 IN IN TIN AN1 IRQ3 IRQ2 P32 P33 P34 P35 P36 IN IN OUT OUT OUT P37 OUT DS97Z8X0502 AN2 REF AN1-Out IRQ0 IRQ1 P0 HS P1 HS P2 HS Ext D/R D/R D/R R/D /DM R/D TOUT R/D An2-Out PRELIMINARY 29 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog PIN FUNCTIONS (Continued) Comparator Inputs. Port 3, P31, and P32, each have a comparator front end. The comparator reference voltage P33 is common to both comparators. In analog mode, P31 and P32 are the positive input of the comparators and P33 is the reference voltage of the comparators. Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs (except P33-P31) that are not externally driven. Whether this level is 0 or 1, cannot be determined. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. Auto Latches are available on Port 0, Port 2, and P30. There are no Auto Latches on P31, P32, and P33. Low EMI Emission. The Z86E40 can be programmed to operate in a low EMI Emission Mode in the PCON register. The oscillator and all I/O ports can be programmed as low EMI emission mode independently. Use of this feature results in: 30 The pre-drivers slew rate reduced to 10 ns typical. Low EMI output drivers have resistance of 200 Ohms (typical). Low EMI Oscillator. Internal SCLK/TCLK= XTAL operation limited to a maximum of 4 MHz - 250 ns cycle time, when Low EMI Oscillator is selected and system clock (SCLK = XTAL, SMR Reg. Bit D1 =1). Note for emulation only: Do not set the emulator to emulate Port 1 in low EMI mode. Port 1 must always be configured in Standard Mode. PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog FUNCTIONAL DESCRIPTION The MCU incorporates the following special functions to enhance the standard Z8 architecture to provide the user with increased design flexibility. RESET. The device is reset in one of three ways: 1. Power-On Reset 2. Watch-Dog Timer 3. STOP-Mode Recovery Source Note: Having the Auto Power-On Reset circuitry built-in, the MCU does not need to be connected to an external power-on reset circuit. The reset time is 5 ms (typical). The MCU does not reinitialize WDTMR, SMR, P2M, and P3M registers to their reset values on a STOP-Mode Recovery operation. 65535 4096 4095 Location of First Byte of Instruction Executed After RESET Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) Note: The device VCC must rise up to the operating VCC specification before the TPOR expires. Program Memory. The MCU can address up to 4 KB of Internal Program Memory (Figure 22). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. For EPROM mode, byte 12 (000CH) to address 4095 (0FFFH) consists of programmable EPROM. After reset, the program counter points at the address 000CH, which is the starting address of the user program. In ROMless mode, the Z86E40 can address up to 64 KB of External Program Memory. The ROM/ROMless option is only available on the 44-pin devices. EPROM ROMless External ROM and RAM On-Chip One Time PROM External ROM and RAM 11 IRQ5 IRQ5 10 IRQ5 IRQ5 9 IRQ4 IRQ4 8 IRQ4 IRQ4 7 IRQ3 IRQ3 6 IRQ3 IRQ3 5 IRQ2 IRQ2 4 IRQ2 IRQ2 3 IRQ1 IRQ1 2 IRQ1 IRQ1 1 IRQ0 IRQ0 0 IRQ0 IRQ0 12 Figure 22. Program Memory Map (ROMless Z86E40 Only) EPROM Protect. When in ROM Protect Mode, and executing out of External Program Memory, instructions LDC, LDCI, LDE, and LDEI cannot read Internal Program Memory. DS97Z8X0502 When in ROM Protect Mode and executing out of Internal Program Memory, instructions LDC, LDCI, LDE, and LDEI can read Internal Program Memory. PRELIMINARY 31 1 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog FUNCTIONAL DESCRIPTION (Continued) Data Memory (DM). In EPROM Mode, the Z86E40 can address up to 60 KB of external data memory beginning at location 4096. In ROMless mode, the Z86E40 can address up to 64 KB of data memory. External data memory may be included with, or separated from, the external program memory space. DM, an optional I/O function that can be programmed to appear on pin P34, is used to distinguish between data and program memory space (Figure 23). The state of the DM signal is controlled by the type of instruction being executed. An LDC opcode references PROGRAM (DM inactive) memory, and an LDE instruction references data (DM active Low) memory. EPROM ROMless External Data Memory External Data Memory 65535 4096 4095 Not Addressable 0 Figure 23. Data Memory Map 32 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Register File. The register file consists of three I/O port registers, 236/125 general-purpose registers, 15 control and status registers, and three system configuration registers in the expanded register group. The instructions can access registers directly or indirectly through an 8-bit address field. This allows a short 4-bit register address using the Register Pointer (Figure 24). In the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working-register group. Note: Register Bank E0-EF can only be accessed through working register and indirect addressing modes. (This bank is available in Z86E30/E40 only.) R253 RP D7 D6 D5 D4 D3 D2 D1 D0 Expanded Register Group Working Register Group Default setting after RESET = 00000000 Figure 24. Register Pointer Register Expanded Register File (ERF). The register file has been expanded to allow for additional system control registers, mapping of additional peripheral devices and input/output ports into the register address area. The Z8 register address space R0 through R15 is implemented as 16 groups of 16 registers per group (Figure 26). These register groups are known as the Expanded Register File (ERF). DS97Z8X0502 The low nibble (D3-D0) of the Register Pointer (RP) select the active ERF group, and the high nibble (D7-D4) of register RP select the working register group. Three system configuration registers reside in the Expanded Register File at bank FH: PCON, SMR, and WDTMR. The rest of the Expanded Register is not physically implemented and is reserved for future expansion. PRELIMINARY 33 1 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog FUNCTIONAL DESCRIPTION (Continued) r7 r6 r5 r4 r3 r2 r1 r0 R253 (Register Pointer) The upper nibble of the register file address provided by the register pointer specifies the active working-register group. FF Register Group F F0 EF Note: Registers 80H through EFH are available in the Z86C30 only. 80 7F 70 6F 60 5F 50 4F 40 3F 30 2F Specified Working Register Group The lower nibble of the register file address provided by the instruction points to the specified register. 20 1F Register Group 1 R15 to R0 Register Group 0 R15 to R4* 10 0F 00 I/O Ports R3 to R0* * Expanded Register Group (0) is selected in this figure by handling bits D3 to D0 as "0" in Register R253 (RP). Figure 25. Register Pointer 34 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Z8(R) STANDARD CONTROL REGISTERS 1 RESET CONDITION D7 D6 D5 D4 D3 D2 D1 D0 REGISTER REGISTER POINTER 7 6 5 4 3 2 Working Register Group Pointer 1 % FF SPL 0 0 0 0 0 0 0 0 % FE SPH 0 0 0 0 0 0 0 0 % FD RP 0 0 0 0 0 0 0 0 % FC FLAGS U U U U U U U U % FB IMR 0 U U U U U U U % FA IRQ 0 0 0 0 0 0 0 0 % F9 IPR U U U U U U U U % F8 P01M 0 1 0 0 1 1 0 1 * % F7 P3M 0 0 0 0 0 0 0 0 * % F6 P2M 1 1 1 1 1 1 1 1 % F5 PRE0 U U U U U U U 0 % F4 T0 U U U U U U U U % F3 PRE1 U U U U U U 0 0 % F2 T1 U U U U U U U U % F1 TMR 0 0 0 0 0 0 0 0 % F0 Reserved 0 Expanded Register Group Pointer Z8 Reg. File %FF %FO Z86E30/E40 Only EXPANDED REG. GROUP (F) REGISTER * Z86E30/E40 Only %7F * ** Reserved %0F %00 Notes: U = Unknown For Z86E40 (ROMless) reset condition: "10110110" * Will not be reset with a STOP Mode Recovery ** Will not be reset with a STOP Mode Recovery, except Bit D0. % (F) 0F WDTMR % (F) 0E Reserved % (F) 0D SMR2 % (F) 0C Reserved % (F) 0B SMR % (F) 0A Reserved % (F) 09 Reserved % (F) 08 Reserved % (F) 07 Reserved % (F) 06 Reserved % (F) 05 Reserved % (F) 04 Reserved % (F) 03 Reserved % (F) 02 Reserved % (F) 01 Reserved % (F) 00 PCON EXPANDED REG. GROUP (0) REGISTER * * RESET CONDITION U U U 0 1 1 0 1 U U U U U U 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 0 RESET CONDITION % (0) 03 P3 1 1 1 1 U U U U % (0) 02 P2 U U U U U U U U % (0) 01 P1 U U U U U U U U % (0) 00 P0 U U U U U U U U Figure 26. Expanded Register File Architecture DS97Z8X0502 PRELIMINARY 35 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog FUNCTIONAL DESCRIPTION (Continued) General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the VCC voltage-specified operating range. The register R254 is general-purpose on Z86E30/E31. R254 and R255 are set to 00H after any reset or STOP-Mode Recovery. RAM Protect. The upper portion of the RAM's address spaces 80H to EFH (excluding the control registers) can be protected from reading and writing. This option can be selected during the EPROM Programming Mode. After this option is selected, the user can activate this feature from the internal EPROM. D6 of the IMR control register (R251) is used to turn off/on the RAM protect by loading a 0 or 1, respectively. A "1" in D6 indicates RAM Protect enabled. RAM Protect is not available on the Z86E31. Stack. The Z86E40 external data memory or the internal register file can be used for the stack. The 16-bit Stack Pointer (R254-R255) is used for the external stack, which can reside anywhere in the data memory for ROMless mode, but only from 4096 to 65535 in ROM mode. An 8-bit Stack Pointer (R255) is used for the internal stack on the Z86E30/E31/E40 that resides within the 236 general-purpose registers (R4-R239). SPH (R254) can be used as a general-purpose register when using internal stack only. R254 and R255 are set to 00H after any reset or StopMode Recovery. 36 Counter/Timers. There are two 8-bit programmable counter/timers (T0 and T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the T0 prescaler is driven by the internal clock only (Figure 27). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256), that has been loaded into the counter. When the counter reaches the end of count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated. The counters can be programmed to start, stop, restart to continue, or restart from the initial value. The counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counters, but not the prescalers, can be read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and can be either the internal microprocessor clock divided by four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. Port 3 line P36 serves as a timer output (TOUT) through which T0, T1, or the internal clock can be output. The counter/timers can be cascaded by connecting the T0 output to the input of T1. PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog OSC 1 Internal Data Bus D1 (SMR) Write Write Read /2 PRE0 Initial Value Register T0 Initial Value Register 6-Bit Down Counter 8-bit Down Counter T0 Current Value Register D0 (SMR) / 16 /4 Internal Clock IRQ4 /2 TOUT External Clock P36 Clock Logic /4 Internal Clock Gated Clock Triggered Clock TIN P31 Write 6-Bit Down Counter 8-Bit Down Counter PRE1 Initial Value Register T1 Initial Value Register Write IRQ5 T1 Current Value Register Read Internal Data Bus Figure 27. Counter/Timer Block Diagram DS97Z8X0502 PRELIMINARY 37 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog FUNCTIONAL DESCRIPTION (Continued) Interrupts. The MCU has six different interrupts from six different sources. The interrupts are maskable and prioritized (Figure 28). The six sources are divided as follows: four sources are claimed by Port 3 lines P33-P30) and two in counter/timers. The Interrupt Mask Register globally or individually enables or disables the six interrupt requests (Table 10). IRQ0 IRQ2 IRQ1, 3, 4, 5 Interrupt Edge Select IRQ (D6, D7) IRQ IMR 6 IPR Global Interrupt Enable Interrupt Request Priority Logic Vector Select Figure 28. Interrupt Block Diagram Table 10. Interrupt Types, Sources, and Vectors 38 Name Source Vector Location IRQ0 IRQ1 IRQ2 DAV0, IRQ0 IRQ1 DAV2, IRQ2, TIN 0, 1 2, 3 4, 5 IRQ3 IRQ4 IRQ5 IRQ3 T0 TI 6, 7 8, 9 10, 11 Comments External (P32), Rising/Falling Edge Triggered External (P33), Falling Edge Triggered External (P31), Rising/Falling Edge Triggered External (P30), Falling Edge Triggered Internal Internal PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority Register (IPR). An interrupt machine cycle is activated when an interrupt request is granted. Thus, disabling all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. All interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16-bit starting address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests need service. An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 may be rising, falling or both edge triggered, and are programmable by the user. The software may poll to identify the state of the pin. Programming bits for the Interrupt Edge Select are located in bits D7 and D6 of the IRQ Register (R250). The configuration is shown in Table 11. XTAL1 C1 Table 11. IRQ Register Configuration IRQ D7 D6 P31 P32 0 0 1 1 0 1 0 1 F F R R/F F R F R/F Clock. The on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, RC, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal should be AT cut, 10 KHz to 16 MHz max, with a series resistance (RS) less than or equal to 100 Ohms. The crystal should be connected across XTAL1 and XTAL2 using the vendor's recommended capacitor values from each pin directly to device pin Ground. The RC oscillator option can be selected in the programming mode. The RC oscillator configuration must be an external resistor connected from XTAL1 to XTAL2, with a frequency-setting capacitor from XTAL1 to Ground (Figure 29). XTAL1 XTAL1 XTAL1 XTAL2 XTAL2 C1 L XTAL2 Ceramic Resonator or Crystal C1, C2 = 47 pF TYP * F = 8 MHz 1 Notes: F = Falling Edge R = Rising Edge C1 C2 Interrupt Edge R XTAL2 C2 LC C1, C2 = 22 pF RC @ 5V Vcc (TYP) L = 130 H * F = 3 MHz * C1 = 100 pF R = 2K F = 6 MHz External Clock * Typical value including pin parasitics Figure 29. Oscillator Configuration DS97Z8X0502 PRELIMINARY 39 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog FUNCTIONAL DESCRIPTION (Continued) Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR timer allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three conditions: In order to enter STOP or HALT Mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute a NOP (Opcode=FFH) immediately before the appropriate sleep instruction, that is: FF 6F 1. Power fail to Power OK status FF 7F 2. Stop-Mode Recovery (if D5 of SMR=0) 3. WDT time-out The POR time is a nominal 5 ms. Bit 5 of the STOP mode Register (SMR) determines whether the POR timer is bypassed after STOP-Mode Recovery (typical for an external clock and RC/LC oscillators with fast start up times). HALT. Turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and external interrupt IRQ0, IRQ1, and IRQ2 remain active. The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT. NOP STOP or NOP HALT ; clear the pipeline ; enter STOP Mode ; clear the pipeline ; enter HALT Mode STOP. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 microamperes or less. STOP Mode is terminated by one of the following resets: either by WDT time-out, POR, a Stop-Mode Recovery Source, which is defined by the SMR register or external reset. This causes the processor to restart the application program at address 000CH. Port Configuration Register (PCON). The PCON register configures the ports individually; comparator output on Port 3, open-drain on Port 0 and Port 1, low EMI on Ports 0, 1, 2 and 3, and low EMI oscillator. The PCON register is located in the expanded register file at Bank F, location 00 (Figure 30). PCON (FH) 00H D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output* 1 P34, P37 Comparator Output 0 Port 1 Open Drain 1 Port 1 Push-pull Active* 0 Port 0 Open Drain 1 Port 0 Push-pull Active* 0 Port 0 Low EMI 1 Port 0 Standard* 0 Port 1 Low EMI 1 Port 1 Standard* 0 Port 2 Low EMI 1 Port 2 Standard* 0 Port 3 Low EMI 1 Port 3 Standard* * Default Setting After Reset Low EMI Oscillator 0 Low EMI 1 Standard* Figure 30. Port Configuration Register (PCON) (Write Only) 40 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Comparator Output Port 3 (D0). Bit 0 controls the comparator output in Port 3. A "1" in this location brings the comparator outputs to P34 and P37, and a "0" releases the Port to its standard I/O configuration. The default value is 0. Port 1 Open-Drain (D1). Port 1 can be configured as an open-drain by resetting this bit (D1=0) or configured as push-pull active by setting this bit (D1=1). The default value is 1. Port 0 Open-Drain (D2). Port 0 can be configured as an open-drain by resetting this bit (D2=0) or configured as push-pull active by setting this bit (D2=1). The default value is 1. Low EMI Port 0 (D3). Port 0 can be configured as a Low EMI Port by resetting this bit (D3=0) or configured as a Standard Port by setting this bit (D3=1). The default value is 1. Low EMI Port 1 (D4). Port 1 can be configured as a Low EMI Port by resetting this bit (D4=0) or configured as a Standard Port by setting this bit (D4=1). The default value is 1. Note: The emulator does not support Port 1 low EMI mode and must be set D4 = 1. Low EMI Port 3 (D6). Port 3 can be configured as a Low EMI Port by resetting this bit (D6=0) or configured as a Standard Port by setting this bit (D6=1). The default value is 1. Low EMI OSC (D7). This bit of the PCON Register controls the low EMI noise oscillator. A "1" in this location configures the oscillator with standard drive. While a "0" configures the oscillator with low noise drive, however, it does not affect the relationship of SCLK and XTAL. The low EMI mode will reduce the drive of the oscillator (OSC). The default value is 1. Note: 4 MHz is the maximum external clock frequency when running in the low EMI oscillator mode. Stop-Mode Recovery Register (SMR). This register selects the clock divide value and determines the mode of Stop-Mode Recovery (Figure 31). All bits are Write Only except bit 7 which is a Read Only. Bit 7 is a flag bit that is hardware set on the condition of STOP Recovery and reset by a power-on cycle. Bit 6 controls whether a low or high level is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits 2, 3, and 4 of the SMR register specify the Stop-Mode Recovery Source. The SMR is located in Bank F of the Expanded Register Group at address 0BH. Low EMI Port 2 (D5). Port 2 can be configured as a Low EMI Port by resetting this bit (D5=0) or configured as a Standard Port by setting this bit (D5=1). The default value is 1. DS97Z8X0502 PRELIMINARY 41 1 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog FUNCTIONAL DESCRIPTION (Continued) SMR (F) 0B D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide by 16 0 OFF ** 1 ON External Clock Divide by 2 0 SCLK/TCLK =XTAL/2* 1 SCLK/TCLK =XTAL Stop Mode Recovery Source 000 POR and/or External Reset * 001 P30 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0:3 111 P2 NOR 0:7 Stop Delay 0 OFF 1 ON* Stop Recovery Level 0 Low * 1 High Stop Flag 0 POR* 1 Stop Recovery * Default setting after RESET. ** Default setting after RESET and STOP-Mode Recovery. Figure 31. STOP-Mode Recovery Register (Write-Only Except Bit D7, Which is Read-Only) 42 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog SCLK/TCLK Divide-by-16 Select (D0). This bit of the SMR controls a divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic). External Clock Divide-by-Two (D1). This bit can eliminate the oscillator divide-by-two circuitry. When this bit is 0, the System Clock (SCLK) and Timer Clock (TCLK) are equal to the external clock frequency divided by two. The SCLK/TCLK is equal to the external clock frequency when this bit is set (D1=1). Using this bit together with D7 of PCON further helps lower EMI (i.e., D7 (PCON) = 0, D1 (SMR) = 1). The default setting is zero. STOP-Mode Recovery Source (D2, D3, and D4). These three bits of the SMR register specify the wake up source of the STOP-Mode Recovery (Figure 32). Table 12 shows the SMR source selected with the setting of D2 to D4. P33-P31 cannot be used to wake up from STOP mode when programmed as analog inputs. When the STOPMode Recovery sources are selected in this register then SMR2 register bits D0, D1 must be set to zero. Note: If the Port2 pin is configured as an output, this output level will be read by the SMR circuitry. SMR2 D1 D0 0 0 SMR2 D1 D0 0 1 VDD P20 P20 P23 P27 SMR2 D1 D0 1 0 SMR D4 D3 D2 0 0 0 VDD P30 P31 P32 SMR D4 0 0 0 D3 0 1 1 D2 SMR D4 D3 D2 1 1 0 0 0 1 P33 SMR D4 D3 D2 1 0 1 SMR D4 D3 D2 1 1 0 P20 P20 P23 P27 SMR D4 D3 D2 1 1 1 P27 To POR RESET Stop-Mode Recovery Edge Select (SMR) To P33 Data Latch and IRQ1 MUX P33 From Pads Digital/Analog Mode Select (P3M) Figure 32. Stop-Mode Recovery Source DS97Z8X0502 PRELIMINARY 43 1 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog FUNCTIONAL DESCRIPTION (Continued) Table 12. Stop-Mode Recovery Source D4 D3 D2 SMR Source selection 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 1 1 0 1 1 1 0 1 POR recovery only P30 transition P31 transition (Not in analog mode) P32 transition (Not in analog mode) P33 transition (Not in analog mode) P27 transition Logical NOR of Port 2 bits 0-3 Logical NOR of Port 2 bits 0-7 Stop-Mode Recovery Delay Select (D5). The 5 ms RESET delay after Stop-Mode Recovery is disabled by programming this bit to a zero. A "1" in this bit will cause a 5 ms RESET delay after Stop-Mode Recovery. The default condition of this bit is 1. If the fast wake up mode is selected, the Stop-Mode Recovery source needs to be kept active for at least 5TpC. Stop-Mode Recovery Level Select (D6). A "1" in this bit defines that a high level on any one of the recovery sources wakes the MCU from STOP Mode. A 0 defines low level recovery. The default value is 0. Cold or Warm Start (D7). This bit is set by the device upon entering STOP Mode. A "0" in this bit indicates that the device has been reset by POR (cold). A "1" in this bit indicates the device was awakened by a SMR source (warm). Stop-Mode Recovery Register 2 (SMR2). This register contains additional Stop-Mode Recovery sources. When the Stop-Mode Recovery sources are selected in this register then SMR Register. Bits D2, D3, and D4 must be 0. SMR:10 Operation D1 D0 Description of Action 0 0 1 0 1 0 POR and/or external reset recovery Logical AND of P20 through P23 Logical AND of P20 through P27 Watch-Dog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is disabled after Power-On Reset and initially enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT is driven either by an on-board RC oscillator or an external oscillator from XTAL1 pin. The 44 POR clock source is selected with bit 4 of the WDT register. Note: Execution of the WDT instruction affects the Z (Zero), S (Sign), and V (Overflow) flags. WDT Time-Out Period (D0 and D1). Bits 0 and 1 control a tap circuit that determines the time-out periods that can be obtained (Table 13). The default value of D0 and D1 are 1 and 0, respectively. Table 13. Time-out Period of WDT D1 D0 0 0 1 1 0 1 0 1 Time-out of Time-out of the Internal the System RC OSC Clock 5 ms 10 ms* 20 ms 80 ms 128 SCLK 256 SCLK* 512 SCLK 2048 SCLK Notes: *The default setting is 10 ms. WDT During HALT Mode (D2). This bit determines whether or not the WDT is active during HALT Mode. A "1" indicates that the WDT is active during HALT. A "0" disables the WDT in HALT Mode. The default value is "1". WDT During STOP Mode (D3). This bit determines whether or not the WDT is active during STOP mode. A "1" indicates active during STOP. A "0" disables the WDT during STOP Mode. This is applicable only when the WDT clock source is the internal RC oscillator. Clock Source For WDT (D4). This bit determines which oscillator source is used to clock the internal POR and WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WDT clock source is driven from the external pin, XTAL1, and the WDT is stopped in STOP Mode. The default configuration of this bit is 0, which selects the RC oscillator. Permanent WDT. When this feature is enabled, the WDT is enabled after reset and will operate in Run and Halt Mode. The control bits in the WDTMR do not affect the WDT operation. If the clock source of the WDT is the internal RC oscillator, then the WDT will run in STOP mode. If the clock source of the WDT is the XTAL1 pin, then the WDT will not run in STOP mode. Note: WDT time-out in STOP Mode will not reset SMR,SMR2,PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data Registers. WDTMR Register Accessibility. The WDTMR register is accessible only during the first 60 internal system clock PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog cycles from the execution of the first instruction after Power-On Reset, Watch-Dog reset or a STOP-Mode Recovery (Figures 33 and 34). After this point, the register cannot be modified by any means, intentional or otherwise. The WDTMR cannot be read and is located in Bank F of the Expanded Register Group at address location 0FH. WDTMR (F) 0F D7 D6 D5 D4 D3 D2 D1 D0 WDT TAP 00 01 * 10 11 INT RC OSC System Clock 5 ms 128 SCLK 10 ms 256 SCLK 20 ms 512 SCLK 80 ms 2048 SCLK WDT During HALT 0 OFF 1 ON * WDT During STOP 0 OFF 1 ON * XTAL1/INT RC Select for WDT 0 On-Board RC * 1 XTAL Reserved (Must be 0) * Default setting after RESET Figure 33. Watch-Dog Timer Mode Register Write Only DS97Z8X0502 PRELIMINARY 45 1 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog FUNCTIONAL DESCRIPTION (Continued) Reset 4 Clock Filter Clear CLK 18 Clock RESET Generator RESET Internal RESET WDT Select (WDTMR) WDT TAP SELECT CLK Source Select (WDTMR) XTAL M U X Internal RC OSC. VDD + VLV - 5ms POR 5ms 15ms 25ms 100ms CK WDT/POR Counter Chain CLR 2V Operating Voltage Det. WDT From Stop Mode Recovery Source Stop Delay Select (SMR) Figure 34. Resets and WDT 46 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Auto Reset Voltage. An on-board Voltage Comparator checks that VCC is at the required level to ensure correct operation of the device. Reset is globally driven if VCC is below VLV (Figure 35). VCC (Volts) Note: VCC must be in the allowed operating range prior to the minimum Power-On Reset time-out (TPOR). 1 3.7 3.5 3.3 3.1 2.9 2.7 2.5 2.3 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (C) Figure 35. Typical Z86E40 VLV Voltage vs. Temperature DS97Z8X0502 PRELIMINARY 47 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog FUNCTIONAL DESCRIPTION (Continued) EPROM MODE Table 14 shows the programming voltages of each programming mode. Table 15, and figures that follow show the programming timing of each programming mode. Figure 38 shows the circuit diagram of a Z86E40 programming adapter, which adapts from 2764A to Z86E40 and Figure 39 shows the Z86E30/E31 Programming Adapter Circuitry. Figure 40 shows the flowchart of an Intelligent Programming Algorithm, which is compatible with 2764A EPROM (Z86E40 is 4K EPROM, 2764A is 8K EPROM). Since the EPROM size of Z86E30/E31/E40 differs from 2764A, the programming address range has to be set from 0000H to 0FFFH for the Z86E30/E40 and 0000H to 07FFH for Z86E31. Otherwise, the upper portion of EPROM data will overwrite the lower portion of EPROM data. Figure 39 shows the adaptation from the 2764A to Z86E30/E31. EPROM R/W mode allows the programming of the user mode program ROM. Option Bit R/W allows the programming of the Z8 option bits. When the device is latched into Option Bit R/W mode, the address must then be changed to 63 decimals (000000111111 Binary). The Options are mapped into this address as follows: Bit 7 6 5 4 3 2 1 0 Note: EPROM Protect feature allows the LDC, LDCI, LDE, and LDEI instructions from internal program memory. A ROM lookup table can be used with this feature. During programming, the VPP input pin supplies the programming voltage and current to the EPROM. This pin is also used to latch which EPROM mode is to be used (R/W EPROM or R/W Option bits). The mode is set by placing the correct mode number on the least significant bits of the address and raising the EPM pin above V. After a setup time, the VPP pin can then be raised or lowered. The latched EPROM mode will remain until the EPM pin is reduced below VH. Mode Name EPROM R/W Option Bit R/W 48 Mode # LSB Addr 0 3 0000 0011 Option Unused Unused 32 KHz XTAL Option Permanent WDT Auto Latch Disable RC Oscillator Option RAM Protect ROM Protect Table 14 gives the proper conditions for EPROM R/W operations, once the mode is latched. PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Table 14. EPROM Programming Table Programming Modes VPP EPM CE OE PGM ADDR DATA VCC* EPROM READ1 X VH VIL VIL VIH ADDR Out 4.5V EPROM READ2 X VH VIL VIL VIH ADDR Out 5.5V PROGRAM VH VH VIL VIH VIL ADDR In 6.4V PROGRAM VERIFY OPTION BIT PGM VH VH VIL VIL VIH ADDR Out 6.0V VH VH VIL VIH VIL 63 IN 6.4V OPTION BIT READ X VH VIL VIL VIH 63 OUT 6.0V 1 Notes: VH = 13.0 V 0.1 V VIH = As per specific Z8 DC specification VIL= As per specific Z8 DC specification X=Not used, but must be set to VH, VIH, or VIL level. NU = Not used, but must be set to either VIH or VIL level. IPP during programming = 40 mA maximum. ICC during programming, verify, or read = 40 mA maximum. *VCC has a tolerance of 0.25V. Zilog recommends an EPROM read at VCC = 4.5 V and 5.5 V to ensure proper device operations during the VCC after programming, but VCC = 5.0 V is acceptable. Table 15. EPROM Programming Timing Parameters Name Min Max Units 1 2 3 Address Setup Time Data Setup Time VPP Setup 2 2 2 s s s 4 VCC Setup Time 2 s 5 6 7 8 9 10 11 Chip Enable Setup Time Program Pulse Width Data Hold Time OE Setup Time Data Access Time Data Output Float Time Overprogram Pulse Width/Option Program Pulse Width EPM Setup Time PGM Setup Time Address to OE Setup Time OE Width Address to OE Low 2 0.95 2 2 200 2.85 s ms s s ns ns ms 2 2 2 250 125 s s s ns ns 12 13 14 15 16 DS97Z8X0502 1.05 100 PRELIMINARY 49 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog FUNCTIONAL DESCRIPTION (Continued) VIH Address Address Stable VIL 16 VIH Data VIL Address Stable Invalid Valid Invalid Valid 9 VH VPP VIL VH EPM VIL 5.5V 12 VCC 4.5V VIH CE VIL OE VIL 15 VIH PGM 15 5 VIH 15 VIL 3 Figure 36. EPROM Read Mode Timing Diagram 50 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Z86E40 TIMING DIAGRAMS 1 VIH Address Address Stable VIL 1 VIH Data Data Stable VIL Data Out Valid 2 9 10 VH VPP VIH 3 VH EPM VIL 6V VCC 4.5V VIH 4 7 CE VIL 5 VIH OE VIL VIH PGM VIL 6 8 15 11 Program Cycle Verify Cycle Figure 37. Timing Diagram of EPROM Program and Verify Modes DS97Z8X0502 PRELIMINARY 51 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Z86E40 TIMING DIAGRAMS (Continued) U2 U1 D4 39 D5 2 D6 3 D7 4 A0 26 A1 27 A2 30 A3 34 A4 5 A5 6 A6 A7 7 10 1 20 40 GND 21 9 P12 32 33 P13 8 P14 9 P15 12 P16 13 P17 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 P22 P23 P24 P25 P26 P27 P00 P30 P01 P31 P02 P32 A9 A10 21 17 EPM A11 23 18 VPP P03 P33 P04 P34 19 A8 P05 P35 22 A9 P06 P36 24 A10 P07 P37 2 27 1 KOhm 1 1 KOhm 1 23 A11 R2 R1 2 20 2 22 DS XTAL1 RESET XTAL2 A4 A5 A6 A7 D5 D6 D7 A9 A10 A11 A12 GND 14 GND CS VCC 28 VCC OE VPP 1 PGM VPP 0.01F 14 GND 12.5V D1 1 X3 D3 3 0.1F C2 2 1 X1 EPM 4 D4 15 CE U3 12.5V 16 D3 2764 Pins Z86E40 40-Pin DIP Socket GND A3 11 VCC AS D2 03 15 16 04 17 05 18 06 07 19 02 31 GND R/W 13 A2 25 A8 16 OE D1 01 A8 24 25 PGM 12 A1 2 38 A1 P11 D0 00 C1 37 D3 29 P21 11 A0 1 D2 10 1 R4 2 1 KOhm 1 R3 2 10 KOhm 1 36 A0 P10 D1 D1 28 P20 2 35 1N5243 D0 GND GND 12.5 Volt 2 1 P1 VCC 15 IX1 1 5.0V S4 D4 6 X 1 KOhm 1 5 X X D2 D2 3 2 2 S2 1N5231 4 X R5 GND 10 X IX2 VCC 5.0 V IH5043 Figure 38. Z86E40 Z8 OTP Programming Adapter For use with Standard EPROM Programmers 52 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog 1 U2 U1 D0 24 D1 25 D2 26 D3 27 D4 28 D5 1 D6 2 D7 3 A0 19 A1 20 A2 21 A3 23 A4 4 A5 5 A6 6 A7 7 P20 P21 P22 P23 P24 P25 P26 P27 A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A4 25 P00 P30 18 PGM A5 24 P01 P31 11 OE A6 21 12 EPM A7 23 13 VPP P02 P32 P03 P33 P04 P34 14 A8 P05 P35 15 A9 P06 P36 P07 P37 A10 17 16 A11 1 KOhm 1 R1 2 20 2 22 12 D1 13 D2 03 15 16 04 17 05 18 06 19 07 D3 GND 14 GND CS VCC 28 VCC OE VPP A1 01 02 A3 A4 A5 A6 A7 D4 D5 D6 D7 A8 A9 A10 A11 A12 27 R2 D0 00 A2 2 1 KOhm 1 11 A0 PGM VPP 1 GND D1 1 R4 2 1 KOhm 1 4 GND GND 12.5 Volt 2 1 P1 D3 3 X3 2 10 KOhm EPM GND R3 1 1 D1 0.1F C2 2 1 12.5V U3 X1 C1 1 9 Z86E30/31 28-Pin DIP Socket 12.5V 16 1 5.0V 15 IX1 D2 3 5 X S4 D4 6 10 X IX2 VCC IH5043 X 2 1 1 KOhm D2 S2 R5 2 4 X 1N5231 VCC 0.01F 2 XTAL2 CE 10 1N5243 XTAL1 2 2764 Pins GND X 5.0 V Note: The programming address must be set to 0000H - 0FFFH (Lower 4K Byte Memory). For Z86E30 0000H - 07FFH (Lower 2K Byte Memory). For Z86E31 Figure 39. Z86E30/E31 Programming Adapter Circuitry DS97Z8X0502 PRELIMINARY 53 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Start 1 Addr = First Location Vcc = 6.4 V Vpp = 13.0 V N=0 Program 1 ms Pulse Increment N Yes N = 25 ? No Fail Fail Verify One Byte Verify Byte Pass Pass Prog. One Pulse 3xN ms Duration Increment Address No Last Addr ? Yes Vcc = Vpp = 4.5V * Note: * To ensure proper operaton, Zilog recommends Vcc range of the device Vcc specification, But Vcc = 5.0V is acceptable. Verify All Bytes Fail Pass Device Failed Vcc = Vpp = 5.5V * Verify All Bytes Pass Fail Device Passed Figure 40. Z86E40 Programming Algorithm DS97Z8X0502 PRELIMINARY 55 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog EXPANDED REGISTER FILE CONTROL REGISTERS PCON (FH) 00H WDTMR (F) 0F D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 WDT TAP 00 01 * 10 11 Comparator Output Port 3 0 P34, P37 Standard* 1 P34, P37 Comparator Output 0 Port 1 Open-Drain 1 Port 1 Push-Pull Active* WDT During HALT 0 OFF 1 ON * 0 Port 0 Open-Drain 1 Port 0 Push-pull Active* WDT During STOP 0 OFF 1 ON * 0 Port 0 Low EMI 1 Port 0 Standard* 0 Port 1 Low EMI 1 Port 1 Standard* XTAL1/INT RC Select for WDT 0 On-Board RC * 1 XTAL 0 Port 2 Low EMI 1 Port 2 Standard* 0 Port 3 Low EMI 1 Port 3 Standard* * Default Setting After Reset Must Be 1 for Z86E30/E31 Low EMI Oscillator 0 Low EMI 1 Standard* INT RC OSC System Clock 5 ms 128 SCLK 10 ms 256 SCLK 20 ms 512 SCLK 80 ms 2048 SCLK Reserved (Must be 0) * Default setting after RESET Figure 43. Watch-Dog Timer Mode Register Write Only Figure 41. Port Configuration Register Write Only SMR2 (0F) DH D7 D6 D5 D4 D3 D2 D1 D0 SMR (FH) 0B Stop-Mode Recovery Source 2 00 POR only* 01 AND P20,P21,P22,P23 10 AND P20,P21,P22,P23,P24, P25,P26,P27 D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF ** 1 ON Reserved (Must be 0) Note: Not used in conjunction with SMR Source External Clock Divide by 2 0 SCLK/TCLK =XTAL/2* 1 SCLK/TCLK =XTAL Stop Mode Recovery Source 000 POR Only and/or External Reset* 001 P30 010 P31 011 P32 100 P33 101 P27 110 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON* Stop Recovery Level 0 Low* 1 High Figure 44. STOP-Mode Recovery Register 2 Write Only Stop Flag 0 POR* 1 Stop Recovery * Default setting after RESET. ** Default setting after RESET and STOP-Mode Recovery. Figure 42. STOP-Mode Recovery Register Write Only Except Bit D7, Which is Read Only 56 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Z8 CONTROL REGISTER DIAGRAMS R240 1 R243 PRE1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Count Mode 0 T1 Single Pass* 1 T1 Modulo N Clock Source 1 T1 Internal 0 T1 External Timing Input (TIN Mode) Figure 45. Reserved Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) R241 TMR D7 D6 D5 D4 D3 D2 D1 D0 *Default After Reset 0 No Function* 1 Load T0 Figure 48. Prescaler 1 Register F3H: Write Only 0 Disable T0 Count* 1 Enable T0 Count 0 No Function* 1 Load T1 0 Disable T1 Count* 1 Enable T1 Count R244 T0 D7 D6 D5 D4 D3 D2 D1 D0 TIN Modes 00 External Clock Input* 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) T0 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T0 Current Value (When Read) TOUT Modes 00 Not Used* 01 T0 Out 10 T1 Out 11 Internal Clock Out Figure 49. Counter/Timer 0 Register F4H; Read/Write Default After Reset = 00H R245 PRE0 Figure 46. Timer Mode Register F1H: Read/Write D7 D6 D5 D4 D3 D2 D1 D0 Count Mode 0 T1 Single Pass 1 T1 Modulo N R242 T1 D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) T1 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T1 Current Value (When Read) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) Figure 50. Prescaler 0 Register F5H: Write Only Figure 47. Counter/Timer 1 Register F2H: Read/Write DS97Z8X0502 PRELIMINARY 57 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Z8 CONTROL REGISTER DIAGRAMS (Continued) R248 P01M R246 P2M D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 * Default After Reset P03 - P00 Mode 00 Output 01 Input 1X A11-A8 P20 - P27 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input* Stack Selection 0 External 1 Internal P17 - P10 Mode 00 Byte Output 01 Byte Input 10 AD7-AD0 11 High-Impedance AD7-AD0, AS, DS, R/W, A11-A8, A15-A12, If Selected Figure 51. Port 2 Mode Register F6H: Write Only R247 P3M External Memory Timing 0 Normal 1 Extended D7 D6 D5 D4 D3 D2 D1 D0 0 Port 2 Open-Drain 1 Port 2 Push-pull Active P07 - P04 Mode 00 Output 01 Input 1X A15 - A12 0 P31, P32 Digital Mode 1 P31, P32 Analog Mode Reset Condition = 0100 1101B For ROMless Condition = 1011 0110B Z86E30/E31 Must be 00 0 P32 = Input P35 = Output 1 P32 = DAV0/RDY0 P35 = RDY0/DAV0 00 01 10 11 P33 = Input P34 = Output P33 = Input P34 = DM P33 = DAV1/RDY1 P34 = RDY1/DAV1 0 P31 = Input (TIN) P36 = Output (TOUT) 1 P31 = DAV2/RDY2 P36 = RDY2/DAV2 Figure 53. Port 0 and 1 Mode Register F8H: Write Only Z86E30/E31 Only R249 IPR D7 D6 D5 D4 0 P30 = Input P37 = Output Reserved (Must be 0) Default After Reset = 00H Z86E30/E31 Must Be 00 Figure 52. Port 3 Mode Register F7H: Write Only D3 D2 D1 D0 Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B > C 011 A > C > B 100 B > C > A 101 C > B > A 110 B > A > C 111 Reserved IRQ1, IRQ4 Priority (Group C) 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1 IRQ0, IRQ2 Priority (Group B) 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5 Reserved (Must be 0) Figure 54. Interrupt Priority Register F9H: Write Only 58 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog R253 RP R250 IRQ D7 D6 D5 D4 D3 D2 IRQ0 = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = P30 Input IRQ4 = T0 IRQ5 = T1 Default After Reset = 00H 1 D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 Expanded Register File Working Register Pointer Default After Reset = 00H Inter Edge P31 P32 = 00 P31 P32 = 01 P31 P32 = 10 P31 P32 = 11 Figure 58. Register Pointer FDH: Read/Write R254 SPH Figure 55. Interrupt Request Register FAH: Read/Write D7 D6 D5 D4 D3 D2 D1 D0 (Z86E40) Stack Pointer Upper Byte (SP8 - SP15) R251 IMR (Z86E30/E31) 0 = 0 State 1 = 1 State D7 D6 D5 D4 D3 D2 D1 D0 1 Enables IRQ5-IRQ0 (D0 = IRQ0) Figure 59. Stack Pointer High FEH: Read/Write 1 Enables RAM Protect 1 Enables Interrupts This option must be selected when ROM code is submitted for ROM Masking, otherwise this control bit is disabled permanently. R255 SPL D7 D6 D5 D4 D3 D2 D1 D0 Figure 56. Interrupt Mask Register FBH: Read/Write Stack Pointer Lower Byte (SP0 - SP7) R252 FLAGS Figure 60. Stack Pointer Low FFH: Read/Write D7 D6 D5 D4 D3 D2 D1 D0 User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag Figure 57. Flag Register FCH: Read/Write DS97Z8X0502 PRELIMINARY 59 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog PACKAGE INFORMATION (Continued) PACKAGE INFORMATION Figure 61. 40-Pin DIP Package Diagram 60 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog 1 Figure 62. 44-Pin PLCC Package Diagram PackageDiagram Diagram Figure 63. 44-Pin 44-Pin LQFP QFP Package DS97Z8X0502 PRELIMINARY 61 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Figure 64. 28-Pin DIP Package Diagram Figure 65. 28-Pin SOIC Package Diagram 62 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog 1 Figure 66. 28-Pin PLCC Package Diagram DS97Z8X0502 PRELIMINARY 63 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog ORDERING INFORMATION Z86E40 (16 MHz) 40-Pin DIP 44-Pin PLCC 44-Pin QFP LQFP 44-Pin Z86E4016PSC Z86E4016PEC Z86E4016VSC Z86E4016VEC Z86E4016FSC Z86E4016FEC 28-Pin DIP 28-Pin SOIC 28-Pin PLCC Z86E3016PSC Z96E3016PEC Z86E3016SSC Z86E3016SEC Z86E3016VSC Z86E3016VEC 28-Pin DIP 28-Pin SOIC 28-Pin PLCC Z86E3116PSC Z86E3116PEC Z86E3116SSC Z86E3116SEC Z86E3116VSC Z86E3116VEC Z86E30 (16 MHz) Z86E31 (16 MHz) For fast results, contact your local Zilog sales office for assistance in ordering the part desired. Package Temperature P = Plastic DIP S = 0 C to +70 C E = -40 C to +105 C V = Plastic Leaded Chip Carrier Speed F = Plastic Quad Flat Pack 16 = 16 MHz S = SOIC (Small Outline Integrated Circuit) Environmental C= Plastic Standard E = Hermetic Standard Example: Z 86E40 16 P S C is a Z86E40, 16 MHz, DIP, 0C to +70C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix 64 PRELIMINARY DS97Z8X0502 Z86E30/E31/E40 Z8 4K OTP Microcontroller Zilog Customer Support (c) 1998 by Zilog, Inc. All rights reserved. No part of this Zilog, Inc. shall not be responsible for any errors that may document may be copied or reproduced in any form or by appear in this document. Zilog, Inc. makes no commitment any means without the prior written consent of Zilog, Inc. to update or keep current the information contained in this The information in this questions documentabout is subject to change document. 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