Z86E4001ZDF - Zilog, Inc. - Datasheet.Directory

DS97Z8X0502

P R E L I M I N A R Y

RELIMINARY

RODUCT

PECIFICATION

Z86E30/E31/E40

4K OTP M

ICROCONTROLLER

FEATURES

■

Standard Temperature (V

= 3.5V to 5.5V)

■

Extended Temperature (V

= 4.5V to 5.5V)

■

Available Packages:

28-Pin DIP/SOIC/PLCC OTP (Z86E30/31 only)

40-Pin DIP OTP (Z86E40 only)

44-Pin PLCC/QFP OTP (Z86E40 only)

■

Software Enabled Watch-Dog Timer (WDT)

■

Push-Pull/Open-Drain Programmable on

Port 0, Port 1, and Port 2

■

24/32 Input/Output Lines

■

Auto Latches

■

Auto Power-On Reset (POR)

■

Programmable OTP Options:

RC Oscillator

EPROM Protect

Auto Latch Disable

Permanently Enabled WDT

Crystal Oscillator Feedback Resistor Disable

RAM Protect

■

Low-Power Consumption: 60 mW

■

Fast Instruction Pointer: 0.75

■

Two Standby Modes: STOP and HALT

■

Digital Inputs CMOS Levels, Schmitt-Triggered

■

Software Programmable Low EMI Mode

■

Two Programmable 8-Bit Counter/Timers Each

with a 6-Bit Programmable Prescaler

■

Six Vectored, Priority Interrupts from Six

Different Sources

■

Two Comparators

■

On-Chip Oscillator that Accepts a Crystal, Ceramic

Resonator, LC, RC, or External Clock Drive

GENERAL DESCRIPTION

The Z86E30/E31/E40 8-Bit One-Time Programmable

(OTP) Microcontrollers are members of Zilog's single-chip

MCU family featuring enhanced wake-up circuitry,

programmable Watch-Dog Timers, Low Noise EMI op-

tions, and easy hardware/software system expansion ca-

pability.

Four basic address spaces support a wide range of mem-

ory configurations. The designer has access to three addi-

tional control registers that allow easy access to register

mapped peripheral and I/O circuits.

For applications demanding powerful I/O capabilities, the

Z86E30/E31 have 24 pins, and the Z86E40 has 32 pins of

dedicated input and output. These lines are grouped into

four ports, eight lines per port, and are configurable under

software control to provide timing, status signals, and par-

allel I/O with or without handshake, and address/data bus

for interfacing external memory.

Notes:

All signals with a preceding front slash, “/”, are

active Low. For example, B/W (WORD is active Low); B/W

(BYTE is active Low, only).

Device ROM

(KB) RAM*

(Bytes) I/O

Lines Speed

(MHz)

Z86E30 4 237 24 16

Z86E31 2 125 24 16

Z86E40 4 236 32 16

Note:

*General-Purpose

44-Pin PLCC/LQFP OTP (Z86E40 only)

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

P R E L I M I N A R Y

DS97Z8X0502

Power connections follow conventional descriptions be-

low:

Connection Circuit Device

Power V

Ground GND V

Figure 1. Z86E30/E31/E40 Functional Block Diagram

Port 3

Counter/

Timers (2)

Interrupt

Control

T wo Analog

Comparators

Port 2

I/O

(Bit Programmable)

ALU

FLAGS

Machine Timing

Instruction Control

Program

Counter

VGND XTAL

Port 0

Output Input

Address or I/O

(Nibble Programmable)

Address/Data or I/O

(Byte Programmable)

AS DS R/W RESET

RESET

WDT, POR

Port 1

OTP

Pointer

(E40 Only)

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502

P R E L I M I N A R Y

Figure 2. EPROM Programming Block Diagram

Address

MUX

EPROM

TEST ROM

OTP

Options

AD 11- 0

Z8 MCU

Port 0

MSN

Port 3

PGM + Test

Mode Logic

EPM

P32 CE

XT1

PGM

P30

D7 - 0

AD 11- 0

AD 11- 0 Data

MUX

Port 2

D7 - 0

P31

P33

D7 - 0

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

P R E L I M I N A R Y

DS97Z8X0502

PIN IDENTIFICATION

Figure 3. 40-Pin DIP Pin Conﬁguration

Standard Mode

R/W

P25

P26

P27

P04

P05

P06

P14

P15

P07

VCC

P16

P17

XTAL2

XTAL1

P31

P32

P33

P34

P24

P23

P22

P21

P20

P03

P13

P12

GND

P02

P11

P10

P01

P00

P30

P36

P37

P35

RESET

40-Pin DIP

20 21

Table 1. 40-Pin DIP Pin Identiﬁcation

Standard Mode

Pin # Symbol Function Direction

1 R/W Read/Write Output

2–4 P25–P27 Port 2, Pins 5,6,7 In/Output

5–7 P04–P06 Port 0, Pins 4,5,6 In/Output

8–9 P14–P15 Port 1, Pins 4,5 In/Output

10 P07 Port 0, Pin 7 In/Output

11 V

Power Supply

12–13 P16–P17 Port 1, Pins 6,7 In/Output

14 XTAL2 Crystal Oscillator Output

15 XTAL1 Crystal Oscillator Input

16–18 P31–P33 Port 3, Pins 1,2,3 Input

19 P34 Port 3, Pin 4 Output

20 AS Address Strobe Output

21 RESET Reset Input

22 P35 Port 3, Pin 5 Output

23 P37 Port 3, Pin 7 Output

24 P36 Port 3, Pin 6 Output

25 P30 Port 3, Pin 0 Input

26–27 P00–P01 Port 0, Pins 0,1 In/Output

28–29 P10–P11 Port 1, Pins 0,1 In/Output

30 P02 Port 0, Pin 2 In/Output

31 GND Ground

32–33 P12–P13 Port 1, Pins 2,3 In/Output

34 P03 Port 0, Pin 3 In/Output

35–39 P20–P24 Port 2, Pins 0,1,2,3,4 In/Output

40 DS Data Strobe Output

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502

P R E L I M I N A R Y

Figure 4. 44-Pin PLCC Pin Conﬁguration

Standard Mode

44-Pin PLCC

P21

P22

P23

P24

R/W

P25

P26

P27

P04

P30

P36

P37

P35

RESET

R/RL

P34

P33

P32

P31

P05

P06

P14

P15

P07

VCC

P16

P17

XTAL2

XTAL1

P20

P03

P13

P12

GND

P02

P11

P10

P01

P00

2818

Table 2. 44-Pin PLCC Pin Identiﬁcation

Pin # Symbol Function Direction

1–2 GND Ground

3–4 P12–P13 Port 1, Pins 2,3 In/Output

5 P03 Port 0, Pin 3 In/Output

6–10 P20–P24 Port 2, Pins 0,1,2,3,4 In/Output

11 DS Data Strobe Output

12 NC No Connection

13 R/W Read/Write Output

14–16 P25–P27 Port 2, Pins 5,6,7 In/Output

17–19 P04–P06 Port 0, Pins 4,5,6 In/Output

20–21 P14–P15 Port 1, Pins 4,5 In/Output

22 P07 Port 0, Pin 7 In/Output

23–24 V

Power Supply

25–26 P16–P17 Port 1, Pins 6,7 In/Output

27 XTAL2 Crystal Oscillator Output

28 XTAL1 Crystal Oscillator Input

29–31 P31–P33 Port 3, Pins 1,2,3 Input

32 P34 Port 3, Pin 4 Output

33 AS Address Strobe Output

34 R/RL ROM/ROMless select Input

35 RESET Reset Input

36 P35 Port 3, Pin 5 Output

37 P37 Port 3, Pin 7 Output

38 P36 Port 3, Pin 6 Output

39 P30 Port 3, Pin 0 Input

40–41 P00–P01 Port 0, Pins 0,1 In/Output

42–43 P10–P11 Port 1, Pins 0,1 In/Output

44 P02 Port 0, Pin 2 In/Output

Table 2. 44-Pin PLCC Pin Identiﬁcation

Pin # Symbol Function Direction

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

P R E L I M I N A R Y

DS97Z8X0502

PIN IDENTIFICATION

(Continued)

Figure 5. 44-Pin QFP Pin Conﬁguration

Standard Mode

P21

P22

P23

P24

R/W

P25

P26

P27

P04

P30

P36

P37

P35

RESET

R/RL

P34

P33

P32

P31

P05

P06

P14

P15

P07

VCC

P16

P17

XTAL2

XTAL1

P20

P03

P13

P12

GND

P02

P11

P10

P01

P00

2333

44-Pin QFP

Table 3. 44-Pin QFP Pin Identiﬁcation

Pin # Symbol Function Direction

1–2 P05–P06 Port 0, Pins 5,6 In/Output

3–4 P14–P15 Port 1, Pins 4,5 In/Output

5 P07 Port 0, Pin 7 In/Output

6–7 V

Power Supply

8–9 P16–P17 Port 1, Pins 6,7 In/Output

10 XTAL2 Crystal Oscillator Output

11 XTAL1 Crystal Oscillator Input

12–14 P31–P33 Port 3, Pins 1,2,3 Input

15 P34 Port 3, Pin 4 Output

16 AS Address Strobe Output

17 R/RL ROM/ROMless select Input

18 RESET Reset Input

19 P35 Port 3, Pin 5 Output

20 P37 Port 3, Pin 7 Output

21 P36 Port 3, Pin 6 Output

22 P30 Port 3, Pin 0 Input

23–24 P00–P01 Port 0, Pin 0,1 In/Output

25–26 P10–P11 Port 1, Pins 0,1 In/Output

27 P02 Port 0, Pin 2 In/Output

28–29 GND Ground

30–31 P12–P13 Port 1, Pins 2,3 In/Output

32 P03 Port 0, Pin 3 In/Output

33–37 P20–4 Port 2, Pins 0,1,2,3,4 In/Output

38 DS Data Strobe Output

39 NC No Connection

40 R/W Read/Write Output

41–43 P25–P27 Port 2, Pins 5,6,7 In/Output

44 P04 Port 0, Pin 4 In/Output

Table 3. 44-Pin QFP Pin Identiﬁcation

Pin # Symbol Function Direction

44-Pin LQFP

Figure 5. 44-Pin LQFP Pin Configuration

Standard Mode

Table 3. 44-Pin LQFP Pin Identification

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502

P R E L I M I N A R Y

Figure 6. 40-Pin DIP Pin Conﬁguration

EPROM Mode

VCC

EPM

VPP

GND

PGM

A10

A11

40-Pin DIP

20 21

Table 4. 40-Pin DIP Package Pin Identiﬁcation

EPROM Mode

Pin # Symbol Function Direction

1 NC No Connection

2–4 D5–D7 Data 5,6,7 In/Output

5–7 A4–A6 Address 4,5,6 Input

8–9 NC No Connection

10 A7 Address 7 Input

11 V

Power Supply

12–14 NC No Connection

15 CE Chip Select Input

16 OE Output Enable Input

17 EPM EPROM Prog. Mode Input

18 V

Prog. Voltage Input

19 A8 Address 8 Input

20–21 NC No Connection

22 A9 Address 9 Input

23 A11 Address 11 Input

24 A10 Address 10 Input

25 PGM Prog. Mode Input

26–27 A0–A1 Address 0,1 Input

28–29 NC No Connection

30 A2 Address 2 Input

31 GND Ground

32–33 NC No Connection

34 A3 Address 3 Input

35–39 D0–D4 Data 0,1,2,3,4 In/Output

40 NC No Connection

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

P R E L I M I N A R Y

DS97Z8X0502

PIN IDENTIFICATION

(Continued)

Figure 7. 44-Pin PLCC Pin Conﬁguration

EPROM Programming Mode

44-Pin PLCC

PGM

A10

A11

VPP

EPM

VCC

GND

2818

Table 5. 44-Pin PLCC Pin Conﬁguration

EPROM Programming Mode

Pin # Symbol Function Direction

1–2 GND Ground

3–4 NC No Connection

5 A3 Address 3 Input

6–10 D0–D4 Data 0,1,2,3,4 In/Output

11–13 NC No Connection

14–16 D5–D7 Data 5,6,7 In/Output

17–19 A4–A6 Address 4,5,6 Input

20–21 NC No Connection

22 A7 Address 7 Input

23–24 V

Power Supply

25–27 NC No Connection

28 CE Chip Select Input

29 OE Output Enable Input

30 EPM EPROM Prog.

Mode Input

31 V

Prog. Voltage Input

32 A8 Address 8 Input

33–35 NC No Connection

36 A9 Address 9 Input

37 A11 Address 11 Input

38 A10 Address 10 Input

39 PGM Prog. Mode Input

40–41 A0,A1 Address 0,1 Input

42–43 NC No Connection

44 A2 Address 2 Input

Table 5. 44-Pin PLCC Pin Conﬁguration

EPROM Programming Mode

Pin # Symbol Function Direction

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502

P R E L I M I N A R Y

Figure 8. 44-Pin QFP Pin Conﬁguration

EPROM Programming Mode

PGM

A10

A11

VPP

EPM

VCC

GND

2333

44 -Pin QFP

Table 6. 44-Pin QFP Pin Identiﬁcation

EPROM Programming Mode

Pin # Symbol Function Direction

1–2 A5–A6 Address 5,6 Input

3–4 NC No Connection

5 A7 Address 7 Input

6–7 VCC Power Supply

8–10 NC No Connection

11 CE Chip Select Input

12 OE Output Enable Input

13 EPM EPROM Prog.

Mode Input

14 VPP Prog. Voltage Input

15 A8 Address 8 Input

16–18 NC No Connection

19 A9 Address 9 Input

20 A11 Address 11 Input

21 A10 Address 10 Input

22 PGM Prog. Mode Input

23–24 A0,A1 Address 0,1 Input

25–26 NC No Connection

27 A2 Address 2 Input

28–29 GND Ground

30–31 NC No Connection

32 A3 Address 3 Input

33–37 D0–D4 Data 0,1,2,3,4 In/Output

38–40 NC No Connection

41–43 D5–D7 Data 5,6,7 In/Output

44 A4 Address 4 Input

Table 6. 44-Pin QFP Pin Identiﬁcation

EPROM Programming Mode

Pin # Symbol Function Direction

44-Pin LQFP

Figure 8. 44-Pin LQFP Pin Configuration

EPROM Programming Mode

Table 6. 44-Pin LQFP Pin Configuration

EPROM Programming Mode

Table 6. 44-Pin LQFP Pin Configuration

EPROM Programming Mode

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

10 P R E L I M I N A R Y DS97Z8X0502

PIN IDENTIFICATION (Continued)

Figure 9. Standard Mode

28-Pin DIP/SOIC Pin Conﬁguration

Table 7. 28-Pin DIP/SOIC/PLCC

Pin Identiﬁcation*

Pin # Symbol Function Direction

1–3 P25–P27 Port 2, Pins 5,6, In/Output

4–7 P04–P07 Port 0, Pins 4,5,6,7 In/Output

CC Power Supply

9 XTAL2 Crystal Oscillator Output

10 XTAL1 Crystal Oscillator Input

11–13 P31–P33 Port 3, Pins 1,2,3 Input

14–15 P34–P35 Port 3, Pins 4,5 Output

16 P37 Port 3, Pin 7 Output

17 P36 Port 3, Pin 6 Output

18 P30 Port 3, Pin 0 Input

19–21 P00–P02 Port 0, Pins 0,1,2 In/Output

22 VSS Ground

23 P03 Port 0, Pin 3 In/Output

24–28 P20–P24 Port 2, Pins

0,1,2,3,4 In/Output

P25

P26

P27

P04

P05

P06

P07

VCC

XTAL2

XTAL1

P31

P32

P33

P34

P24

P23

P22

P21

P20

P03

VSS

P02

P01

P00

P30

P36

P37

P35

28-Pin DIP

14 15

Figure 10. EPROM Programming Mode

28-Pin DIP/SOIC Pin Conﬁguration

Figure 11. Standard Mode

28-Pin PLCC Pin Conﬁguration

VCC

EPM

VPP

VSS

PGM

A10

A11

28-Pin DIP

14 15

11 18

264

28-Pin PLCC

1XXX

XXX

P21

P20

P03

VSS

P02

P01

P00

P05

P06

P07

VCC

XT2

XT1

P31

P04

P27

P26

P25

P24

P23

P22

P32

P33

P34

P35

P37

P36

P30

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 11

Figure 12. EPROM Programming Mode

28-Pin PLCC Pin Conﬁguration

11 18

264

28-Pin PLCC

1XXX

XXX

VSS

VCC

EPM

VPP

A11

A10

PGM

Table 8. 28-Pin EPROM

Pin Identiﬁcation

Pin # Symbol Function Direction

1–3 D5–D7 Data 5,6,7 In/Output

4–7 A4–A7 Address 4,5,6,7 Input

CC Power Supply

9 NC No connection

10 CE Chip Select Input

11 OE Output Enable Input

12 EPM EPROM Prog.

Mode Input

13 VPP Prog. Voltage Input

14–15 A8–A9 Address 8,9 Input

16 A11 Address 11 Input

17 A10 Address 10 Input

18 PGM Prog. Mode Input

19–21 A0–A2 Address 0,1,2 Input

22 VSS Ground

23 A3 Address 3 Input

24–28 D0–D4 Data 0,1,2,3,4 In/Output

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

12 P R E L I M I N A R Y DS97Z8X0502

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under Absolute Maxi-

mum Ratings may cause permanent damage to the de-

vice. This is a stress rating only; functional operation of the

device at any condition above those indicated in the oper-

ational sections of these specifications is not implied. Ex-

posure to absolute maximum rating conditions for an ex-

tended period may affect device reliability.

Total power dissipation should not exceed 1.2 W for the

package. Power dissipation is calculated as follows:

Total Power Dissipation = VDD x [ IDD – (sum of IOH) ]

+ sum of [ (VDD – VOH) x IOH ]

+ sum of (V0L x I0L)

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test

conditions as noted. All voltages are referenced to

Ground. Positive current flows into the referenced pin

(Test Load).

Parameter Min Max Units

Ambient Temperature under Bias –40 +105 C

Storage Temperature –65 +150 C

Voltage on any Pin with Respect to VSS [Note 1] –0.6 +7 V

Voltage on VDD Pin with Respect to VSS –0.3 +7 V

Voltage on XTAL1 and RESET Pins with Respect to VSS [Note 2] –0.6 VDD+1 V

Total Power Dissipation 1.21 W

Maximum Allowable Current out of VSS 220 mA

Maximum Allowable Current into VDD 180 mA

Maximum Allowable Current into an Input Pin [Note 3] –600 +600 µA

Maximum Allowable Current into an Open-Drain Pin [Note 4] –600 +600 µA

Maximum Allowable Output Current Sinked by Any I/O Pin 25 mA

Maximum Allowable Output Current Sourced by Any I/O Pin 25 mA

Maximum Allowable Output Current Sinked by RESET Pin 3 mA

Notes:

1. This applies to all pins except XTAL pins and where otherwise noted.

2. There is no input protection diode from pin to VDD.

3. This excludes XTAL pins.

4. Device pin is not at an output Low state.

Figure 13. Test Load Diagram

150 pF

From Output

Under Test

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 13

CAPACITANCE

TA = 25°C, VCC = GND = 0V, f = 1.0 MHz; unmeasured pins returned to GND.

DC ELECTRICAL CHARACTERISTICS

Parameter Min Max

Input capacitance 0 12 pF

Output capacitance 0 12 pF

I/O capacitance 0 12 pF

TA= 0 °C to +70 °C

Sym Parameter VCC

Note [3] Min Max Typical

@ 25°C Units Conditions Notes

VCH Clock Input High Voltage 3.5V

5.5V 0.7 VCC

0.7 VCC

VCC+0.3

VCC+0.3 1.8

2.5 V

VDriven by External

Clock Generator

VCL Clock Input Low Voltage 3.5V

4.5V GND -0.3

GND -0.3 0.2 VCC

0.2 VCC

0.9

1.5 V

VDriven by External

Clock Generator

VIH Input High Voltage 3.5V

5.5V 0.7 VCC

0.7 VCC

VCC+0.3

VCC+0.3 2.5

2.5 V

VIL Input Low Voltage 3.5V

5.5V GND -0.3

GND -0.3 0.2 VCC

0.2 VCC

1.5

1.5 V

VOH Output High Voltage

Low EMI Mode 3.5V

5.5V VCC -0.4

VCC -0.4 3.3

4.8 V

VIOH = – 0.5 mA

VOH1 Output High Voltage 3.5V

5.5V VCC -0.4

VCC -0.4 3.3

4.8 V

VIOH = -2.0 mA

IOH = -2.0 mA

VOL Output Low Voltage

Low EMI Mode 3.5V

4.5V 0.4

0.4 0.2

0.2 V

VIOL = 1.0 mA

IOL = 1.0 mA

VOL1 Output Low Voltage 3.5V

4.5V 0.4

0.4 0.1

0.1 V

VIOL = + 4.0 mA

IOL = + 4.0 mA 8

VOL2 Output Low Voltage 3.5V

4.5V 1.2

1.2 0.5

0.5 V

VIOL = + 12 mA

IOL = + 12 mA 8

VRH Reset Input High

Voltage 3.5V

5.5V .8 VCC

.8 VCC

VCC

1.7

2.1 V

VRL Reset Input Low Voltage 3.5V

5.5V GND -0.3

GND -0.3 0.2 VCC

0.2 VCC

1.3

1.7 V

V13

VOLR Reset Output Low

Voltage 3.5V

5.5V 0.6

0.6 0.3

0.2 V

VIOL = 1.0 mA

IOL = 1.0 mA

VOFFSET Comparator Input

Offset Voltage 3.5V

4.5V 25

25 10

10 mV

VICR Input Common Mode

Voltage Range 3.5V

5.5V 0

0VCC -1.0V

VCC -1.0V V

V10

IIL Input Leakage 3.5V

4.5V -1

-1 2

20.032

0.032 µA

µAVIN = 0V, VCC

VIN = 0V, VCC

IOL Output Leakage 3.5V

4.5V -1

-1 2

20.032

0.032 µA

µAVIN = 0V, VCC

VIN = 0V, VCC

IIR Reset Input Current 3.5V

4.5V -20

-20 -130

-180 -65

-112 µA

µA

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

14 P R E L I M I N A R Y DS97Z8X0502

DC ELECTRICAL CHARACTERISTICS (Continued)

ICC Supply Current 3.5V

5.5V 20

25 7

20 mA

mA @ 16 MHz

@ 16 MHz 4,5

4,5

ICC1 Standby Current

Halt Mode 3.5V

5.5V 8

83.7

3.7 mA

mA VIN = 0V, VCC

@ 16 MHz 4,5

4,5

3.5V

5.5V 7.0

7.0 2.9

2.9 mA

mA Clock Divide by

16 @ 16 MHz 4,5

4,5

ICC2 Standby Current

Stop Mode 3.5V

5.5V

3.5V

5.5V

800

600

µA

VIN = 0V, VCC

6,11

6,11,1

IALL Auto Latch

Low Current 3.5V

5.5V 0.7

1.4 8

15 2.4

4.7 µA

µA0V <VIN<VCC

0V <VIN<VCC

IALH Auto Latch

High Current 3.5V

5.5V -0.6

-1 -5

-8 -1.8

-3.8 µA

µA0V<VIN<VCC

0V<VIN<VCC

TPOR Power On Reset 3.5V

5.5V 3.0

2.0 24

13 7

4ms

VLV Auto Reset Voltage 2.3 3.1 2.9 V 1,7

Notes:

1. Device does function down to the Auto Reset voltage.

2. GND=0V

3. The VCC voltage specification of 5.5V guarantees 5.0V ± 0.5V and

the VCC voltage specification of 3.5V guarantees only 3.5V.

4. All outputs unloaded, I/O pins floating, inputs at rail.

5. CL1= CL2 = 22 pF

6. Same as note [4] except inputs at VCC.

7. Max. temperature is 70°C.

8. STD Mode (not Low EMI Mode)

9. Auto Latch (mask option) selected

10. For analog comparator inputs when analog comparators are

enabled.

11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2

is floating.

12. Typicals are at VCC = 5.0V and VCC = 3.5V

13. Z86E40 only

14. WDT running

TA= 0 °C to +70 °C

Sym Parameter VCC

Note [3] Min Max Typical

@ 25°C Units Conditions Notes

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 15

TA=–40 °C to +105 °C

Sym Parameter VCC

Note [3] Min Max Typical

@ 25°C Units Conditions Notes

VCH Clock Input High

Voltage 4.5V

5.5V 0.7 VCC

0.7 VCC

VCC+0.3

VCC+0.3 2.5

2.5 V

VDriven b y External

Clock Generator

VCL Clock Input Low

Voltage 4.5V

5.5V GND-0.3

GND-0.3 0.2 VCC

0.2 VCC

1.5

1.5 V

VDriven b y External

Clock Generator

VIH Input High Voltage 4.5V

5.5V 0.7 VCC

0.7 VCC

VCC+0.3

VCC+0.3 2.5

2.5 V

VIL Input Low Voltage 4.5V

5.5V GND-0.3

GND-0.3 0.2 VCC

0.2 VCC

1.5

1.5 V

VOH Output High

Voltage Low EMI

Mode

4.5V

5.5V VCC -0.4

VCC -0.4 4.8

4.8 V

VIOH = – 0.5 mA

IOH = – 0.5 mA 8

VOH1 Output High Voltage 4.5V

4.5V VCC -0.4

VCC -0.4 4.8

4.8 V

VIOH = -2.0 mA

IOH = -2.0 mA 8

VOL Output Low Voltage

Low EMI Mode 4.5V

5.5V 0.4

0.4 0.2

0.2 V

VIOL = 1.0 mA

IOL = 1.0 mA

VOL1 Output Low Voltage 4.5V

5.5V 0.4

0.4 0.1

0.1 V

VIOL = + 4.0 mA

IOL = +4.0 mA 8

VOL2 Output Low Voltage 4.5V

5.5V 1.2

1.2 0.5

0.5 V

VIOL = + 12 mA

IOL = + 12 mA 8

VRH Reset Input High

Voltage 3.5V

5.5V .8 VCC

.8 VCC

VCC

1.7

2.1 V

V13

VOLR Reset Output Low

Voltage 3.5V

5.5V 0.6

0.6 0.3

0.2 V

VIOL = 1.0 mA

IOL = 1.0 mA 13

VOFFSET Comparator Input

Offset Voltage 4.5V

5.5V 25

25 10

10 mV

VICR Input Common

Mode Voltage

Range

4.5V

5.5V 0

0VCC-1.5V

VCC-1.5V V

V10

IIL Input Leakage 4.5V

5.5V -1

-1 2

2<1

<1 µA

µAVIN = 0V, VCC

VIN = 0V, VCC

IOL Output Leakage 4.5V

5.5V -1

-1 2

2<1

<1 µA

µAVIN = 0V, VCC

VIN = 0V, VCC

IIR Reset Input Current 4.5V

5.5V -18

-18 -180

-180 -112

-112 µA

µA

ICC Supply Current 4.5V

5.5V 25

25 20

20 mA

mA @ 16 MHz

@ 16 MHz 4,5

4,5

ICC1 Standby Current

Halt Mode 4.5V

5.5V

3.7

VIN = 0V, VCC

@ 16 MHz

VIN = 0V, VCC

@ 16 MHz

4,5

ICC2 Standby Current

(Stop Mode) 4.5V

5.5V 10

10 2

3µA

µAVIN = 0V, VCC

VIN = 0V, VCC

6,11,14

IALL Auto Latch Low

Current 4.5V

5.5V 1.4

1.4 20

20 4.7

4.7 µA

µA0V < VIN < VCC

0V < VIN < VCC

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

16 P R E L I M I N A R Y DS97Z8X0502

DC ELECTRICAL CHARACTERISTICS (Continued)

IALH Auto Latch High

Current 4.5V

5.5V -1.0

-1.0 -10

-10 -3.8

-3.8 µA

µA0V < VIN < VCC

0V < VIN < VCC

TPOR Power On Reset 4.5V

5.5V 2.0

2.0 14

14 4

4mS

VLV Auto Reset Voltage 2.0 3.3 2.9 V 1

1. Device does function down to the Auto Reset voltage.

2. GND=0V

3. The VCC voltage specification of 5.5V guarantees 5.0V ± 0.5V.

4. All outputs unloaded, I/O pins floating, inputs at rail.

5. CL1= CL2 = 22 pF

6. Same as note [4] except inputs at VCC.

7. Maximum temperature is 70°C

8. STD Mode (not Low EMI Mode)

9. Auto Latch (mask option) selected

10. For analog comparator inputs when analog comparators are

enabled.

11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2

is floating.

12. Typicals are at VCC = 5.0V

13. Z86E40 only

14. WDT is not running.

TA=–40 °C to +105 °C

Sym Parameter VCC

Note [3] Min Max Typical

@ 25°C Units Conditions Notes

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 17

Figure 14. External I/O or Memory Read/Write Timing

Z86E40 Only

R/W , DM

18 3

811

Port 0

Port 1

(Read)

Port1

(Write)

A7 - A0 D7 - D0 IN

D7 - D0 OUTA7 - A0

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

18 P R E L I M I N A R Y DS97Z8X0502

DC ELECTRICAL CHARACTERISTICS (Continued)

TA = 0°C to 70°C

16 MHz

No Symbol Parameter Note [3]

VCC Min Max Units Notes

1 TdA(AS) Address Valid to AS Rise

Delay 3.5V

5.5V 25

25 ns

ns 2

2 TdAS(A) AS Rise to Address Float

Delay 3.5V

5.5V 35

35 ns

ns 2

3 TdAS(DR) AS Rise to Read Data Req’ d

Valid 3.5V

5.5V 180

180 ns

ns 1,2

4 TwAS AS Low Width 3.5V

5.5V 40

40 ns

ns 2

5 TdAS(DS) Address Float to DS Fall 3.5V

5.5V 0

0ns

6 TwDSR DS (Read) Low Width 3.5V

5.5V 135

135 ns

ns 1,2

7 TwDSW DS (Write) Low Width 3.5V

5.5V 80

80 ns

ns 1,2

8 TdDSR(DR) DS Fall to Read Data Req’d

Valid 3.5V

5.5V 75

75 ns

ns 1,2

9 ThDR(DS) Read Data to DS Rise Hold

Time 3.5V

5.5V 0

0ns

ns 2

10 TdDS(A) DS Rise to Address Active

Delay 3.5V

5.5V 50

50 ns

ns 2

11 TdDS(AS) DS Rise to AS Fall Delay 3.5V

5.5V 35

35 ns

ns 2

12 TdR/W(AS) R/W Valid to AS Rise Delay 3.5V

5.5V 25

25 ns

ns 2

13 TdDS(R/W) DS Rise to R/W Not Valid 3.5V

5.5V 35

35 ns

ns 2

14 TdDW(DSW) Write Data Valid to DS Fall

(Write) Delay 3.5V

5.5V 55

55 25

25 ns

ns 2

15 TdDS(DW) DS Rise to Write Data Not

Valid Delay 3.5V

5.5V 35

35 ns

ns 2

16 TdA(DR) Address Valid to Read Data

Req’ d V alid 3.5V

5.5V 230

230 ns

ns 1,2

17 TdAS(DS) AS Rise to DS Fall Delay 3.5V

5.5V 45

45 ns

ns 2

18 TdDM(AS) DM Valid to AS Fall Delay 3.5V

5.5V 30

30 ns

ns 2

20 ThDS(AS) DS Valid to Address Valid

Hold Time 3.5V

5.5V 35

35 ns

Notes:

1. When using extended memory timing, add 2 TpC.

2. Timing numbers given are for minimum TpC.

3. The VCC voltage specification of 5.5V guarantees 5.0V ±0.5V and

the VCC voltage specification of 3.5V guarantees only 3.5V

Standard Test Load

All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.

For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0.

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 19

TA = -40°C to 105°C

16 MHz

No Symbol Parameter Note [3]

VCC Min Max Units Notes

1 TdA(AS) Address Valid to AS Rise

Delay 4.5V

5.5V 25

25 ns

ns 2

2 TdAS(A) ASAS Rise to Address Float

Delay 4.5V

5.5V 35

35 ns

ns 2

3 TdAS(DR) AS Rise to Read Data Req’ d

Valid 4.5V

5.5V 180

180 ns

ns 1,2

4 TwAS AS Low Width 4.5V

5.5V 40

40 ns

ns 2

5 TdAS(DS) Address Float to DS Fall 4.5V

5.5V 0

0ns

6 TwDSR DS (Read) Low Width 4.5V

5.5V 135

135 ns

ns 1,2

7 TwDSW DS (Write) Low Width 4.5V

5.5V 80

80 ns

ns 1,2

8 TdDSR(DR) DS Fall to Read Data Req’d

Valid 4.5V

5.5V 75

75 ns

ns 1,2

9 ThDR(DS) Read Data to DS Rise Hold

Time 4.5V

5.5V 0

0ns

ns 2

10 TdDS(A) DS Rise to Address Active

Delay 4.5V

5.5V 50

50 ns

ns 2

11 TdDS(AS) DS Rise to AS Fall Delay 4.5V

5.5V 35

35 ns

ns 2

12 TdR/W(AS) R/W Valid to AS Rise Delay 4.5V

5.5V 25

25 ns

ns 2

13 TdDS(R/W) DS Rise to R/W Not Valid 4.5V

5.5V 35

35 ns

ns 2

14 TdDW(DSW) Write Data Valid to DS Fall

(Write) Delay 4.5V

5.5V 55

55 25

25 ns

ns 2

15 TdDS(DW) DS Rise to Write Data Not

Valid Delay 4.5V

5.5V 35

35 ns

ns 2

16 TdA(DR) Address Valid to Read Data

Req’ d V alid 4.5V

5.5V 230

230 ns

ns 1,2

17 TdAS(DS) AS Rise to DS Fall Delay 4.5V

5.5V 45

45 ns

ns 2

18 TdDM(AS) /DM Valid to AS Fall Delay 4.5V

5.5V 30

30 ns

ns 2

20 ThDS(AS) DS Valid to Address Valid

Hold Time 4.5V

5.5V 35

35 ns

Notes:

1. When using extended memory timing, add 2 TpC.

2. Timing numbers given are for minimum TpC.

3. The VCC voltage specification of 5.5V guarantees 5.0V ±0.5V and

the VCC voltage specification of 3.5V guarantees only 3.5V

Standard Test Load

All timing references use 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.

For Standard Mode (not Low-EMI Mode for outputs) with SMR, D1 = 0, D0 = 0.

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

20 P R E L I M I N A R Y DS97Z8X0502

DC ELECTRICAL CHARACTERISTICS (Continued)

Figure 15. Additional Timing Diagram

Clock

2 2 3

TIN

IRQN

7 7

Clock

Setup

Stop

Mode

Recovery

Source

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 21

Additional Timing Table (Divide-By-One Mode)

TA = 0 °C to +70 °C T

= -40 °C to +105 °C

4 MHz 4 MHz

No Symbol Parameter VCC

Note [6] Min Max Min Max Units Notes

1 TpC Input Clock Period 3.5V

5.5V 250

250 DC

DC 250

250 DC

DC ns

ns 1,7,8

1,7,8

2 TrC,TfC Clock Input Rise &

F all Times 3.5V

5.5V 25

25 25

25 ns

ns 1,7,8

1,7,8

3 TwC Input Clock Width 3.5V

5.5V 100

100 100

100 ns

ns 1,7,8

1,7,8

4 TwTinL Timer Input Low

Width 3.5V

5.5V 100

70 100

70 ns

ns 1,7,8

1,7,8

5 TwTinH Timer Input High

Width 3.5V

5.5V 5TpC

5TpC 5TpC

5TpC 1,7,8

1,7,8

6 TpTin Timer Input Period 3.5V

5.5V 8TpC

8TpC 8TpC

8TpC 1,7,8

1,7,8

7 TrTin, TfTin Timer Input Rise

& Fall Timer 3.5V

5.5V 100

100 100

100 ns

ns 1,7,8

1,7,8

8A TwIL Int. Request Low

Time 3.5V

5.5V 100

70 100

70 ns

ns 1,2,7,8

1,2,7,8

8B TwIL Int. Request Low

Time 3.5V

5.5V 5TpC

5TpC 5TpC

5TpC 1,3,7,8

1,3,7,8

9 TwIH Int. Request Input

High Time 3.5V

5.5V 5TpC

5TpC 5TpC

5TpC 1,2,7,8

1,2,7,8

10 Twsm STOP Mode

Recov ery Width

Spec

3.5V

5.5V 12

12 12

12 ns

ns 4,8

4,8

11 Tost Oscillator Startup

Time 3.5V

5.5V 5TpC

5TpC 5TpC 4,8,9

Notes:

1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.

2. Interrupt request via Port 3 (P31–P33).

3. Interrupt request via Port 3 (P30).

4. SMR-D5 = 1, POR STOP Mode Delay is on.

5. Reg. WDTMR.

6. The VCC voltage specification of 5.5V guarantees 5.0V ± 0.5V and

the VCC voltage specification of 3.5V guarantees 3.5V only.

7. SMR D1 = 0.

8. Maximum frequency for internal system clock is 4 MHz when

using XTAL divide-by-one mode.

9. For RC and LC oscillator, and for oscillator driven by clock driver.

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

22 P R E L I M I N A R Y DS97Z8X0502

DC ELECTRICAL CHARACTERISTICS (Continued)

Handshake Timing Diagrams

Figure 16. Input Handshake Timing

Data In

4 5 6

DAV

(Input)

RDY

(Output)

Next Data In Valid

Delayed RDY

Delayed DAV

Data In Valid

Figure 17. Output Handshake Timing

Data Out

DAV

(Output)

RDY

(Input)

Next Data Out Valid

Delayed RDY

Delayed DAV

Data Out Valid

8 9

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 23

Additional Timing Table

TA = -40 °C to +105 °C

16 MHz

No Symbol Parameter VCC

Note [6] Min Max Units Conditions Notes

1 TpC Input Clock Period 3.5V

5.5V 62.5

62.5 DC

DC ns

ns 1,7,8

1,7,8

2 TrC ,TfC Clock Input Rise &

F all Times 3.5V

5.5V 15

15 ns

ns 1,7,8

1,7,8

3 TwC Input Clock Width 3.5V

5.5V 31

31 ns

ns 1,7,8

1,7,8

4 TwTinL Timer Input Low

Width 3.5V

5.5V 70

70 ns

ns 1,7,8

1,7,8

5 TwTinH Timer Input High

Width 3.5V

5.5V 5TpC

5TpC 1,7,8

1,7,8

6 TpTin Timer Input Period 3.5V

5.5V 8TpC

8TpC 1,7,8

1,7,8

7 TrTin, TfTin Timer Input Rise

& Fall Timer 3.5V

5.5V 100

100 ns

ns 1,7,8

1,7,8

8A TwIL Int. Request Low

Time 3.5V

5.5V 70

70 ns

ns 1,2,7,8

1,2,7,8

8B TwIL Int. Request Low

Time 3.5V

5.5V 5TpC

5TpC 1,3,7,8

1,3,7,8

9 TwIH Int. Request Input

High Time 3.5V

5.5V 5TpC 1,2,7,8

10 Twsm STOP Mode

Recov ery Width

Spec

3.5V

5.5V 12

12 ns

ns 4,8

4,8

11 Tost Oscillator Startup

Time 3.5V

5.5V 5TpC

5TpC 4,8

4,8

12 Twdt W atch-Dog Timer

Dela y Time

Bef ore Timeout

3.5V

5.5V 10

5ms

ms D0 = 0

D1 = 0 5,11

5,11

3.5V

5.5V 20

10 ms

ms D0 = 1

D1 = 0 5,11

5,11

3.5V

5.5V 40

20 ms

ms D0 = 0

D1 = 1 5,11

5,11

3.5V

5.5V 160

80 ms

ms D0 = 1

D1 = 1 5,11

5,11

Notes:

1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0.

2. Interrupt request via Port 3 (P31–P33)

3. Interrupt request via Port 3 (P30)

4. SMR-D5 = 1, POR STOP Mode Delay is on

5. Reg. WDTMR

6. The VCC voltage spec. of 5.5V guarantees 5.0V ± 0.5V.

7. SMR D1 = 0

8. Maximum frequency for internal system clock is 4 MHz when using

XTAL divide-by-one mode.

9. For RC and LC oscillator, and for oscillator driven by clock driver.

10. Standard Mode (not Low EMI output ports)

11. Using internal RC

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

24 P R E L I M I N A R Y DS97Z8X0502

PIN FUNCTIONS

EPROM Programming Mode

D7–D0 Data Bus. The data can be read from or written to

external memory through the data bus.

A11–A0 Address Bus. During programming, the EPROM

address is written to the address bus.

VCC Power Supply. This pin must supply 5V during the

EPROM read mode and 6V during other modes.

CE Chip Enable (active Low). This pin is active during

EPROM Read Mode, Program Mode, and Program Verify

Mode.

OE Output Enable (active Low). This pin drives the direc-

tion of the Data Bus. When this pin is Low, the Data Bus is

output, when High, the Data Bus is input.

EPM EPROM Program Mode. This pin controls the differ-

ent EPROM Program Mode by applying different voltages.

VPP Program Voltage. This pin supplies the program volt-

age.

PGM Program Mode (active Low). When this pin is Low,

the data is programmed to the EPROM through the Data

Bus.

Application Precaution

The production test-mode environment may be enabled

accidentally during normal operation if excessive noise

surges above VCC occur on pins XTAL1 and RESET.

In addition, processor operation of Z8 OTP devices may be

affected by excessive noise surges on the VPP, CE, EPM,

OE pins while the microcontroller is in Standard Mode.

Recommendations for dampening voltage surges in both

test and OTP mode include the following:

■Using a clamping diode to VCC

■Adding a capacitor to the affected pin

Standard Mode

XTAL Crystal 1 (time-based input). This pin connects a

parallel-resonant crystal, ceramic resonator, LC, RC net-

work, or external single-phase clock to the on-chip oscilla-

tor input.

XTAL2 Crystal 2 (time-based output). This pin connects a

parallel-resonant crystal, ceramic resonator, LC, or RC

network to the on-chip oscillator output.

R/W Read/Write (output, write Low). The R/W signal is

Low when the CCP is writing to the external program or

data memory (Z86E40 only).

RESET Reset (input, active Low). Reset will initialize the

MCU. Reset is accomplished either through Power-On,

Watch-Dog Timer reset, STOP-Mode Recovery, or exter-

nal reset. During Power-On Reset and Watch-Dog Timer

Reset, the internally generated reset drives the reset pin

low for the POR time. Any devices driving the reset line

must be open-drain in order to avoid damage from a pos-

sible conflict during reset conditions. Pull-up is provided in-

ternally. After the POR time, RESET is a Schmitt-triggered

input.

To avoid asynchronous and noisy reset problems, the

Z86E40 is equipped with a reset filter of four external

clocks (4TpC). If the external reset signal is less than 4TpC

in duration, no reset occurs. On the fifth clock after the re-

set is detected, an internal RST signal is latched and held

for an internal register count of 18 external clocks, or for

the duration of the external reset, whichever is longer. Dur-

ing the reset cycle, DS is held active Low while AS cycles

at a rate of TpC/2. Program execution begins at location

000CH, 5–10 TpC cycles after RESET is released. For

Power-On Reset, the reset output time is 5 ms. The

Z86E40 does not reset WDTMR, SMR, P2M, and P3M

registers on a STOP-Mode Recovery operation.

ROMless (input, active Low). This pin, when connected to

GND, disables the internal ROM and forces the device to

function as a Z86C90/C89 ROMless Z8. (Note that, when

left unconnected or pulled High to VCC, the device func-

tions normally as a Z8 ROM version).

Note: When using in ROM Mode in High EMI (noisy) envi-

ronment, the ROMless pins should be connected directly

to VCC.

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 25

Port 0 (P07–P00). Port 0 is an 8-bit, bidirectional, CMOS-

compatible I/O port. These eight I/O lines can be config-

ured under software control as a nibble I/O port, or as an

address port for interfacing external memory. The input

buffers are Schmitt-triggered and nibble programmed. Ei-

ther nibble output that can be globally programmed as

push-pull or open-drain. Low EMI output buffers can be

globally programmed by the software. Port 0 can be placed

under handshake control. In Handshake Mode, Port 3

lines P32 and P35 are used as handshake control lines.

The handshake direction is determined by the configura-

tion (input or output) assigned to Port 0's upper nibble. The

lower nibble must have the same direction as the upper

nibble.

For external memory references, Port 0 provides address

bits A11–A8 (lower nibble) or A15–A8 (lower and upper

nibble) depending on the required address space. If the

address range requires 12 bits or less, the upper nibble of

Port 0 can be programmed independently as I/O while the

lower nibble is used for addressing. If one or both nibbles

are needed for I/O operation, they must be configured by

writing to the Port 0 mode register. In ROMless mode, after

a hardware reset, Port 0 is configured as address lines

A15–A8, and extended timing is set to accommodate slow

memory access. The initialization routine can include re-

configuration to eliminate this extended timing mode. In

ROM mode, Port 0 is defined as input after reset.

Port 0 can be set in the High-Impedance Mode if selected

as an address output state, along with Port 1 and the con-

trol signals AS, DS, and R/W (Figure 18).

Figure 18. Port 0 Conﬁguration

Handshake Controls

/DAV0 and RDY0

(P32 and P35)

1.5 2.3V Hysteresis

PAD

Port 0 (I/O)

OEN

Out

Open-Drain

Auto Latch

R 500 kΩ

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

26 P R E L I M I N A R Y DS97Z8X0502

PIN FUNCTIONS (Continued)

Port 1 (P17–P10). Port 1 is an 8-bit, bidirectional, CMOS-

compatible port with multiplexed Address (A7–A0) and

Data (D7–D0) ports. These eight I/O lines can be pro-

grammed as inputs or outputs or can be configured under

software control as an Address/Data port for interfacing

external memory. The input buffers are Schmitt-triggered

and the output buffers can be globally programmed as ei-

ther push-pull or open-drain. Low EMI output buffers can

be globally programmed by the software. Port 1 can be

placed under handshake control. In this configuration, Port

3, lines P33 and P34 are used as the handshake controls

RDY1 and /DAV1 (Ready and Data Available). To inter-

face external memory, Port 1 must be programmed for the

multiplexed Address/Data mode. If more than 256 external

locations are required, Port 0 outputs the additional lines

(Figure 19).

Port 1 can be placed in the high-impedance state along

with Port 0, AS, DS, and R/W, allowing the Z86E40 to

share common resources in multiprocessor and DMA ap-

plications.

Figure 19. Port 1 Conﬁguration (Z86E40 Only)

1.5 2.3V Hysteresis

PAD

OEN

Out

Open-Drain

Auto Latch

R 500 kΩ

Port 2 (I/O)

Handshake Controls

DAV1 and RDY1

(P33 and P34)

MCU

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 27

Port 2 (P27–P20). Port 2 is an 8-bit, bidirectional, CMOS-

compatible I/O port. These eight I/O lines can be config-

ured under software control as an input or output, indepen-

dently. All input buffers are Schmitt-triggered. Bits pro-

grammed as outputs can be globally programmed as

either push-pull or open-drain. Low EMI output buffers can

be globally programmed by the software. When used as an

I/O port, Port 2 can be placed under handshake control.

In Handshake Mode, Port 3 lines P31 and P36 are used as

handshake control lines. The handshake direction is deter-

mined by the configuration (input or output) assigned to bit

7 of Port 2 (Figure 20).

Figure 20. Port 2 Conﬁguration

OEN

Out

PAD

Port 2 (I/O)

Handshake Controls

DAV2 and RDY2

(P31 and P36)

Z86E40

MCU

TTL Level Shifter

Auto Latch

R ≈ 500 KΩ

Open-Drain

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

28 P R E L I M I N A R Y DS97Z8X0502

PIN FUNCTIONS (Continued)

Port 3 (P37–P30). Port 3 is an 8-bit, CMOS-compatible

port with four fixed inputs (P33–P30) and four fixed outputs

(P37–P34). These eight lines can be configured by soft-

ware for interrupt and handshake control functions. Port 3,

Pin 0 is Schmitt- triggered. P31, P32, and P33 are stan-

dard CMOS inputs with single trip point (no Auto Latches)

and P34, P35, P36, and P37 are push-pull output lines.

Low EMI output buffers can be globally programmed by

the software. Two on-board comparators can process an-

alog signals on P31 and P32 with reference to the voltage

on P33. The analog function is enabled by setting the D1

of Port 3 Mode Register (P3M). The comparator output can

be outputted from P34 and P37, respectively, by setting

PCON register Bit D0 to 1 state. For the interrupt function,

P30 and P33 are falling edge triggered interrupt inputs.

P31 and P32 can be programmed as falling, rising or both

edges triggered interrupt inputs (Figure 21). Access to

Counter/Timer 1 is made through P31 (TIN) and P36

(TOUT). Handshake lines for Port 0, Port 1, and Port 2 are

also available on Port 3 (Table 9).

Note: When enabling/ or disabling analog mode, the fol-

lowing is recommended:

1. Allow two NOP delays before reading this comparator

output.

2. Disable global interrupts, switch to analog mode, clear

interrupts, and then re-enable interrupts.

3. IRQ register bits 3 to 0 must be cleared after enabling

analog mode.

Note: P33–P30 differs from the Z86C30/C31/C40 in that

there is no clamping diode to VCC due to the EPROM high-

voltage circuits. Exceeding the VIH maximum specification

during standard operating mode may cause the device to

enter EPROM mode.

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 29

Figure 21. Port 3 Conﬁguration

R247 = P3M

P31 (AN1)

P32 (AN2)

P33 (REF)

From Stop Mode

Recovery Source

1 = Analog

0 = Digital

IRQ2, Tin, P31 Data Latch

IRQ0, P32 Data Latch

IRQ1, P33 Data Latch

DIG.

AN.

Auto Latch

P30 Data

Latch IRQ3

Port 3

(I/O or Control)

Z86E40

MCU

P30 R ≈ 500 KΩ

Table 9. Port 3 Pin Assignments

Pin I/O CTC1 Analog Interrupt P0 HS P1 HS P2 HS Ext

P30 IN IRQ3

P31 IN TIN AN1 IRQ2 D/R

P32 IN AN2 IRQ0 D/R

P33 IN REF IRQ1 D/R

P34 OUT AN1-Out R/D /DM

P35 OUT R/D

P36 OUT TOUT R/D

P37 OUT An2-Out

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

30 P R E L I M I N A R Y DS97Z8X0502

PIN FUNCTIONS (Continued)

Comparator Inputs. Port 3, P31, and P32, each have a

comparator front end. The comparator reference voltage

P33 is common to both comparators. In analog mode, P31

and P32 are the positive input of the comparators and P33

is the reference voltage of the comparators.

Auto Latch. The Auto Latch puts valid CMOS levels on all

CMOS inputs (except P33–P31) that are not externally

driven. Whether this level is 0 or 1, cannot be determined.

A valid CMOS level, rather than a floating node, reduces

excessive supply current flow in the input buffer. Auto

Latches are available on Port 0, Port 2, and P30. There

are no Auto Latches on P31, P32, and P33.

Low EMI Emission. The Z86E40 can be programmed to

operate in a low EMI Emission Mode in the PCON register.

The oscillator and all I/O ports can be programmed as low

EMI emission mode independently. Use of this feature re-

sults in:

■The pre-drivers slew rate reduced to 10 ns typical.

■Low EMI output drivers have resistance of 200 Ohms

(typical).

■Low EMI Oscillator.

■Internal SCLK/TCLK= XTAL operation limited to a

maximum of 4 MHz – 250 ns cycle time, when Low EMI

Oscillator is selected and system clock (SCLK = XTAL,

SMR Reg. Bit D1 =1).

■Note for emulation only:

Do not set the emulator to emulate Port 1 in low EMI

mode. Port 1 must always be configured in Standard

Mode.

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 31

FUNCTIONAL DESCRIPTION

The MCU incorporates the following special functions to

enhance the standard Z8 architecture to provide the user

with increased design flexibility.

RESET. The device is reset in one of three ways:

1. Power-On Reset

2. Watch-Dog Timer

3. STOP-Mode Recovery Source

Note: Having the Auto Power-On Reset circuitry built-in,

the MCU does not need to be connected to an external

power-on reset circuit. The reset time is 5 ms (typical). The

MCU does not reinitialize WDTMR, SMR, P2M, and P3M

registers to their reset values on a STOP-Mode Recovery

operation.

Note: The device VCC must rise up to the operating VCC

specification before the TPOR expires.

Program Memory. The MCU can address up to 4 KB of

Internal Program Memory (Figure 22). The first 12 bytes of

program memory are reserved for the interrupt vectors.

These locations contain six 16-bit vectors that correspond

to the six available interrupts. For EPROM mode, byte 12

(000CH) to address 4095 (0FFFH) consists of program-

mable EPROM. After reset, the program counter points at

the address 000CH, which is the starting address of the

user program.

In ROMless mode, the Z86E40 can address up to 64 KB

of External Program Memory. The ROM/ROMless option

is only available on the 44-pin devices.

EPROM Protect. When in ROM Protect Mode, and exe-

cuting out of External Program Memory, instructions LDC,

LDCI, LDE, and LDEI cannot read Internal Program Mem-

ory.

When in ROM Protect Mode and executing out of Internal

Program Memory, instructions LDC, LDCI, LDE, and LDEI

can read Internal Program Memory.

Figure 22. Program Memory Map

(ROMless Z86E40 Only)

External

ROM and RAM

Location of

First Byte of

Instruction

Executed

After RESET

Interrupt

Vector

(Lower Byte)

Interrupt

Vector

(Upper Byte)

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

IRQ0

IRQ5

On-Chip One Time PROM External

ROM and RAM

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

IRQ0

IRQ5

65535 EPROM ROMless

4096

4095

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

32 P R E L I M I N A R Y DS97Z8X0502

FUNCTIONAL DESCRIPTION (Continued)

Data Memory (DM). In EPROM Mode, the Z86E40 can

address up to 60 KB of external data memory beginning at

location 4096. In ROMless mode, the Z86E40 can address

up to 64 KB of data memory. External data memory may

be included with, or separated from, the external program

memory space. DM, an optional I/O function that can be

programmed to appear on pin P34, is used to distinguish

between data and program memory space (Figure 23).

The state of the DM signal is controlled by the type of in-

struction being executed. An LDC opcode references

PROGRAM (DM inactive) memory, and an LDE instruction

references data (DM active Low) memory.

Figure 23. Data Memory Map

65535

4096

External

Data

Memory

Not Addressable

External

Data

Memory

EPROM ROMless

4095

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 33

registers, 236/125 general-purpose registers, 15 control

and status registers, and three system configuration regis-

ters in the expanded register group. The instructions can

access registers directly or indirectly through an 8-bit ad-

dress field. This allows a short 4-bit register address using

the Register Pointer (Figure 24). In the 4-bit mode, the reg-

ister file is divided into 16 working register groups, each

occupying 16 continuous locations. The Register Pointer

addresses the starting location of the active working-regis-

ter group.

Note: Register Bank E0–EF can only be accessed through

working register and indirect addressing modes. (This

bank is available in Z86E30/E40 only.)

Expanded Register File (ERF). The register file has been

expanded to allow for additional system control registers,

mapping of additional peripheral devices and input/output

ports into the register address area. The Z8 register ad-

dress space R0 through R15 is implemented as 16 groups

of 16 registers per group (Figure 26). These register

groups are known as the Expanded Register File (ERF).

The low nibble (D3–D0) of the Register Pointer (RP) select

the active ERF group, and the high nibble (D7–D4) of reg-

ister RP select the working register group. Three system

configuration registers reside in the Expanded Register

File at bank FH: PCON, SMR, and WDTMR. The rest of

the Expanded Register is not physically implemented and

is reserved for future expansion.

Figure 24. Register Pointer Register

D7 D6 D5 D4 D3 D2 D1 D0

Expanded Register Group

R253 RP

Working Register Group

Default setting after RESET = 00000000

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

34 P R E L I M I N A R Y DS97Z8X0502

FUNCTIONAL DESCRIPTION (Continued)

Figure 25. Register Pointer

The upper nibble of the register file address

provided by the register pointer specifies

the active working-register group.

r7 r6 r5 r4 R253

(Register Pointer)

I/O Ports

Specified Working

The lower nibble

of the register

file address

provided by the

instruction points

to the specified

r3 r2 r1 r0

R15 to R0

R15 to R4*

R3 to R0*

* Expanded Register Group (0) is selected

in this figure by handling bits D3 to D0 as

"0" in Register R253 (RP).

Note: Registers 80H

through EFH are

available in the Z86C30

only.

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 35

Figure 26. Expanded Register File Architecture

76543210

Working Register

Group Pointer Expanded Register

Group Pointer

%FF

%FO

%7F

%0F

%00

Z8 Reg. File

% FE

% FD

% FC

% FB

% FA

% F9

% F8

% F7

% F6

% F5

% F4

% F3

% F2

% F1

% F0

SPL

FLAGS

IMR

IRQ

IPR

P01M

P3M

P2M

PRE0

PRE1

TMR

% (F) 0F

% (F) 0E

% (F) 0D

% (F) 0C

% (F) 0B

% (F) 0A

% (F) 09

% (F) 08

% (F) 07

% (F) 06

% (F) 05

% (F) 04

% (F) 03

% (F) 02

% (F) 01

% (F) 00

WDTMR

SMR

UUU0 11 0 1

00100000

1111UUUU

UUUUUUUU

EXPANDED REG. GROUP (F) RESET CONDITION

EXPANDED REG. GROUP (0) RESET CONDITION

Z8® STANDARD CONTROL REGISTERS

RESET CONDITION

% (0) 03 P3

% (0) 02 P2

% (0) 01 P1

% (0) 00 P0

D7 D6 D5 D4 D3 D2 D1 D0

Reserved

SMR2

Reserved

PCON 11111110

†

U = Unknown

For Z86E40 (ROMless) reset condition: "10110110"

* Will not be reset with a STOP Mode Recovery

†

Will not be reset with a STOP Mode Recovery, except Bit D0.

Notes: *

Z86E30/E40 Only

SPH

*UUUUUU00

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

36 P R E L I M I N A R Y DS97Z8X0502

FUNCTIONAL DESCRIPTION (Continued)

General-Purpose Registers (GPR). These registers are

undefined after the device is powered up. The registers

keep their last value after any reset, as long as the reset

occurs in the VCC voltage-specified operating range. The

and R255 are set to 00H after any reset or STOP-Mode

Recovery.

RAM Protect. The upper portion of the RAM's address

spaces 80H to EFH (excluding the control registers) can

be protected from reading and writing. This option can be

selected during the EPROM Programming Mode. After this

option is selected, the user can activate this feature from

the internal EPROM. D6 of the IMR control register (R251)

is used to turn off/on the RAM protect by loading a 0 or 1,

respectively. A “1” in D6 indicates RAM Protect enabled.

RAM Protect is not available on the Z86E31.

Stack. The Z86E40 external data memory or the internal

Pointer (R254–R255) is used for the external stack, which

can reside anywhere in the data memory for ROMless

mode, but only from 4096 to 65535 in ROM mode. An 8-bit

Stack Pointer (R255) is used for the internal stack on the

Z86E30/E31/E40 that resides within the 236 general-pur-

pose registers (R4–R239). SPH (R254) can be used as a

general-purpose register when using internal stack only.

R254 and R255 are set to 00H after any reset or Stop-

Mode Recovery.

Counter/Timers. There are two 8-bit programmable

counter/timers (T0 and T1), each driven by its own 6-bit

programmable prescaler. The T1 prescaler is driven by in-

ternal or external clock sources; however, the T0 prescaler

is driven by the internal clock only (Figure 27).

The 6-bit prescalers can divide the input frequency of the

clock source by any integer number from 1 to 64. Each

prescaler drives its counter, which decrements the value

(1 to 256), that has been loaded into the counter. When the

counter reaches the end of count, a timer interrupt request,

IRQ4 (T0) or IRQ5 (T1), is generated.

The counters can be programmed to start, stop, restart to

continue, or restart from the initial value. The counters can

also be programmed to stop upon reaching zero (single

pass mode) or to automatically reload the initial value and

continue counting (modulo-n continuous mode).

The counters, but not the prescalers, can be read at any

time without disturbing their value or count mode. The

clock source for T1 is user-definable and can be either the

internal microprocessor clock divided by four, or an exter-

nal signal input through Port 3. The Timer Mode register

configures the external timer input (P31) as an external

clock, a trigger input that can be retriggerable or non-retrig-

gerable, or as a gate input for the internal clock. Port 3 line

P36 serves as a timer output (TOUT) through which T0, T1,

or the internal clock can be output. The counter/timers can

be cascaded by connecting the T0 output to the input of

T1.

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 37

Figure 27. Counter/Timer Block Diagram

PRE0

Initial Value

Current Value

6-Bit

Down

Counter

8-bit

Down

Counter

÷ 16 ÷4

6-Bit

Down

Counter

8-Bit

Down

Counter

PRE1

Initial Value

Current Value

÷ 2

Clock

Logic

IRQ4

TOUT

P36

IRQ5

Internal Data Bus

Write Write Read

Internal Clock

Gated Clock

Triggered Clock

TIN P31

Write Write Read

Internal Data Bus

External Clock

Internal

Clock

D0 (SMR)

÷4

÷2

OSC

D1 (SMR)

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

38 P R E L I M I N A R Y DS97Z8X0502

FUNCTIONAL DESCRIPTION (Continued)

Interrupts. The MCU has six different interrupts from six

different sources. The interrupts are maskable and priori-

tized (Figure 28). The six sources are divided as follows:

four sources are claimed by Port 3 lines P33–P30) and two

in counter/timers. The Interrupt Mask Register globally or

individually enables or disables the six interrupt requests

(Table 10).

Figure 28. Interrupt Block Diagram

Table 10. Interrupt Types, Sources, and Vectors

Name Source Vector Location Comments

IRQ0 DAV0, IRQ0 0, 1 External (P32), Rising/Falling Edge Triggered

IRQ1 IRQ1 2, 3 External (P33), Falling Edge Triggered

IRQ2 DAV2, IRQ2, TIN 4, 5 External (P31), Rising/Falling Edge Triggered

IRQ3 IRQ3 6, 7 External (P30), Falling Edge Triggered

IRQ4 T0 8, 9 Internal

IRQ5 TI 10, 11 Internal

Interrupt

Edge

Select IRQ (D6, D7)

IRQ1, 3, 4, 5

IRQ

IMR

IPR

Priority

Logic

Global

Interrupt

Enable

Vector Select

Interrupt

Request

IRQ0 IRQ2

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 39

When more than one interrupt is pending, priorities are re-

solved by a programmable priority encoder that is con-

trolled by the Interrupt Priority Register (IPR). An interrupt

machine cycle is activated when an interrupt request is

granted. Thus, disabling all subsequent interrupts, saves

the Program Counter and Status Flags, and then branches

to the program memory vector location reserved for that in-

terrupt. All interrupts are vectored through locations in the

program memory. This memory location and the next byte

contain the 16-bit starting address of the interrupt service

routine for that particular interrupt request.

To accommodate polled interrupt systems, interrupt inputs

are masked and the interrupt request register is polled to

determine which of the interrupt requests need service.

An interrupt resulting from AN1 is mapped into IRQ2, and

an interrupt from AN2 is mapped into IRQ0. Interrupts

IRQ2 and IRQ0 may be rising, falling or both edge trig-

gered, and are programmable by the user. The software

may poll to identify the state of the pin.

Programming bits for the Interrupt Edge Select are located

in bits D7 and D6 of the IRQ Register (R250). The

configuration is shown in Table 11.

Clock. The on-chip oscillator has a high-gain, parallel-res-

onant amplifier for connection to a crystal, RC, ceramic

resonator, or any suitable external clock source (XTAL1 =

Input, XTAL2 = Output). The crystal should be AT cut, 10

KHz to 16 MHz max, with a series resistance (RS) less

than or equal to 100 Ohms.

The crystal should be connected across XTAL1 and

XTAL2 using the vendor's recommended capacitor values

from each pin directly to device pin Ground. The RC oscil-

lator option can be selected in the programming mode.

The RC oscillator configuration must be an external resis-

tor connected from XTAL1 to XTAL2, with a frequency-set-

ting capacitor from XTAL1 to Ground (Figure 29).

Table 11. IRQ Register Conﬁguration

IRQ Interrupt Edge

D7 D6 P31 P32

00FF

01FR

10RF

1 1 R/F R/F

Notes:

F = Falling Edge

R = Rising Edge

Figure 29. Oscillator Conﬁguration

XTAL1

XTAL2

XTAL1

XTAL2

XTAL1

XTAL2

XTAL1

XTAL2

Ceramic Resonator or

Crystal

C1, C2 = 47 pF TYP *

F = 8 MHz

C1, C2 = 22 pF

L = 130 µH *

F = 3 MHz *

@ 5V Vcc (TYP)

C1 = 100 pF

R = 2K

F = 6 MHz

External Clock

* Typical value including pin parasitics

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

40 P R E L I M I N A R Y DS97Z8X0502

FUNCTIONAL DESCRIPTION (Continued)

Power-On Reset (POR). A timer circuit clocked by a ded-

icated on-board RC oscillator is used for the Power-On Re-

set (POR) timer function. The POR timer allows VCC and

the oscillator circuit to stabilize before instruction execu-

tion begins.

The POR timer circuit is a one-shot timer triggered by one

of three conditions:

1. Power fail to Power OK status

2. Stop-Mode Recovery (if D5 of SMR=0)

3. WDT time-out

The POR time is a nominal 5 ms. Bit 5 of the STOP mode

passed after STOP-Mode Recovery (typical for an external

clock and RC/LC oscillators with fast start up times).

HALT. Turns off the internal CPU clock, but not the XTAL

oscillation. The counter/timers and external interrupt IRQ0,

IRQ1, and IRQ2 remain active. The device is recovered by

interrupts, either externally or internally generated. An in-

terrupt request must be executed (enabled) to exit HALT

Mode. After the interrupt service routine, the program con-

tinues from the instruction after the HALT.

In order to enter STOP or HALT Mode, it is necessary to

first flush the instruction pipeline to avoid suspending exe-

cution in mid-instruction. To do this, the user must execute

a NOP (Opcode=FFH) immediately before the appropriate

sleep instruction, that is:

STOP. This instruction turns off the internal clock and ex-

ternal crystal oscillation and reduces the standby current

to 10 microamperes or less. STOP Mode is terminated by

one of the following resets: either by WDT time-out, POR,

a Stop-Mode Recovery Source, which is defined by the

SMR register or external reset. This causes the processor

to restart the application program at address 000CH.

Port Configuration Register (PCON). The PCON regis-

ter configures the ports individually; comparator output on

Port 3, open-drain on Port 0 and Port 1, low EMI on Ports

0, 1, 2 and 3, and low EMI oscillator. The PCON register is

located in the expanded register file at Bank F, location 00

(Figure 30).

FF NOP ; clear the pipeline

6F STOP ; enter STOP Mode

FF NOP ; clear the pipeline

7F HALT ; enter HALT Mode

Figure 30. Port Conﬁguration Register (PCON)

(Write Only)

0 Port 0 Open Drain

1 Port 0 Push-pull Active*

D7 D6 D5 D4 D3 D2 D1 D0

PCON (FH) 00H

Comparator Output Port 3

0 P34, P37 Standard Output*

1 P34, P37 Comparator Output

0 Port 0 Low EMI

1 Port 0 Standard*

0 Port 2 Low EMI

1 Port 2 Standard*

Low EMI Oscillator

0 Low EMI

1 Standard*

0 Port 3 Low EMI

1 Port 3 Standard*

* Default Setting After Reset

0 Port 1 Open Drain

1 Port 1 Push-pull Active*

0 Port 1 Low EMI

1 Port 1 Standard*

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 41

Comparator Output Port 3 (D0). Bit 0 controls the com-

parator output in Port 3. A “1” in this location brings the

comparator outputs to P34 and P37, and a “0” releases the

Port to its standard I/O configuration. The default value

is 0.

Port 1 Open-Drain (D1). Port 1 can be configured as an

open-drain by resetting this bit (D1=0) or configured as

push-pull active by setting this bit (D1=1). The default val-

ue is 1.

Port 0 Open-Drain (D2). Port 0 can be configured as an

open-drain by resetting this bit (D2=0) or configured as

push-pull active by setting this bit (D2=1). The default val-

ue is 1.

Low EMI Port 0 (D3). Port 0 can be configured as a Low

EMI Port by resetting this bit (D3=0) or configured as a

Standard Port by setting this bit (D3=1). The default value

is 1.

Low EMI Port 1 (D4). Port 1 can be configured as a Low

EMI Port by resetting this bit (D4=0) or configured as a

Standard Port by setting this bit (D4=1). The default value

is 1. Note: The emulator does not support Port 1 low EMI

mode and must be set D4 = 1.

Low EMI Port 2 (D5). Port 2 can be configured as a Low

EMI Port by resetting this bit (D5=0) or configured as a

Standard Port by setting this bit (D5=1). The default value

is 1.

Low EMI Port 3 (D6). Port 3 can be configured as a Low

EMI Port by resetting this bit (D6=0) or configured as a

Standard Port by setting this bit (D6=1). The default value

is 1.

Low EMI OSC (D7). This bit of the PCON Register con-

trols the low EMI noise oscillator. A “1” in this location con-

figures the oscillator with standard drive. While a “0” con-

figures the oscillator with low noise drive, however, it does

not affect the relationship of SCLK and XTAL. The low EMI

mode will reduce the drive of the oscillator (OSC). The de-

fault value is 1. Note: 4 MHz is the maximum external

clock frequency when running in the low EMI oscillator

mode.

Stop-Mode Recovery Register (SMR). This register

selects the clock divide value and determines the mode of

Stop-Mode Recovery (Figure 31). All bits are Write Only

except bit 7 which is a Read Only. Bit 7 is a flag bit that is

hardware set on the condition of STOP Recovery and

reset by a power-on cycle. Bit 6 controls whether a low or

high level is required from the recovery source. Bit 5

controls the reset delay after recovery. Bits 2, 3, and 4 of

the SMR register specify the Stop-Mode Recovery Source.

The SMR is located in Bank F of the Expanded Register

Group at address 0BH.

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

42 P R E L I M I N A R Y DS97Z8X0502

FUNCTIONAL DESCRIPTION (Continued)

Figure 31. STOP-Mode Recovery Register

(Write-Only Except Bit D7, Which is Read-Only)

D7 D6 D5 D4 D3 D2 D1 D0

SMR (F) 0B

SCLK/TCLK Divide by 16

0 OFF

1 ON

Stop Mode Recovery Source

000 POR and/or External Reset

001 P30

010 P31

011 P32

100 P33

101 P27

110 P2 NOR 0:3

111 P2 NOR 0:7

Stop Delay

0 OFF

1 ON

Stop Recovery Level

0 Low

1 High

Stop Flag

0 POR

1 Stop Recovery

* Default setting after RESET.

** Default setting after RESET and STOP-Mode Recovery.

External Clock Divide by 2

0 SCLK/TCLK =XTAL/2*

1 SCLK/TCLK =XTAL

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 43

SCLK/TCLK Divide-by-16 Select (D0). This bit of the

SMR controls a divide-by-16 prescaler of SCLK/TCLK.

The purpose of this control is to selectively reduce device

power consumption during normal processor execution

(SCLK control) and/or HALT mode (where TCLK sources

counter/timers and interrupt logic).

External Clock Divide-by-Two (D1). This bit can elimi-

nate the oscillator divide-by-two circuitry. When this bit is

0, the System Clock (SCLK) and Timer Clock (TCLK) are

equal to the external clock frequency divided by two. The

SCLK/TCLK is equal to the external clock frequency when

this bit is set (D1=1). Using this bit together with D7 of

PCON further helps lower EMI (i.e., D7 (PCON) = 0, D1

(SMR) = 1). The default setting is zero.

STOP-Mode Recovery Source (D2, D3, and D4). These

three bits of the SMR register specify the wake up source

of the STOP-Mode Recovery (Figure 32). Table 12 shows

the SMR source selected with the setting of D2 to D4.

P33–P31 cannot be used to wake up from STOP mode

when programmed as analog inputs. When the STOP-

Mode Recovery sources are selected in this register then

SMR2 register bits D0, D1 must be set to zero.

Note: If the Port2 pin is configured as an output, this output

level will be read by the SMR circuitry.

Figure 32. Stop-Mode Recovery Source

P30

P31

P32 P33 P27

Stop-Mode Recovery Edge

Select (SMR)

P33 From Pads

Digital/Analog Mode

Select (P3M)

To P33 Data

Latch and IRQ1

To POR

RESET

SMR SMR SMRD4 D3 D2

0 0 1

0 1 0

0 1 1

D4 D3 D2

1 0 0 D4 D3 D2

1 0 1

MUX

SMR SMRD4 D3 D2

1 1 0 D4 D3 D2

1 1 1

P20

P23

P20

P27

SMR2 SMR2D1 D0

0 1 D1 D0

1 0

P20

P23

P20

P27

SMR D4 D3 D2

0 0 0

VDD

SMR2 D1 D0

0 0

VDD

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

44 P R E L I M I N A R Y DS97Z8X0502

FUNCTIONAL DESCRIPTION (Continued)

Stop-Mode Recovery Delay Select (D5). The 5 ms RE-

SET delay after Stop-Mode Recovery is disabled by pro-

gramming this bit to a zero. A “1” in this bit will cause a 5

ms RESET delay after Stop-Mode Recovery. The default

condition of this bit is 1. If the fast wake up mode is select-

ed, the Stop-Mode Recovery source needs to be kept ac-

tive for at least 5TpC.

Stop-Mode Recovery Level Select (D6). A “1” in this bit

defines that a high level on any one of the recovery sourc-

es wakes the MCU from STOP Mode. A 0 defines low level

recovery. The default value is 0.

Cold or Warm Start (D7). This bit is set by the device

upon entering STOP Mode. A “0” in this bit indicates that

the device has been reset by POR (cold). A “1” in this bit

indicates the device was awakened by a SMR source

(warm).

Stop-Mode Recovery Register 2 (SMR2). This register

contains additional Stop-Mode Recovery sources. When

the Stop-Mode Recovery sources are selected in this reg-

ister then SMR Register. Bits D2, D3, and D4 must be 0.

Watch-Dog Timer Mode Register (WDTMR). The WDT

is a retriggerable one-shot timer that resets the Z8 if it

reaches its terminal count. The WDT is disabled after Pow-

er-On Reset and initially enabled by executing the WDT in-

struction and refreshed on subsequent executions of the

WDT instruction. The WDT is driven either by an on-board

RC oscillator or an external oscillator from XTAL1 pin. The

POR clock source is selected with bit 4 of the WDT regis-

ter.

Note: Execution of the WDT instruction affects the Z (Ze-

ro), S (Sign), and V (Overflow) flags.

WDT Time-Out Period (D0 and D1). Bits 0 and 1 control

a tap circuit that determines the time-out periods that can

be obtained (Table 13). The default value of D0 and D1

are 1 and 0, respectively.

WDT During HALT Mode (D2). This bit determines

whether or not the WDT is active during HALT Mode. A “1”

indicates that the WDT is active during HALT. A “0” dis-

ables the WDT in HALT Mode. The default value is “1”.

WDT During STOP Mode (D3). This bit determines

whether or not the WDT is active during STOP mode. A “1”

indicates active during STOP. A “0” disables the WDT dur-

ing STOP Mode. This is applicable only when the WDT

clock source is the internal RC oscillator.

Clock Source For WDT (D4). This bit determines which

oscillator source is used to clock the internal POR and

WDT counter chain. If the bit is a 1, the internal RC oscil-

lator is bypassed and the POR and WDT clock source is

driven from the external pin, XTAL1, and the WDT is

stopped in STOP Mode. The default configuration of this

bit is 0, which selects the RC oscillator.

Permanent WDT. When this feature is enabled, the WDT

is enabled after reset and will operate in Run and Halt

Mode. The control bits in the WDTMR do not affect the

WDT operation. If the clock source of the WDT is the inter-

nal RC oscillator, then the WDT will run in STOP mode. If

the clock source of the WDT is the XTAL1 pin, then the

WDT will not run in STOP mode.

Note: WDT time-out in STOP Mode will not reset

SMR,SMR2,PCON, WDTMR, P2M, P3M, Ports 2 & 3 Data

Registers.

WDTMR Register Accessibility. The WDTMR register is

accessible only during the first 60 internal system clock

Table 12. Stop-Mode Recovery Source

D4 D3 D2 SMR Source selection

0 0 0 POR recovery only

0 0 1 P30 transition

0 1 0 P31 transition (Not in analog

mode)

0 1 1 P32 transition (Not in analog

mode)

1 0 0 P33 transition (Not in analog

mode)

1 0 1 P27 transition

1 1 0 Logical NOR of Port 2 bits 0–3

1 1 1 Logical NOR of Port 2 bits 0–7

SMR:10 Operation

D1 D0 Description of Action

0 0 POR and/or external reset recovery

0 1 Logical AND of P20 through P23

1 0 Logical AND of P20 through P27

Table 13. Time-out Period of WDT

D1 D0

Time-out of

the Internal

RC OSC

Time-out of

the System

Clock

0 0 5 ms 128 SCLK

0 1 10 ms* 256 SCLK*

1 0 20 ms 512 SCLK

1 1 80 ms 2048 SCLK

Notes:

*The default setting is 10 ms.

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 45

cycles from the execution of the first instruction after

Power-On Reset, Watch-Dog reset or a STOP-Mode

Recovery (Figures 33 and 34). After this point, the register

cannot be modified by any means, intentional or

otherwise. The WDTMR cannot be read and is located in

Bank F of the Expanded Register Group at address

location 0FH.

Figure 33. Watch-Dog Timer Mode Register

Write Only

D7 D6 D5 D4 D3 D2 D1 D0

WDTMR (F) 0F

WDT TAP INT RC OSC System Clock

00 5 ms 128 SCLK

01 10 ms 256 SCLK

10 20 ms 512 SCLK

11 80 ms 2048 SCLK

WDT During HALT

0 OFF

1 ON

WDT During STOP

0 OFF

1 ON

XTAL1/INT RC Select for WDT

0 On-Board RC

1 XTAL

Reserved (Must be 0)

* Default settin

after RESET

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

46 P R E L I M I N A R Y DS97Z8X0502

FUNCTIONAL DESCRIPTION (Continued)

Figure 34. Resets and WDT

CLK 18 Clock RESET

Generator RESET

Clear

WDT TAP SELECT

Internal

RC OSC.

CK CLR

5ms POR 5ms 15ms 25ms 100ms

2V Operating

Voltage Det.

Internal

RESET

WDT Select

(WDTMR)

CLK Source

Select

(WDTMR)

XTAL

VDD

VLV

From Stop

Mode

Recovery

Source

WDT

Stop Delay

Select (SMR)

4 Clock

Filter

WDT/POR Counter Chain

Reset

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 47

Auto Reset Voltage. An on-board Voltage Comparator

checks that VCC is at the required level to ensure correct

operation of the device. Reset is globally driven if VCC is

below VLV (Figure 35).

Note: VCC must be in the allowed operating range prior to

the minimum Power-On Reset time-out (TPOR).

Figure 35. Typical Z86E40 VLV Voltage vs. T emperature

-60 -40 -20 0 20 40 60 80 100 120 140

VCC

(Volts)

3.5

3.3

3.1

2.9

2.7

2.5

2.3

Temperature

(°C)

3.7

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

48 P R E L I M I N A R Y DS97Z8X0502

FUNCTIONAL DESCRIPTION (Continued)

EPROM MODE

Table 14 shows the programming voltages of each pro-

gramming mode. Table 15, and figures that follow show

the programming timing of each programming mode. Fig-

ure 38 shows the circuit diagram of a Z86E40 program-

ming adapter, which adapts from 2764A to Z86E40 and

Figure 39 shows the Z86E30/E31 Programming Adapter

Circuitry. Figure 40 shows the flowchart of an Intelligent

Programming Algorithm, which is compatible with 2764A

EPROM (Z86E40 is 4K EPROM, 2764A is 8K EPROM).

Since the EPROM size of Z86E30/E31/E40 differs from

2764A, the programming address range has to be set from

0000H to 0FFFH for the Z86E30/E40 and 0000H to 07FFH

for Z86E31. Otherwise, the upper portion of EPROM data

will overwrite the lower portion of EPROM data. Figure 39

shows the adaptation from the 2764A to Z86E30/E31.

Note: EPROM Protect feature allows the LDC, LDCI, LDE,

and LDEI instructions from internal program memory. A

ROM lookup table can be used with this feature.

During programming, the VPP input pin supplies the pro-

gramming voltage and current to the EPROM. This pin is

also used to latch which EPROM mode is to be used (R/W

EPROM or R/W Option bits). The mode is set by placing

the correct mode number on the least significant bits of the

address and raising the EPM pin above V. After a setup

time, the VPP pin can then be raised or lowered. The

latched EPROM mode will remain until the EPM pin is re-

duced below VH.

EPROM R/W mode allows the programming of the user

mode program ROM.

Option Bit R/W allows the programming of the Z8 option

bits. When the device is latched into Option Bit R/W mode,

the address must then be changed to 63 decimals

(000000111111 Binary). The Options are mapped into this

address as follows:

Table 14 gives the proper conditions for EPROM R/W op-

erations, once the mode is latched.

Mode Name Mode # LSB Addr

EPROM R/W 0 0000

Option Bit R/W 3 0011

Bit Option

7 Unused

6 Unused

5 32 KHz XTAL Option

4 P ermanent WDT

3 Auto Latch Disable

2 RC Oscillator Option

1 RAM Protect

0 ROM Protect

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 49

Table 14. EPROM Programming Table

Programming

Modes VPP EPM CE OE PGM ADDR DATA VCC*

EPROM READ1 X VHVIL VIL VIH ADDR Out 4.5V†

EPROM READ2 X VHVIL VIL VIH ADDR Out 5.5V†

PROGRAM VH VH VIL VIH VIL ADDR In 6.4V

PROGRAM

VERIFY VH VH VIL VIL VIH ADDR Out 6.0V

OPTION BIT PGM VH VH VIL VIH VIL 63 IN 6.4V

OPTION BIT READ X VHVIL VIL VIH 63 OUT 6.0V

Notes:

VH = 13.0 V ± 0.1 V

VIH = As per specific Z8 DC specification

VIL= As per specific Z8 DC specification

X=Not used, but must be set to VH, VIH, or VIL level.

NU = Not used, but must be set to either VIH or VIL level.

IPP during programming = 40 mA maximum.

ICC during programming, verify, or read = 40 mA maximum.

*VCC has a tolerance of ±0.25V.

† Zilog recommends an EPROM read at VCC = 4.5 V and 5.5 V to

ensure proper device operations during the VCC after programming,

but VCC = 5.0 V is acceptable.

Table 15. EPROM Programming Timing

Parameters Name Min Max Units

1 Address Setup Time 2 µs

2 Data Setup Time 2 µs

PP Setup 2 µs

CC Setup Time 2 µs

5 Chip Enable Setup Time 2 µs

6 Program Pulse Width 0.95 1.05 ms

7 Data Hold Time 2 µs

8OE

Setup Time 2 µs

9 Data Access Time 200 ns

10 Data Output Float Time 100 ns

11 Overprogram Pulse

Width/Option Program

Pulse Width

2.85 ms

12 EPM Setup Time 2 µs

13 PGM Setup Time 2 µs

14 Address to OE Setup Time 2 µs

15 OE Width 250 ns

16 Address to OE Low 125 ns

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

50 P R E L I M I N A R Y DS97Z8X0502

FUNCTIONAL DESCRIPTION (Continued)

Figure 36. EPROM Read Mode Timing Diagram

Data

VIH

VIL Invalid Valid Invalid Valid

VIH

VIL Address Stable

Address Address Stable

EPM

VIL

V4.5V

VIH

VIL

VIH

VIL

VPP

VIL

5.5V

PGM

VIH

VIL

515

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 51

Z86E40 TIMING DIAGRAMS

Figure 37. Timing Diagram of EPROM Program and Verify Modes

Address

VIH

VIL Address Stable

Data

VIH

VIL Data Stable Data Out Valid

2109

VVH

VIH

EPM VIL

CE VIL

6 8

PGM

VIH

VIL

VIH

V4.5V

VIH

VIL

Program Cycle Verify Cycle

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

52 P R E L I M I N A R Y DS97Z8X0502

Z86E40 TIMING DIAGRAMS (Continued)

Figure 38. Z86E40 Z8 OTP Programming Adapter

For use with Standard EPROM Programmers

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34

P35

P36

P37

XTAL1

XTAL2

P04

P00

P01

P02

P03

6P05

P06

P07

306

PGM

A10

A11

A12

25 A8

GND

EPM

U1 U2

0.01µF

14 GND

28 VCC

1VPP

GND

2764 Pins

Z86E40

40-Pin DIP

Socket

20 CS

1 KOhm R2

1 KOhm R1

A10

A11

A10

A11

20 R/W

RESET

GND

P10

P11

P12

P13

P14

P15

P16

P17

25 PGM

16 OE

23 GND

GND

VCC

IH5043

12.5V 16 X1

4X3

4S2

5S4

EPM

D1 1

D3 3

D4 6

IX1

IX2

VCC 5.0 V

12.5 Volt

0.1µF

10 KOhm

12.5V R4

1 KOhm

GND

1N5243

1C2

GND 12 P1

GND

1N5231

1 KOhm

5.0V

VCC

VPP

VCC

VPP

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 53

Figure 39. Z86E30/E31 Programming Adapter Circuitry

GND

IH5043

12.5V 16 X1

4X3

4S2

5S4

EPM

D1 1

D3 3

D4 6

IX1

IX2

12.5 Volt

0.1µF

10 KOhm

12.5V R4

1 KOhm

GND

1N5243

1C2

GND 12 P1

GND

1N5231

1 KOhm

5.0V

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34

P35

P36

P37

XTAL1

XTAL2

P04

P00

P01

P02

P03

5P05

P06

P07

306

PGM

A10

A11

A12

25 A8

GND

EPM

U1 U2

0.01µF

14 GND

GND

2764 Pins

Z86E30/31

28-Pin DIP

Socket

20 CS

1 KOhm R2

1 KOhm R1

A10

A11

VCC 5.0 V Note: The programming address must be set to

0000H - 0FFFH (Lower 4K Byte Memory). For Z86E30

0000H - 07FFH (Lower 2K Byte Memory). For Z86E31

PGM

VPP

VCC VCC

VPP VPP

VCC

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 55

Figure 40. Z86E40 Programming Algorithm

Start

Vcc = 6.4 V

Vpp = 13.0 V

N = 0

Program

1 ms Pulse

Increment N

N = 25 ? Yes

Verify

One Byte

Pass

Fail

Prog. One Pulse

3xN ms Duration

Verify Byte Fail

Pass

Increment

Address Last Addr ?

Yes

Vcc = Vpp = 4.5V *

V erify All

Bytes

Device Failed

Addr =

First Location

Fail

Pass

V erify All

Bytes

Device Passed

Pass

Fail

Vcc = Vpp = 5.5V *

Note:

* To ensure proper operaton,

Zilog recommends Vcc range

of the device Vcc specification,

But Vcc = 5.0V is acceptable.

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

56 P R E L I M I N A R Y DS97Z8X0502

EXPANDED REGISTER FILE CONTROL REGISTERS

Figure 41. Port Conﬁguration Register

Write Only

Figure 42. STOP-Mode Recovery Register

Write Only Except Bit D7, Which is Read Only

0 Port 0 Open-Drain

1 Port 0 Push-pull Active*

D7 D6 D5 D4 D3 D2 D1 D0

PCON (FH) 00H

Comparator Output Port 3

0 P34, P37 Standard*

1 P34, P37 Comparator Output

0 Port 0 Low EMI

1 Port 0 Standard*

0 Port 2 Low EMI

1 Port 2 Standard*

Low EMI Oscillator

0 Low EMI

1 Standard*

0 Port 3 Low EMI

1 Port 3 Standard*

* Default Setting After Reset

† Must Be 1 for Z86E30/E31

0 Port 1 Open-Drain

1 Port 1 Push-Pull Active*†

0 Port 1 Low EMI

1 Port 1 Standard*†

D7 D6 D5 D4 D3 D2 D1 D0

SMR (FH) 0B

SCLK/TCLK Divide-by-16

0 OFF

1 ON

Stop Mode Recovery Source

000 POR Only and/or External Reset*

001 P30

010 P31

011 P32

100 P33

101 P27

110 P2 NOR 0-3

111 P2 NOR 0-7

Stop Delay

0 OFF

1 ON*

Stop Recovery Level

0 Low*

1 High

Stop Flag

0 POR*

1 Stop Recovery

* Default setting after RESET.

** Default setting after RESET and STOP-Mode Recovery.

External Clock Divide by 2

0 SCLK/TCLK =XTAL/2*

1 SCLK/TCLK =XTAL

Figure 43. Watch-Dog Timer Mode Register

Write Only

Figure 44. STOP-Mode Recovery Register 2

Write Only

D7 D6 D5 D4 D3 D2 D1 D0

WDTMR (F) 0F

WDT TAP INT RC OSC System Clock

00 5 ms 128 SCLK

01 10 ms 256 SCLK

10 20 ms 512 SCLK

11 80 ms 2048 SCLK

WDT During HALT

0 OFF

1 ON

WDT During STOP

0 OFF

1 ON

XTAL1/INT RC Select for WDT

0 On-Board RC

1 XTAL

Reserved (Must be 0)

* Default setting after RESET

D7 D6 D5 D4 D3 D2 D1 D0

SMR2 (0F) DH

Note: Not used in conjunction with SMR Source

Stop-Mode Recovery Source 2

00 POR only*

01 AND P20,P21,P22,P23

10 AND P20,P21,P22,P23,P24,

P25,P26,P27

Reserved (Must be 0)

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 57

Z8 CONTROL REGISTER DIAGRAMS

Figure 45. Reserved

Figure 46. Timer Mode Register

F1H: Read/Write

Figure 47. Counter/Timer 1 Register

F2H: Read/Write

D7 D6 D5 D4 D3 D2 D1 D0

Reserved (Must be 0)

R240

D7 D6 D5 D4 D3 D2 D1 D0

0 Disable T0 Count*

1 Enable T0 Count

0 No Function*

1 Load T0

0 No Function*

1 Load T1

0 Disable T1 Count*

1 Enable T1 Count

TIN Modes

00 External Clock Input*

01 Gate Input

10 Trigger Input

(Non-retriggerable)

11 Trigger Input

(Retriggerable)

TOUT Modes

00 Not Used*

01 T0 Out

10 T1 Out

11 Internal Clock Out

R241 TMR

Default After Reset = 00H

D7 D6 D5 D4 D3 D2 D1 D0

T1 Initial Value

(When Written)

(Range: 1-256 Decimal

01-00 HEX)

T1 Current Value

(When Read)

R242 T1

Figure 48. Prescaler 1 Register

F3H: Write Only

Figure 49. Counter/Timer 0 Register

F4H; Read/Write

Figure 50. Prescaler 0 Register

F5H: Write Only

D7 D6 D5 D4 D3 D2 D1 D0

Count Mode

0 T1 Single Pass*

1 T1 Modulo N

Clock Source

1 T1 Internal

0 T1 External Timing Input

(TIN Mode)

Prescaler Modulo

(Range: 1-64 Decimal

01-00 HEX)

R243 PRE1

*Default After Reset

D7 D6 D5 D4 D3 D2 D1 D0

T0 Initial Value

(When Written)

(Range: 1-256 Decimal

01-00 HEX)

T0 Current Value

(When Read)

R244 T0

D7 D6 D5 D4 D3 D2 D1 D0

Count Mode

0 T1 Single Pass

1 T1 Modulo N

Reserved (Must be 0)

R245 PRE0

Prescaler Modulo

(Range: 1-64 Decimal

01-00 HEX)

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

58 P R E L I M I N A R Y DS97Z8X0502

Z8 CONTROL REGISTER DIAGRAMS (Continued)

Figure 51. Port 2 Mode Register

F6H: Write Only

Figure 52. Port 3 Mode Register

F7H: Write Only

D7 D6 D5 D4 D3 D2 D1 D0

P20 - P27 I/O Definition

0 Defines Bit as Output

1 Defines Bit as Input*

R246 P2M

* Default After Reset

D7 D6 D5 D4 D3 D2 D1 D0

R247 P3M

0 Port 2 Open-Drain

1 Port 2 Push-pull Active

Reserved (Must be 0)

0 P32 = Input

P35 = Output

1 P32 = DAV0/RDY0

P35 = RDY0/DAV0

00 P33 = Input

P34 = Output

01 P33 = Input

10 P34 = DM

11 P33 = DAV1/RDY1

P34 = RDY1/DAV1

0 P31 = Input (TIN)

P36 = Output (TOUT)

1 P31 = DAV2/RDY2

P36 = RDY2/DAV2

0 P30 = Input

P37 = Output

0 P31, P32 Digital Mode

1 P31, P32 Analog Mode

Default After Reset = 00H

† Z86E30/E31 Must Be 00

†

Figure 53. Port 0 and 1 Mode Register

F8H: Write Only

Z86E30/E31 Only

Figure 54. Interrupt Priority Register

F9H: Write Only

D7 D6 D5 D4 D3 D2 D1 D0

R248 P01M

P03 – P00 Mode

00 Output

01 Input

1X A11–A8

Stack Selection

0 External

1 Internal

P17 – P10 Mode

00 Byte Output†

01 Byte Input

10 AD7–AD0

11 High-Impedance AD7–AD0,

AS, DS, R/W, A11–A8,

A15–A12, If Selected

P07 – P04 Mode

00 Output

01 Input

1X A15 - A12

External Memory Timing

0 Normal

1 Extended

Reset Condition = 0100 1101B

For ROMless Condition = 1011 0110B

† Z86E30/E31 Must be 00

D7 D6 D5 D4 D3 D2 D1 D0

Interrupt Group Priority

000 Reserved

001 C > A > B

010 A > B > C

011 A > C > B

100 B > C > A

101 C > B > A

110 B > A > C

111 Reserved

IRQ3, IRQ5 Priority (Group A)

0 IRQ5 > IRQ3

1 IRQ3 > IRQ5

IRQ0, IRQ2 Priority (Group B)

0 IRQ2 > IRQ0

1 IRQ0 > IRQ2

IRQ1, IRQ4 Priority (Group C)

0 IRQ1 > IRQ4

1 IRQ4 > IRQ1

Reserved (Must be 0)

R249 IPR

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 59

Figure 55. Interrupt Request Register

FAH: Read/Write

Figure 56. Interrupt Mask Register

FBH: Read/Write

Figure 57. Flag Register

FCH: Read/Write

D7 D6 D5 D4 D3 D2 D1 D0

R250 IRQ

Inter Edge

P31 ↓ P32 ↓ = 00

P31 ↓ P32 ↑ = 01

P31 ↑ P32 ↓ = 10

P31 ↑↓ P32 ↑↓ = 11

IRQ0 = P32 Input

IRQ1 = P33 Input

IRQ2 = P31 Input

IRQ3 = P30 Input

IRQ4 = T0

IRQ5 = T1

Default After Reset = 00H

D7 D6 D5 D4 D3 D2 D1 D0

1 Enables RAM Protect †

1 Enables IRQ5-IRQ0

(D0 = IRQ0)

1 Enables Interrupts

R251 IMR

† This option must be selected when ROM code is

submitted for ROM Masking, otherwise this control bit

is disabled permanently.

D7 D6 D5 D4 D3 D2 D1 D0

R252 FLAGS

User Flag F1

User Flag F2

Half Carry Flag

Decimal Adjust Flag

Overflow Flag

Sign Flag

Zero Flag

Carry Flag

Figure 58. Register Pointer

FDH: Read/Write

Figure 59. Stack Pointer High

FEH: Read/Write

Figure 60. Stack Pointer Low

FFH: Read/Write

D7 D6 D5 D4 D3 D2 D1 D0

R253 RP

Expanded Register File

Working Register Pointer

Default After Reset = 00H

D7 D6 D5 D4 D3 D2 D1 D0

(Z86E40)

Stack Pointer Upper

Byte (SP8 - SP15)

R254 SPH

(Z86E30/E31)

0 = 0 State

1 = 1 State

D7 D6 D5 D4 D3 D2 D1 D0

Stack Pointer Lower

Byte (SP0 - SP7)

R255 SPL

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

60 P R E L I M I N A R Y DS97Z8X0502

PACKAGE INFORMATION (Continued)

PACKAGE INFORMATION

Figure 61. 40-Pin DIP Package Diagram

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 61

Figure 62. 44-Pin PLCC Package Diagram

Figure 63. 44-Pin QFP Package Diagram

Figure 63. 44-Pin LQFP Package Diagram

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

62 P R E L I M I N A R Y DS97Z8X0502

Figure 64. 28-Pin DIP Package Diagram

Figure 65. 28-Pin SOIC Package Diagram

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 63

Figure 66. 28-Pin PLCC Package Diagram

Z86E30/E31/E40

Z8 4K OTP Microcontroller Zilog

64 P R E L I M I N A R Y DS97Z8X0502

ORDERING INFORMATION

Z86E40 (16 MHz)

For fast results, contact your local Zilog sales office for assistance in ordering the part desired.

Package

P = Plastic DIP

V = Plastic Leaded Chip Carrier

F = Plastic Quad Flat Pack

S = SOIC (Small Outline Integrated Circuit)

Temperature

S = 0 °C to +70 °C

E = -40 °C to +105 °C

Speed

16 = 16 MHz

Environmental

C= Plastic Standard

E = Hermetic Standard

40-Pin DIP 44-Pin PLCC 44-Pin QFP

Z86E4016PSC Z86E4016VSC Z86E4016FSC

Z86E4016PEC Z86E4016VEC Z86E4016FEC

Z86E30 (16 MHz)

28-Pin DIP 28-Pin SOIC 28-Pin PLCC

Z86E3016PSC Z86E3016SSC Z86E3016VSC

Z96E3016PEC Z86E3016SEC Z86E3016VEC

Z86E31 (16 MHz)

28-Pin DIP 28-Pin SOIC 28-Pin PLCC

Z86E3116PSC Z86E3116SSC Z86E3116VSC

Z86E3116PEC Z86E3116SEC Z86E3116VEC

Example:

Z 86E40 16 P S C

Environmental Flow

Temperature

Package

Speed

Product Number

Zilog Prefix

is a Z86E40, 16 MHz, DIP, 0°C to +70°C, Plastic Standard Flow

44-Pin LQFP

Z86E30/E31/E40

Zilog Z8 4K OTP Microcontroller

DS97Z8X0502 P R E L I M I N A R Y 65

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