FEATURES FUNCTIONAL BLOCK DIAGRAM SPI interface with error detection Includes CRC, invalid read/write address, and SCLK count error detection Supports burst and daisy-chain mode Industry-standard SPI Mode 0 and Mode 3 interfacecompatible Guaranteed break-before-make switching, allowing external wiring of switches to deliver multiplexer configurations VSS to VDD analog signal range Fully specified at 15 V, 20 V, +12 V, and +36 V 9 V to 40 V single-supply operation (VDD) 9 V to 22 V dual-supply operation (VDD/VSS) 8 kV HBM ESD rating Low on resistance 1.8 V logic compatibility with 2.7 V VL 3.3 V ADGS5414 S1 D1 S2 D2 S3 D3 S4 D4 S5 D5 S6 D6 S7 D7 S8 D8 SPI INTERFACE SCLK SDI CS RESET/VL SDO 15902-001 Data Sheet SPI Interface, Octal SPST Switches, 13.5 RON, 20 V/+36 V, Mux ADGS5414 Figure 1. APPLICATIONS Relay replacement Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems GENERAL DESCRIPTION The ADGS5414 contains eight independent single-pole/singlethrow (SPST) switches. An SPI interface controls the switches and has robust error detection features, including cyclic redundancy check (CRC) error detection, invalid read/write address error detection, and SCLK count error detection. It is possible to daisy-chain multiple ADGS5414 devices together. This enables the configuration of multiple devices with a minimal amount of digital lines. The ADGS5414 can also operate in burst mode to decrease the time between SPI commands. PRODUCT HIGHLIGHTS 1. 2. 3. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. 4. The on-resistance profile is flat over the full analog input range, ensuring ideal linearity and low distortion when switching audio signals. The ADGS5414 exhibits break-before-make switching action, allowing the use of the device in multiplexer applications with external wiring. 6. Rev. 0 5. The SPI interface removes the need for parallel conversion, logic traces, and reduces the general-purpose input/output (GPIO) channel count. Daisy-chain mode removes the need for additional logic traces when using multiple devices. CRC error detection, invalid read/write address error detenction, and SCLK count error detection ensures a robust digital interface. CRC and error detection capabilities allow the use of the ADGS5414 in safety critical systems. Break-before-make switching allows external wiring of the switches to deliver multiplexer configurations. The trench isolation analog switch section guards against latch-up. A dielectric trench separates the positive and negative channel transistors, preventing latch-up even under severe overvoltage conditions. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedby Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADGS5414 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Error Detection Features ........................................................... 22 Applications ....................................................................................... 1 Clearing the Error Flags Register ............................................. 23 Functional Block Diagram .............................................................. 1 Burst Mode .................................................................................. 23 General Description ......................................................................... 1 Software Reset ............................................................................. 23 Product Highlights ........................................................................... 1 Daisy-Chain Mode ..................................................................... 23 Revision History ............................................................................... 1 Power-On Reset .......................................................................... 24 Specifications..................................................................................... 3 Break-Before-Make Switching .................................................. 25 15 V Dual Supply ....................................................................... 3 Trench Isolation .......................................................................... 25 20 V Dual Supply ....................................................................... 5 Applications Information .............................................................. 26 12 V Single Supply ........................................................................ 7 Power Supply Rails ..................................................................... 26 36 V Single Supply ........................................................................ 9 Power Supply Recommendations............................................. 26 Continuous Current per Channel, Sx or Dx Pins .................. 11 Register Summary .......................................................................... 27 Timing Characteristics .............................................................. 11 Register Details ............................................................................... 28 Absolute Maximum Ratings.......................................................... 13 Switch Data Register .................................................................. 28 Thermal Resistance .................................................................... 13 Error Configuration Register.................................................... 28 ESD Caution ................................................................................ 13 Error Flags Register .................................................................... 29 Pin Configurations and Function Descriptions ......................... 14 Burst Enable Register ................................................................. 29 Typical Performance Characteristics ........................................... 15 Software Reset Register ............................................................. 29 Test Circuits ..................................................................................... 19 Outline Dimensions ....................................................................... 30 Terminology .................................................................................... 21 Ordering Guide .......................................................................... 30 Theory of Operation ...................................................................... 22 Address Mode ............................................................................. 22 REVISION HISTORY 10/2017--Revision 0: Initial Version Rev. 0 | Page 2 of 30 Data Sheet ADGS5414 SPECIFICATIONS 15 V DUAL SUPPLY Digital logic voltage (VDD) = +15 V 10%, negative supply voltage (VSS) = -15 V 10%, positive supply voltage (VL) = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) +25C -40C to +85C -40C to +125C Unit VDD to VSS V typ 13.5 18 22 max typ 0.8 1.8 2.2 1.3 1.4 VS = 10 V, IS = -10 mA 2.6 3 max typ max nA typ VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VD = 10 V; see Figure 32 0.1 0.25 0.1 1 Drain Off Leakage, ID (Off ) 0.25 0.15 0.4 1 7 2 14 DIGITAL OUTPUT Output Voltage Low, VOL Output Current, Low (IOL) or High (IOH) Digital Output Capacitance, COUT DIGITAL INPUTS Input Voltage High, VINH 7 tOFF Break-Before-Make Time Delay, tD Charge Injection, QINJ nA max nA typ nA max VS = 10 V, VD = 10 V; see Figure 32 VS = VD = 10 V; see Figure 28 V max V max A typ 0.1 A max pF typ 2 1.35 0.8 0.8 3.3 V < VL 5.5 V 2.7 V VL 3.3 V 3.3 V < VL 5.5 V 2.7 V VL 3.3 V VIN = VGND or VL 4 V min V min V max V max A typ A max pF typ 410 ns typ Load resistance (RL) = 300 , load capacitance (CL) = 35 pF VS = 10 V; see Figure 37 RL = 300 , CL = 35 pF VS = 10 V; see Figure 37 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 36 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 38 0.001 4 0.001 0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS tON nA max nA typ 0.4 0.2 Low, VINL Input Current, Low (IINL) or High (IINH) Source voltage (VS) = 10 V, IS = -10 mA; see Figure 29 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, source current (IS) = -10 mA 15 0.3 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Channel On Leakage, ID (On), IS (On) Test Conditions/Comments 420 135 140 260 250 125 515 515 185 195 210 Rev. 0 | Page 3 of 30 ns max ns typ ns max ns typ ns min pC typ Sink current (ISINK) = 5 mA ISINK = 1 mA Output voltage (VOUT) = ground voltage (VGND)or VL ADGS5414 Parameter Off Isolation Data Sheet +25C -60 -40C to +85C -40C to +125C Unit dB typ Channel to Channel Crosstalk -75 dB typ Total Harmonic Distortion + Noise (THD + N) -3 dB Bandwidth 0.01 % typ 200 MHz typ Insertion Loss -0.9 dB typ 11 11 30 pF typ pF typ pF typ Source Capacitance (CS) (Off ) Drain Capacitance(CD) (Off ) CD (On), CS (On) POWER REQUIREMENTS Positive Supply Current (IDD) 45 70 45 70 310 430 A typ A max A typ A max A typ A max Test Conditions/Comments RL = 50 , CL = 5 pF, frequency (f) = 1 MHz; see Figure 32 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 RL = 1 k, 15 V p-p, f = 20 Hz to 20 kHz; see Figure 33 RL = 50 , CL = 5 pF; see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 34 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +16.5 V, VSS = -16.5 V All switches open All switches open All switches closed, VL = 5.5 V All switches closed, VL = 5.5 V All switches closed, VL = 2.7 V All switches closed, VL = 2.7 V IL Inactive 6.3 14 A typ A max A typ 7 A typ 390 A typ 210 A typ 15 A typ 7.5 A typ 230 A typ 120 A typ 1.8 mA typ 8.0 SCLK = 1 MHz SCLK = 50 MHz SDI = 1 MHz SDI = 25 MHz Active at 50 MHz 2 2.1 0.7 1.0 Negative Supply Current (ISS) Dual-Supply Operation (VDD/VSS) 0.05 1.0 9 22 Rev. 0 | Page 4 of 30 mA max mA typ mA max A typ A max V min V max Digital inputs = 0 V or VL CS and SDI = 0 V or VL, VL = 5 V CS and SDI = 0 V or VL, VL = 3V CS = VL and SDI = 0 V or VL, VL = 5 V CS = VL and SDI = 0 V or VL, VL = 3 V CS and SCLK = 0 V or VL, VL =5V CS and SCLK = 0 V or VL, VL =3V CS and SCLK = 0 V or VL, VL =5V CS and SCLK = 0 V or VL, VL =3V Digital inputs toggle between 0 V and VL, VL = 5.5 V Digital inputs toggle between 0 V and VL, VL = 2.7 V Digital inputs = 0 V or VL GND = 0 V GND = 0 V Data Sheet ADGS5414 20 V DUAL SUPPLY VDD = +20 V 10%, VSS = -20 V 10%, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) +25C -40C to +85C -40C to +125C Unit VDD to VSS V typ 12.5 17 21 max typ 0.8 2.3 2.7 1.3 1.4 VS = 15 V, IS = -10 mA 3.1 3.5 max typ max nA typ VDD = +22 V, VSS = -22 V VS = 15 V, VD = 15 V; see Figure 32 0.1 0.25 0.1 1 Drain Off Leakage, ID (Off ) 0.25 0.15 0.4 1 7 2 14 DIGITAL OUTPUT Output Voltage Low, VOL Output Current, IOL or IOH 7 0.4 0.2 0.001 0.1 Digital Output Capacitance, COUT DIGITAL INPUTS Input Voltage High, VINH 4 2 1.35 0.8 0.8 Low, VINL Input Current, IINL or IINH 0.001 0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS tON 4 nA max nA typ nA max nA typ nA max V min V min V max V max A typ A max pF typ 3.3 V < VL 5.5 V 2.7 V VL 3.3 V 3.3 V < VL 5.5 V 2.7 V VL 3.3 V VIN = VGND or VL ns typ ns max ns typ ns max ns typ ns min pC typ RL = 300 , CL = 35 pF VS = 10 V; see Figure 37 RL = 300 , CL = 35 pF VS = 10 V; see Figure 37 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 36 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 38 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 RL = 1 k, 20 V p-p, f = 20 Hz to 20 kHz; see Figure 33 Off Isolation -60 dB typ Channel to Channel Crosstalk -75 dB typ (THD + N) 0.012 % typ 495 185 195 205 Rev. 0 | Page 5 of 30 VS = VD = 15 V; see Figure 28 ISINK = 5 mA ISINK = 1 mA VOUT = VGND or VL Charge Injection, QINJ Break-Before-Make Time Delay, tD 485 VS = 15 V, VD = 15 V; see Figure 32 V max V max A typ A max pF typ 410 418 135 144 255 245 160 tOFF VS = 15 V, IS = -10 mA; see Figure 29 VDD = +18 V, VSS = -18 V VS = 15 V, IS = -10 mA 14 0.3 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Channel On Leakage, ID (On), IS (On) Test Conditions/Comments ADGS5414 Data Sheet Parameter -3 dB Bandwidth Insertion Loss +25C 200 -0.8 CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 11 11 30 -40C to +85C -40C to +125C Unit MHz typ dB typ pF typ pF typ pF typ 50 110 50 110 320 450 A typ A max A typ A max A typ A max Test Conditions/Comments RL = 50 , CL = 5 pF; see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 34 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +22 V, VSS = -22 V All switches open All switches open All switches closed, VL = 5.5 V All switches closed, VL = 5.5 V All switches closed, VL = 2.7 V All switches closed, VL = 2.7 V IL Inactive 6.3 14 7 390 A typ A max A typ A typ A typ 210 A typ 15 7.5 230 120 1.8 A typ A typ A typ A typ mA typ 8.0 SCLK = 1 MHz SCLK = 50 MHz SDI = 1 MHz SDI = 25 MHz Active at 50 MHz 2 2.1 0.7 1.0 ISS Dual-Supply Operation (VDD/VSS) 0.05 1.0 9 22 Rev. 0 | Page 6 of 30 mA max mA typ mA max A typ A max V min V max Digital inputs = 0 V or VL CS and SDI = 0 V or VL, VL = 5 V CS and SDI = 0 V or VL, VL = 3 V CS = VL and SDI = 0 V or VL, VL = 5 V CS = VL and SDI = 0 V or VL, VL = 3 V CS and SCLK = 0 V or VL, VL = 5 V CS and SCLK = 0 V or VL, VL = 3 V CS and SCLK = 0 V or VL, VL = 5 V CS and SCLK = 0 V or VL, VL = 3 V Digital inputs toggle between 0 V and VL, VL = 5.5 V Digital inputs toggle between 0 V and VL, VL = 2.7 V Digital inputs = 0 V or VL GND = 0 V GND = 0 V Data Sheet ADGS5414 12 V SINGLE SUPPLY VDD = 12 V 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT (ON) +25C -40C to +85C Unit 0 V to VDD V typ 26 42 max typ 1 5.5 6.5 1.5 1.6 VS = 0 V to 10 V, IS = -10 mA 8 12 max typ max nA typ VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 32 0.25 0.1 1 Drain Off Leakage, ID (Off ) 0.25 0.15 1 Channel On Leakage, ID (On), IS (On) 0.4 2 DIGITAL OUTPUT Output Voltage Low, VOL 7 7 V max V max A typ A max pF typ ISINK = 5 mA ISINK = 1 mA VOUT = VGND or VL V min V min V max V max A typ A max pF typ 3.3 V < VL 5.5 V 2.7 V VL 3.3 V 3.3 V < VL 5.5 V 2.7 V VL 3.3 V VIN = VGND or VL ns typ ns max ns typ ns max ns typ ns min pC typ RL = 300 , CL = 35 pF VS = 8 V; see Figure 37 RL = 300 , CL = 35 pF VS = 8 V; see Figure 37 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; see Figure 36 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 38 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 31 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 4 2 1.35 0.8 0.8 0.001 4 Charge Injection, QINJ 450 455 135 141 285 275 55 Off Isolation -60 dB typ Channel to Channel Crosstalk -75 dB typ tOFF Break-Before-Make Time Delay, tD VS = VD = 1 V/10 V; see Figure 28 0.4 0.2 0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS tON nA max nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 32 nA max 0.001 Low, VINL nA max nA typ 14 0.1 Input Current, IINL or IINH VS = 0 V to 10 V, IS = -10 mA; see Figure 29 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -10 mA 36 0.1 Digital Output Capacitance, COUT DIGITAL INPUTS Input Voltage High, VINH Test Conditions/Comments 30 0.3 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Output Current, IOL or IOH -40C to +125C 555 575 195 205 225 Rev. 0 | Page 7 of 30 ADGS5414 Parameter THD +N Data Sheet +25C 0.1 -40C to +85C -40C to +125C Unit % typ -3 dB Bandwidth 220 MHz typ Insertion Loss -1.55 dB typ 12 12 30 pF typ pF typ pF typ CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 40 65 40 65 300 420 A typ A max A typ A max A typ A max Test Conditions/Comments RL = 1 k, 6 V p-p, f = 20 Hz to 20 kHz; see Figure 33 RL = 50 , CL = 5 pF; see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 34 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V All switches open All switches open All switches closed, VL = 5.5 V All switches closed, VL = 5.5 V All switches closed, VL = 2.7 V All switches closed, VL = 2.7 V IL Inactive 6.3 14 7 390 A typ A max A typ A typ A typ 210 A typ 15 A typ 7.5 A typ 230 A typ 120 A typ 1.8 mA typ 8.0 SCLK = 1 MHz SCLK = 50 MHz SDI = 1 MHz SDI = 25 MHz Active at 50 MHz 2 2.1 0.7 Single-Supply Operation (VDD) 1.0 9 40 Rev. 0 | Page 8 of 30 mA max mA typ mA max V min V max Digital inputs = 0 V or VL CS and SDI = 0 V or VL, VL = 5 V CS and SDI = 0 V or VL, VL = 3 V CS = VL and SDI = 0 V or VL, VL = 5 V CS = VL and SDI = 0 V or VL, VL = 3 V CS and SCLK = 0 V or VL, VL = 5V CS and SCLK = 0 V or VL, VL = 3V CS and SCLK = 0 V or VL, VL = 5V CS and SCLK = 0 V or VL, VL = 3V Digital inputs toggle between 0 V and VL, VL = 5.5 V Digital inputs toggle between 0 V and VL, VL = 2.7 V GND = 0 V, VSS = 0 V GND = 0 V, VSS = 0 V Data Sheet ADGS5414 36 V SINGLE SUPPLY VDD = 36 V 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, RON On-Resistance Flatness, RFLAT(ON) +25C -40C to +85C Unit 0 V to VDD V typ 14.5 23 max typ 0.8 3.5 4.3 1.3 1.4 VS = 0 V to 30 V, IS = -10 mA 5.5 6.5 max typ max nA typ VDD = 39.6 V, VSS = 0 V VS = 1 V/30 V, VD = 30 V/1 V; see Figure 32 0.25 0.1 1 Drain Off Leakage, ID (Off ) 0.25 0.15 1 Channel On Leakage, ID (On), IS (On) 0.4 2 DIGITAL OUTPUT Output Voltage Low, VOL 7 7 V max V max A typ A max pF typ ISINK = 5 mA ISINK = 1 mA VOUT = VGND or VL V min V min V max V max A typ A max pF typ 3.3 V < VL 5.5 V 2.7 V VL 3.3 V 3.3 V < VL 5.5 V 2.7 V VL 3.3 V VIN = VGND or VL ns typ ns max ns typ ns max ns typ ns min RL = 300 , CL = 35 pF VS = 18 V; see Figure 37 RL = 300 , CL = 35 pF VS = 18 V; see Figure 37 RL = 300 , CL = 35 pF VS1 = VS2 = 18 V; see Figure 36 VS = 18 V, RS = 0 , CL = 1 nF; see Figure 38 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 31 RL = 50 , CL = 5 pF, f = 1 MHz; Figure 30 4 2 1.35 0.8 0.8 0.001 tOFF Break-Before-Make Time Delay, tD 4 425 435 145 151 260 245 VS = VD = 1 V/30 V; see Figure 28 0.4 0.2 0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS tON nA max nA typ VS = 1 V/30 V, VD = 30 V/1 V; see Figure 32 nA max 0.001 Low, VINL nA max nA typ 14 0.1 Input Current, IINL or IINH VS = 0 V to 30 V, IS = -10 mA; see Figure 29 VDD = 32.4 V, VSS = 0 V VS = 0 V to 30 V, IS = -10 mA 19 0.1 Digital Output Capacitance, COUT DIGITAL INPUTS Input Voltage High, VINH Test Conditions/Comments 16 0.3 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Output Current, IOL or IOH -40C to +125C 515 515 195 195 205 Charge Injection, QINJ 145 pC typ Off Isolation -60 dB typ Channel to Channel Crosstalk -75 dB typ Rev. 0 | Page 9 of 30 ADGS5414 Parameter THD + N Data Sheet +25C 0.04 -40C to +85C -40C to +125C Unit % typ -3 dB Bandwidth 200 MHz typ Insertion Loss -0.85 dB typ 11 11 26 pF typ pF typ pF typ CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 80 130 80 130 330 490 A typ A max A typ A max A typ A max Test Conditions/Comments RL = 1 k, 18 V p-p, f = 20 Hz to 20 kHz; see Figure 33 RL = 50 , CL = 5 pF; see Figure 34 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 34 VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VDD = 39.6 V All switches open All switches open All switches closed, VL = 5.5 V All switches closed, VL = 5.5 V All switches closed, VL = 2.7 V All switches closed, VL = 2.7 V IL Inactive 6.3 14 A typ A max A typ 7 A typ 390 A typ 210 A typ 15 A typ 7.5 A typ 230 A typ 120 A typ 1.8 mA typ 8.0 SCLK = 1 MHz SCLK = 50 MHz SDI = 1 MHz SDI = 25 MHz Active at 50 MHz 2 2.1 0.7 Single-Supply Operation (VDD) 1.0 9 40 Rev. 0 | Page 10 of 30 mA max mA typ mA max V min V max Digital inputs = 0 V or VL CS and SDI = 0 V or VL, VL = 5 V CS and SDI = 0 V or VL, VL = 3 V CS = VL and SDI = 0 V or VL, VL = 5 V CS = VL and SDI = 0 V or VL, VL = 3 V CS and SCLK = 0 V or VL, VL = 5V CS and SCLK = 0 V or VL, VL = 3V CS and SCLK = 0 V or VL, VL = 5V CS and SCLK = 0 V or VL, VL = 3V Digital inputs toggle between 0 V and VL, VL = 5.5 V Digital inputs toggle between 0 V and VL, VL = 2.7 V GND = 0 V, VSS = 0 V GND = 0 V, VSS = 0 V Data Sheet ADGS5414 CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Pins Table 5. Eight Channels On Parameter CONTINUOUS CURRENT, Sx OR Dx PINS VDD = +15 V, VSS = -15 V (JA = 50C/W) VDD = +20 V, VSS = -20 V (JA = 50C/W) VDD = 12 V, VSS = 0 V (JA = 50C/W) VDD = 36 V, VSS = 0 V (JA = 50C/W) 25C 85C 125C Unit 82 86 63 85 61 63 47 62 38 41 29 40 mA maximum mA maximum mA maximum mA maximum 25C 85C 125C Unit 199 210 157 206 124 129 104 127 75 77 68 76 mA maximum mA maximum mA maximum mA maximum Table 6. One Channel On Parameter CONTINUOUS CURRENT, Sx OR Dx PINS VDD = +15 V, VSS = -15 V (JA = 50C/W) VDD = +20 V, VSS = -20 V (JA = 50C/W) VDD = 12 V, VSS = 0 V (JA = 50C/W) VDD = 36 V, VSS = 0 V (JA = 50C/W) TIMING SPECIFICATIONS VL = 2.7 V to 5.5 V; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 7. Parameter TIMING CHARACTRISTICS t1 t2 t3 t4 t5 t6 t7 t8 t91 t10 t11 t12 t13 1 Limit Unit Test Conditions/Comments 20 8 8 10 6 8 10 20 20 20 20 8 8 ns min ns min ns min ns min ns min ns min ns min ns max ns max ns max ns min ns min ns min SCLK period SCLK high pulse width SCLK low pulse width CS falling edge to SCLK active edge Data setup time Data hold time SCLK active edge to CS rising edge CS falling edge to SDO data available SCLK falling edge to SDO data available CS rising edge to SDO returns to high impedance CS high time between SPI commands CS falling edge to SCLK becomes stable CS rising edge to SCLK becomes stable Measured with the 1 k pull-up resistor to VL and a 20 pF load. t9 determines the maximum SCLK frequency when using SDO. Rev. 0 | Page 11 of 30 ADGS5414 Data Sheet Timing Diagrams t1 SCLK t4 t2 t3 t7 CS t5 R/W SDI t6 A6 A5 D2 D1 D0 t10 t9 0 0 1 D2 D1 D0 15902-002 SDO t8 Figure 2. Addressable Mode Timing Diagram t1 SCLK t2 t3 t4 t7 CS D7 D6 D0 INPUT BYTE FOR DEVICE N t9 SDO 0 t8 0 0 ZERO BYTE D7 D6 D1 D0 INPUT BYTE FOR DEVICE N + 1 D7 D6 D1 D0 INPUT BYTE FOR DEVICE N Figure 3. Daisy Chain Timing Diagram t11 CS SCLK t13 t12 Figure 4. SCLK/CS Timing Diagram Rev. 0 | Page 12 of 30 t10 15902-003 SDI t6 15902-004 t5 Data Sheet ADGS5414 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 8. Parameter VDD to VSS VDD to GND VSS to GND VL to GND Analog Inputs1 Digital Inputs1 Peak Current, Sx or Dx Pins Continuous Current, Sx or Dx Pins2 Operating Temperature Range Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature, Pb Free Human Body Model (HBM) Electrostatic Discharge (ESD) Rating 48 V -0.3 V to +48 V +0.3 V to -48 V -0.3 V to +5.75 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first -0.3 V to +5.75 V 422 mA (pulsed at 1 ms, 10% duty cycle maximum) Data (see Table 5 and Table 6) + 15% -40C to +125C -65C to +150C 150C 260(+0 or -5)C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. Table 9. Thermal Resistance 8 kV Package Type CP-24-171 JA 50 JC2 3.28 Unit C/W 1 Overvoltages at the Sx and Dx pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 See Table 5 and Table 6. 1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board. See JEDEC JESD51. 2 JCB is the junction to the bottom of the case value. ESD CAUTION Rev. 0 | Page 13 of 30 ADGS5414 Data Sheet 20 RESET/VL 19 SDO 22 SCLK 21 CS 24 SDI 23 GND PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 18 VSS VDD 1 S1 2 17 S8 D1 3 ADGS5414 16 D8 S2 4 TOP VIEW (Not to Scale) 15 S7 D2 5 14 D7 S3 6 NOTES 1. EXPOSED PAD. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE SUBSTRATE, VSS. 15902-005 S5 11 D6 12 D4 9 D5 10 S4 8 D3 7 13 S6 Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Mnemonic VDD S1 D1 S2 D2 S3 D3 S4 D4 D5 S5 D6 S6 D7 S7 D8 S8 VSS SDO 20 RESET/VL 21 CS 22 SCLK 23 24 GND SDI Exposed Pad Description Most Positive Power Supply Potential. Source Terminal 1. This pin can be an input or output. Drain Terminal 1. This pin can be an input or output. Source Terminal 2. This pin can be an input or output. Drain Terminal 2. This pin can be an input or output. Source Terminal 3. This pin can be an input or output. Drain Terminal 3. This pin can be an input or output. Source Terminal 4. This pin can be an input or output. Drain Terminal 4. This pin can be an input or output. Drain Terminal 5. This pin can be an input or output. Source Terminal 5. This pin can be an input or output. Drain Terminal 6. This pin can be an input or output. Source Terminal 6. This pin can be an input or output. Drain Terminal 7. This pin can be an input or output. Source Terminal 7. This pin can be an input or output. Drain Terminal 8. This pin can be an input or output. Source Terminal 8. This pin can be an input or output. Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground. Serial Data Output. This pin can daisy-chain a numeral ADGS5414 devices together or for reading back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of SCLK. Pull this open-drain output to VL with an external resistor. RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply. Pull the pin low to complete a hardware reset. All switches are opened, and the appropriate registers are set to their default. Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it powers on the SCLK buffers and enables the input shift register. Data is transferred in on the falling edges of the following clocks. Taking CS high updates the switch condition. Serial Clock Input. Data is captured on the positive edge of SCLK . Data can be transferred at rates of up to 50 MHz. Ground (0 V) Reference. Serial Data Input. Data is captured on the positive edge of the serial clock input. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. Rev. 0 | Page 14 of 30 Data Sheet ADGS5414 TYPICAL PERFORMANCE CHARACTERISTICS 25 16 TA = 25C 20 12 VDD = +11V VSS = -11V 15 10 VDD = +13.5V VSS = -13.5V VDD = +15V VSS = -15V VDD = +16.5V VSS = -16.5V 5 TA = 25C 14 ON RESISTANCE () ON RESISTANCE () VDD = +10V VSS = -10V VDD = +9V VSS = -9V 10 VDD = 32.4V VSS = 0V 8 VDD = 39.6V VSS = 0V VDD = 36V VSS = 0V 6 4 -14 -10 -6 -2 2 6 10 14 18 VS, VD (V) 0 15902-106 0 -18 5 10 15 20 25 30 35 40 45 VS, VD (V) Figure 6. RON as a Function of VS and VD (Dual Supply) 16 0 15902-109 2 Figure 9. RON as a Function of VS and VD (Single Supply) 25 TA = 25C 14 ON RESISTANCE () ON RESISTANCE () 20 VDD = +18V VSS = -18V 12 10 8 VDD = +22V VSS = -22V VDD = +20V VSS = -20V 6 TA = +125C 15 TA = +85C TA = +25C 10 TA = -40C 4 -20 -15 -10 -5 0 5 10 15 20 VS, VD (V) 25 VDD = 10.8V VSS = 0V VDD = 9V VSS = 0V ON RESISTANCE () -20 -15 VDD = 13.2V VSS = 0V -10 VDD = 12V VSS = 0V 5 10 15 VDD = +20V VSS = -20V 20 -25 VDD = 11V VSS = 0V 15 TA = +125C 10 TA = +25C TA = +85C TA = -40C 5 0 0 -2 -4 -6 -8 VS, VD (V) -10 -12 -14 Figure 8. RON as a Function of VS and VD (Single Supply) 0 -20 -15 -10 -5 0 VS, VD (V) 5 10 15 20 15902-111 -5 15902-108 ON RESISTANCE () -30 VDD = 10V VSS = 0V 0 VS, VD (V) 25 TA = 25C -5 Figure 10. RON as a Function of VS and VD for Different Temperatures, 15 V Dual Supply Figure 7. RON as a Function of VS and VD (Dual Supply) -35 VDD = +15V VSS = -15V 0 -15 -10 15902-107 0 -25 15902-110 5 2 Figure 11. RON as a Function of VS and VD for Different Temperatures, 20 V Dual Supply Rev. 0 | Page 15 of 30 ADGS5414 Data Sheet 40 0.20 35 0.15 TA = +85C 25 20 TA = +25C 15 TA = -40C 10 5 0 2 4 6 8 10 12 VS, VD (V) 0 -0.05 -0.10 -0.20 VDD = +20V VSS = -20V VBIAS = +10V, -10V 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 15. Leakage Currents vs. Temperature, 20 V Dual Supply Figure 12. RON as a Function of VS and VD for Different Temperatures, 12 V Single Supply 25 0.05 15902-112 0 IS (OFF) -, + IS, ID (ON) -, - 0.10 -0.15 VDD = 12V VSS = 0V ID (OFF) +, - IS, ID (ON) +, + 15902-115 ON RESISTANCE () LEAKAGE CURRENT (nA) TA = +125C 30 IS (OFF) +, - ID (OFF) -, + 0.20 VDD = 36V VSS = 0V IS (OFF) +, - ID (OFF) -, + 0.15 ID (OFF) +, - IS, ID (ON) +, + IS (OFF) -, + IS, ID (ON) -, - LEAKAGE CURRENT (nA) ON RESISTANCE () 20 TA = +125C 15 TA = +85C TA = +25C 10 TA = -40C 0.10 0.05 0 -0.05 -0.10 5 0 5 10 15 20 25 30 35 40 VS, VD (V) -0.20 15902-113 IS (OFF) +, - ID (OFF) -, + 0.3 60 80 100 120 IS (OFF) +, - ID (OFF) -, + ID (OFF) +, - IS, ID (ON) +, + IS (OFF) -, + IS, ID (ON) -, - 0.2 LEAKAGE CURRENT (nA) 0.10 0.05 0 -0.05 -0.10 0 20 40 0.1 0 -0.1 -0.2 VDD = +15V VSS = -15V VBIAS = +10V, -10V -0.15 -0.20 40 Figure 16. Leakage Currents vs. Temperature, 12 V Single Supply IS (OFF) -, + IS, ID (ON) -, - 60 80 100 15902-114 LEAKAGE CURRENT (nA) 0.15 ID (OFF) +, - IS, ID (ON) +, + 20 TEMPERATURE (C) Figure 13. RON as a Function of VS and VD for Different Temperatures, 36 V Single Supply 0.20 0 120 TEMPERATURE (C) Figure 14. Leakage Currents vs. Temperature, 15 V Dual Supply Rev. 0 | Page 16 of 30 -0.3 VDD = 36V VSS = 0V VBIAS = 1V, 30V 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 17. Leakage Currents vs. Temperature, 36 V Single Supply 15902-117 0 15902-116 VDD = +12V VSS = 0V VBIAS = +1V, -1V -0.15 Data Sheet TA = 25C VDD = +15V VSS = -15V -10 -60 -80 -50 -70 -100 -90 -120 -110 -140 100 1k 10k 100k 1M 10M 100M 1G 10G FREQUENCY (Hz) -130 100 -20 10k 100k 1M 10M Figure 21. ACPSRR vs. Frequency, 15 V Dual Supply 0.12 TA = 25C VDD = +15V VSS = -15V VDD = 12V, VSS = 0V, VS = 6V p-p 0.10 -40 LOAD = 1k TA = 25C 0.08 THD + N (%) CROSSTALK (dB) 1k FREQUENCY (Hz) Figure 18. Off Isolation vs. Frequency, 15 V Dual Supply 0 100nF DECOUPLING CAP 10F + 100nF DECOUPLIG CAP NO DECOUPLING -30 ACPSRR (dB) -40 15902-118 OFF ISOLATION (dB) -20 10 TA = 25C VDD = +15V VSS = -15V 15902-121 0 ADGS5414 -60 -80 0.06 VDD = 36V, VSS = 0V, VS = 18V p-p 0.04 -100 VDD = 15V, VSS = 15V, VS = 15V p-p 0.02 -120 100k 1M 10M 100M 1G FREQUENCY (Hz) 0 15902-119 -140 10k 0 = +20V, = +15V, = +12V, = +36V, VSS VSS VSS VSS 0 TA = 25C = -20V = -15V = 0V = 0V 20 TA = 25C VDD = +15V VSS = -15V -1 BANDWIDTH (dB) 200 150 100 -2 -3 -10 0 10 20 VS (V) 30 40 -5 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 23. Bandwidth vs. Frequency Figure 20. Charge Injection vs. VS Rev. 0 | Page 17 of 30 1G 15902-123 -4 50 0 -20 15 Figure 22. THD + N vs. Frequency, Dual Supply 15902-120 CHARGE INJECTION (pC) 250 VDD VDD VDD VDD 10 FREQUENCY (kHz) Figure 19. Crosstalk vs. Frequency, 15 V Dual Supply 300 5 15902-122 VDD = 20V, VSS = 20V, VS = 20V p-p ADGS5414 Data Sheet 0.5 500 450 SCLK = 2.5MHz SCLK IDLE 0.4 15V DS, tON 15V DS, tOFF 20V DS, tON 20V DS, tOFF 12V SS, tON 12V SS, tOFF 36V SS, tON 36V SS, tOFF 350 300 250 200 0.3 VOUT (mV) tON AND tOFF (ns) 400 0.2 0.1 0 150 -0.1 100 -0.2 50 0 20 40 60 80 100 120 -0.3 TEMPERATURE (C) 0 2 TA = 25C IDD WITH ONE SWITCH CLOSED 450 TA = 25C 400 350 80 IL (uA) 300 60 40 250 200 150 100 20 50 3.0 3.5 4.0 4.5 VL (V) 5.0 5.5 Figure 25. IDD vs. VL VL = 5V VL = 3V 0 0 10 20 30 40 SCLK FREQUENCY (MHz) Figure 27. IL vs. SCLK Frequency when CS is High Rev. 0 | Page 18 of 30 50 15902-127 0 2.7 15902-125 IDD (A) 8 Figure 26. Digital Feedthrough VL +12V 15V 20V +36V 100 6 TIME (s) Figure 24. tON and tOFF Times vs. Temperature 120 4 15902-126 -20 15902-124 0 -40 Data Sheet ADGS5414 TEST CIRCUITS Sx A VS VD VD Figure 32. Off Leakage VDD 0.1F VDD V1 Dx Dx VDD VOUT 15902-031 RL 1k GND Figure 29. On Resistance Figure 33. THD + Noise VSS 0.1F 0.1F VDD VSS S1 D1 VDD VSS 0.1F 0.1F NC VDD S2 VS RS VS V p-p 15902-027 RON = V1/IDS RL 50 AUDIO PRECISION VSS Sx VS VOUT VSS 0.1F IDS NETWORK ANALYZER A VS Figure 28. On Leakage Sx ID (ON) Dx 15902-030 ID (ON) Dx 15902-026 Sx D2 NETWORK ANALYZER VSS RL 50 Sx 50 GND VS Dx INSERTION LOSS = 20 log VOUT WITH SWITCH VS WITHOUT SWITCH 15902-032 Figure 30. Channel to Channel Crosstalk VDD V RL OUT 50 GND 15902-028 VOUT CHANNEL TO CHANNEL CROSSTALK = 20 log VS Figure 34. Bandwidth VSS 0.1F VDD Sx VSS NETWORK ANALYZER VSS 50 NETWORK ANALYZER 50 RL 50 VS Dx Figure 31. Off Isolation VOUT VS 15902-029 VOUT OFF ISOLATION = 20 log VDD VSS VS V RL OUT 50 GND INTERNAL BIAS S1 RL 50 ACPSRR = 20 log GND D1 VOUT VS NOTES 1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED FROM THE ACPSRR MEASUREMENT. Figure 35. ACPSRR Rev. 0 | Page 19 of 30 NC 15902-033 0.1F ADGS5414 Data Sheet VDD VSS 0.1F 0.1F SCLK 50% 50% 0V VSS VS1 S1 D1 VS2 S2 D2 INPUT LOGIC RL1 300 CL2 35pF RL2 300 CL1 35pF VOUT1 80% VOUT1 80% 0V VOUT2 VOUT2 GND 80% 80% 0V tD 15902-034 VDD tD Figure 36. Break-Before-Make Time Delay, tD VDD VSS 0.1F 0.1F VSS Sx VOUT Dx VS INPUT LOGIC RL 300 CL 35pF SCLK 50% 50% 90% VOUT GND 10% tON tOFF 15902-035 VDD Figure 37. Switching Times 3V SCLK RS VDD VSS VDD VSS Sx Dx QINJ = CL x VOUT INPUT LOGIC VOUT SWITCH OFF SWITCH ON Figure 38. Charge Injection Rev. 0 | Page 20 of 30 GND 15902-036 VOUT VOUT CL 1nF VS Data Sheet ADGS5414 TERMINOLOGY IDD IDD is the positive supply current. CIN CIN is the digital input capacitance. ISS ISS is the negative supply current. tON tON is the delay between applying the digital control input and the output switching on. VD, VS VD and VS are the analog voltages on Terminal D and Terminal S, respectively. RON RON represents the ohmic resistance between Terminal D and Terminal S. RON RON is the difference between the RON of any two channels. RFLAT(ON) RFLAT(ON) is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. IS (Off) IS (Off) is the source leakage current with the switch off. ID (Off) ID (Off) is the drain leakage current with the switch off. ID (On), IS (On) ID (On) and IS (On) are the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic 0. tOFF tOFF is the delay between applying the digital control input and the output switching off. tD tD is the off time measured between the 80% point of both switches when switching from one address state to another. Off Isolation Off isolation is a measure of unwanted signal coupling through an off switch. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 dB. On Response On response is the frequency response of the on switch. VINH VINH is the minimum input voltage for Logic 1. IINL, IINH IINL and IINH are the low and high input currents of the digital inputs. CD (Off) CD (Off) is the off switch drain capacitance, which is measured with reference to GND. CS (Off) CS (Off) is the off switch source capacitance, which is measured with reference to GND. Insertion Loss Insertion loss is the loss due to the on resistance of the switch. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR is the ratio of the amplitude of signal on the output to the amplitude of the modulation. ACPSRR is a measure of the ability of the device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. CD (On), CS (On) CD (On) and CS (On) are the on switch capacitances, which are measured with reference to GND. Rev. 0 | Page 21 of 30 ADGS5414 Data Sheet THEORY OF OPERATION A register write occurs on the 16th SCLK rising edge during SPI writes. The ADGS5414 is a set of SPI controlled, octal SPST switches with error detection features. SPI Mode 0 and Mode 3 can be used with the device, and it operates with SCLK frequencies up to 50 MHz. The default mode for the ADGS5414 is address mode in which the registers of the device are accessed by a 16-bit SPI command that is bounded by CS. The SPI command becomes 24 bits long if the user enables CRC error detection. Other error detection features include SCLK count error detection and invalid read/write error detection. If any of these SPI interface errors occur, they are detectable by reading the error flags register. The ADGS5414 can also operate in two other modes: burst mode and daisy-chain mode. During any SPI command, SDO sends out eight alignment bits on the first eight SCLK falling edges. The alignment bits observed at SDO are 0x25. ERROR DETECTION FEATURES Protocol and communication errors on the SPI interface are detectable. There are three detectable errors: incorrect SCLK error detection, invalid read and write address error detection, and CRC error detection. Each of these errors has a corresponding enable bit in the error configuration register. In addition, there is an error flag bit for each of these errors in the error flags register. The interface pins of the ADGS5414 are CS, SCLK, SDI, and SDO. Hold CS low when using the SPI interface. Data is captured on SDI on the rising edge of SCLK, and data is propagated out on SDO on the falling edge of SCLK. SDO has an open-drain output; thus, connect a pull-up to this output. When not pulled low by the ADGS5414, SDO is in a high impedance state. CRC Error Detection The CRC error detection feature extends a valid SPI frame by eight SCLK cycles. These eight extra cycles send the CRC byte for that SPI frame. The CRC byte is calculated by the SPI block using the 16-bit payload: the R/W bit, a selected register address, Bits[6:0], and selected Register Data Bits[7:0]. The CRC polynomial used in the SPI block is x8 + x2 + x1 + 1 with a seed value of 0. For a timing diagram with CRC enabled, see Figure 40. Register writes occur at the 24th SCLK rising edge with CRC error checking enabled. ADDRESS MODE Address mode is the default mode for the ADGS5414 upon power-up. A single SPI frame in address mode is bounded by a CS falling edge and the succeeding CS rising edge. The SPI frame is comprised of 16 SCLK cycles. The timing diagram for address mode is shown in Figure 39. The first SDI bit indicates if the SPI command is a read or write command. When the first bit is set to 0, a write command is issued, and if the first bit is set to 1, a read command is issued. The next seven bits determine the target register address. The remaining eight bits provide the data to the addressed register. The last eight bits are ignored during a read command, because, during these clock cycles, SDO propagates out the data contained in the addressed register. During an SPI write, the microcontroller or computer processing unit (CPU) provides the CRC byte through SDI. The SPI block checks the CRC byte just before the 24th SCLK rising edge. On this same edge, the register write is prevented if an incorrect CRC byte is received by the SPI interface. The CRC error flag is asserted in the error flags register in the case of the incorrect CRC byte being detected. During an SPI read, the CRC byte is provided to the microcontroller through SDO. The target register address of an SPI command is determined on the eighth SCLK rising edge. Data from this register propagates out on SDO from the ninth to the 16th SCLK falling edge during SPI reads. The CRC error detection feature is disabled by default and can be configured by the user through the error configuration register. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 CS SDI SDO 0 0 1 0 0 1 0 1 D7 D6 D5 Figure 39. Address Mode Timing Diagram Rev. 0 | Page 22 of 30 D4 D3 D2 D1 D0 15902-037 SCLK Data Sheet ADGS5414 1 2 8 9 10 16 17 18 19 20 21 22 23 24 R/W A6 A0 D7 D6 D0 C7 C6 C5 C4 C3 C2 C1 C0 CS SDI SDO 0 0 1 D7 D6 D0 C7 C6 C5 C4 C3 C2 C1 C0 15902-038 SCLK Figure 40. Timing Diagram with CRC Enabled SCLK Count Error Detection BURST MODE SCLK count error detection allows the user to detect if an incorrect number of SCLK cycles are sent by the microcontroller or CPU. When in address mode, with CRC disabled, 16 SCLK cycles are expected. If 16 SCLK cycles are not detected, the SCLK count error flag asserts in the error flags register. When less than 16 SCLK cycles are received by the device, a write to the register map does not occur. When the ADGS5414 receives more than 16 SCLK cycles, a write to the memory map still occurs at the 16th SCLK rising edge, and the flag asserts in the error flags register. With CRC enabled, the expected number of SCLK cycles becomes 24. SCLK count error detection is enabled by default and can be configured by the user through the error configuration register. The SPI interface can accept consecutive SPI commands without the need to deassert the CS line, which is called burst mode. Burst mode is enabled through the burst enable register (Address 0x05). This mode uses the same 16-bit command to communicate with the device. In addition, the response of the device at SDO is still aligned with the corresponding SPI command. Figure 41 shows an example of SDI and SDO during burst mode. An invalid read/write address error detects when a nonexistent register address is a target for a read or write. In addition, this error asserts when a write to a read only register is attempted. The invalid read/write address error flag asserts in the error flags register when an invalid read/write address error occurs. The invalid read/write address error is detected on the ninth SCLK rising edge, which means a write to the register does not occur when an invalid address is targeted. Invalid read/write address error detection is enabled by default and can be disabled by the user through the error configuration register. CLEARING THE ERROR FLAGS REGISTER To clear the error flags register, write the 16-bit SPI frame (not included in the register map), 0x6CA9, to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, the user must send the correct CRC byte for a successful error clear command. At the 16th or 24th SCLK rising edge, the error flags register resets to zero. CS SDI COMMAND0[15:0] COMMAND1[15:0] COMMAND2[15:0] COMMAND3[15:0] SDO RESPONSE0[15:0] RESPONSE1[15:0] RESPONSE2[15:0] RESPONSE3[15:0] 15902-039 Invalid Read/Write Address Error The invalid read/write address and CRC error checking functions operate similarly during burst mode as they do during address mode. However, SCLK count error detection operates in a slightly different manner. The total number of SCLK cycles within a given CS frame is counted, and if the total is not a multiple of 16, or a multiple of 24 when CRC is enabled, the SCLK count error flag asserts. Figure 41. Burst Mode Frame SOFTWARE RESET When in address mode, the user can initiate a software reset. To do so, write two consecutive SPI commands, namely 0xA3 followed by 0x05, to Register 0x0B. After a software reset, all register values are set to default. DAISY-CHAIN MODE The connection of several ADGS5414 devices in a daisy-chain configuration is possible, and Figure 42 shows this setup. All devices share the same CS and SCLK line, whereas the SDO of a device forms a connection to the SDI of the next device, creating a shift register. In daisy-chain mode, SDO is an eight cycle delayed version of SDI. When in daisy-chain mode, all commands target the switch data register (SW_DATA). Therefore, it is not possible to make configuration changes while in daisy-chain mode. Rev. 0 | Page 23 of 30 ADGS5414 Data Sheet ADGS5414 ADGS5414 DEVICE 1 DEVICE 2 S1 D1 S1 D1 S2 D2 S2 D2 S3 D3 S3 D3 S4 D4 S4 D4 S5 D5 S5 D5 S6 D6 S6 D6 S7 D7 S7 D7 S8 D8 S8 D8 VL SDO SPI INTERFACE SPI INTERFACE SDO SDI 15902-040 SCLK CS VL Figure 42. Two SPI Controlled Switches Connected in a Daisy-Chain Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 CS SDI SDO 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 15902-041 SCLK 0 Figure 43. SPI Command to Enter Daisy-Chain Mode SDI COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0] COMMAND0[7:0] DEVICE 1 SDO 8'h00 COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0] DEVICE 2 SDO2 8'h00 8'h00 COMMAND3[7:0] COMMAND2[7:0] DEVICE 3 8'h00 8'h00 8'h00 COMMAND3[7:0] DEVICE 4 SDO3 NOTES 1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY. 15902-042 CS Figure 44. Example of an SPI Frame when Four ADGS5414 Devices are Connected in Daisy-Chain Mode The ADGS5414 can only enter daisy-chain mode when in address mode by sending the 16-bit SPI command, 0x2500 (see Figure 43). When the ADGS5414 receives this command, the SDO of the device sends out the same command because the alignment bits at SDO are 0x25, which allows multiple daisy-connected devices to enter daisy-chain mode in a single SPI frame. A hardware reset is required to exit daisy-chain mode. For the timing diagram of a typical daisy-chain SPI frame, see Figure 44. For example, when CS goes high, Device 1 writes Command 0, SW_DATA, Bits[7:0] to its switch data register, Device 2 writes Command 1, SW_DATA, Bits[7:0] to its switches. The SPI block uses the last eight bits it receives through SDI to update the switches. After entering daisy-chain mode, the first eight bits sent out by SDO on each device in the chain are 0x00. When CS goes high, the internal shift register value does not reset back to zero. An SCLK rising edge reads in data on SDI while data is propagated out on SDO on an SCLK falling edge. The expected number of SCLK cycles must be a multiple of eight before CS goes high. If this is not the case, the SPI interface sends the last eight bits received to the switch data register. POWER-ON RESET The digital section of the ADGS5414 goes through an initialization phase during VL power-up. This initialization also occurs after a hardware or software reset. After VL power-up or a reset, ensure a minimum of 120 s from the time of power-up or reset before any SPI command is issued. Ensure VL does not drop out during the 120 s initialization phase because it can result in the incorrect operation of the ADGS5414. Rev. 0 | Page 24 of 30 Data Sheet ADGS5414 4 x SPST In junction isolation, the P-well and N-well of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. A silicon controlled rectifier (SCR) circuit is formed by the two transistors, causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latchup proof switch. SPI INTERFACE The Analog Devices, Inc., high voltage latch-up proof family of switches and multiplexers provides a robust olution for instrumentation, industrial, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The ADGS5414 high voltage switches allow single-supply operation from 9 V to 40 V and dual-supply operation from 9 V to 22 V. BREAK-BEFORE-MAKE SWITCHING The ADGS5414 exhibits break-before-make switching action, which allows the use of the device in multiplexer applications. A multiplexer function can be achieved by externally hardwiring the device in the required mux configuration, as shown in Figure 45. 4:1 MUX S1 S2 Dx S3 SCLK SDI CS RESET/VL 15902-043 S4 NMOS PMOS P-WELL N-WELL Figure 45. An SPI Controlled Switch Configured in a 4:1 Mux TRENCH ISOLATION In the analog switch section of the ADGS5414, an insulating oxide layer (trench) is placed between the N-type metal-oxide semiconductor (NMOS) and the P-type metal-oxide semiconductor (PMOS) transistors of each complementary metal-oxide semiconductor CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. TRENCH HANDLE WAFER Figure 46. Trench Isolation Rev. 0 | Page 25 of 30 15902-044 BURIED OXIDE LAYER ADGS5414 Data Sheet APPLICATIONS INFORMATION Figure 47 also shows two optional low dropout regulators (LDOs), ADP7118 and ADP7182, positive and negative LDOs respectively, that can reduce the output ripple of the ADP5070 in ultralow noise sensitive applications. To guarantee correct operation of the ADGS5414, 0.1 F decoupling capacitors are required. The ADGS5414 can operate with bipolar supplies between 9 V and 22 V. The supplies on VDD and VSS do not need to be symmetrical; however, the VDD to VSS range must not exceed 44 V. The ADGS5414 can also operate with single supplies between 9 V and 40 V with VSS connected to GND. The ADM7160 can be used to generate the VL voltage that is required to power the digital circuitry within the ADGS5414. ADM7160 LDO +16.5V The voltage range that can be supplied to VL is from 2.7 V to 5.5 V. +5V INPUT The device is fully specified at 15 V, 20 V, +12 V, and +36 V, analog supply voltage ranges. ADP7118 LDO ADP5070 -16.5V ADP7182 LDO +3.3V +15V -15V Figure 47. Bipolar Power Solution POWER SUPPLY RECOMMENDATIONS Table 10. Recommended Power Management Devices Analog Devices has a wide range of power management products that meet the requirements of most high performance signal chains. Product ADP5070 An example of a bipolar power solution is shown in Figure 47. The ADP5070 dual switching regulator generates a positive and negative supply rail for the ADGS5414, an amplifier, and/or a precision converter in a typical signal chain. 15902-045 POWER SUPPLY RAILS ADM7160 ADP7118 ADP7182 Rev. 0 | Page 26 of 30 Description 1 A/0.6 A, dc-to-dc switching regulator with independent positive and negative outputs 5.5 V, 200 mA, ultralow noise, linear regulator 20 V, 200 mA, low noise, CMOS LDO linear regulator -28 V, -200 mA, low noise, LDO linear regulator Data Sheet ADGS5414 REGISTER SUMMARY Table 11. Register Summary Reg. 0x01 0x02 0x03 0x05 0x0B Name Bit 7 Bit 6 SW_DATA SW8_EN SW7_EN ERR_CONFIG ERR_FLAGS BURST_EN SOFT_RESETB Bit 5 Bit 4 Bit 3 Bit 2 SW6_EN SW5_EN SW4_EN SW3_EN Reserved RW_ERR_EN Reserved RW_ERR_FLAG Reserved SOFT_RESETB Rev. 0 | Page 27 of 30 Bit 1 SW2_EN SCLK_ERR_EN SCLK_ERR_FLAG Bit 0 SW1_EN CRC_ERR_EN CRC_ERR_FLAG BURST_MODE_EN Default 0x00 0x06 0x00 0x00 0x00 RW R/W R/W R R/W R/W ADGS5414 Data Sheet REGISTER DETAILS SWITCH DATA REGISTER SW_DATA, Address 0x01, Reset: 0x00 The switch data register controls the status of the eight switches of the ADGS5414. Table 12. Bit Descriptions for SW_DATA Bit 7 Bit Name SW8_EN Setting 0 1 6 SW7_EN 0 1 5 SW6_EN 0 1 4 SW5_EN 0 1 3 SW4_EN 0 1 2 SW3_EN 0 1 1 SW2_EN 0 1 0 SW1_EN 0 1 Description Enable bit for Switch 8. Switch 8 open. Switch 8 closed. Enable bit for Switch 7. Switch 7 open. Switch 7 closed. Enable bit for Switch 6. Switch 6 open. Switch 6 closed. Enable bit for Switch 5. Switch 5 open. Switch 5 closed. Enable bit for Switch 4. Switch 4 open. Switch 4 closed. Enable bit for Switch 3. Switch 3 open. Switch 3 closed. Enable bit for Switch 2. Switch 2 open. Switch 2 closed. Enable bit for Switch 1. Switch 1 open. Switch 1 closed. Default 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Default 0x0 0x1 Access R R/W 0x1 R/W 0x0 R/W ERROR CONFIGURATION REGISTER ERR_CONFIG, Address 0x02, Reset: 0x06 The error configuration register allows the user to enable or disable the relevant error features as required. Table 13. Bit Descriptions for ERR_CONFIG Bit [7:3] 2 Bit Name Reserved RW_ERR_EN Setting 0 1 1 SCLK_ERR_EN 0 1 0 CRC_ERR_EN 0 1 Description These bits are reserved; set these bits to 0. Enable bit for detecting an invalid read/write address. Disabled. Enabled. Enable bit for detecting the correct number of SCLK cycles in an SPI frame. 16 SCLK cycles are expected when CRC is disabled and burst mode is disabled. 24 SCLK cycles are expected when CRC is enabled and burst mode is disabled. A multiple of 16 SCLK cycles is expected when CRC is disabled and burst mode is enabled. A multiple of 24 SCLK cycles is expected when CRC is enabled and burst mode is enabled. Disabled. Enabled. Enable bit for CRC error detection. SPI frames must be 24 bits wide when enabled. Disabled. Enabled. Rev. 0 | Page 28 of 30 Data Sheet ADGS5414 ERROR FLAGS REGISTER ERR_FLAGS, Address 0x03, Reset: 0x00, The error flags register allows the user to determine if an error occurs. To clear the error flags register, write the special 16-bit SPI command, 0x6CA9, to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, the user must include the correct CRC byte during the SPI write for the clear Error Flags Register command to be successful. Table 14. Bit Descriptions for ERR_FLAGS Bit [7:3] 2 Bit Name RESERVED RW_ERR_FLAG Setting 0 1 1 SCLK_ERR_FLAG 0 1 0 CRC_ERR_FLAG 0 1 Description These bits are reserved and are set to 0. Error flag for invalid read/write address. The error flag asserts during an SPI read if the target address does not exist. The error flag also asserts when the target address of a SPI write is does not exist or is read only. No Error. Error. Error flag for the detection of the correct number of SCLK cycles in an SPI frame. No Error. Error. Error Flag that determines if a CRC error occurs during a register write. No Error. Error. Default 0x0 0x0 Access R R 0x0 R 0x0 R BURST ENABLE REGISTER BURST_EN, Address 0x05, Reset: 0x00 The burst enable register allows the user to enable/disable the burst mode. When enabled, the user can send multiple consecutive SPI commands without deasserting CS. Table 15. Bit Descriptions for BURST_EN Bits [7:1] 0 Bit Name Reserved BURST_MODE_EN Settings 0 1 Description These bits are reserved; set these bits to 0. Burst mode enable bit. Disabled. Enabled. Default 0x0 0x0 Access R R/W SOFTWARE RESET REGISTER SOFT_RESETB, Address 0x0B, Reset: 0x00 This register performs a software reset. Consecutively, write 0xA3 and 0x05 to this register and to reset the device registers to their default state. Table 15. Bit Descriptions for SOFT_RESETB Bits [7:0] Bit Name SOFT_RESETB Settings Description To Perform a Software Reset, consecutively write 0xA3 followed by 0x05 to this register. Rev. 0 | Page 29 of 30 Default 0x0 Access R ADGS5414 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 4.10 4.00 SQ 3.90 1 0.50 BSC 2.70 2.60 SQ 2.50 EXPOSED PAD 13 TOP VIEW 1.00 0.95 0.90 0.50 0.40 0.30 6 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PKG-004677 SEATING PLANE PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 24 19 18 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8. 02-09-2017-A PIN 1 INDICATOR 0.30 0.25 0.18 Figure 48. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body and 0.95 mm Package Height (CP-24-17) Dimensions shown in millimeters ORDERING GUIDE Model1 ADGS5414BCPZ ADGS5414BCPZ-RL7 EVAL-ADGS5414SDZ 1 Temperature Range -40C to +125C -40C to +125C Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. (c)2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15902-0-10/17(0) Rev. 0 | Page 30 of 30 Package Option CP-24-17 CP-24-17