HYUNDAI ELECTRONICS em a SLE D MM 4675088 0001315 930 MBHYNK Baek (Aw: aU DESCRIPTION The HY6264 is a high speed, low power 8,192 words by 8-bit CMOS static RAM fabrica- ted using high performance CMOS process technology. This high reliability process coupled with innovative circuit design techniques, yields maximum access time of 70ns. The HY6264 has a data retention mode that guarantees data to remain valid at a mini- mum power supply voltage of 2.0 volt. Using CMOS technology, supply voltages from 2.0 to 5.5 volts have little effect on supply current in data retention mode. Reducing the supply voltage to minimize current drain is unnecessary with the HY6264 family. 8K 8-Bit CMOS: SRAM M221201B-MAY92 FEATURES Prag 23 ANZ * High speed 70/85/100/120/150ns (max.) * Low power consumption 200 mW typical operating 10 uW typical standby (L-version) * Battery back up (L-version) 2 volt data retention * Fully static operation No clock or refresh required * All inputs and outputs directly TTL compatible Tri-state output * High reliability 28-pin 600 mil P-DIP and 330 mil SOP HY6264-70 HY6264-85 HY6264-10 HY6264-12 HY6264-15 Maximum Access Time (ns) 70 85 100 120 150 Maximum Operating Current (mA) 70 70 70 70 70 2 2 2 2 2 Maximum Standby Current (mA) 0.1 0.1 0.1 0.1 0.1 BLOCK DIAGRAM ROW DECODER 256 X 256 MEMORY ARRAY COLUMN VO INPUT DATA CIRCUIT COLUMN DECODER CONTROL CIRCUIT m@ OVec +OGND PIN CONNECTIONS NcQ1 VY as D Yee Aig f] 2 27D We a3 26 cs 64 25 1 As As Cs 24 A] Ag Ne 10 WY eBkovcec 12 42 27 E> C82 46 23 [DA Ar 93 26 F= Aig AaQ7 22 DOE fe 4 25 F> Ag C45 I A208 2D AD Ase Boa, Ata 20S, Moo? 22 > OE Ag (fio 19 248 21 Aro o q Ovo, Mods 20 E> ty io C11 18g Aocdio 19 Fo voz vO; [12 17 DOs woe " 18 F> 06 vo. 13 +412 17 FP vo. 2 16 [1 0, VWO2 413 16 ES VO, Gno [14 1511 VOg GNDeS 14 15 F203 DIP SOP AoAy> | ADDRESS INPUT VOoi/O7 | DATA INPUT/QUTPUT CSy CHIP SELECT ONE C32 CHIP SELECT TWO WE WRITE ENABLE OE OUTPUT ENABLE Voc POWER GND | GROUNDHYUNDAT ELECTRONICS SLE D MM 4675084 0001116 477 MBHYNK HY6264 8,192 X8-Bit CMOS SRAM a T-46-2 3-12 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT Yop, Vins Vvo Power Supply, Input, Inpu/Output Voltage -0.52) to 7.0 Vv Taras Temperature Under Bias 10 to 125 C Tstc Storage Temperature 65 to 150 Os Pp Power Dissipation 1.0 Ww Tout Data Output Current 50 mA NOTES : 1, Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. 3.5V for 20ns pulse. RECOMMENDED DC OPERATING CONDITIONS (Ta=0C to 70C) SYMBOL PARAMETER - MIN. TYP. MAX, UNIT Vec Supply Voltage 45 5.0 5.5 v Vie Input High Voltage 2.2 3.5 6.0 Vv Vir Input Low Voltage 0.5 0 0.8 Vv TRUTH TABLE MODE WE cs CS OE | VO OPERATION | Vcc CURRENT NOTE Not Selected x H x x High-Z Isp, Isai (Power Down) x x L X High-Z Isp. Tse2 Output Disabled H L H H High-Z Tec, Teer Read H L H L Dout Tec, Ice1 Write L L H H Din lees Ieci Write Cycle 1 L_ L L H L Dw Ice, Iect Write Cycle 2 5-10HYUNDAI ELECTRONICS 54E D MM 467504848 0001117 703 MBHYNK HY6264 8,192 8-Bit CMOS SRAM a T~46-2 3-12 DC CHARACTERISTICS (Vec= 5V+ 10%, Ta=0C to 70C) : HY6264 SYMBOL PARAMETER TEST CONDITIONS UNIT MIN. | Typ? | MAX. Wy | Input Leakage Current Vin=GND to Vcc - - 2 pA CSi=Viw CS:=Vi_ or OE=Vin. _ _ lItol Output Leakage Current Vyo=GND to Vec 2 pA lec Operating Power Supply | ,=Vy, CS2=Vims Lyo=OmA - 30 50 mA : Min. D le= 100%, Teer Average Operating Current CS ee = Vin - 40 70 mA Isp CSi=Vin or CS2=Vit _- 1 3 mA lee Standby Power Supply CS81>Vec0.2V, - 20 2000 uA SBI Current CS82< 0.2V or > Vec0.2V uO 3 100 CS, <1 =- - Isp2 CS50.2V or >Vcc0.2V._ 20 2000 uA CS2<0.2V L - 2 100 VoL Output Low Voltage lol =2.1mA - - 0.4 Vv Vou Output High Voltage lon= 1.0mA 24 - - Vv NOTES : 1. Typical limits are at Voc =5.0V, Ta =25C and specified loading 2. Vi_ min=0.5V AC CHARACTERISTICS (Vec=5Vt 10%, Ta= 0C to 70C) READ CYCLE HY6264-70 | HY6264-85 | HY6264-10 | HY6264-12 | HY6264-15 SYMBOL) PARAMETER UNIT tre Read Cycle Time 70 - 85 - 100 - 120 _ 150 - ns taa Address Access Time - 70 - 85 - 100 - 120 - 150 | ns tacsi s,i| - | 7 | - | 88 |} | 100]; | 120] | 150 | os Chip Select Access Time tacs2 C82; - 70 - 85 - 100 - 120 - 150 | ns toe Output Enable to Output Valid - 45 - 50 - 55 - 6 - 70 ns tcizi cs,{/ 1 | - | 1 | - | 10 | - | 100 |) | 15 | | ms Chip Select to Output in Low-Z teLz2 CS,! 10 - 10 - 10 - 10 - 15 - ns toLz Output Enable to Output in Low-Z 5 - - 5 - 5 - - ns touz1 cs,| 0 30 35 35 40 0 50 | ns Chip Deselect to Output in High-Z tcHzz CS. 30 35 35 40 50 ns tonz Output Disable to Output in High-Z 30 35 35 40 50 ns tou Output Hold from Address Change 10 - 10 - 10 - 10 - 15 - ns 5-11BYYNDAL ELECTRONICS HY6264 8,1928-Bit CMOS SRAM SLE D MM 4675088 O0011286 BYT MBHYNK Eas WRITE CYCLE s P. TER HY6264-70 | HY6264-85 | HY6264-10 | HY6264-12 | HY626415 twe Write Cycle Time 70 - 85 - 100 - 120 - 150 - ns tcw Chip Select to End of Write 55 _ 60 _ 70 - 85 - 100 - ns tas Address Setup Time 0 - 0 - 0 - 6 _ 0 - ns taw Address Valid to End of Write 60 - 70 _ 80 - 85 > 100 - ns twp Write Pulse Width 50 - 55 - 60 - 70 - 90 - ns twri CS,.WE| 5 - 5 - 5 - 10 | ~ 10 | | ns Write Recovery Time twr2 CS2 5 - 10 - 10 - 1 - 15 - ns twHz Write to Output in High-Z 0 30 0 35 0 35 0 40 0 50 ns tow Data to Write Time Overlap 30 - 35 - 40 - 50 - 60 - ns tou Data Hold from Write Time 0 - - 0 - 0 - 0 - ns louz Output Enable to Output in High-Z 0 30 35 0 35 0 40 0 50 ns tow Output Active from End of Write 5 - - 5 - 5 - 0 | = ns AC TEST CONDITIONS OUTPUT LOAD (T,=0C to 70C) +5V Input Pulse Level 0.8V to 2.4V Input Rise and Fall Time Sns 1d Input and Output Timing Reference Level ISv Dour O67kO Ci. =100pF 1? NOTE : 1. Including scope and the jig CAPACITANCE (Ta=25C, f= 1.0MHz) | SYMBOL PARAMETER CONDITIONS MAX. UNIT Cin Input Capacitance Vin=0V 6 pF Input/Output = Cro | Capacitance Vio=0Vv 8 pF NOTE: 1, This parameter is sampled and not 100% tested. TIMING DIAGRAMS READ CYCLE 1? | RC Vi Ag Ata ve __ tea __. la | to, "OH Vou Dour Vo. VALID DATA OUT 5-12HYUNDAI ELECTRONICS SIE D MM 4675088 0001119 58b MBHYNK HY6264 8,192X8-Bit CMOS SRAM READ CYCLE 24 = VG 1 Vy K | @ $$ tag, @$toy2: ($) touzr' Vou Pour yg HIGH-Z VALID DATA OUT - (1,4.7) READ CYCLE 3 Vy Se vi a tacse ouz0t9) oy forza! Dour von = HIGHZ VALID DATA OUT }- READ CYCLE 4'b? Vin AgAi2 Vii oe ie YE mm VLA Se TLL red oe TTR NANI Kouzes tonza\9} > VoH our va HIGHZ VALID DATA OUT , NOTES : L. WE is high for read cycle. 2. Device is continuously selected C5y= VL and CS2=Vin 3. Addresses are valid prior to or coincident with CS; transition low. 4. OE=Vy. . Transition is measured + 500mV from steady state. This parameter is sampled and not 100% tested. 6. CS is high. 7, CS, is low. 5-13HYUNDAI ELECTRONICS SLE D MM 4675088 0001120 278 MMHYNK HY6264 8,192 8-Bit CMOS SRAM T-46-2 3-12 WRITE CYCLE 1 ome yh xX 3 3 ___+ <e twat (3) OE MLL EE A SAM, LT) , towa (11) tay = twre 03) tas ey A x vu J tonz (4,10) >} tw (2) Vor . Dour HIGH-2 Vou ed J tow + tot Ve On Vi HIGH-Z VALID DATA IN 5-14HYUNDAI ELECTRONICS S1E D @@ 4675088 OOOlIe1 134 MBHYNK HY6264 8,192 8-Bit CMOS SRAM a q-46-2 3-12 WRITE CYCLE 2 Vin AorAy2 Vb tows 1 twat (3) = {oS MMM ZILLI oS vw\ \ MEL Z ce MH UML QR fowe (11) taw ~~ <>_ twre 1) we (2) ey NAN Ff }<6- to} _ je tas twuz (4.10) tow (10) -> ta) e) Ss a 5 tow <+ ton > vin NOTES : 1. WE must be high during address transitions. 2. A write occurs during the overtap(tywp) of low CS;, high CS2 and low WE. 3. twr is measured from the earlier of CS, or WE going high or CS2 going tow to the end of write cycle. 4. During this period, [/O pins are in output state so that the input signals of opposite phase to the output must not be applied. S. If the CS] low transition or the CS) high transition occurs simultaneously with the WE low transition ar after the WE transition, outputs remain in a high impedance stale. 6. OF is continuously low(OE = V1). 7. Dour is the same phase of write data of this write cycle. 8. Dou rt is the read data of next address, 9. If CS; is low and CS; is high during this period, [/O pins are in the output state. Then the data input signals of opposite phase to the output must not be applied to them. LO. Transition is measured + 500mV from steady state. 14. tw is measured from the later of CS] going low or CS2 going high to the end of write.HYUNDAI ELECTRONICS SLE D MM@ 4675088 0001122 O70 MBHYNK HY6264 8,192 X8-Bit CMOS SRAM a 1-46-2 3-12 DATA RETENTION CHARACTERISTICS (T,=0C to 70C) SYMBOL PARAMETER TEST CONDITIONS MIN, | TYP. | MAX. | UNIT Vopr Data Retention Supply CS12Vcc0.2V, CS822>Vec0.2V or CS2<0.2V 2.0 - - Vv Vopr2 Voltage CS2<0.2V, CS1>Vec0.2V or C5; <0.2V 2.0 - - Vv Vec=3V, Vin= OV to Vcc tecprt CS1>Vec0.2V, CS22>Vec0.2V or CS2<0.2V | > sO; uA Data Retention Current = = = lecpra Vec=3V, Vin= OV to Vcc _ _ 3 50 uA CS82<0.2V, CS12Vec0.2V or CS;<0.2V Chip Deselect to *cDR Data Retention Time , . / ~ ~ tr Operation Recovery Time See Data Retention Timing Diagram tec - ~ ns NOTES : 1. These characteristics are guaranteed only for L-version 2.Ta= 25C 3. IRc=Read Cycle Time DATA RETENTION TIMING DIAGRAM 1 (CS, Controlled) DATA RETENTION MODE cs, 2Vcc -0.2V cs, GND = ---------+---~- ~~ ---- ee ee eee ee DATA RETENTION TIMING DIAGRAM 2 (CS, Controlled) DATA RETENTION MODE CS2 Vor ae enw ew ee ele fe eeeHYUNDAT ELECTRONICS S\E D MM 4675088 0001123 TO? MBHYNK HY6264 8,1928-Bit CMOS SRAM a T-46~2 3-12 ELECTRICAL CHARACTERISTIC CURVES (Vec=5V, Ta=25C, unless otherwise noted) SUPPLY CURRENT vs. SUPPLY CURRENT vs. SUPPLY VOLTAGE AMBIENT TEMPERATURE 16 16 14 14 3 3 H a] oi ; 12 2 2 8 10 8 10 g - 3 3 2 Os 2 08 a a a a 06 06 o4 04 45 475 50 5.25 55 0 20 40 60 0 Supply Voltage Voc(V) Ambient Temperature Ta(C) ACCESS TIME vs. ACCESS TIME vs. 13 SUPPLY VOLTAGE AMBIENT TEMPERATURE . 1.3 1.2 ~ 12 3 i 3 WwW ae 5 5 5 . 14 fas 10 s 10 $ FE 09 1 og i 08 os a7 OF 425 4.75 50 5.25 55 o zs oD so 50 Supply Voltage Vootv) Ambient Temperature Tal C) INPUT LOW VOLTAGE vs. INPUT HIGH VOLTAGE vs. SUPPLY VOLTAGE SUPPLY VOLTAGE 13 13 12 (12 g g 5 1 5 1 = z > = g 1.0 a 3 1 $ anaes 2 a og 2 09 08 os or 425 475 50 5.25 55 o7 45 475 5 5,25 55 Supply Voltage Voc (V) Supply Voltage Voc (V) 5-17HYUNDAI ELECTRONICS HY6264 8,192 8-Bit CMOS SRAM SLE D MM 4675088 oo01124 943 MBHYNK OUTPUT CURRENT vs. OUTPUT VOLTAGE 16 \ 14 \ 1A Output High Current lop (Normalized) 3 : 06 0.4 1 2 3 4 5 Output High Voltage Voy(V) STANDBY CURRENT vs. AMBIENT TEMPERATURE &S, =48v 10! a a Standby Current fgg1 (A) ZO 1071 - 1] 20 40 60 BO Ambient Temperature Ta(C) 5-18 Output Low Current Igy (Normalized) Standby Current Igg1 (Normalized) T-46-2 3-12 OUTPUT CURRENT vs. OUTPUT VOLTAGE Y A L 08 06 04 L L 02 04 06 08 Output Low Voltage Vo. (V) STANDBY CURRENT vs. SUPPLY VOLTAGE CS1=Vec -0.2v | / 08 / 06 4 04 =a 02 2 3 4 5 6 Supply Voltage Voc(V)HYHNDAI ELECTRONICS SLE D MM 4675088 0001125 S&T MHYNK HY6264 8,1928-Bit CMOS SRAM a 7-40-72 3- 12 PACKAGE INFORMATION * 28 PIN PLASTIC DUAL IN LINE PACKAGE-600MIL NOOO DOO : ; UNIT | INCH(mm) wet \ t | | a a 1.467( 37.262) 1.447(36.754) 0.600BSC (15.240) |__0.580(13.970)_, _ 0,.830( 13.462) 33 - Oo <i! i 38 as 22 8 Ut Ss (0388) ~a]|. 3~ 11 _ Ot 200) 0.140(3.556) 0.120(3.048) ae e 0,090( 2.286) 0.062( 1.575) 0.021 (0.583) 0.100 BSC 0.070(1.778) 0.050(1.270) 0.015(0.381) (2.540) * 28 PIN SMALL OUTLINE PACKAGE 330MIL LLURERERAREE] . - MAX UNIT : INCH(mm) MIN" | | 23 33 Pp ba | as 38 FUP R EO REA EEE! | nose asc poaoiosoe s8 ene | gs 1 ee a Ai } 4a eeRe she + 0.7280( 18.4912) 8 010600(1 2700) 0.7200{ 18.2880) 29 0.0300(0.7620) 88 38 5-19