LINEAR TECHNOLOG
Y
LINEAR TECHNOLOG
Y
LINEAR TECHNOLOG
Y
FEBRUARY 1998 VOLUME VIII NUMBER 1
, LTC and LT are registered trademarks of Linear Technology Corporation. Adaptive Power, Burst Mode, C-Load,
FilterCAD, Linear View, Micropower SwitcherCAD, Operational Filter and SwitcherCAD are trademarks of Linear
Technology Corporation. Other product names may be trademarks of the companies that manufacture the products.
U
niversal Continuous-Time
Filter Challenges
Discrete Designs by Max Hauser
The LTC1562 is the first in a new
family of tunable, DC-accurate, con-
tinuous-time filter products featuring
very low noise and distortion. It con-
tains four independent 2nd order,
3-terminal filter blocks that are resis-
tor programmable for lowpass or
bandpass filtering functions up to
150kHz, and has a complete PC board
footprint smaller than a dime. More-
over, the part can deliver arbitrary
continuous-time pole-zero responses,
including highpass, notch and ellip-
tic, if one or more programming
resistors are replaced with capaci-
tors. The center frequency (f
0
) of the
LTC1562 is internally trimmed, with
an absolute accuracy of 0.5%, and
can be adjusted independently in each
2nd order section from 10kHz to
150kHz by an external resistor. Other
features include:
❏ Rail-to-rail inputs and outputs
❏ Wideband signal-to-noise ratio
(SNR) of 103dB
❏ Total harmonic distortion (THD)
of –96dB at 20kHz, –80dB at
100kHz
❏ Built-in multiple-input summing
and gain features; capable of
118dB dynamic range
❏ Single- or dual-supply operation,
4.75V to 10.5V total
❏ “Zero-power” shutdown mode
under logic control
❏ No clocks, PLLs, DSP or tuning
cycles required
The LTC1562, in the SSOP package,
provides eight poles of programmable
continuous-time filtering in a total
surface mount board area (including
the programming resistors) of 0.24
square inches (155 mm
2
)—smaller
than a U.S. 10-cent coin. This filter
can also replace op amp–R-C active
filter circuits and LC filters in appli-
cations requiring compactness,
flexibility, high dynamic range or fewer
precision components.
What’s Inside?
As shown in Figure 1, the LTC1562
includes four identical 3-terminal
blocks. Each contains active circuitry,
precision capacitors and precision
resistors, forming a flexible 2nd order
filter core. These blocks are designed
to make filters as easy to configure as
op amps. The 3-terminal arrange-
ment minimizes the number of
external parts necessary for a com-
plete 2nd order filter with arbitrarily
programmable f
0
, Q and gain. Figure
2 shows the contents of one block,
along with three external resistors,
forming a complete lowpass/band-
pass filter (the most basic application
of the LTC1562). In Figure 2, a low-
pass response appears between the
V
IN
source and the LP output pin, and
simultaneously a bandpass response
is available at the BP output pin. Both
outputs have rail-to-rail capability
for the maximum possible signal
swing, and hence, maximum signal-
to-noise ratio (SNR).
continued on page 3
IN THIS ISSUE…
COVER ARTICLE
Universal Continuous-Time Filter
Challenges Discrete Designs .......... 1
Max Hauser
Issue Highlights ............................ 2
LTC
®
in the News ........................... 2
DESIGN FEATURES
An SMBus-Controlled 10-Bit, Current
Output, 50
µ
A, Full-Scale DAC........ 6
Ricky Chow
Micropower 600kHz Fixed-Frequency
DC/DC Converters Step Up from a
1-Cell or 2-Cell Battery .................. 8
Steve Pietkiewicz
New 333ksps, 16-Bit ADC Offers 90dB
SINAD and –100dB THD .............. 11
Marco Pan
Ultralow Power 14-Bit ADC Samples
at 200ksps .................................. 14
Dave Thomas
A 10MB/s Multiple-Protocol Chip Set
Supports Net1 and Net2 Standards
................................................... 17
David Soo
DESIGN IDEAS
High Clock-to-Center Frequency Ratio
LTC1068-200 Extends Capabilities of
Switched Capacitor Highpass Filter
................................................... 23
Frank Cox
LT1533 Ultralow Noise Switching
Regulator for High Voltage or
High Current Applications .......... 24
Jim Williams
A Complete Battery Backup Solution
Using a Rechargeable NiCd Cell .. 26
L.Y. Lin and S.H. Lim
Zero-Bias Detector Yields High
Sensitivity with Nanopower
Consumption ............................... 28
Mitchell Lee
DESIGN INFORMATION
Micropower Octal 10-Bit DAC
Conserves Board Space with SO-8
Footprint ..................................... 29
Kevin R. Hoskins
Tiny MSOP Dual Switch Driver is
SMBus Controlled ........................ 31
Peter Guan
New Device Cameos ..................... 34
Design Tools ................................ 35
Sales Offices ............................... 36
Linear Technology Magazine • February 1998
2
EDITOR’S PAGE
LTC in the News…
LTC Reports
Another Strong Quarter
“Demand for our products remained
strong and well diversified across
end markets,” said Robert Swanson,
president and CEO of Linear Tech-
nology Corporation. “We had another
strong quarter, achieving record lev-
els for sales and profits. The turmoil
in the Asian financial markets did
not have a material impact on our
business in this quarter, although
we continue to closely monitor this
geographical area for its impact in
the future.”
Douglas Lee, an analyst at
NationsBanc Montgomery Securities
in San Francisco, predicts that Lin-
ear Technology will “see a sequential
sales growth of about 7% for the
March quarter.” This was reported
in the January 19, 1998 issue of
Electronic Buyers’ News.
Net sales for the second quarter
ended December 28, 1997 were
$117,004,000, an increase of 30%
over net sales of $90,080,000 for the
second quarter of the previous year.
The Company also reported
net income for the quarter of
$43,582,000, an increase of 38%
over the $31,631,000 reported for
the second quarter of last year.
Diluted earnings per share (EPS)
were $0.55 compared to $0.40 for
the similar quarter last year. This is
the first quarter that earnings per
share (EPS) are reported in com-
pliance with the new Financial
Accounting Standards Board pro-
nouncement No. 128. Diluted EPS is
analogous to the methodology the
Company used in the past in report-
ing EPS.
During the quarter, Linear Tech-
nology purchased 1,002,500 shares
of its stock for $56.4 million, $5.9
million of which was paid after quar-
ter end. A cash dividend of $0.40 will
be paid on February 11, 1998 to
shareholders of record on January
23, 1998
Issue Highlights
Our cover article for this issue intro-
duces a new filter product, the
LTC1562. The LTC1562 is the first in
a new family of tunable, DC-accurate,
continuous-time filter products fea-
turing very low noise and distortion. It
contains four independent 2nd order,
3-terminal filter blocks that are resis-
tor programmable for lowpass or
bandpass filtering functions up to
150kHz, and has a complete PC board
footprint smaller than a dime.
Data converters are strongly repre-
sented in this issue, with a new DAC
and several new ADCs:
The LTC1427-50 is a 10-bit, cur-
rent-source-output DAC with an
SMBus interface. This device provides
precision, full-scale current of 50µA
±1.5% at room temperature (±3% over
temperature), wide output voltage DC
compliance (from –15V to [V
CC
– 1.3V])
and guaranteed monotonicity over a
wide supply-voltage range. It is an
ideal part for applications in con-
trast/brightness control or voltage
adjustment in feedback loops.
We also introduce the LTC1604, a
fast, high performance 16-bit sam-
pling ADC in a tiny 36-pin SSOP
package. This device runs at 333ksps
and delivers excellent DC and AC
performance. It operates on ±5V sup-
plies and typically draws only 220mW.
It is a complete differential, high speed,
low power, 16-bit sampling ADC that
requires no external components. The
LTC1604 also provides two power-
shutdown modes, NAP and SLEEP, to
reduce power consumption during
inactive periods. It not only offers the
performance of the best hybrids but
also provides low power, small size,
an easy-to-use interface and the low
cost of a monolithic part.
A new, versatile 14-bit ADC, the
LTC1418, can digitize at 200ksps
while consuming only 15mW from a
single 5V supply. The LTC1418 is
designed to be easy to use and adapt-
able, requiring little or no support
circuitry in a wide variety of applica-
tions. It features 0.25LSB INL max
and 1LSB DNL max, parallel and se-
rial data output modes and NAP and
SLEEP power-shutdown modes.
In the power conversion arena, we
debut two new micropower DC/DC
converters designed to provide power
from a single-cell or higher input volt-
age, the LT1308 and the LT1317. The
LT1308 is intended for generating
power on the order of 2W–5W, for RF
power amplifiers in GSM or DECT
terminals or for digital-camera power
supplies. The LT1317, intended for
lower power requirements, operates
from an input voltage as low as 1.5V.
It can generate 100mW to 2W of power.
Both devices feature Burst Mode™
operation for high efficiency at light
loads. Both devices switch at 600kHz;
this high frequency keeps associated
power components small and flat.
On the interface front, we present
a new multiprotocol chip set that is
guaranteed to be Net1 and Net2 com-
pliant. The LTC1543/LTC1544/
LTC1344A chip set creates a com-
plete software-selectable serial
interface using an inexpensive DB-
25 connector. The LTC1543 is a
dedicated data/clock chip and the
LTC1544 is a control-signal chip. The
chip set supports the V.28 (RS232),
V.35, V.36, RS449, EIA-530, EIA-530A
and X.21 protocols in either DTE or
DCE mode.
In the Design Ideas section, we
feature a 1kHz, 8th order Butter-
worth highpass filter, power gain
stages to extend the output-power
capability of the LT1533 ultralow noise
switching regulator, a nanopower
zero-bias detector and a complete bat-
tery backup solution based on a single
NiCd cell and the LT1558 battery-
backup controller.
We conclude with Design Informa-
tion on the LTC1660 10-bit octal DAC
and the LTC1632 SMBus switch con-
troller and a pair of New Device
Cameos.
Linear Technology Magazine • February 1998
3
DESIGN FEATURES
The LTC1562 is versatile; it is not
limited to the lowpass/bandpass fil-
ter of Figure 2. Cascading multiple
sections, of course, yields higher-
order filters (Figure 3a). A highpass
response results if the external input
resistor (R
IN
of Figure 2) is replaced by
a capacitor, C
IN
, which sets only gain,
not critical frequencies (Figure 3b).
Responses with arbitrary zeroes (for
example, elliptic or notch responses)
are implemented with feedforward
connections with multiple 2nd order
blocks, as shown in the application
circuit in Figure 8. Moreover, the vir-
tual-ground INV input gives each
2nd-order section the built-in capa-
bility for analog operations such as
gain (preamplification), summing and
weighting of multiple inputs, or
accepting current or charge signals
directly. These flexible 3-terminal
elements are Operational Filter™
blocks.
Although the LTC1562 is offered in
a 20-pin SSOP package, the LTC1562
is a 16-pin circuit; the extra pins are
connected to the die substrate and
should be returned to the negative
power supply. In single-supply appli-
cations, these extra V– pins should be
connected directly to a PC board’s
ground plane for the best grounding
and shielding of the filter. 16-pin plas-
tic DIP packaging is also available
(consult the factory).
DC Performance
and Power Shutdown
The LTC1562 operates from single or
dual supply voltages, nominally 5V to
10V total. It generates an internal
half-supply reference point (the AGND
pin), establishing a reference voltage
for the inputs and outputs in
single-supply applications. In these
applications, the AGND pin should be
bypassed with a capacitor to the
ground plane (at V
–
); the pin can be
connected directly to ground when a
split supply is used. The DC offset
voltage from the filter input to the LP
output for a typical 2nd order section
(unity DC gain) is typically 5mV. Both
outputs swing to within approximately
100mV of each supply rail with loads
of 5kΩ and 30pF.
To save power in a “sleep” situa-
tion, a logic high input on the SHDN
pin will put the LTC1562 into its
shutdown mode, in which the chip’s
power supply current is reduced to
only junction leakage (typically 2µA
from a single 5V supply). The shut-
down pin is designed to accept CMOS
levels with 5V swing, for example, 0V
and 5V logic levels when the LTC1562
is powered from either a single 5V or
a split ±5V supply. Note that in the
LTC1562, unlike some other prod-
ucts, a small bias current source
(approximately 2µA) at the SHDN pin
causes the chip to default to the shut-
down state if this pin is left open.
Therefore, the user must remember
to connect the SHDN pin to a logic low
for normal operation if the shutdown
feature is not used. (This default-to-
shutdown convention saves system
power in the shutdown state, since it
eliminates even the microampere cur-
rent that would otherwise flow from
the driving logic to the bias-current
source.)
V
+
V
–
SHDN
1562 F02
2ND ORDER SECTIONS
A
INV BP LP
B
DC
INV BP LP
INV BP LP INV BP LP
SHUTDOWN
SWITCH
SHUTDOWN
SWITCH AGND
V
+
V
–
–
+
+
–
R2 RQ
RIN
VIN
LP INV BP
1562 F01
C
1
sR1C*
*R1 AND C ARE PRECISION
INTERNAL COMPONENTS
INV BP LP
2ND ORDER
INV BP LP
2ND ORDER
VIN
VOUT
INV BP LP
2ND ORDER
V
OUT
C
IN
V
IN
Figure 1. LTC1562 block diagram
Figure 2. Single 2nd order section, illustrating connection
with external resistors R2, R
IN
and R
Q
Figure 3a. Two 2nd order sections cascaded for higher order response
Figure 3b. 2nd order section configured for
highpass output
LTC1562, continued from page 1
Linear Technology Magazine • February 1998
4
DESIGN FEATURES
Frequency Responses
Lowpass filters with standard all-pole
responses (Butterworth, Chebyshev,
Bessel, Gaussian and so on) of up to
8th order (eight poles) can be realized
with LTC1562 sections connected as
in Figures 2 and 3a; practical
examples appear later in this article.
Resistor ratios program the standard
filter parameters f
0
, Q and gain;
required values of these filter param-
eters can be found from tables or from
software such as FilterCAD™ for Win-
dows
®
, available free from LTC.
The “LP” and “BP” outputs of each
2nd order section, although named
after their functions in Figure 2, can
display other responses than lowpass
and bandpass, respectively, if the
external components are not all
resistors. The highpass configuration
of Figure 3b has a passband gain set
by the ratio C
IN
/C, where C is an
internal 160pF capacitor in the
LTC1562. The two resistors in Figure
3b control f
0
and Q, as in the other
modes.
The LTC1562 is the first
truly compact universal
active filter, yet it offers
instrumentation-grade
performance rivaling much
larger discrete-component
designs.
Bandpass applications can use the
LTC1562 in either of two ways. In the
basic configuration, with the only
external components being resistors
(Figure 2), the BP output has a band-
pass response from V
IN
. With an input
capacitor, as in Figure 3b, the BP
output has a highpass response as
noted above and the LP pin shows a
bandpass response.
The f
0
range is approximately
10kHz–150kHz, limited mainly by the
magnitudes of the external resistors
required. At high f
0
these resistors fall
below 5k, heavily loading the outputs
of the LTC1562 and leading to in-
creased THD and other effects. A lower
f
0
limit of 10kHz reflects an arbitrary
resistor magnitude limit of 1 Megohm.
The LTC1562’s MOS input circuitry
can accommodate higher resistor val-
ues than this, but junction leakage
current from the input-protection cir-
cuitry may cause DC errors.
Design formulas and further details
on frequency-response programming
appear in the LTC1562 data sheet.
Low Noise and Distortion
The active (that is, amplifier) circuitry
in the LTC1562 was designed ex-
pressly for filtering. Because of this,
filter noise is due primarily to the
circuit resistors rather than to the
amplifiers. The amplifiers also exhibit
exceptional linearity, even at high
frequencies (patents pending). The
noise and distortion performance for
filters built with the LTC1562 com-
pares favorably with filters using
expensive, high performance, off-the-
shelf op amps that demand many
more external parts and far more
board area (we know, because we’ve
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV B
BP B
LP B
V+
SHDN
LP A
BP A
INV A
INV C
BP C
LP C
V–
AGND
LP D
BP D
INV D
LTC1562
RIN2, 10k
RIN4, 10k
RIN1
10k
VIN2
VIN1
VOUT1
1562 TA01
VOUT2
RIN3
10k
–5V
5V
RQ1, 5.62k
R21, 10k
R23, 10k
0.1µF0.1µF
RQ3, 5.62k
R24, 10k
RQ4, 13k
RQ2, 13k
R22, 10k
FREQUENCY (Hz)
10k
GAIN (dB)
10
0
–10
–20
–30
–40
–50
–60
–70
–80 100k 1M
1562 TA02
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV B
BP B
LP B
V
+
SHDN
LP A
BP A
INV A
INV C
BP C
LP C
V
–
AGND
LP D
BP D
INV D
LTC1562
C
IN1
150pF
C
IN
TO C
IN3
1562 TA08
V
OUT
–5V
5V
FROM
HP C
R
Q1
, 10.2k
R21, 35.7k
R23, 107k
0.1µF0.1µF
R
Q3
, 54.9k
R24, 127k
R
Q4
, 98.9k
R
Q2
, 22.1k
R22, 66.5k
C
IN3
150pF C
IN4
150pF
C
IN2
150pF
FREQUENCY (Hz)
1k
GAIN (dB)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 10k 100k 1M
1562 TA09
Figure 4. Dual, matched 4th order 100kHz Butterworth lowpass filter Figure 5. Frequency response of Figure 4’s
circuit
Figure 6. 8th order Chebyshev highpass filter with 0.05dB ripple (f
CUTOFF
= 30kHz) Figure 7. Frequency response of Figure 6’s
circuit
Linear Technology Magazine • February 1998
5
DESIGN FEATURES
built them). The details of this perfor-
mance depend on Q and other
parameters and are reported for spe-
cific application examples below. As
with other low distortion circuits,
accurately measuring distortion per-
formance requires both an input
signal and distortion-analyzing equip-
ment with adequately low distortion
floors.
Low level signals can exploit a low
noise preamplification feature in the
LTC1562. A 2nd order section oper-
ated with unity gain, Q = 1 and f
0
=
100kHz shows a typical output noise
of 24µV
RMS
, which gives a 103dB SNR
with full-scale output from a 10V
total supply. However, reducing the
value of R
IN
in Figure 2 increases the
gain without a proportional increase
in the output noise (unlike many active
filters). A gain of 100 (40dB) with the
same Q and f
0
gives a measured output
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV B
BP B
LP B
V
+
SHDN
LP A
BP A
INV A
INV C
BP C
LP C
V
–
AGND
LP D
BP D
INV D
LTC1562
R
FF1
,
10k
R
IN2
,
8.06k
R
IN4
,
7.32k
R
FF2
,
17.8k
R
IN1,
19.6k
C
IN1,
87pF
V
IN
ALL RESISTORS = 1% METAL FILM
V
OUT
1562 TA03
R
IN3
, 69.8k
–5V
5V
R
Q1
, 13k
R21, 8.87k
R23, 8.87k
0.1µF
R
Q3
, 28k
R24, 17.8k
R
Q4
, 6.98k
R
Q2
, 8.87k
R22, 12.1k
C
IN3,
47pF
0.1µF
FREQUENCY (Hz)
1k
GAIN (dB)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90 10k 100k 1M
1562 TA04
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV B
BP B
LP B
V
+
SHDN
LP A
BP A
INV A
INV C
BP C
LP C
V
–
AGND
LP D
BP D
INV D
LTC1562
R
IN1B
3.83k
R
IN1A
6.19k
R
IN3A
6.19k
V
IN1
V
IN3
C
IN1
680pF
V
IN2
1562 TA07
V
OUT2
V
OUT3
V
OUT4
V
OUT1
R
IN3B
3.83k
–5V
5V
R
Q1
, 10k
R21, 10k
R23, 10k
0.1µF0.1µF
R
Q3
, 10k
R24, 10k
R
Q4
, 10k
R
Q2
, 10k
R22, 10k
C
IN2
680pF
C
IN3
680PF
ALL RESISTORS = 1% METAL FILM
R
IN2B
3.83k R
IN2A
6.19k
V
IN4
C
IN4
680pF
R
IN4B
3.83k R
IN4A
6.19k
Figure 8. 8th order 100kHz elliptic lowpass filter
Figure 9. Frequency response of Figure 8’s
circuit.
Figure 10. Quad 3-pole 100kHz Butterworth lowpass filter
noise of 449µV
RMS
or an input-re-
ferred noise of 4.5µV
RMS
—a 78dB
output SNR with an input that is
40dB down. Thus, the same circuit
can handle a wide range of input
levels with high SNR by changing (or
switching) the input resistor. In the
example just cited, the ratio of maxi-
mum input signal to minimum input
noise, by changing R
IN
, is 118dB.
Dual 4th Order 100kHz
Butterworth Lowpass Filter
The practical circuit in Figure 4 is a
dual lowpass filter with a Butter-
worth (maximally-flat-passband)
frequency response. Each half gives a
DC-accurate, unity-passband-gain
lowpass response with rail-to-rail
input and output. With a 10V total
power supply, the measured output
noise for one filter is 36µV
RMS
in a
200kHz bandwidth, and the large-
signal output SNR is 100dB. Mea-
sured THD at 1V
RMS
input is –83.5dB
at 50kHz and –80dB at 100kHz. Fig-
ure 5 shows the frequency response
of one filter.
8th Order 30kHz
Chebyshev Highpass Filter
Figure 6 shows a straightforward use
of the highpass configuration in Fig-
ure 3b with some practical values.
Each of the four cascaded 2nd order
sections has an external capacitor in
the input path, as in Figure 3b. The
resistors in Figure 6 set the f
0
and Q
values of the four sections to realize a
Chebyshev (equiripple-passband)
response with 0.05dB ripple and a
30kHz highpass corner. Figure 7
shows the frequency response. Total
output noise for this circuit is
40µV
RMS
.
8th Order 100kHz
Elliptic Lowpass Filter
Figure 8 illustrates how sharp-cutoff
filtering can exploit the Operational
Filter capabilities of the LTC1562. In
this design, two external capacitors
are added and the virtual-ground
inputs of the LTC1562 sum parallel
paths to obtain two notches in the
stopband of a lowpass filter, as plot-
ted in Figure 9. This response falls
80dB in one octave; the total output
noise is 46µV
RMS
and the Signal/
continued on page 32
Linear Technology Magazine • February 1998
6
DESIGN FEATURES
The LTC1427-50 is a 10-bit, cur-
rent-output DAC with an SMBus
interface. This device provides preci-
sion, full-scale current of 50µA ±1.5%
at room temperature (±2.5% over tem-
perature), wide output voltage DC
compliance (from –15V to (V
CC
– 1.3V))
and guaranteed monotonicity over a
wide supply-voltage range. It is an
ideal part for applications in con-
trast/brightness control or voltage
adjustment in feedback loops.
Description
The LTC1427-50 communicates with
external circuitry using the standard
2-wire I
2
C or SMBus interface. The
operating sequence (Figure 1) shows
the signals on the SMBus. The two
bus lines, SDA and SCL, must be high
when the bus is not in use. External
pull-up resistors are required on these
lines. The LTC1427-50 is a receive-
only (slave) device; the system master
must apply the Write Byte protocol
(Figure 1) to communicate with the
LTC1427-50.
The master places the LTC1427-
50 in a START condition and transmits
a 7-bit address. The write bit is then
made 0. The LTC1427-50 acknowl-
edges and the master transmits the
command byte. The LTC1427 again
acknowledges and latches the active
bits of the command byte into register
A (see the block diagram in Figure 2)
at the falling edge of the acknowledge
pulse. The master then sends the
data byte; the LTC1427-50 acknowl-
edges receipt of the data byte; and,
finally, the 8-bit data byte and the
last two output bits (the two MSBs of
the 10-bit input data) from register A
are latched into the register C at the
falling edge of the final acknowledge
and the DAC current output assumes
the new 10-bit value. A stop condition
is optional.
The LTC1427-50 can respond to
one of four 7-bit addresses. The first
five bits have been factory pro-
An SMBus-Controlled 10-Bit, Current
Output, 50µA Full-Scale DAC by Ricky Chow
grammed and are always 01011. The
last two LSB address bits are pro-
grammed by the user via AD1 and
AD0 (Table 1). When AD1 and AD0
are both connected to V
CC
, upon power
up, the 10-bit internal register C is
reset to 1000000000B and the DAC
output is set to midrange. If either
AD1 or AD0 is connected to ground,
at power-up, register C resets to
0000000000B and the DAC output is
set to zero. For the LTC1427-50, the
source current output (I
OUT
) can be
biased from –15V to (V
CC
– 1.3V);
precision full-scale current is trimmed
to ±1.5% at room temperature and
±2.5% over the commercial tempera-
ture range.
There are two ways to shut down
the LTC1427 (see Figure 2). A logic
low at the SHDN pin or a logic high at
bit 7 of the command byte sent
through the SMBus interface will put
the LTC1427 into shutdown mode. In
shutdown mode, the digital data is
retained internally and the supply
current drops to only 12µA typically.
XXXXX11110SDA
SCL
I
OUT
1
123456789101112131415161718192021222324252627 FULL-SCALE
CURRENT
S = START
P = STOP
*OPTIONAL
SMBus WRITE BYTE PROTOCOL, WITH SMBus ADDRESS = 0101111B,
COMMAND BYTE = 0XXXXX11B AND DATA BYTE = 11111111B, AD1 = 0, AD0 =1
ZERO-SCALE
CURRENT
P
0 111111
WR
ACK
SHDN
ACK
ACK
1111
S
SMBus ADDRESS COMMAND BYTE DATA BYTE
1427_01.EPS
R
ADJ
I
OUT
SCL
SDA
AD0 AD1
10
SHDN
SHDN
VOLTAGE
REFERENCE
REGISTER B
1-BIT LATCH
EN2 SD
EN2
REGISTER C
10-BIT
LATCH
SMBus
INTERFACE 3-BIT
LATCH
REGISTER A
EN1
POWER-ON
RESET
1
3
2
8
10-BIT
CURRENT DAC
SD
1427_02.EPS
SD
Figure 1. LTC1427-50 operating sequence
Figure 2. LTC1427-50 block diagram
1DA0DAnoitacoLsserddAsuBMSeulaVpU-rewoPCADnoitacilppA
LL 1011010elacs-oreZlortnoCthgilkcaBDCL
LH 1111010elacs-oreZesopruPlareneG
HL 0111010elacs-oreZesopruPlareneG
HH 0011010elacs-diMlortnoCtsartnoCDCL
Table 1. LTC1427-50 function table
Linear Technology Magazine • February 1998
7
DESIGN FEATURES
Digitally Controlled
LCD Bias Generator
Figure 3 is a schematic of a digitally
controlled LCD bias generator using
a standard SMBus 2-wire interface.
The LT1317 is configured as a boost
converter, with the output voltage
(V
OUT
) determined by the values of the
feedback resistors, R1 and R2. The
LTC1427-50’s DAC current output is
connected to the feedback node of the
SHDN
AD1
AD0
GND
V
CC
I
OUT
SCL
SDA
1
2
3
4
8
7
6
5
µP
(e.g., 8051)
P1.2
P1.1
P1.0
LTC1427-50
SHDN
SHDN
V
IN
SW
FB
GND V
C
LT1317
L1 D1
100k
4700pF
R2
12.1k
1%
R1
226k
1%
C1
1µF
1µF
2–4
CELLS
V
CC
= 3.3V
V
OUT
*
V
OUT
= 12.7V–24V IN 11mV STEPS
15mA FROM 2 CELLS
35mA FROM 3 CELLS
*
L1 = 10µH (SUMIDA CD43
MURATA-ERIE LQH3C
OR COILCRAFT DO1608)
D1 = MBR0530
65
2
14
3
++
+
LAMP
C2
27pF
3kV
R2
220k
R3
100k Q2* Q1*
C1*
0.1µF
L2
100µH
C3A
2.2µF
35V
C3B
2.2µF
35V
V
BAT
8V–28V
C5
1000pF
10 6
3214 5
L1
D1
1N5818
R1
750Ω
D5
BAT85
C7
1µF
C4
2.2µF
V
IN
3.3V
1
12
3
4
5
7
8
9
16
15
14
13
11
10
6
2
5
6
4
8
1
7
2
3
CCFL
PGND
V
IN
DIO
CCFL V
C
AGND
NC
NC
NC
CCFL
V
SW
BULB
BAT
ROYER
REF
NC
SHDN
I
CCFL
LT1184F
V
CC
3.3V
SHDN
I
OUT
AD1
AD0
SDA
SCL
GND
V
CC
AN ALUMINUM ELECTROLYTIC WITH
AN ESR ≥0.5Ω IS RECOMMENDED
FOR C3B TO PREVENT DAMAGE TO
THE LT1184F HIGH-SIDE SENSE
RESISTOR DUE TO SURGE
CURRENTS AT TURN-ON.
C1 MUST BE A LOW LOSS
CAPACITOR (WIMA MKP-20)
Q1, Q2 = ZETEX ZTX849 OR ROHM
2SC5001
L1 = COILTRONICS CTX210605
L2 = COILTRONICS CTX100-4
COILCTRONICS (561) 241-7876
*DO NOT SUBSTITUTE COMPONENTS
0µA–50µA I
CCFL
CURRENT GIVES
0mA–6mA LAMP CURRENT FOR A
TYPICAL DISPLAY
SHDN
LTC1427-50
SMBus TO HOST
}
C6 0.1µF
Digitally Controlled
CCFL Current Using
the SMBus Interface
Figure 4 is a schematic of a 90%
efficient, digitally controlled floating
CCFL lamp supply using the SMBus
serial interface. The DAC current out-
put is connected to the I
CCFL
pin of
LT1184F. With the DAC output cur-
rent range of 0µA to 50µA, this circuit
gives 0mA to 6mA lamp current for a
typical display. Varying the lamp cur-
rent from its minimum to maximum
level adjusts the lamp intensity, and
hence, the display brightness.
Conclusion
The LTC1427-50 is a precision 10-bit,
50µA full-scale DAC that communi-
cates directly with an I
2
C or SMBus
interface. It operates from a wide sup-
ply range, consumes low power, has
guaranteed monotonicity and is pack-
aged in a popular SO-8. It is ideal for
applications such as contrast/
brightness controls, output voltage
adjustment in power supplies and
other potentiometer applications.
LT1317. The LTC1427-50’s DAC cur-
rent output increases or decreases
according to the data sent via the
SMBus. As the DAC output current
varies from 0µA to 50µA, the output
voltage is controlled over the range of
12.7V to 24V. A 1LSB change in the
DAC output current corresponds to
an 11mV change in the output voltage.
Figure 3. Digitally controlled LCD bias generator
Figure 4. 90% efficient digitally controlled floating CCFL supply using the SMBus serial interface
Linear Technology Magazine • February 1998
8
DESIGN FEATURES
Micropower 600kHz Fixed-Frequency
DC/DC Converters Step Up from
a 1-Cell or 2-Cell Battery by Steve Pietkiewicz
Linear Technology introduces two
new micropower DC/DC converters
designed to provide power from a
single-cell or higher input voltage.
The LT1308 features an onboard
switch capable of handling 2A with a
voltage drop of 300mV and operates
from an input voltage as low as 1V.
The LT1317, intended for lower power
requirements, operates from an input
voltage as low as 1.5V. Its internal
switch handles 600mA with a drop of
360mV. Both devices feature Burst
Mode operation at light load; efficien-
cies are above 70% for load currents
of 1mA. Both devices switch at
600kHz; this high frequency keeps
associated power components small
and flat; additionally, troublesome
interference problems in the sensi-
tive 455kHz IF band are avoided. The
LT1308 is intended for generating
power on the order of 2W–5W. This is
sufficient for RF power amplifiers in
GSM or DECT terminals or for digital-
camera power supplies. The LT1317,
with its smaller switch, can generate
100mW to 2W of power. The LT1317
is available in LTC’s smallest 8-lead
package, the MSOP. This package is
approximately one-half the size of a
standard 8-lead SO package. The
LT1308 is available in the 8-lead SO
package.
Single Li-Ion Cell to 5V/1A
DC/DC Converter for GSM
GSM terminals have emerged as a
worldwide standard. A common
requirement for these products is an
efficient, compact, step-up converter
to develop 5V from a single Li-Ion cell
to power the RF amplifier. The LT1308
performs this function with a mini-
mum of external components. The
circuit is detailed in Figure 1. Many
designs use a large aluminum elec-
trolytic capacitor (1000µF to 3300µF)
at the DC/DC converter output to
hold up the output voltage during the
transmit time slice, since the ampli-
fier can require more than 1A. The
V
IN
SW
FB
LT1308
L1
4.7µH
3V TO 4.2V
D1
LBO
LBI
R
C
47k
R2
100k
5V
1A
R1
301k
C
C
22nF
1308_01,eps
C1
100µF
C2
100µF
Li-Ion
CELL
V
C
GND
SHDN
AVX TPS SERIES
INTERNATIONAL RECTIFIER 10BQ015
COILTRONICS CTX5-1
COILCRAFT DO3316-472
++
2200µF
C1,C2:
D1:
L1:
LOAD CURRENT (mA)
1
EFFICIENCY (%)
95
90
85
80
75
70
65 10 100 1000
1308 F01a
V
IN
= 4.2V
V
IN
= 3.6V
V
IN
= 3V
V
IN
SW
FB
LT1308
L1
4.7µH
D1
LBO
LBI
R
C
47k
R2
100k
3.3V
400mA
R1
169k
C
C
22nF
1308_04.eps
C1
10µF
C2
100µF
NiCD
CELL
V
C
GND
SHDN
C1: CERAMIC
C2: AVX TPS SERIES
D1:IR 10BQ015
L1: COILTRONICS CTX5-1
COILCRAFT DO3316-472
+
LOAD CURRENT (mA)
90
85
80
75
70
65
60
55
50 1 100 1000
1308 G01
10
EFFICIENCY (%)
V
IN
= 1.2V
V
OUT
= 3.3V
R1
= 169k
Figure 2. Efficiency of Figure 1’s
circuit reaches 90%
Figure 3. Transient response of
DC/DC converter: V
IN
= 3V, 0A–1A
load step
Figure 5. Efficiency of Figure 4’s
circuit reaches 81%
VOUT
200mV/DIV
AC COUPLED
INDUCTOR
CURRENT
1A/DIV
1ms/DIV
Figure 1. Single Li-Ion cell to 5V/1A DC/DC converter Figure 4. Single NiCd cell to 3.3V/400mA DC/DC converter
Linear Technology Magazine • February 1998
9
DESIGN FEATURES
output capacitor, along with the
LT1308 compensation network,
serves to smooth out the input cur-
rent demanded from the Li-Ion cell.
Efficiency, which reaches 90%, is
shown in Figure 2. Transient response
of a 0A to 1A load step with typical
GSM profiling (1:8 duty cycle, 577µs
pulse duration) is depicted in Figure
3. Voltage droop (top trace) is 200mV.
Inductor current (bottom trace)
increases to 1.7A peak; the input
capacitor supplies some of this cur-
rent, with the remainder drawn from
the Li-Ion cell.
Single NiCd Cell to 3.3V/
400mA Supply for DECT
Only minor changes are required in
Figure 1’s circuit to construct a single-
cell NiCd to 3.3V converter. The large
output capacitor is no longer required
as the output current can be handled
directly by the LT1308. Figure 4 shows
the DECT DC/DC converter circuit.
Efficiency, reaching 81% from a 1.2V
input, is pictured in Figure 5. Tran-
sient response of a typical DECT load
of 50mA to 400mA is detailed in Figure
6. Output voltage droop (top trace) is
under 200mV. Figure 7 zooms in on a
single pulse to show the output volt-
age and inductor current responses
more clearly.
2-Cell Digital Camera
Supply Produces
3.3V, 5V, 18V and –10V
Power supplies for digital cameras
must be small and efficient while
generating several voltages. The DSP
and logic need 3.3V, the ADC and
LCD display need 5V and biasing for
the CCD element requires 18V and
–10V. The power supplies must also
be free of low frequency noise, so that
postfiltering can be done easily. The
obvious approach, to use a separate
DC/DC converter IC for each output
voltage, is not cost-effective. A single
V
IN
SW
FB
LT1308
L1A
N = 1
10µH
L1C
N = 0.3
R4
47k R1
100k
5V
200mA
3.3V
200mA
CCD BIAS
–10V
10mA
CCD BIAS
18V
10mA
V
IN
1.6V
TO 6V
R3
340k
R2
2.01M
D1
C7
22nF
C8
1nF
1308_08.eps
C6
10µF
V
C
GND
SHDN
C1, C2, C3 = AVX TPS
C4, C5 = AVX TAJ
C6 = CERAMIC
18 23
L1B
N = 0.7
3
4
C2
100µF
C1
100µF
+
D2
D3
D4
+
C3
100µF
+
C4
10µF
+
C5
10µF
+
L1D
N = 3.5
7
6
L1E
N = 2
6
5
D1, D2 = IR 10BQ015
D3, D4 = BAT-85
L1 = COILTRONICS CTX02-13973
INPUT VOLTAGE (V)
1
EFFICIENCY (%)
70
80
85
75
65
55
5
1308_09.EPS
60
50 21.5 2.5 3.5 4.5
34
90
100mA LOADS
150mA
LOADS 200mA LOADS
LT1308, along with an inexpensive
transformer, generates 3.3V/200mA,
5V/200mA, 18V/10mA and –10V/
10mA from a pair of AA or AAA cells.
Figure 8 shows the circuit. A coupled-
flyback scheme is used, actually an
extension of the SEPIC (single ended
primary inductance converter) topol-
ogy. The addition of capacitor C6
clamps the SW pin, eliminating a
snubber network. Both the 3.3V and
5V outputs are fed back to the LT1308
FB pin, a technique known as split
feedback. This compromise results in
better overall line and load regula-
tion. The 5V output has more influence
than the 3.3V output, as can be seen
from the relative values of R2 and R3.
Transformer T1 is available from
Coiltronics, Inc. (561-241-7876).
Efficiency vs input voltage for several
load currents on both 3.3V and 5V
outputs is pictured in Figure 9. The
CCD bias voltages are loaded with
10mA in all cases.
V
OUT
200mV/DIV
AC COUPLED
400mA
I
LOAD
50mA
I
L1
1A/DIV
100µs/DIV
V
OUT
200mV/DIV
AC COUPLED
400mA
I
LOAD
20ms/DIV
50mA
Figure 6. DECT load transient response: with a single
NiCd cell, the LT1308 provides 3.3V with a 400mA
pulsed load. The pulse width = 416µs.
Figure 7. DECT load transient response: faster sweep speed
(100µs/DIV) details V
OUT
and inductor current of a single
DECT transmit pulse.
Figure 8. This digital camera power supply delivers 5V/200mA, 3.3V/200mA, 18V/
10mA and –10V/10mA from two AA cells. Figure 9. Camera power supply efficiency
reaches 78%.
Linear Technology Magazine • February 1998
10
DESIGN FEATURES
V
IN
SW
FB
LT1317
L1
22µH
D1
LBO
LBI
R
C
100k
R2
324k
1%
5V
200mA
R1
1M
C
C
680pF
1308_10.eps
C1
10µF
10V
C2
33µF
2 CELLS
V
C
GND
SHDN
C1: CERAMIC
D1:MOTOROLA MBRO520L
L1: 22 µH SUMIDA CD43-220
+
SHUTDOWN
R3
47k
C6
680pF
L1
22µH
L2
22µH
C2
33µF
C1
10µF
C5
1µF
C4
1µF
C3
15µF
D2A D2B
D1
–V
OUT
–4V/10mA
+V
OUT
4V/70mA
V
IN
2.5V–5V
SHUTDOWN
R1 1M
R2
442k
V
IN
SW
V
C
GND
LB0
SHDN
FB
LB1
LT1317
L1, L2 =MURATA LQH3C220
C1 =MURATA GRM235Y5V106Z01
D1 =MBR0520
D2 =BAT54S (DUAL DIODE)
C2 =AVX TAJB33M6010
C3 =AVX TAJA156MO1O
C4, C5 =CERAMIC
+
+
LT1317 2-Cell to 5V
DC/DC Converter
Figure 10 shows a simple 2-cell to 5V
DC/DC converter using the LT1317.
This device generates a clean, low
ripple output from an input voltage as
low as 1.5V. Designed for 2-cell appli-
cations, it offers better performance
than its 1-cell predecessor, the
LT1307. More gain in the error ampli-
fier results in lower Burst Mode ripple,
and an internal preregulator elimi-
nates oscillator variation with input
voltage. For comparison, Figure 11
details transient responses of both
the LT1307 and the LT1317 generat-
ing 5V from a 3V input. The load step
is 5mA to 200mA. Output capacitance
in both cases is 33µF. The LT1307 has
VOUT
LT1307
100mV/DIV
5V OFFSET
VOUT
LT1317
100mV/DIV
5V OFFSET
500µs/DIV
I
LOAD
200mA
5mA
low frequency ripple of 100mV,
whereas the LT1317 Burst Mode ripple
of 20mV is the same as the 600kHz
ripple resulting from the output
capacitor’s ESR with a 200mA load.
Single Li-Ion Cell
to ±4V DC/DC Converter
By again employing the SEPIC topol-
ogy, a ±4V supply can be designed
with one IC. Figure 12’s circuit gener-
ates 4V at 70mA and –4V at 10mA
from an input voltage ranging from
2.5V to over 5V. Maximum compo-
nent height is 2mm. This converter
uses two separate inductors (L1 and
L2), so it is an uncoupled SEPIC con-
verter. This reduces the overall cost,
but requires that all output current
pass through C1. Since C1 is ceramic,
its ESR is low and there is no appre-
ciable efficiency loss. C5 is charged to
–V
OUT
when the switch is off, then its
bottom plate is grounded when the
switch turns on. The negative output
is fairly well regulated, since the di-
ode drops tend to cancel. The circuit
is switching continuously at rated
load, where efficiency is 75%. Output
ripple is under 40mV and can be
reduced further with conventional
postfiltering techniques.
Conclusion
The LT1308 and LT1317 provide low
noise compact solutions for contem-
porary portable-product power
supplies.
Figure 10. 2-cell to 5V boost converter using the LT1317
Figure 12. This single Li-Ion cell to ±4V DC/DC converter has a maximum height of 2mm.
Figure 11. The LT1317 has reduced Burst Mode
ripple compared to the LT1307.
Linear Technology Magazine • February 1998
11
DESIGN FEATURES
New 333ksps, 16-Bit ADC Offers
90dB SINAD and –100dB THD
The fastest, highest performance
16-bit sampling ADC is now available
in a tiny 36-pin SSOP package from
Linear Technology. It is the LTC1604.
This device runs at 333ksps and
delivers excellent DC and AC perfor-
mance. The LTC1604 operates on ±5V
supplies and typically draws only
220mW. It is a complete differential,
high speed, low power, 16-bit sam-
pling ADC that requires no external
components. The LTC1604 also pro-
vides two power shutdown modes,
NAP and SLEEP, to reduce power
consumption during inactive periods.
This 333ksps, 16-bit device not only
offers the performance of the best
hybrids but also provides low power,
small size, an easy-to-use interface
and the low cost of a monolithic part.
Some of the key features of this new
device include:
❏333ksps throughput
❏16 bits with no missing codes
and ±2LSB INL
❏Low power dissipation and power
shutdown
❏Excellent AC and DC performance
❏Small package—36-pin SSOP
These features of the LTC1604 can
simplify, improve, and lower the cost
of current data acquisition systems
and open up new applications that
were not previously possible because
no similar part was available.
Fast Architecture
To achieve 333ksps with outstanding
AC and DC performance at the 16-bit
level, careful design is required. Fig-
ure 1, the LTC1604 block diagram,
illustrates the design of this part. A
high performance differential sample-
and-hold circuit, combined with an
extremely fast successive-approxima-
tion ADC and an on-chip reference,
delivers an excellent combination of
AC and DC performance. A digital
interface allows easy connection to
microprocessors, FIFOs or DSPs.
Outstanding AC
and DC Performance
The DC specifications include 16 bits
with no missing codes and ±2LSB
integral nonlinearity error guaran-
teed over temperature. The gain of the
ADC is held nearly constant over tem-
perature with an on-chip 10ppm/°C
(typical) curvature-corrected bandgap
reference. Figures 2 and 3 show INL
and DNL error plots, respectively, for
the LTC1604.
The sample-and-hold circuit
determines the dynamic performance
of the ADC. The LTC1604 has a wide
bandwidth, very low distortion, dif-
ferential sample-and-hold. Fast
Fourier transform (FFT) test tech-
niques are used to test the LTC1604’s
frequency response, distortion and
noise at the rated throughput. By
applying a low distortion sine wave
and analyzing the digital output using
an FFT algorithm, the ADC’s spectral
by Marco Pan
SAMPLE/
HOLD
CIRCUIT
PRECISION
16-BIT DAC
LTC1604
SAR
+A
IN
–A
IN
V
REF
(2.50V)
REFCOMP
(4.375V)
OUTPUT
BUFFER
16 16
LOW DRIFT
VOLTAGE
REFERENCE
CLOCK CONTROL LOGIC BUSY
COMPARATOR
RD CS
7.5k
CONVST
SHDN
CODE
INL (LSB)
–32768 –16384 0 16384 32767
1604_02. eps
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
CODE
–32768 –16384 16384 32767
DNL (LSB)
1604_03. eps
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
Figure 2. The LTC1604 is very accurate, as
shown in the INL error plot. This accuracy is
achieved without autocalibration and its
associated overhead. Accuracy relies on
capacitor matching, which is very stable over
temperature and time.
Figure 1. LTC1604 block diagram
Figure 3. The differential nonlinearity error
plot shows the excellent performance of the
LTC1604.
Linear Technology Magazine • February 1998
12
DESIGN FEATURES
content can be examined for frequen-
cies other than the fundamental.
Figures 4 and 5 show the excellent AC
performance of the LTC1604 at
333ksps with f
IN
= 5kHz and 100kHz,
respectively. The AC performance of
the LTC1604 include total harmonic
distortion of –100dB for a 5kHz input
and –94dB for a 100kHz input and an
input bandwidth of 15MHz for the
sample-and-hold.
Very Low Noise
The noise of an ADC can be evaluated
in two ways: by signal-to-noise ratio
(SNR) in the frequency domain and by
histogram in the time domain. The
LTC1604 excels in both. Figure 4
demonstrates that the LTC1604 has
a SNR of over 90dB in the frequency
domain. The noise in the time-domain
histogram is the transition noise as-
sociated with a high resolution ADC,
which can be measured with a fixed
DC signal applied to the input of the
ADC. The resulting output codes are
collected over a large number of con-
versions. The shape of the distribution
of codes will give an indication of the
magnitude of the transition noise. In
Figure 6, the distribution of output
codes is shown for a DC input that
has been digitized 4096 times. The
distribution is Gaussian and the RMS
code transition noise is about
0.66LSB. This corresponds to a noise
level of 90.9dB relative to full scale.
When added to the theoretical 98dB
of quantization error for a 16-bit ADC,
this yields an SNR of 90.1dB, which
correlates very well with the frequency
domain measurements.
Differential Inputs Ignore
Common Mode Noise
Getting a clean signal to the input(s)
of an ADC, especially a 16-bit ADC, is
not an easy task in many systems.
Large noise signals from EMI, the AC
power line and digital circuitry are
usually present. Filtering and shield-
ing are the common techniques for
reducing noise, but these are not
always adequate (see “The Care and
Feeding of High Performance ADCs:
Getting All the Bits You Paid For”;
Linear Technology VI:3 [August,
1996]). The LTC1604 offers another
tool to fight noise: differential inputs.
Figure 7a depicts a typical single-
ended sampling system with ground
noise, which may be 60Hz noise, digi-
tal clock noise or some other type of
noise. When a single-ended input is
used, the ground noise adds directly
to the input signal. By using the dif-
ferential inputs of the LTC1604 the
ground noise can be rejected by con-
necting the inputs directly across the
signal of interest, as shown in Figure
7b. Ground noise becomes “common
mode” and is rejected internally by
the LTC1604 by virtue of its excellent
common mode rejection ratio (CMRR).
Figure 8 shows the CMRR of the
LTC1604 versus frequency. Notice
that the CMRR is constant over the
entire Nyquist bandwidth and is only
6dB lower at 300kHz. This ability to
reject high frequency common mode
signals is very helpful in sampling
systems, where noise often has high
frequency components due to switch-
ing transients.
FREQUENCY (kHz)
0
AMPLITUDE (dB)
–60
–40
–20
60
1604_04.EPS
–80
–100
20 40 80 100 120 140 160
–120
–140
0
f
SAMPLE
= 333kHz
f
IN
= 4.959kHz
SINAD = 90.2dB
THD = –103.2dB
FREQUENCY (kHz)
AMPLITUDE (dB)
–60
–40
–20
1604_05.EPS
–80
–100
–120
–140
0
f
IN
= 97.152kHz
SINAD = 89.0dB
THD = –96dB
f
SAMPLE
= 333kHz
06020 40 80 100 120 140 160
1604_06.eps
CODE
COUNT
2500
2000
1500
1000
500
0
–5 –4 –3 –2 –1 012345
SIGNAL TO BE
MEASURED
GROUND
NOISE
SINGLE-INPUT
ADC
AGND
AIN
SIGNAL TO BE
MEASURED
GROUND
NOISE
LTC1604
AGND
–A
IN
+A
IN
0
20
40
10
30
60
50
1604_08.eps
10000 10 100
INPUT FREQUENCY (kHz)
COMMON MODE REJECTION (dB)
70
Figure 4. This FFT of the LTC1604’s
conversion of a full-scale 5kHz sine wave
shows outstanding response with a very low
noise floor when sampling at 333ksps.
Figure 5. Even with inputs at 100kHz, the
LTC1604’s dynamic linearity remains
robust.
Figure 6. This histogram shows that the
LTC1604 has an RMS code transition noise of
0.66dB.
Figure 7a. Single-input ADC measuring
a signal riding on common mode noise. Figure 7b. Differential-input ADC measuring a
signal riding on common mode noise. Figure 8. LTC1604 CMRR vs frequency
Linear Technology Magazine • February 1998
13
DESIGN FEATURES
3V Input/Output Compatible
The LTC1604 operates on ±5V sup-
plies, which makes the device easy to
interface to 5V digital systems. This
device can also talk to 3V digital sys-
tems: the digital input pins (SHDN,
CS, CONVST and RD) of the LTC1604
recognize 3V or 5V inputs. The
LTC1604 has a dedicated output sup-
ply pin (OV
DD
) that controls the output
swings of the digital output pins (D0–
D15, BUSY) and allows the part to
talk to either 3V or 5V digital systems.
Low Power Dissipation
and Shutdown
The LTC1604 runs at full speed on
±5V supplies and typically draws only
220mW. This power consumption can
be reduced further by using the two
power shutdown modes, NAP and
SLEEP, during inactive periods. NAP
mode cuts down the power to 8mW,
leaving the reference and logic pow-
ered up. The ADC wakes up “instantly”
(400ns) from NAP mode, so NAP mode
can be invoked even during brief
inactive periods with no penalty or
delay when conversions must start
again.
SLEEP mode is used when there
are extended inactive periods. In
SLEEP mode, the ADC powers down
all the circuitry, leaving the logic out-
puts in a high impedance state. The
only current that remains is junc-
tion-leakage current (less than 1µA).
It takes much longer for the ADC to
wake up from SLEEP mode because
the reference circuit must power up
and settle to 0.0006% for full accu-
racy. The wake-up time also depends
on the value of the compensation
capacitor used on the REF COMP pin.
With the recommended 47µF capaci-
tor, the wake-up time is 160ms.
Applications
The performance of the LTC1604
makes it very attractive to use in a
wide variety of applications, such as
digital signal processing, PC data
acquisition cards, medical instru-
mentation and high resolution or
multiplexed data acquisition.
DSP applications often require
excellent dynamic performance, since
the ADC must sample high frequency
AC signals. The LTC1604 is the right
choice in these types of applications
because of the performance of its
sample-and-hold. Figure 9 shows how
well the signal-to-noise plus distor-
tion ratio and the spurious free
FREQUENCY (kHz)
1000
1604_09.eps
0 10 100
EFFECTIVE BITS
16
15
14
13
12
11
10
9
8
98
92
86
80
74
68
62
56
50
SINAD (dB)
dynamic range of the converter hold
up as the input frequency is increased.
Another common application is PC
data acquisition cards. The high
sample rate, the simple, complete
configuration and excellent linearity
of the LTC1604 make it an ideal choice
here. Another advantage that the
LTC1604 provides is the synchro-
nized internal conversion clock, which
is very useful in this application. This
feature eliminates the second exter-
nal clock required by other sampling
ADCs to run conversion, in addition
to the normal sample signal. Clearly,
this feature makes the LTC1604 an
outstanding choice for PC data acqui-
sition cards.
For single-channel or multiplexed
high speed data acquisition systems,
the LTC1604 has the high sample
rate and high impedance inputs that
help smooth the design of these appli-
cations. High sample rates allow more
channels in the data acquisition sys-
tem on a very low power and cost
budget and the high impedance in-
puts of the ADC make them very easy
to multiplex.
Conclusion
The new LTC1604 is a complete 16-bit
ADC with a built-in sample-and-hold
and reference. It samples at 333ksps
and is the fastest device of its kind on
the market. The excellent DC and AC
performance of the LTC1604 not only
make it extremely valuable in a wide
variety of existing high resolution ap-
plications while also opening up new
applications.
Figure 9. The LTC1604 has essentially flat
SINAD and effective bits out to Nyquist.
for
the latest information
on LTC products,
visit
www.linear-tech.com
Linear Technology Magazine • February 1998
14
DESIGN FEATURES
Ultralow Power 14-Bit ADC
Samples at 200ksps by Dave Thomas
Introduction
A new, versatile 14-bit ADC, the
LTC1418, can digitize at 200ksps
while consuming only 15mW from a
single 5V supply. The LTC1418 is
designed to be easy to use and adapt-
able, requiring little or no support
circuitry in a wide variety of applica-
tions. Some of the key features of this
new device include:
❏200ksps throughput
❏Low power—15mW
❏Single 5V or ±5V supplies
❏1.25LSB INL max and 1LSB DNL
max
❏Parallel and serial data output
modes
❏NAP and SLEEP power shutdown
modes
❏Small package—28-pin SSOP
High Performance
without High Power
Figure 1 shows a block diagram of the
LTC1418. This device includes a high
performance differential sample-and-
hold circuit, an ultra-efficient
successive approximation ADC, an
on-chip reference and a digital inter-
face that allows easy serial or parallel
interface to a microprocessor, FIFO
or DSP. The LTC1418 is factory cali-
brated, so a lengthy calibration cycle
is not required to achieve 14-bit per-
formance. DC specifications include
a 1LSB max differential linearity error
(no missing codes) and 1.25LSB max
integral linearity error guaranteed
over temperature. The gain of the
ADC is controlled by an on-chip
10ppm/°C reference that can be eas-
ily overdriven with an external
reference if required.
For AC applications, the dynamic
performance of the LTC1418 is
exceptional. The extremely low dis-
tortion differential sample-and-hold
acquires input signals at frequencies
up to 10MHz. At the Nyquist fre-
quency, 100kHz, the spurious free
dynamic range is typically 95dB. The
noise is also low with a signal-to-
noise ratio (SNR) of 82dB from DC to
well beyond Nyquist.
The superior AC and DC perfor-
mance of the LTC1418 doesn’t require
a lot of power. In fact, the LTC1418
has the lowest power of any 14-bit
ADC available, just 15mW at 200kHz
(10mW at sample rates below 50kHz).
Two shutdown modes make it pos-
sible to cut power further at lower
sample rates.
High Impedance Inputs
The LTC1418’s high impedance in-
puts allow direct connection of high
impedance sources without introduc-
ing errors. Many ADCs have a resistive
input or input bias current that re-
quires low source impedance to
achieve low errors. Other ADCs with
switched capacitor inputs exhibit large
offset shifts when driven with high
source impedance or a large source-
impedance imbalance between their
differential inputs. The unique
sample-and-hold circuit of the
LTC1418 has a low capacitance, high
resistance (10MΩ||25pF) switched-
capacitor input that has only 2LSB of
offset shift with a source impedance
imbalance between 0Ω and 1M (see
Figure 2a). (There is no shift if the
input impedance is equal for +A
IN
and
S/H 14
BUFFER
8k
10µF
10µF
REFCOMP
A
IN
–
A
IN
+
V
REF
4.096V
5V
LTC1418
14-BIT ADC SELECTABLE
SERIAL/
PARALLEL
PORT
D13
D
GND
1418 TA01
V
SS
(0V OR –5V)
A
GND
SER/PAR
D5
D4 (EXTCLKIN)
D3 (SCLK)
D2 (CLKOUT)
D1 (D
OUT
)
V
DD
D0 (EXT/INT)
TIMING AND
LOGIC
2.5V
REFERENCE
BUSY
CS
RD
CONVST
SHDN
1µF
SOURCE IMPEDANCE MISMATCH (OHMS)
100
CHANGE IN OFFSET VOLTAGE (LSB)
1M
1418_02a.EPS
2
4
5
8
10
01k 10k 100k
SOURCE RESISTANCE (OHMS)
1k
MAXIMUM SAMPLE RATE (SAMPLES/SEC)
1M
1418_02b.EPS
10k
100k
200k
1k 10k 100k
Figure 1. LTC1418 block diagram
Figure 2a. Change in offset voltage with
source impedance mismatch
Figure 2b. Maximum sample rate vs
unbuffered source resistance
Linear Technology Magazine • February 1998
15
DESIGN FEATURES
–A
IN
.) Connecting the ADC directly to
a high impedance source avoids addi-
tional noise and offset errors that
may be introduced by buffering cir-
cuitry. The only downside to directly
connecting the ADC to a high source
impedance is that the acquisition time
will increase. The low input capaci-
tance (20pF) of the LTC1418 allows
full-speed operation with resistances
up to 2k. Above 2k the sample rate
must be lowered (see Figure 2b).
Differential Inputs
with Wideband CMRR
The differential input of the LTC1418
has excellent common mode rejec-
tion, eliminating the need for some
input-conditioning circuitry. Op amps
and instrumentation amplifiers are
often used to reject common mode
noise from EMI, AC power and switch-
ing noise. Although these circuits
perform well at low frequencies, their
rejection at high frequencies deterio-
rates substantially. Figure 3 shows
the CMRR of the LTC1418 vs
frequency.
Single-Supply or
Dual-Supply Operation
Single-supply ADCs can be cumber-
some to work with in a dual-supply
system. A signal with a common mode
of zero volts has to be shifted up to the
common mode of the ADC. Shifting
the common mode can be accom-
plished with AC coupling, but DC
information is lost. Alternatively, an
op amp level shifter can be used, but
this adds circuit complexity and
additional errors. The LTC1418 can
operate with single or dual supplies
and allows direct coupling to the
inputs in both cases. The ADC is
equipped with circuitry that auto-
matically detects when –5V is present
at the V
SS
pin. With a –5V supply, the
ADC operates in bipolar mode and the
full-scale range becomes ±2.048V for
+A
IN
with respect to –A
IN
. With a single
supply, V
SS
= 0V and the ADC oper-
ates in unipolar mode with an input
range of 0V to 4.096V.
On-Chip Reference
The on-chip reference of the LTC1418
is a standard 2.5V and is compatible
with many system references; it is
available on the REF output (pin 3).
An internal amplifier boosts the 2.5V
reference up to 4.096V; this sets the
span for the ADC. The 4.096V output
is available on the REFCOMP output
(pin4) and may be used as a reference
for other external circuitry. With a
temperature coefficient of 10ppm/°C,
both REF and REFCOMP are suited to
serve as the master reference for the
system. However, if an external refer-
ence circuit is required, its easy to
overdrive either reference output. The
2.5V reference output is resistive (4k)
and can be easily overdriven by any
reference with low output impedance
by directly connecting the external
reference to the REF pin. If REFCOMP
(the 4.096V reference) is to be
overdriven, tie the REF pin to ground.
This disables the output drive of the
REFCOMP amplifier, allowing it to be
easily overdriven.
Parallel Data Output
for High Speed
The parallel output mode of the
LTC1418 allows the lowest digital over-
head. A microcontroller can strobe the
ADC to start the conversion and per-
form other tasks while the conversion
is running. The ADC will then signal
the microcontroller after the conver-
sion is complete with the BUSY signal,
at which time valid data is available on
the parallel output bus. BUSY may
also be used to clock latches or a FIFO
directly, since data is guaranteed to be
valid with the rising edge of BUSY.
Serial Data Output
for Minimal Wiring
The serial output mode of the LTC1418
is simple, requiring just three pins for
data transfer: a data-out pin, a serial
clock pin and a control pin. However,
its simplicity doesn’t sacrifice flexibil-
ity. Serial data can be clocked with
the internal shift clock for minimal
hardware or an external shift clock
for synchronization. Additionally, data
can be clocked out during the conver-
sion for the highest throughput rate
or after the conversion for maximum
noise immunity.
Perfect for Telecom:
Wide Dynamic Range
Telecommunications systems require
wide dynamic range. With its low
noise and low distortion, the LTC1418
offers extremely wide dynamic range
over its entire Nyquist bandwidth.
Spurious free dynamic range is typi-
cally 95dB and only starts to drop off
at input frequencies above Nyquist.
The ultralow jitter of the sample-and-
hold circuit, 5ps
RMS
, keeps the SNR
flat from DC to 1MHz, making this
device useful for undersampling
applications.
Another important requirement for
telecom systems is a low error rate. In
any ADC, there is a finite probability
that a large conversion error (greater
than 1% of full scale) will occur. In
video or flash converters, these large
errors are called “sparkle codes.” Large
errors are a problem in telecom sys-
tems such as ISDN, because they
result in errors in data transmission.
All ADCs have a rate at which errors
occur, referred to as the error rate.
The error rate is dependent on the
ADC architecture, design and pro-
cess. Error rates vary greatly and can
be as low as 1 in 10 billion to as high
as 1 is 1 million. Telecom systems
typically require error rates to be 1 in
1 billion or better.
The LTC1418 is designed to have
ultralow error rates. The error rate is
so low that it is difficult to measure
because of the time in between errors.
To make measurement more practi-
cal, the error rate was measured at an
elevated temperature of 150°C,
INPUT FREQUENCY (Hz)
1k
COMMON MODE REJECTION (dB)
1M
1418_03.EPS
20
40
60
80
100
010k 100k
Figure 3. Input common mode rejection vs
input frequency
Linear Technology Magazine • February 1998
16
DESIGN FEATURES
because error rate increases with
temperature. Even at this high tem-
perature, the error rate was 1 in 100
billion. The projected error rate at room
temperature is 1 in 2,000,000 billion
or about 1 error every 320 years if
running at full conversion rate.
Ideal for
Low Power Applications
LTC1418 is especially well suited for
applications that require low power
and high speed. The normal operat-
ing power is low—only 15mW. Power
may be further reduced if there are
extended periods of time between con-
versions. During these inactive periods
when the ADC is not converting, the
LTC1418 may be shut down. There
are two power shutdown modes: NAP
and SLEEP.
NAP mode shuts down 85% of the
power and leaves only the reference
and logic powered up. The LTC1418
can wake up from NAP mode very
quickly; in just 500ns it can be ready
to start converting. In NAP mode, all
data-output control is functional; data
from the last conversion prior to start-
ing NAP mode can be read during NAP
mode. RD also controls the state of
the output buffers. NAP mode is use-
ful for applications that must be ready
to immediately take data after long
inactive periods.
With slow sample rates, power can
be saved by automatically invoking
NAP mode between conversions.
Referring to Figure 4, the SHDN pin
and CONVST pin are driven together.
A conversion will be started with the
falling edge of this signal; once the
conversion is completed, the ADC will
automatically shut down. Before the
next conversion can start, the
CONVST and SHDN pins must be
brought high early enough to allow
for the 500ns wake-up time. Power
drops with the sample frequency until
it approaches the power of the
reference circuit, about 2mW at fre-
quencies less than 10kHz.
The SLEEP mode is used when the
NAP-mode current drain is too high or
if wake-up time is not critical. In
5V
5V
0V
3mA
I
DD
I
DD
CONVST = SHDN
1418_04a.EPS
CONVERSION
TIME
NAP
WAKE-UP
AND
AQUISITION
TIME
NAP
CONVST
LTC1418
SHDN
CS
0
Figure 4a. NAP mode between conversions
SAMPLE RATE (SPS)
1k
2mW
POWER DISSIPATION
15mW
10k
1418_04b.EPS
100k 200k
Figure 4b. Power dissipation vs sample rate
with NAP mode between conversions
SLEEP mode, all bias currents are
shut down, the reference is shut down
and the logic outputs are put in a high
impedance state. The only current
that remains is junction leakage cur-
rent, less than 1µA. Wake-up from
the SLEEP mode is much slower, since
the reference circuit must power up
and settle to 0.01% for full accuracy.
The wake-up time is also dependent
on the value of the compensation
capacitor used on the REFCOMP pin;
with the recommended 10µF capaci-
tor the wake up time is 10ms. SLEEP
mode is useful for long inactive peri-
ods, that is, times greater than 10ms.
Conclusion
The new LTC1418 low power, 14-bit
ADC will find uses in many types of
applications, from industrial ins-
trumentation to telephony. The
LTC1418’s adaptable design reduces
the need for expensive support cir-
cuitry. This can result in a smaller,
lower cost system.
Authors can be contacted
at (408) 432-1900
Linear Technology Magazine • February 1998
17
DESIGN FEATURES
A 10MB/s Multiple-Protocol Chip Set
Supports Net1 and Net2 Standards
by David Soo
Introduction
With the increase in multinational
computer networks comes the need
for the network equipment to support
different serial protocols. One solu-
tion is to provide a different serial
interface board for each market. This
can become unmanageable as prod-
uct volume increases. The issues of
board swapping and inventory are
often discounted. Another solution is
to place all of the serial interfaces,
each isolated, on a single board. For
example, when the product is sold
with V.35, the serial cable is mapped
to that section of the board. This
requires a large connector plus signal
routing and board space.
The best solution is to support many
different serial protocols on one con-
nector, but that requires the circuitry
for each serial protocol to share the
same connector pins. At first glance
this may not appear to be difficult.
Further examination reveals conflict-
ing line-termination standards that
require resistors to be switched to the
connector pins. As the designer
becomes occupied with the details of
the interface specification, there is
always the possibility that one small
detail will be missed. This compliance
headache causes designers to seek
out a cost-effective integrated solution.
With the LTC1543, LTC1544 and
LTC1344A, LTC has taken the inte-
grated approach to multiple-protocol.
It does not make sense to use a hand-
ful of standard interface parts when
Net1 and Net2 compliance is guaran-
teed with the LTC1543, LTC1544 and
LTC1344A. Detecon, Inc. documents
this compliance in Test Report No.
NET2/102201/97. With this chip set,
network designers can concentrate
on functions that increase the
end-product value rather than on
standards compliance.
Typical Application
Like the LTC1343 software-selectable
multiprotocol transceiver, introduced
in the August, 1996 issue of Linear
Technology , the LTC1543/LTC1544/
LTC1344A chip set creates a com-
plete software-selectable serial
interface using an inexpensive DB-
25 connector. The main difference
between these parts is the division of
functions: the LTC1343 can be con-
figured as a data/clock chip or as a
control-signal chip using the CTRL/
CLK pin, whereas the LTC1543 is a
dedicated data/clock chip and the
LTC1544 is a control-signal chip. The
chip set supports the V.28 (RS232),
V.35, V.36, RS449, EIA-530, EIA-530A
and X.21 protocols in either DTE or
DCE mode.
Figure 1 shows a typical applica-
tion using the LTC1543, LTC1544
and LTC1344A. By just mapping the
chip pins to the connector, the design
of the interface port is complete. The
figure shows a DCE mode connection
to a DB-25 connector.
The LTC1543 contains three drivers
and three receivers, whereas the
LTC1544 contains four drivers and
four receivers. The LTC1344A
contains six switchable resistive ter-
minators that are connected only to
the high speed clock and data sig-
nals. When the interface protocol is
changed via the mode selection pins,
M2, M1 and M0, the drivers, receivers
and line terminators are placed in
their proper configuration. The mode
pin functions are summarized in
Table 1. There are internal 50µA pull-
up current sources on the mode select
pins, DCE/DTE and the INVERT pins.
DTE vs DCE Operation
The LTC1543/LTC1544/LTC1344A
chip set can be configured for either
DTE or DCE operation in one of two
ways. The first way is when the chip
set is a dedicated DTE or DCE port
with a connector of appropriate gen-
der. The second way is when the port
has one connector that can be config-
ured for DTE or DCE operation by
rerouting the signals to the chip set
using a dedicated DTE or DCE cable.
Figure 1 is an example of a dedi-
cated DCE port using a female DB-25
connector. The complement to this port
is the DTE-only port using a male DB-
25 connector, as shown in Figure 2.
If the port must accommodate both
DTE and DCE modes, the mapping of
the drivers and receivers to connector
pins must change accordingly. For
example, in Figure 1, driver 1 in the
LTC1543 is connected to pin 3 and
pin 16 of the DB-25 connector. In DTE
mode, as shown in Figure 2, driver 1
is mapped to pins 2 and 14 of the DB-
25 connector. A port that can be
configured for either DTE or DCE
operation is shown in Figure 3. This
configuration requires separate cables
for proper signal routing.
Cable-Selectable
Multiprotocol Interface
The interface protocol may be selected
by simply plugging the appropriate
interface cable into the connector. A
cable-selectable multiprotocol DTE/
DCE interface is shown in Figure 4.
4451CTL/3451CTL
emaNedoM2M1M0M
desUtoN 000
A035-AIE 001
035-AIE 010
12.X 011
53.V 100
63.V/944SR 101
82.V/232SR 110
elbaCoN 111
Table 1. Mode pin functions
text continued on page 32/figures on pp. 18–22
Linear Technology Magazine • February 1998
18
DESIGN FEATURES
1
7
8
10
20
23
13
5
RXD
RXC
TXC
SCTE
TXD
CTS
DSR
DCD
DTR
RTS
LL
M2
M1
M0
14
2
11
24
12
15
6
22
4
19
18
22
21
20
19
25
26
27
GND
28
V
EE
24
23
18
17
16
15NC
9
17
16
3
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
DB-25 FEMALE
CONNECTOR
24232220191718151610976452
3 8 11 12
3
1
2
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
M0
M1
M2 INVERT
DCE/DTE
8
9
11
12
13
14
NC
10
NC
14
LTC1344A
RXD A (104)
RXD B
RXC A (115)
RXC B
TXC A (114)
TXC B
SCTE A (113)
SCTE B
TXD A (103)
TXD B
SGND (102)
SHIELD (101)
CTS A (106)
CTS B
DSR A (107)
DSR B
DCD A (109)
DCD B
DTR A (108)
DTR B
RTS A (105)
RTS B
LL A (141)
V
CC
5.0V
V
CC
V
CC
V
CC
V
CC
MO
M1
M2
V
EE
V
DD
C1
1.0µF
C3
1.0µF
C2
1.0µF
C4
3.3µF
C5
1µF
C8
100pF
C7
100pF
C6
100pF
+
++
+
13
DCE/DTE
LTC1543
LTC1544
DCE/DTE
M2
M1
M0
CHARGE
PUMP
D1
D2
D3
R1
R2
R3
D1
D2
D3
R1
R2
R3
R4
D4
1544_01.eps
21
LATCH
+
Figure 1. Controller-selectable DCE port with DB-25 connector
Linear Technology Magazine • February 1998
19
DESIGN FEATURES
1
7
8
10
6
22
19
4
TXD
SCTE
TXC
RXC
RXD
RTS
DTR
DCD
DSR
CTS
LL
M2
M1
M0
16
3
9
17
12
15
20
23
5
13
18
22
21
20
19
25
26
27
GND
28
V
EE
24
23
18
17
16
15NC
11
24
14
2
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
DB-25 MALE
CONNECTOR
24232220191718151610976452
3 8 11 12
3
1
2
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
M0
M1
M2 INVERT
DCE/DTE
8
9
11
12
13
14
10
14
LTC1344A
V
CC
5.0V
V
CC
V
CC
V
CC
MO
M1
M2
V
EE
V
DD
C1
1.0µF
C3
1.0µF
C2
1.0µF
C4
3.3µF
C5
1µF
C8
100pF
C7
100pF
C6
100pF
+
++
+
13
DCE/DTE
LTC1543
LTC1544
DCE/DTE
M2
M1
M0
CHARGE
PUMP
D1
D2
D3
R1
R2
R3
D1
D2
D3
R1
R2
R3
R4
D4
1544_02.eps
TXD A (103)
TXD B
SCTE A (113)
SCTE B
TXC A (114)
TXC B
RXC A (115)
RXC B
RXD A (104)
RXD B
SGND (102)
SHIELD (101)
RTS A (105)
RTS B
DTR A (108)
DTR B
DCD A (109)
DCD B
DSR A (107)
DSR B
CTS A (106)
CTS B
LL A (141)
21
LATCH
+
Figure 2. Controller-selectable multiprotocol DTE port with DB-25 connector