ADC08032CIWMX - National Semiconductor

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January 15, 2007

ADC08031/ADC08032/ADC08034/ADC08038

8-Bit High-Speed Serial I/O A/D Converters with Multiplexer

Options, Voltage Reference, and Track/Hold Function

General Description

The ADC08031/ADC08032/ADC08034/ADC08038 are 8-bit

successive approximation A/D converters with serial I/O and

configurable input multiplexers with up to 8 channels. The se-

rial I/O is configured to comply with the NSC MI-

CROWIRE™ serial data exchange standard for easy inter-

face to the COPS™ family of controllers, and can easily

interface with standard shift registers or microprocessors.

The ADC08034 and ADC08038 provide a 2.6V band-gap de-

rived reference. For devices offering guaranteed voltage ref-

erence performance over temperature see ADC08131,

ADC08134 and ADC08138.

A track/hold function allows the analog voltage at the positive

input to vary during the actual A/D conversion.

The analog inputs can be configured to operate in various

combinations of single-ended, differential, or pseudo-differ-

ential modes. In addition, input voltage spans as small as 1V

can be accommodated.

Applications

■Digitizing automotive sensors

■Process control monitoring

■Remote sensing in noisy environments

■Instrumentation

■Test systems

■Embedded diagnostics

Features

■Serial digital data link requires few I/O pins

■Analog input track/hold function

■2-, 4-, or 8-channel input multiplexer options with address

logic

■0V to 5V analog input range with single 5V power supply

■No zero or full scale adjustment required

■TTL/CMOS input/output compatible

■On chip 2.6V band-gap reference

■0.3″ standard width 8-, 14-, or 20-pin DIP package

■14-, 20-pin small-outline packages

Key Specifications

■Resolution: 8 bits

■Conversion time (fC = 1 MHz): 8μs (max)

■Power dissipation: 20mW (max)

■Single supply: 5VDC (±5%)

■Total unadjusted error: ±½ LSB and ±1LSB

■No missing codes over temperature

Ordering Information

Industrial (−40°C ≤ TA ≤ +85°C) Package

ADC08031CIN N08E

ADC08038CIN N20A

ADC08031CIWM,

ADC08032CIWM, M14B

ADC08034CIWM

ADC08038CIWM M20B

This device is obsolete in all packages.

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

10555 Version 6 Revision 6 Print Date/Time: 2008/01/10 20:18:10

ADC08031/ADC08032/ADC08034/ADC08038 8-Bit High-Speed Serial I/O A/D Converters with

Multiplexer Options, Voltage Reference, and Track/Hold Function

Connection Diagrams

ADC08038

1055502

ADC08034

1055503

ADC08031

Dual-In-Line Package

1055505

ADC08032

Small Outline Package

1055530

ADC08031

Small Outline Package

1055531

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ADC08031/ADC08032/ADC08034/ADC08038

Absolute Maximum Ratings (Notes 1, 3)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage (VCC)6.5V

Voltage at Inputs and Outputs −0.3V to VCC + 0.3V

Input Current at Any Pin (Note 4) ±5 mA

Package Input Current (Note 4) ±20 mA

Power Dissipation at TA = 25°C

(Note 5) 800 mW

ESD Susceptibility (Note 6) 1500V

Soldering Information

N Package (10 sec.)

SO Package:

Vapor Phase (60 sec.)

Infrared (15 sec.) (Note 7)

235°C

215°C

220°C

Storage Temperature −65°C to +150°C

Operating Ratings (Notes 2, 3)

Temperature Range TMIN ≤ TA ≤ TMAX

ADC08031BIN, ADC08031CIN, −40°C ≤ TA ≤ +85°

ADC08032BIN, ADC08032CIN,

ADC08034BIN, ADC08034CIN,

ADC08038BIN, ADC08038CIN,

ADC08031BIWM, ADC08032BIWM,

ADC08034BIWM, ADC08038BIWM

ADC08031CIWM, ADC08032CIWM,

ADC08034CIWM, ADC08038CIWM

Supply Voltage (VCC) 4.5 VDC to 6.3 VDC

Electrical Characteristics

The following specifications apply for VCC = VREF = +5 VDC, and fCLK = 1 MHz unless otherwise specified. Boldface limits apply

for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.

Symbol Parameter Conditions Typical Limits Units

(Note 8) (Note 9) (Limits)

CONVERTER AND MULTIPLEXER CHARACTERISTICS

Total Unadjusted Error (Note 10)

BIN, BIWM ±½ LSB (max)

CIN, CIWM ±1 LSB (max)

Differential 8Bits (min)

Linearity

RREF Reference Input Resistance (Note 11) 3.5 kΩ

1.3 kΩ (min)

6.0 kΩ (max)

VIN Analog Input Voltage (Note 12) (VCC + 0.05) V (max)

(GND − 0.05) V (min)

DC Common-Mode Error ±¼ LSB (max)

Power Supply Sensitivity VCC = 5V ±5%, ±¼ LSB (max)

VREF = 4.75V

On Channel Leakage On Channel = 5V, 0.2 μA (max)

Current (Note 13) Off Channel = 0V 1

On Channel = 0V, −0.2 μA (max)

Off Channel = 5V −1

Off Channel Leakage On Channel = 5V, −0.2 μA (max)

Current (Note 13) Off Channel = 0V −1

On Channel = 0V, 0.2 μA (max)

Off Channel = 5V 1

DIGITAL AND DC CHARACTERISTICS

VIN(1) Logical “1” Input Voltage VCC = 5.25V 2.0 V (min)

VIN(0) Logical “0” Input Voltage VCC = 4.75V 0.8 V (max)

IIN(1) Logical “1” Input Current VIN = 5.0V 1μA (max)

IIN(0) Logical “0” Input Current VIN = 0V −1 μA (max)

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ADC08031/ADC08032/ADC08034/ADC08038

Symbol Parameter Conditions Typical Limits Units

(Note 8) (Note 9) (Limits)

VOUT(1) Logical “1” Output Voltage VCC = 4.75V:

IOUT = −360 μA 2.4 V (min)

IOUT = −10 μA 4.5 V (min)

VOUT(0) Logical “0” Output Voltage VCC = 4.75V 0.4 V (max)

IOUT = 1.6 mA

IOUT TRI-STATE® Output Current VOUT = 0V −3.0 μA (max)

VOUT = 5V 3.0 μA (max)

ISOURCE Output Source Current VOUT = 0V −6.5 mA (min)

ISINK Output Sink Current VOUT = VCC 8.0 mA (min)

ICC Supply Current

ADC08031, ADC08034, CS = HIGH 3.0 mA (max)

and ADC08038

ADC08032 (Note 16) 7.0 mA (max)

REFERENCE CHARACTERISTICS

VREFOUT Nominal Reference Output VREFOUT Option

Available Only on 2.6 V

ADC08034 and

ADC08038

Electrical Characteristics

The following specifications apply for VCC = VREF = +5 VDC, and tr = tf = 20 ns unless otherwise specified. Boldface limits apply

for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.

Symbol Parameter Conditions Typical Limits Units

(Note 8) (Note 9) (Limits)

fCLK Clock Frequency 10 kHz (min)

1MHz (max)

Clock Duty Cycle 40 % (min)

(Note 14) 60 % (max)

TCConversion Time (Not Including fCLK = 1 MHz 81/fCLK (max)

MUX Addressing Time) 8μs (max)

tCA Acquisition Time ½1/fCLK(max)

tSELECT CLK High while CS is High 50 ns

tSET-UP CS Falling Edge or Data Input 25 ns (min)

Valid to CLK Rising Edge

tHOLD Data Input Valid after CLK 20 ns (min)

Rising Edge

tpd1, tpd0 CLK Falling Edge to Output CL = 100 pF:

Data Valid (Note 15) Data MSB First 250 ns (max)

Data LSB First 200 ns (max)

t1H, t0H TRI-STATE Delay from Rising Edge CL = 10 pF, RL = 10 kΩ50 ns

of CS to Data Output and SARS Hi-Z (see TRI-STATE Test Circuits)

CL = 100 pF, RL = 2 kΩ 180 ns (max)

CIN Capacitance of Logic Inputs 5 pF

COUT Capacitance of Logic Outputs 5 pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.

Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed

specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions.

Note 3: All voltages are measured with respect to AGND = DGND = 0 VDC, unless otherwise specified.

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ADC08031/ADC08032/ADC08034/ADC08038

Note 4: When the input voltage VIN at any pin exceeds the power supplies (VIN < (AGND or DGND) or VIN > VCC) the current at that pin should be limited to 5

mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four

pins.

Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA and the ambient temperature, TA. The maximum

allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For these

devices, TJMAX = 125°C. The typical thermal resistances (θJA) of these parts when board mounted follow: ADC08031 and ADC08032 with BIN and CIN suffixes

120°C/W, ADC08038 with CIN suffix 80°C/W. ADC08031 with CIWM suffix 140°C/W, ADC08032 140°C/W, ADC08034 140°C/W, ADC08038 with CIWM suffix

91°C/W.

Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor.

Note 7: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or Linear Data Book section “Surface Mount” for other methods of soldering

surface mount devices.

Note 8: Typical figures are at TJ = 25°C and represent the most likely parametric norm.

Note 9: Guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 10: Total unadjusted error includes offset, full-scale, linearity, multiplexer.

Note 11: Cannot be tested for the ADC08032.

Note 12: For VIN(−) ≥ VIN(+) the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct

for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. During testing at low VCC levels (e.g., 4.5V), high level analog

inputs (e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors for analog inputs near full-scale. The spec

allows 50 mV forward bias of either diode; this means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code

will be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 VDC to 5 VDC input

voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading.

Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following

two cases are considered: one, with the selected channel tied high (5 VDC) and the remaining seven off channels tied low (0 VDC), total current flow through the

off channels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured.

The two cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.

Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these

limits the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or low is 100 μs.

Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to

allow for comparator response time.

Note 16: For the ADC08032 VREFIN is internally tied to VCC, therefore, for the ADC08032 reference current is included in the supply current.

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ADC08031/ADC08032/ADC08034/ADC08038

Typical Performance Characteristics

Linearity Error vs.

Reference Voltage

1055532

Linearity Error vs.

Temperature

1055533

Linearity Error vs.

Clock Frequency

1055534

Power Supply Current vs.

Temperature (ADC08038,

ADC08034, ADC08031)

1055535

Note: For ADC08032 add IREF

Output Current vs.

Temperature

1055536

Power Supply Current

vs. Clock Frequency

1055537

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ADC08031/ADC08032/ADC08034/ADC08038

Leakage Current Test Circuit

1055507

TRI-STATE Test Circuits and Waveforms

t1H

1055538

1055539

t0H

1055540

1055541

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ADC08031/ADC08032/ADC08034/ADC08038

Timing Diagrams

Data Input Timing

1055510

*To reset these devices, CLK and CS must be simultaneously high for a period of tSELECT or greater. Otherwise these devices are compatible with industry

standards ADC0831/2/4/8.

Data Output Timing

1055511

ADC08031 Start Conversion Timing

1055512

ADC08031 Timing

1055513

*LSB first output not available on ADC08031.

LSB information is maintained for remainder of clock periods until CS goes high.

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ADC08031/ADC08032/ADC08034/ADC08038

ADC08032 Timing

1055514

ADC08034 Timing

1055515

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ADC08031/ADC08032/ADC08034/ADC08038

ADC08038 Timing

1055516

*Make sure clock edge #18 clocks in the LSB before SE is taken low

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ADC08031/ADC08032/ADC08034/ADC08038

ADC08038 Functional Block Diagram

1055517

*Some of these functions/pins are not available with other options.

For the ADC08034, the “SEL 1” Flip-Flop is bypassed, for the ADC08032, both “SEL 0” and “SEL 1” Flip-Flops are bypassed.

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ADC08031/ADC08032/ADC08034/ADC08038

Functional Description

1.0 MULTIPLEXER ADDRESSING

The design of these converters utilizes a comparator structure

with built-in sample-and-hold which provides for a differential

analog input to be converted by a successive-approximation

routine.

The actual voltage converted is always the difference be-

tween an assigned “+” input terminal and a “−” input terminal.

The polarity of each input terminal of the pair indicates which

line the converter expects to be the most positive. If the as-

signed “+” input voltage is less than the “−” input voltage the

converter responds with an all zeros output code.

A unique input multiplexing scheme has been utilized to pro-

vide multiple analog channels with software-configurable sin-

gle-ended, differential, or pseudo-differential (which will

convert the difference between the voltage at any analog in-

put and a common terminal) operation. The analog signal

conditioning required in transducer-based data acquisition

systems is significantly simplified with this type of input flexi-

bility. One converter package can now handle ground refer-

enced inputs and true differential inputs as well as signals with

some arbitrary reference voltage.

A particular input configuration is assigned during the MUX

addressing sequence, prior to the start of a conversion. The

MUX address selects which of the analog inputs are to be

enabled and whether this input is single-ended or differential.

Differential inputs are restricted to adjacent channel pairs. For

example, channel 0 and channel 1 may be selected as a dif-

ferential pair but channel 0 or 1 cannot act differentially with

any other channel. In addition to selecting differential mode

the polarity may also be selected. Channel 0 may be selected

as the positive input and channel 1 as the negative input or

vice versa. This programmability is best illustrated by the

MUX addressing codes shown in the following tables for the

various product options.

The MUX address is shifted into the converter via the DI line.

Because the ADC08031 contains only one differential input

channel with a fixed polarity assignment, it does not require

addressing.

The common input line (COM) on the ADC08038 can be used

as a pseudo-differential input. In this mode the voltage on this

pin is treated as the “−” input for any of the other input chan-

nels. This voltage does not have to be analog ground; it can

be any reference potential which is common to all of the in-

puts. This feature is most useful in single-supply applications

where the analog circuity may be biased up to a potential oth-

er than ground and the output signals are all referred to this

potential.

TABLE 1. Multiplexer/Package Options

Part

Number

Number of Analog Channels Number of

Package

Pins

Single-Ended Differential

ADC08031 1 1 8

ADC08032 2 1 8

ADC08034 4 2 14

ADC08038 8 4 20

TABLE 2. MUX Addressing: ADC08038

Single-Ended MUX Mode

MUX Address Analog Single-Ended Channel #

START SGL/ DIF ODD/

SIGN

SELECT 0 1 2 3 4 5 6 7 COM

1 0

1 1 0 0 0 + −

1 1 0 0 1 + −

1 1 0 1 0 + −

1 1 0 1 1 + −

1 1 1 0 0 + −

1 1 1 0 1 + −

1 1 1 1 0 + −

1 1 1 1 1 + −

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TABLE 3. MUX Addressing: ADC08038

Differential MUX Mode

MUX Address Analog Differential Channel-Pair #

START SGL/ DIF ODD/ SIGN SELECT 0 1 2 3

1 0 0 1 2 3 4 5 6 7

1 0 0 0 0 + −

1 0 0 0 1 + −

1 0 0 1 0 + −

1 0 0 1 1 + −

1 0 1 0 0 −+

1 0 1 0 1 −+

1 0 1 1 0 −+

1 0 1 1 1 −+

TABLE 4. MUX Addressing: ADC08034

Single-Ended MUX Mode

MUX Address Channel #

START SGL/ DIF ODD/

SIGN

SELECT 0123

1 1 0 0 +

1 1 0 1 +

1 1 1 0 +

1 1 1 1 +

COM is internally tied to AGND

MUX Addressing:

ADC08032

Single-Ended MUX Mode

MUX Address Channel #

START SGL/

DIF

ODD/

SIGN 0 1

1 1 0 +

1 1 1 +

COM is internally tied to AGND

Differential MUX Mode

MUX Address Channel #

START SGL/ DIF ODD/

SIGN

SELECT 0123

1 0 0 0 + −

1 0 0 1 + −

1 0 1 0 −+

1 0 1 1 −+

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ADC08031/ADC08032/ADC08034/ADC08038

Differential MUX Mode

MUX Address Channel #

START SGL/

DIF

ODD/

SIGN 0 1

1 0 0 + −

1 0 1 −+

Since the input configuration is under software control, it can

be modified as required before each conversion. A channel

can be treated as a single-ended, ground referenced input for

one conversion; then it can be reconfigured as part of a dif-

ferential channel for another conversion. Figure 1 illustrates

the input flexibility which can be achieved.

The analog input voltages for each channel can range from

50mV below ground to 50mV above VCC (typically 5V) without

degrading conversion accuracy.

2.0 THE DIGITAL INTERFACE

A most important characteristic of these converters is their

serial data link with the controlling processor. Using a serial

communication format offers two very significant system im-

provements; it allows many functions to be included in a small

package and it can eliminate the transmission of low level

analog signals by locating the converter right at the analog

sensor; transmitting highly noise immune digital data back to

the host processor.

To understand the operation of these converters it is best to

refer to the Timing Diagrams and Functional Block Diagram

and to follow a complete conversion sequence. For clarity a

separate timing diagram is shown for each device.

1. A conversion is initiated by pulling the CS (chip select)

line low. This line must be held low for the entire

conversion. The converter is now waiting for a start bit

and its MUX assignment word.

2. On each rising edge of the clock the status of the data in

(DI) line is clocked into the MUX address shift register.

The start bit is the first logic “1” that appears on this line

(all leading zeros are ignored). Following the start bit the

converter expects the next 2 to 4 bits to be the MUX

assignment word.

3. When the start bit has been shifted into the start location

of the MUX register, the input channel has been assigned

and a conversion is about to begin. An interval of ½ clock

period (where nothing happens) is automatically inserted

to allow the selected MUX channel to settle. The SARS

line goes high at this time to signal that a conversion is

now in progress and the DI line is disabled (it no longer

accepts data).

4. The data out (DO) line now comes out of TRI-STATE and

provides a leading zero for this one clock period of MUX

settling time.

5. During the conversion the output of the SAR comparator

indicates whether the analog input is greater than (high)

or less than (low) a series of successive voltages

generated internally from a ratioed capacitor array (first

5 bits) and a resistor ladder (last 3 bits). After each

comparison the comparator's output is shipped to the DO

line on the falling edge of CLK. This data is the result of

the conversion being shifted out (with the MSB first) and

can be read by the processor immediately.

6. After 8 clock periods the conversion is completed. The

SARS line returns low to indicate this ½ clock cycle later.

7. The stored data in the successive approximation register

is loaded into an internal shift register. If the programmer

prefers the data can be provided in an LSB first format

[this makes use of the shift enable (SE) control line]. On

the ADC08038 the SE line is brought out and if held high

the value of the LSB remains valid on the DO line. When

SE is forced low the data is clocked out LSB first. On

devices which do not include the SE control line, the data,

LSB first, is automatically shifted out the DO line after the

MSB first data stream. The DO line then goes low and

stays low until CS is returned high. The ADC08031 is an

exception in that its data is only output in MSB first format.

8. All internal registers are cleared when the CS line is high

and the tSELECT requirement is met. See Data Input

Timing under Timing Diagrams. If another conversion is

desired CS must make a high to low transition followed

by address information.

The DI and DO lines can be tied together and controlled

through a bidirectional processor I/O bit with one wire.

This is possible because the DI input is only “looked-at”

during the MUX addressing interval while the DO line is

still in a high impedance state.

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ADC08031/ADC08032/ADC08034/ADC08038

8 Single-Ended

1055548

8 Pseudo-Differential

1055549

4 Differential

1055550

Mixed Mode

1055551

FIGURE 1. Analog Input Multiplexer Options for the ADC08038

3.0 REFERENCE CONSIDERATIONS

The voltage applied to the reference input on these convert-

ers, VREFIN, defines the voltage span of the analog input (the

difference between VIN(MAX) and VIN(MIN) over which the 256

possible output codes apply. The devices can be used either

in ratiometric applications or in systems requiring absolute

accuracy. The reference pin must be connected to a voltage

source capable of driving the reference input resistance which

can be as low as 1.3kΩ. This pin is the top of a resistor divider

string and capacitor array used for the successive approxi-

mation conversion.

In a ratiometric system the analog input voltage is proportional

to the voltage used for the A/D reference. This voltage is typ-

ically the system power supply, so the VREFIN pin can be tied

to VCC (done internally on the ADC08032). This technique re-

laxes the stability requirements of the system reference as the

analog input and A/D reference move together maintaining

the same output code for a given input condition.

For absolute accuracy, where the analog input varies be-

tween very specific voltage limits, the reference pin can be

biased with a time and temperature stable voltage source. For

the ADC08034 and the ADC08038 a band-gap derived ref-

erence voltage of 2.6V (Note 8) is tied to VREFOUT. This can

be tied back to VREFIN. Bypassing VREFOUT with a 100μF

capacitor is recommended. The LM385 and LM336 reference

diodes are good low current devices to use with these con-

verters.

The maximum value of the reference is limited to the VCC

supply voltage. The minimum value, however, can be quite

small (see Typical Performance Characteristics) to allow di-

rect conversions of transducer outputs providing less than a

5V output span. Particular care must be taken with regard to

noise pickup, circuit layout and system error voltage sources

when operating with a reduced span due to the increased

sensitivity of the converter (1 LSB equals VREF/256).

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ADC08031/ADC08032/ADC08034/ADC08038

1055552

a) Ratiometric

1055553

b) Absolute with a Reduced Span

FIGURE 2. Reference Examples

4.0 THE ANALOG INPUTS

The most important feature of these converters is that they

can be located right at the analog signal source and through

just a few wires can communicate with a controlling processor

with a highly noise immune serial bit stream. This in itself

greatly minimizes circuitry to maintain analog signal accuracy

which otherwise is most susceptible to noise pickup. Howev-

er, a few words are in order with regard to the analog inputs

should the input be noisy to begin with or possibly riding on a

large common-mode voltage.

The differential input of these converters actually reduces the

effects of common-mode input noise, a signal common to

both selected “+” and “−” inputs for a conversion (60 Hz is

most typical). The time interval between sampling the “+” input

and then the “−” input is ½ of a clock period. The change in

the common-mode voltage during this short time interval can

cause conversion errors. For a sinusoidal common-mode sig-

nal this error is:

where fCM is the frequency of the common-mode signal,

VPEAK is its peak voltage value

and fCLK is the A/D clock frequency.

For a 60Hz common-mode signal to generate a ¼ LSB error

(≈5mV) with the converter running at 250kHz, its peak value

would have to be 6.63V which would be larger than allowed

as it exceeds the maximum analog input limits.

Source resistance limitation is important with regard to the DC

leakage currents of the input multiplexer. Bypass capacitors

should not be used if the source resistance is greater than

1kΩ. The worst-case leakage current of ±1μA over tempera-

ture will create a 1mV input error with a 1kΩ source resis-

tance. An op amp RC active low pass filter can provide both

impedance buffering and noise filtering should a high

impedance signal source be required.

5.0 OPTIONAL ADJUSTMENTS

5.1 Zero Error

The zero of the A/D does not require adjustment. If the mini-

mum analog input voltage value, VIN(MIN), is not ground a zero

offset can be done. The converter can be made to output 0000

0000 digital code for this minimum input voltage by biasing

any VIN (−) input at this VIN(MIN) value. This utilizes the differ-

ential mode operation of the A/D.

The zero error of the A/D converter relates to the location of

the first riser of the transfer function and can be measured by

grounding the VIN (−) input and applying a small magnitude

positive voltage to the VIN (+) input. Zero error is the difference

between the actual DC input voltage which is necessary to

just cause an output digital code transition from 0000 0000 to

0000 0001 and the ideal ½ LSB value (½ LSB = 9.8mV for

VREF = 5.000VDC).

5.2 Full Scale

The full-scale adjustment can be made by applying a differ-

ential input voltage which is 1½ LSB down from the desired

analog full-scale voltage range and then adjusting the mag-

nitude of the VREFIN input (or VCC for the ADC08032) for a

digital output code which is just changing from 1111 1110 to

1111 1111.

5.3 Adjusting for an Arbitrary Analog Input

Voltage Range

If the analog zero voltage of the A/D is shifted away from

ground (for example, to accommodate an analog input signal

which does not go to ground), this new zero reference should

be properly adjusted first. A VIN (+) voltage which equals this

desired zero reference plus ½ LSB (where the LSB is calcu-

lated for the desired analog span, using 1 LSB = analog span/

256) is applied to selected “+” input and the zero reference

voltage at the corresponding “−” input should then be adjusted

to just obtain the 00HEX to 01HEX code transition.

The full-scale adjustment should be made [with the proper

VIN (−) voltage applied] by forcing a voltage to the VIN (+) input

which is given by:

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10555 Version 6 Revision 6 Print Date/Time: 2008/01/10 20:18:10

ADC08031/ADC08032/ADC08034/ADC08038

where:

VMAX = the high end of the analog input range

and

VMIN = the low end (the offset zero) of the analog range.

(Both are ground referenced.)

The VREFIN (or VCC) voltage is then adjusted to provide a code

change from FEHEX to FFHEX. This completes the adjustment

procedure.

Applications

A “Stand-Alone” Hook-Up for ADC08038 Evaluation

1055544

*Pinouts shown for ADC08038.

For all other products tie to pin functions as shown.

17 www.national.com

10555 Version 6 Revision 6 Print Date/Time: 2008/01/10 20:18:10

ADC08031/ADC08032/ADC08034/ADC08038

Low-Cost Remote Temperature Sensor

1055545

Digitizing a Current Flow

1055522

Operating with Ratiometric Transducers

1055523

*VIN(−) = 0.15 VCC

15% of VCC ≤ VXDR ≤ 85% of VCC

www.national.com 18

10555 Version 6 Revision 6 Print Date/Time: 2008/01/10 20:18:10

ADC08031/ADC08032/ADC08034/ADC08038

Span Adjust; 0V ≤ VIN ≤ 3V

1055546

Zero-Shift and Span Adjust: 2V ≤ VIN ≤ 5V

1055547

19 www.national.com

10555 Version 6 Revision 6 Print Date/Time: 2008/01/10 20:18:10

ADC08031/ADC08032/ADC08034/ADC08038

Protecting the Input

1055525

Diodes are 1N914

High Accuracy Comparators

1055526

DO = all 1s if +VIN > −VIN

DO = all 0s if +VIN < −VIN

Digital Load Cell

1055527

—Uses one more wire than load cell itself

—Two mini-DIPs could be mounted inside load cell for digital output transducer

—Electronic offset and gain trims relax mechanical specs for gauge factor and offset

—Low level cell output is converted immediately for high noise immunity

www.national.com 20

10555 Version 6 Revision 6 Print Date/Time: 2008/01/10 20:18:10

ADC08031/ADC08032/ADC08034/ADC08038

4 mA-20 mA Current Loop Converter

1055528

—All power supplied by loop

—1500V isolation at output

Isolated Data Converter

1055529

—No power required remotely

—1500V isolation

21 www.national.com

10555 Version 6 Revision 6 Print Date/Time: 2008/01/10 20:18:10

ADC08031/ADC08032/ADC08034/ADC08038

Physical Dimensions inches (millimeters) unless otherwise noted

Order Number ADC08031CIWM, ADC08032CIWM, or ADC08034CIWM

NS Package Number M14B

Order Number ADC08038CIWM

NS Package Number M20B

www.national.com 22

10555 Version 6 Revision 6 Print Date/Time: 2008/01/10 20:18:10

ADC08031/ADC08032/ADC08034/ADC08038

Order Number ADC08031CIN

NS Package Number N08E

Order Number ADC08038CIN

NS Package Number N20A

23 www.national.com

10555 Version 6 Revision 6 Print Date/Time: 2008/01/10 20:18:10

ADC08031/ADC08032/ADC08034/ADC08038

Notes

ADC08031/ADC08032/ADC08034/ADC08038 8-Bit High-Speed Serial I/O A/D Converters with

Multiplexer Options, Voltage Reference, and Track/Hold Function

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10555 Version 6 Revision 6 Print Date/Time: 2008/01/10 20:18:10