ANALOG DEVICES .. L?M0S 16-Bit Voltage Output DAC AD7846 FEATURES 16-Bit Monotonicity over Temperature +2LSBs Integral Linearity Error Microprocessor Compatible with Readback Capability Unipolar or Bipolar Output Multiplying Capability Low Power (100mW typical) GENERAL DESCRIPTION The AD7846 is a 16-bit DAC constructed with Analog Devices LC?MOS process. It has Vazy, and Vazp. reference inputs and an on-chip output amplifier. These can be configured to give a unipolar output range (0 to +5V, 0 to +10V) or bipolar output ranges (+5V, +10V). The DAC uses a segmented architecture. The 4MSBs in the DAC latch select one of the segments in a 16-resistor string. Both taps of the segment are buffered by amplifiers and fed to a 12-bit DAC, which provides a further 12 bits of resolution. This architecture ensures 16-bit monotonicity. Excellent integral lin- earity results from tight matching between the input offset volt- ages of the two buffer amplifiers. In addition to the excellent accuracy specifications, the AD7846 also offers a comprehensive microprocessor interface. There are 16 data I/O pins, plus control lines (CS, RW, LDAC and CLR). R/W and CS allow writing to and reading from the I/O latch. This is the readback function which is useful in ATE ap- plications. LDAC allows simultaneous updating of DACs in a multi-DAC system and the CLR line will reset the contents the DAC latch to 00 . . . 000 or 10 . . . 000 depending on the state of R/W. This means that the DAC output can be reset to OV in both the unipolar and bipolar configurations. The AD7846 is available in 28-pin plastic, ceramic, LCCC and PLCC packages. This is an abridged data sheet. To obtain the most recent version or complete data sheet, call our fax retrieval system at 1-800-446-6212. REV. B FUNCTIONAL BLOCK DIAGRAM AD7846 (3) iG 20) Ves bB15 080 DGND PRODUCT HIGHLIGHTS 1. 16-Bit Monotonicity The guaranteed 16-bit monotonicity over temperature makes the AD7846 ideal for closed-loop applications. 2. Readback The ability to read back the DAC register contents minimizes software routines when the AD7846 is used in ATE systems. 3. Power Dissipation Power dissipation of 100mW makes the AD7846 the lowest power, high accuracy DAC on the market. DIGITAL-TO-ANALOG CONVERTERS 3-217AD7846 SPECIFICATIONS' (Yop = +5.25V. Vou, loaded with 2kQ, 1000pF to OV. Vac, = +5V, Ry connected to OV. All specifications Ty, tO Ty unless otherwise stated.) +14.25V to +15.75, Veg = 14.25V to 15.75V, Veg = +4.75V to J, A Versions | K, B Versions | S Version Units Test Conditions/Comments Resolution 16 16 16 Bits UNIPOLAR OUTPUT Vaer-=0V; Voyr=0V to +10V Relative Accuracy @ 25C 12 +4 12 LSB typ ILSB=153pV Train tO Tenax +16 +8 +16 LSB max Differential Nonlinearity Exror + 0.5 + LSB max All Grades Guaranteed Monotonic Gain Error @ 25C #12 +6 #12 LSB typ Vour Load=10M0 Train 0 Tunes +16 +16 #24 LSB max Offset Error @ 25C +12 +6 +12 LSB typ Trin tO Tarax +16 +16 #24 LSB max Gain TC? +2 +2 +2 ppm FSR/C typ Offset TC? +2 +2 22 ppm FSR/"C typ BIPOLAR OUTPUT Vaer-=5V; Vour=10V to +10V Relative Accuracy @ 25C +6 +2 +6 LSB typ ILSB=305pV Train Tinex +8 +4 +8 LSB max Differential Nonlinearity Error +1 +0.5 +1 LSB max All Grades Guaranteed Monotonic Gain Exror @ 25C +6 +4 +6 LSB typ Vour Load=10MQ Trin 10 Trex +16 +16 +16 LSB max Offset Error @ 25C +6 +4 +6 LSB typ Vour Load=10M. Tin 10 Tras +16 +12 +16 LSB max Bipolar Zero Error @ 25C +6 +4 +6 LSB typ Train 10 Tinex +12 +8 +16 LSB max Gain TC? +2 +2 +2 ppm FSR/C typ Offsec TC? +2 +2 +2 ppm FSR/C typ Bipolar Zero TC? +2 +2 +2 ppm FSR/C typ REFERENCE INPUT Input Resistance 20 20 20 kA min Resistance from Vapr_ to Verp+ 40 40 40 kQ. max Typically 30k2. Vaer. Range Vsg +6 to Vs5 +6 to V5 +6 to Volts DD DDT DD~ Varr- Range Veg +6 to V5 +6 to V5 +6 to Volts Vpp-6 pp-6 Dp OUTPUT CHARACTERISTICS Output Voltage Swing V5 +4 to Vs +4 to Vs t4 to V max Vpp-3 Vpp- DD Resistive Load 2 2 3 k0Q mia To 0V Capacitive Load 1000 1000 1000 pF max To OV Output Resistance 0.3 0.3 0.3 Q p Short Circuit Current +25 +25 +25 mA typ To OV or Any Power Supply DIGITAL INPUTS Vin (Input High Voltage) 2.4 2.4 2.4 V min Viz (input Low Voltage) 0.8 0.8 0.8 V max Igy input Current) +10 +10 +10 pA max Cpy (Input Capacitance)? 10 10 10 pF max DIGITAL OUTPUTS Vox (Output Low Voltage) 0.4 0.4 0.4 Volts max Isuvx=1.6mA Von (Output High Voltage) 4.0 4.0 4.0 Volts min Tsounce=400.A Floating State Leakage Current +10 +10 +10 pA max DBO-DB15=0 to Voc Floating State Ourput Capacitance? ; 10 10 10. pF max POWER REQUIREMENTS Vop +11.4/+15,75 | +11.4/4+15.75 +11.4/+15.75 | Vmin/Vmax Vss -11.4/-15.75 | 11.4/-15.75 11.4/-15.75 | Vmin/Vmax Vee +4,75/+5.25 +4,75/+5,25 +4.75/+5.25 Vmin/Vmax Ipp 5 5 5 mA max Vour Unloaded Ics 5 5 5 mA max Vour Unloaded loc 1 1 1 mA max Power Supply Sensitivity LS 15 2 LSB/V max Power Dissipation 100 100 100 mW typ Vout Unloaded NOTES Temperature Ranges as follows: J, K Versions: 0 to +70C; A, B Versions: 25C to +85C; S Version: 55C to +125C. 2Minimum loed for S version is 3k0. Sample tested to ensure compliance. 3-218 DIGITAL-TO-ANALOG CONVERTERS *AD7846 is functional with power supplies of +12V. See Typical Performance Curves. *Sensitivity of Gain Error, Offset Error and Bipolar Zero Error to Vop, Vss variations. Specifications subject to change without notice. REV.BAD7846 These characteristics are included for design guidance only and are not subject to test. (Very, = +5, Vgp=+14.25V to +15.75V, Voce AC PERFORMANCE CHARACTERISTICS 14.25v to -15.75V" v,.=+4.75V to +5.25V, R,, connected to Ov.) T.= | Ta= Parameter 25C | Tato Tye | Units Test Conditions/Comments Output Settling Time 7 7 ys max To 0.006% FSR. Vour loaded. Varr- =0V. 9 9 pS max To 0.003% FSR. Voyr loaded. Varp = 5V. Digital-to-Analog Glitch 400 400 nV-secs typ DAC alternately loaded with 10 . . . 0000 and 01... 1111. Impulse Vour unloaded. AC Feedthrough os | 05 mV pk-pk typ | Vagr-=O0V; Var, =1V rms, 10kHz sine wave. DAC loaded with all 0s. Digital Feedthrough 10 10 nV-secs typ DAC alternately loaded with all 1s and all 0s. TS High. Output Noise Voltage 50 50 nV//Fz typ Measured at Voy. DAC loaded with 0111011... 11. Density (1kHz-100kHz) Vanr+=Vrer-=0V. TIMING CHARACTERISTICS .,.=+14.25v to +15.75, jg=14.25 to 15.75V, Voc=-+475V to +5.25V,) Limit at Limit at T,=6 to +70C Limit at Parameter T,2=25C T,=25C to +85C Tyz=5S8C to +125C Units Test Conditions/Comments u 40 40 so ns min R/W to CS Setup Time b 150 160 190 ns min CS Pulse Width (Write Cycle) t, 40 40 50 ns min R/W to CS Hold Time te 110 110 120 ns min Data Setup Time t, 0 0 0 ns min Data Hold Time ty 230 270 320 ns max Data Access Time t, 10 10 10 ps min Bus Relinquish Time 80 90 90 ns max ts 20 20 20 ns min CLR Setup Time 4 150 150 150 ns min CLR Pulse Width bio 0 0 0 ns min CLR Hold Time t, 80. 100 100 ns min LDAC Pulse Width ti 240 280 330 ns min CS Pulse Width (Read Cycle) NOTES Timing tested at 25C to ensure compliance. All input control signals are specified with t, = tp = 5 nos specifications are (10% to 90% of +5V) and timed from a voltage level of 1.6V. 2c, is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V. 3t, is defined as the time required for an output to change 0.5V when loaded with the circuits of Figure 2. Specifications subject to change without notice. oBNn DGND L a. High Z to Vow Sv aki! 100pF L DGND b. High Z to Vo, Figure 1. Load Circuits for Access Time (tg) OBN OGND L a. Voy to High Z sv Bhar 10pF L DGND B. Vo, to High Z ! t, | ty | t, ty | 1 | l po *+ poor ts | DATA VALID aa 1! kts | sv ov \ 5v ov t Po (ean) % olen te | Sv ov sv I ly ov LoAC Figure 3. AD7846 Timing Diagram Figure 2. Load Circuits for Bus Relinquish Time (t,} REV. B DIGITAL-TO-ANALOG CONVERTERS 3-219AD7846 ABSOLUTE MAXIMUM RATINGS Vpp to DGND ... 0. eee eee 79. 3V c or +17V Voc to DGND? ran -0.3V, Vpp +0.3V or +7V mhicheres Is Lower) Veg tO DGND 0. ees .+0.3V to -17V Varr+ tODGND. 1.1... eee +25V Vrarp_ to DGND........... Lee eee eee +25V Vour to DGND?.. 6... ee eee ace nee +25V Ry to DGND 2.0... eee eee +25V Digital Input Voltage to DGND ....... -0.3V to Voc +0.3V Digital Output Voltage to DGND..... +7-0.3V to Veg +0.3V Power Dissipation (Any Package) To +78 wi. ee eee Lee eee eee 1000mW Derates above +75C 2... ee ee ee 1omW/C ORDERING GUIDE Temperature Relative Package Model Range Accuracy | Option* AD7846JN OC to +70C +16 LSB | N-28 AD7846KN OC to +70C +8 LSB | N-28 AD7846JP OC to +70C +16 LSB | P-28A AD7846KP OC to +70C +8 LSB | P-28A AD7846AQ ~28C to +85C =| +16 LSB | Q-28 AD7846BQ 25C to +85C | +8 LSB | Q-28 AD7846SQ/883B | 55C to +125C | +16 LSB | Q-28 AD7846SE/883B | -55C to +125C | +16 LSB | E-28A *Q = Ceramic DIP; E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier. For outline information see Package Information section. CAUTION Operating Temperature Range J, K Versions 20.0 ee ce eee 0 to +79C A, B Versions......... Lea Sean 25C to +85C S Version... 0... eee ee ees 55C to +125C Storage Temperature Range ............- -65C to +150C Lead Temperature (Soldering) ............ eee 300C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. Expo- sure to absolute maximum rating conditions for extended periods of time may affect device reliability. Only one Absolute Maximum Rating may be applied at any one time. Voc must not exceed Vpp by more than 0.3V. If it is possible for this to happen during power supply sequencing, the following diode protection scheme will ensure protection. Voo Voc f y IN4148 HPs0e2-2811 im a7 Yoo Voc AD7846 *Vour may be shorted to DGND, Vpp, Vss; Voc provided that the power dissipation of the package is not xceeded. ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electro- static fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed. VU Ten PIN CONFIGURATIONS DIP LCCC - DBz C4 e a6] 083 OBI (] 27] Dea oso [3] 20] pes Veo ica [zs] iat Vouy 5 Vour [5 | [24] con Rw 6 [5] [ea] oe Vues 7 Var. [7] AD7846 22] aw Ver 8 TOP VIEW Veer Le] (norte Seeley [zi Vee Ves 9 (Not to Scale) ve [o] 2a] oN DB15 10 Dats | to 19} OBS OB14 11 OB Ey] 10] O87 pais [12 [17] pee 1213-14 15 16 17 18 0812 La] Dts a 5 5 & 3 8 5 peIt bs] 15 | Date 3-220 DIGITAL-TO-ANALOG CONVERTERS TOP VIEW {Not to Scale) REV. B