LM48822, LM48822TLEVAL
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SNAS456C –MAY 2008–REVISED MAY 2013
LM48822 Boomer ™ Ground-Referenced, Ultra High PSRR, Ultra Low Noise,
35mW/Channel Stereo Headphone Amplifier with Common Mode Sense, and I
2
C Volume
Control
Check for Samples: LM48822,LM48822TLEVAL
1FEATURES DESCRIPTION
The LM48822 is a single supply, ground-referenced
23• Ground Referenced Outputs – Eliminates stereo headphone amplifier designed for portable
Output Coupling Capacitors devices, such as cell phones, where board space is
• Common-Mode Sense at a premium. The LM48822 features TI’s ground-
• Ultra-High PSRR referenced architecture, which eliminates the large
DC blocking capacitor required by traditional
• I2C Volume and Mode Control headphone amplifiers, saving board space and
• High Output Impedance in Shutdown minimizing system cost.
• Differential Inputs The LM48822 features common-mode sensing that
• Advanced Click-and-Pop Suppression corrects for any differences between the amplifier
• Low Supply Current ground and the potential at the headphone return
terminal, minimizing noise created by any ground
• Minimum External Components mismatches.
• Micro-Power Shutdown The LM48822 delivers 35mW/channel into a 16Ω
• Available in Space-Saving 16-Bump DSBGA load with <1% THD+N with a 3.6V supply. High
Package power supply rejection ratio (PSRR), of 110dB at
217Hz, allows the device to operate in noisy
APPLICATIONS environments without additional power supply
conditioning. Flexible power supply requirements
• Mobile Phones allow operation from 2.4V to 5.5V. The LM48822 has
• PDAs a differential inputs for improved noise rejection. High
• Notebook PCs output impedance in Shutdown mode, combined with
a charge pump-only mode allows the LM48822's
• Portable Electronic Devices outputs to be driven by an external source without
• MP3 Players degrading the source signal. Additionally, the
LM48822 features a 64-step I2C volume control and
KEY SPECIFICATIONS mute function. The low power Shutdown mode
• Output Power/Channel at VDD = 3.6V reduces supply current consumption to 0.06µA.
– RL= 16Ω, THD+N ≤1%: 35mW (typ) Superior click and pop suppression eliminates audible
transients on power-up/down and during shutdown.
• Output Power/Channel at VDD = 3.6V The LM48822 is available in an ultra-small 16-bump
– RL= 32Ω, THD+N ≤1%: 40mW (typ) DSBGA package (2mmx2mm).
• Quiescent Power Supply Current at 3.6V:
3.5mA (typ)
• PSRR at 217Hz: 110dB (typ)
• Shutdown Current: 0.06μA (typ)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2is a trademark of ~ Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
VOLUME
CONTROL AND
MIXER
I2C
INTERFACE
BIASING
VOLUME
CONTROL AND
MIXER
CHARGE PUMP
INL+
INL-
SDA
SCL
INR+
INR-
C1P C1N CPVSS CPGND
VDD
OUTL
OUTR
COM
GND
+2.4V to +5.5V
CS
CIN
CIN
CIN
CIN
C1
C2
BIAS
CBIAS
LM48822, LM48822TLEVAL
SNAS456C –MAY 2008–REVISED MAY 2013
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Typical Application
Figure 1. Typical Audio Amplifier Application Circuit
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3
2
1
AB C D
4
CPVSS GND SCLC1P
OUTL BIAS OUTRC1N
INL+ INR+ SDACPGND
INL- INR- COM
VDD
LM48822, LM48822TLEVAL
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SNAS456C –MAY 2008–REVISED MAY 2013
Connection Diagram
Top View
Figure 2. DSBGA Package
2mm x 2mm x 0.8mm
See Package Number YZR001611A
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)(3)
Supply Voltage(1) 6V
Storage Temperature −65°C to +150°C
Input Voltage -0.3V to VDD + 0.3V
Power Dissipation(4) Internally Limited
ESD Rating(5) 2000V
ESD Rating(6) 150V
Junction Temperature 150°C
Thermal Resistance
θJA YZR001611A 63°C/W
Soldering Information See AN-1112 “DSBGA Wafer Level Chip Scale package”
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum
RatingsRatings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The
Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond
such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) Maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is
lower.
(5) Human body model, applicable std. JESD22-A114C.
(6) Machine model, applicable std. JESD22-A115-A.
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Operating Ratings
Temperature Range
TMIN ≤TA≤TMAX −40°C ≤TA≤+85°C
Supply Voltage (VDD) 2.4V ≤VDD ≤5.5V
Electrical Characteristics VDD = 3.6V(1)(2)
The following specifications apply for AV= 0dB, RL= 16Ω, f = 1kHz, unless otherwise specified. Limits apply to TA= 25°C.
LM48822 Units
Parameter Test Conditions (Limits)
Typ(3) Limit(4)
VIN = 0V, both channels active
IDD Quiescent Power Supply Current RL= 16Ω3.5 4.5 mA (max)
RL=∞3.5 4.5 mA (max)
ISD Shutdown Current Shutdown Enabled 0.06 1.2 µA (max)
VOS Differential Output Offset Voltage VIN = 0V, RL= 16Ω1 5 mV (max)
TWU Wake Up Time 200 μs
+0.5 dB (max)
Minimum Gain Setting –59.5 –0.5 dB (min)
AVVoltage Gain +0.5 dB (max)
Maximum Gain Setting 3.8 –0.5 dB (min)
AV= 4dB 25 30 kΩ(max)
RIN Input Resistance AV= –60dB 60 70 kΩ(max)
RL= 16Ω, f = 1kHz, THD+N = 1%
Single channel 70 mW
Two channels in phase 35 27 mW (min)
POOutput Power RL= 32Ω, f = 1kHz, THD+N = 1%
Single channel 65 mW
Two channels in phase 40 mW
PO= 50mW, f = 1kHz, RL= 16Ω0.04 %
single channel
THD+N Total Harmonic Distortion + Noise PO= 40mW, f = 1kHz, RL= 32Ω0.02 %
single channel
VRIPPLE = 200mVP-P, Inputs AC GND
PSRR Power Supply Rejection Ratio CIN = 1μF, input referred, SD_BIAS = 0
fRIPPLE = 217Hz 110 100 dB (min)
fRIPPLE = 1kHz 100 dB
CMRR Common Mode Rejection Ratio VRIPPLE = 1VP-P 95 dB
RL≥16Ω, POUT = 1.6mW, f = 1kHz 80 70 dB (min)
XTALK Crosstalk RL≥10kΩ, VOUT = 1VRMS, f = 1kHz 95 85 dB (min)
SNR Signal-to-Noise Ratio RL= 16Ω, f = 1kHz 100 dB
AV= 4dB, Input referred
∈OS Output Noise 7 μV
A-Weighted Filter
ROUT Output Impedance Charge pump-only mode enabled 40 25 kΩ(min)
Voltage applied to amplifier outputs in
VOUT Maximum Voltage Swing 2 VRMS (min)
charge pump-only mode
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum
RatingsRatings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The
Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond
such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA= +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not specified.
(4) Datasheet min/max specification limits are ensured by test or statistical analysis.
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I2C Interface Characteristics VDD = 3.6V(1)(2)
The following specifications apply for AV= 0dB, RL= 16Ω, f = 1kHz, unless otherwise specified. Limits apply to TA= 25°C.
LM48822 Units
Parameter Test Conditions (Limits)
Typ(3) Limit(4)
t1SCL Period 2.5 μs (min)
t2SDA Setup Time 100 ns (min)
t3SDA Stable Time 0 ns (min)
t4Start Condition Time 100 ns (min)
t5Stop Condition Time 100 ns (min)
VIH Input High Voltage 1.3 V (min)
VIL Input Low Voltage 0.4 V (max)
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum
RatingsRatings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The
Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond
such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms at TA= +25ºC, and at the Recommended Operation Conditions at the time of
product characterization and are not specified.
(4) Datasheet min/max specification limits are ensured by test or statistical analysis.
Bump Descriptions
Pin Name Function
A1 C1N Charge Pump Flying Capacitor Negative Terminal
A2 C1P Charge Pump Flying Capacitor Positive Terminal
A3 CPGND Charge Pump Ground
A4 VDD Power Supply
B1 OUTL Left Channel Output
B2 CPVSS Charge Pump Output
B3 INL+ Left Channel Non-Inverting Input
B4 INL- Left Channel Inverting Input
C1 BIAS Bias Voltage Bypass
C2 GND Ground
C3 INR+ Right Channel Non-Inverting Input
C4 INR- Right Channel Inverting Input
D1 OUTR Right Channel Output
D2 SCL I2C Serial Clock Input
D3 SDA I2C Serial Data Input
D4 COM Common-Mode Sense Input
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0.001
0.01
0.1
1
10
100
10 100 1000 10000 100000
FREQUENCY (Hz)
THD+N (%)
0.001
0.01
0.1
1
10
100
10 100 1000 10000 100000
FREQUENCY (Hz)
THD+N (%)
0.001
0.01
0.1
1
10
100
10 100 1000 10000 100000
FREQUENCY (Hz)
THD+N (%)
0.001
0.01
0.1
1
10
100
10 100 1000 10000 100000
FREQUENCY (Hz)
THD+N (%)
100
0.001
0.01
0.1
1
10
10 100 1000 10000 100000
FREQUENCY (Hz)
THD+N (%)
0.001
0.01
0.1
1
10
100
10 100 1000 10000 100000
FREQUENCY (Hz)
THD+N (%)
LM48822, LM48822TLEVAL
SNAS456C –MAY 2008–REVISED MAY 2013
www.ti.com
Typical Performance Characteristics
THD+N vs Frequency THD+N vs Frequency
VDD = 2.5V, POUT = 10mW, RL= 32ΩVDD = 2.5V, POUT = 12mW, RL= 16Ω
Figure 3. Figure 4.
THD+N vs Frequency THD+N vs Frequency
VDD = 3.6V, POUT = 20mW, RL= 16ΩVDD = 3.6V, POUT = 30mW, RL= 32Ω
Figure 5. Figure 6.
THD+N vs Frequency THD+N vs Frequency
VDD = 5.0V, POUT = 20mW, RL= 16ΩVDD = 5.0V, POUT = 30mW, RL= 32Ω
Figure 7. Figure 8.
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0
50
100
150
200
250
300
0 25 50 75 100
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
VDD = 5V
VDD = 3.6V
VDD = 2.5V
POUT = POUTL + POUTR
0.01
0.1
1
10
100
0.001 0.01 0.1
OUTPUT POWER (W)
THD+N (%)
TWO CHANNELS
IN PHASE
HPVDD = 2.55V
HPVDD = 2.0V
0
50
100
150
200
250
300
350
400
450
0 25 50 75 100
OUTPUT POWER (mW)
POWER DISSIPATION (mW)
VDD = 5V
VDD = 3.6V
VDD = 2.5V
POUT = POUTL + POUTR
0.01
0.1
1
10
100
0.1 1 10 100
OUTPUT POWER (mW)
THD+N (%)
VDD = 5V
VDD = 3.6V
VDD = 2.5V
0.01
0.1
1
10
100
0.1 1 10 100
OUTPUT POWER (mW)
THD+N (%)
VDD = 5V
VDD = 3.6V
VDD = 2.5V
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SNAS456C –MAY 2008–REVISED MAY 2013
Typical Performance Characteristics (continued)
THD+N vs Output Power THD+N vs Output Power
AV= 0dB, RL= 16Ω, f = 1kHz AV= 0dB, RL= 32Ω, f = 1kHz
Both Outputs in Phase Both Outputs in Phase
Figure 9. Figure 10.
THD+N vs Output Power
AV= 9dB, RL= 16Ω, f = 1kHz Power Dissipation vs Output Power
Both Outputs in Phase RL= 16Ω, f = 1kHz
Figure 11. Figure 12.
Power Dissipation vs Output Power Output Power vs Supply Voltage
RL= 32Ω, f = 1kHz RL= 16Ω, f = 1kHz
Figure 13. Figure 14.
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0
1
2
3
4
5
6
7
8
2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1000 10000 100000
FREQUENCY (Hz)
NOISE REJECTION (dB)
-120
-100
-80
-60
-40
-20
0
10 100 1000 10000 100000
FREQUENCY (Hz)
PSRR (dB)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1000 10000 100000
FREQUENCY (Hz)
CROSSTALK (dB)
0
10
20
30
40
50
60
70
80
2.5 3 3.5 4 4.5 5 5.5
SUPPLY VOLTAGE (V)
OUTPUT POWER (mW)
THD+N = 1%
THD+N = 10%
-80
-70
-60
-50
-40
-30
-20
-10
0
10 100 1000 10000 100000
FREQUENCY (Hz)
CMRR(dB)
LM48822, LM48822TLEVAL
SNAS456C –MAY 2008–REVISED MAY 2013
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Typical Performance Characteristics (continued)
Output Power vs Supply Voltage CMRR vs Frequency
RL= 32Ω, f = 1kHz VDD = 3.6V, VCM = 1VP-P, RL= 32Ω
Figure 15. Figure 16.
PSRR vs Frequency Crosstalk vs Frequency
VDD = 3.6V, VRIPPLE = 20mVP-P, RL= 32ΩVDD = 3.6V, VRIPPLE = 1VP-P, RL= 32Ω
Figure 17. Figure 18.
Ground Noise vs Frequency Supply Current vs Supply Voltage
VDD = 3.6V, VRIPPLE = 20mVP-P, RL= 32ΩNo Load
Figure 19. Figure 20.
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SDA
SCL SP
START condition STOP condition
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APPLICATION INFORMATION
I2C COMPATIBLE INTERFACE
The LM48822 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and
a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open collector). The LM48822
and the master can communicate at clock rates up to 400kHz. Figure 21 shows the I2C interface timing diagram.
Data on the SDA line must be stable during the HIGH period of SCL. The LM48822 is a transmit/receive slave-
only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a
START condition and a STOP condition Figure 22. Each data word, device address and data, transmitted over
the bus is 8 bits long as is always followed by an acknowledge pulse (Figure 23). The LM48822 device address
is 1100000.
I2C BUS FORMAT
The I2C bus format is shown in Figure 23. The START signal, the transition of SDA from HIGH to LOW while
SDA is HIGH, is generated, altering all devices on the bus that a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0
indicates the master is writing to the slave device, R/W = 1 indicates the master wants to read data from the
slave device. The LM48822 is a WRITE-ONLY device and will not respond the R/W = 1. The data is latched in
on the rising edge of the clock. Each address bit must be stable while SDA is HIGH. After the last address bit is
transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is generated by the
slave device. If the LM48822 receives the correct address, the device pulls the SDA line low, generating and
acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable
while SCL is HIGH. After the 8-bit register data word is sent, the LM48822 sends another ACK bit. Following the
acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SDA is
high.
Figure 21. I2C Timing Diagram
Figure 22. Start and Stop Diagram
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START MSB DEVICE ADDRESS LSB ACK
SCL
SDA STOPMSB REGISTER DATA LSB ACK
R/W
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Figure 23. Example I2C Write Cycle
Table 1. Device Address
B7 B6 B5 B4 B3 B2 B1 B0 (R/W)
Device 1 1 0 0 0 0 0 0
Address
Table 2. I2C Control Registers
Register Register B7 B6 B5 B4 B3 B2 B1 B0
Address Name
MODE MUTE_ MUTE_
0 0 SDL SD_BIAS CP_ONLY 0 SDR
CONTROL LEFT RIGHT
VOLUME
1 1 SHDN VOL5 VOL4 VOL3 VOL2 VOL1 VOL0
CONTROL
Table 3. Mode Control Register
Bit Name Value Description
0 Left channel enabled
B6 SDL 1 Left channel disabled
0 Bias enabled
B5 SD_BIAS 1 Bias disabled
0 Normal operation
B4 CP_ONLY 1 Charge-pump only mode. Amplifiers and Bias disabled.
B3 UNUSED 0 Set B3 to 0
0 Left channel Normal Operation
B2 MUTE_LEFT 1 Left channel Mute
0 Right channel enabled
B1 SDR Right channel disabled. Right channel audio inputs summed with
1left channel audio inputs and routed to OUTL
0 Right channel Normal Operation
B0 MUTE_RIGHT 1 Right channel Mute
GENERAL AMPLIFIER FUNCTION
The LM48822 headphone amplifier feature TI’s ground referenced architecture that eliminates the large DC-
blocking capacitors required at the outputs of traditional headphone amplifiers. A low-noise inverting charge
pump creates a negative supply (CPVSS) from the positive supply voltage (VDD). The headphone amplifiers
operate from these bipolar supplies, with the amplifier outputs biased about GND, instead of a nominal DC
voltage (typically VDD/2), like traditional amplifiers. Because there is no DC component to the headphone output
signals, the large DC-blocking capacitors (typically 220μF) are not necessary, conserving board space and
system cost, while improving frequency response.
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CHARGE PUMP
C1P C1N CPVSS
C1
C2
VDD
VSS
HI-Z
INCOMING AUDIO
SIGNAL
OUT_
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GENERAL AMPLIFIER EXPLANATION
The LM48822 features a differential input stage, which offers improved noise rejection compared to a single-
ended input amplifier. Because a differential input amplifier amplifies the difference between the two input
signals, any component common to both signals is cancelled. An additional benefit of the differential input
structure is the possible elimination of the DC input blocking capacitors. Since the DC component is common to
both inputs, and thus cancelled by the amplifier, the LM48822 can be used without input coupling capacitors
when configured with a differential input signal.
CHARGE PUMP ONLY MODE
In applications where the headphone jack is used as both an output and input port, signals such as a microphone
input can appear on the headphone amplifier output. Traditional charge pump headphone amplifiers can clamp
or distort the signals that appear on their output. Without the charge pump active, generating the negative
voltage supply, the internal protection diodes of the amplifier clamp the incoming signal, distorting the negative
half cycle, see Figure 24. The LM48822 charge pump only mode eliminates this problem. In charge pump only
mode, the amplifiers are disabled, while the charge pump remains active. The disabled amplifier outputs present
a high impedance (1MΩ) load to the incoming signal. The charge pump maintains the negative rail, allowing the
incoming signal to swing between VDD and VSS without any interference from the device.
Set bit B4 (CP_ONLY) of the MODE CONTROL register to 1 for charge pump only mode. Setting CP_ONLY = 1
disables both the left and right channels, regardless of the status of the shutdown control bits. Set CP_ONLY = 0
for normal operation.
Figure 24. Back-Driving the LM48822 Outputs
COMMON MODE SENSE
The LM48822 features a ground (common mode) sensing feature. In noisy applications, or where the headphone
jack is used as a line out to other devices, noise pick up and ground imbalance can degrade audio quality. The
LM48822 COM input senses and corrects any noise at the headphone return, or any ground imbalance between
the headphone return and device ground, improving audio reproduction. Connect COM directly to the headphone
return terminal of the headphone jack Figure 25. No additional external components are required. Connect COM
to GND if the common-mode sense feature is not in use.
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AUDIO
INPUT
COM
COMMON MODE SENSE
EQUIVALENT CIRCUIT
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Figure 25. COM Connection Example
VOLUME CONTROL
Table 4. Volume Control Table
VOLUME STEP VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 HP GAIN (dB)
1 0 0 0 0 0 0 –96
2 0 0 0 0 0 1 –60
3 0 0 0 0 1 0 –57
4 0 0 0 0 1 1 –54
5 0 0 0 1 0 0 –51
6 0 0 0 1 0 1 –48
7 0 0 0 1 1 0 –45
8 0 0 0 1 1 1 –42
9 0 0 1 0 0 0 –39
10 0 0 1 0 0 1 –36
11 0 0 1 0 1 0 –34.5
12 0 0 1 0 1 1 –33
13 0 0 1 1 0 0 –31.5
14 0 0 1 1 0 1 –30
15 0 0 1 1 1 0 –28.5
16 0 0 1 1 1 1 –27
17 0 1 0 0 0 0 –25.5
18 0 1 0 0 0 1 –24
19 0 1 0 0 1 0 –22.5
20 0 1 0 0 1 1 –21
21 0 1 0 1 0 0 –19.5
22 0 1 0 1 0 1 –18
23 0 1 0 1 1 0 –16.5
24 0 1 0 1 1 1 –16
25 0 1 1 0 0 0 –15.5
26 0 1 1 0 0 1 –15
27 0 1 1 0 1 0 –14.5
28 0 1 1 0 1 1 –14
29 0 1 1 1 0 0 –13.5
30 0 1 1 1 0 1 –13
31 0 1 1 1 1 0 –12.5
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Table 4. Volume Control Table (continued)
VOLUME STEP VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 HP GAIN (dB)
32 0 1 1 1 1 1 –12
33 1 0 0 0 0 0 –11.5
34 1 0 0 0 0 1 –11
35 1 0 0 0 1 0 –10.5
36 1 0 0 0 1 1 –10
37 1 0 0 1 0 0 –9.5
38 1 0 0 1 0 1 –9
39 1 0 0 1 1 0 –8.5
40 1 0 0 1 1 1 –8
41 1 0 1 0 0 0 –7.5
42 1 0 1 0 0 1 –7
43 1 0 1 0 1 0 –6.5
44 1 0 1 0 1 1 –6
45 1 0 1 1 0 0 –5.5
46 1 0 1 1 0 1 –5
47 1 0 1 1 1 0 –4.5
48 1 0 1 1 1 1 –4
49 1 1 0 0 0 0 –3.5
50 1 1 0 0 0 1 –3
51 1 1 0 0 1 0 –2.5
52 1 1 0 0 1 1 –2
53 1 1 0 1 0 0 –1.5
54 1 1 0 1 0 1 –1
55 1 1 0 1 1 0 –0.5
56 1 1 0 1 1 1 0
57 1 1 1 0 0 0 0.5
58 1 1 1 0 0 1 1
59 1 1 1 0 1 0 1.5
60 1 1 1 0 1 1 2
61 1 1 1 1 0 0 2.5
62 1 1 1 1 0 1 3
63 1 1 1 1 1 0 3.5
64 1 1 1 1 1 1 4
SHUTDOWN FUNCTION
The LM48822 features three shutdown controls. Bits B6 (SDL) and B1 (SDR) of the MODE CONTROL register
control the left and right channels, respectively. Set the control bits to 1 to disable the corresponding channel.
When SDR = 1 and SDL = 0, the right channel is disabled, the right and left inputs are summed and output as a
mono signal on the OUTL. When SDL = 1 and SDR = 0, the left channel is disabled, while only the right input
signal is output on OUTR. Setting both SDL and SDR = 1 disables both channels, while the charge pump
remains active. Bit B6 (SHDN) of the VOLUME CONTROL register is the global shutdown control for the entire
device. Set SHDN = 1 to disable the entire device; both amplifiers and charge pump are disabled. Set SHDN = 0
for normal operation. SHDN = 1 overrides any other shutdown control bit.
MUTE FUNCTION
Set bits B2 (MUTE_LEFT) and B0 (MUTE_RIGHT) of the MODE CONTROL register to 1 to mute the respective
channels. Set MUTE_LEFT and MUTE_RIGHT to 0 for normal operation.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM48822 LM48822TLEVAL
LM48822, LM48822TLEVAL
SNAS456C –MAY 2008–REVISED MAY 2013
www.ti.com
SD_BIAS FUNCTION
The LM48822 BIAS is controlled through the I2C interface. Set bit B5 (SD_BIAS) of the MODE CONTROL
register to 1 to enable the LM48822 BIAS. BIAS provides the voltage for both the amplifiers and the charge
pump. When enabled, VBIAS will track VDD for VDD < 3V. Once VDD exceeds 3V, VBIAS remains fixed at 3V, limiting
the output swing of the device the 6VP-P. Set SD_BIAS = 0 to disable BIAS. Disabling BIAS allows the amplifier
and charge pump to track VDD, increasing output swing; however, a slight degradation in PSSR will occur. Limit
VDD to 4.2V or less when BIAS is disabled.
PROPER SELECTION OF EXTERNAL COMPONENTS
Power Supply Bypassing/Filtering
Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass
capacitors as close to the supply pins as possible. Place a 1μF ceramic capacitors from VDD to GND. Additional
bulk capacitance may be added as required.
Charge Pump Capacitor Selection
Use low ESR ceramic capacitors (less than 100mΩ) for optimum performance.
Charge Pump Flying Capacitor (C1)
The flying capacitor (C1) affects the load regulation and output impedance of the charge pump. A C1 value that
is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C1 improves
load regulation and lowers charge pump output impedance to an extent. Above 2.2μF, the RDS(ON) of the charge
pump switches and the ESR of C1 and C2 dominate the output impedance. A lower value capacitor can be used
in systems with low maximum output power requirements.
Charge Pump Flying Capacitor (C2)
The value and ESR of the hold capacitor (C2) directly affects the ripple on CPVSS. Increasing the value of C2
reduces output ripple. Decreasing the ESR of C2 reduces both output ripple and charge pump output impedance.
A lower value capacitor can be used in systems with low maximum output power requirements.
Input Capacitor Selection
Input capacitors may be required for some applications, or when the audio source is single-ended. Input
capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of
the audio source and the bias voltage of the LM48822. The input capacitors create a high-pass filter with the
input resistors RIN. The -3dB point of the high pass filter is found using Equation 1 below.
f = 1 / 2πRINCIN (Hz) (1)
where:
the value of RIN is given in the Electrical Characteristics Table.
High pass filtering the audio signal helps protect the speakers. When the LM48822 is using a single-ended
source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the
power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not
amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance
matching and improved CMRR and PSRR.
SINGLE-ENDED AUDIO AMPLIFIER CONFIGURATION
The LM48822 is compatible with single-ended sources. Figure 26 shows the typical single-ended applications
circuit.
14 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM48822 LM48822TLEVAL
VOLUME
CONTROL AND
MIXER
IN_+
IN_-
OUT_
CIN
CIN
LM48822, LM48822TLEVAL
www.ti.com
SNAS456C –MAY 2008–REVISED MAY 2013
Figure 26. Single-Ended Input Configuration
PCB LAYOUT CONFIGURATION
Minimize trace impedance of the power, ground and all output traces for optimum performance. Voltage loss due
to trace resistance between the LM48822 and the load results in decreased output power and efficiency. Trace
resistance between the power supply and ground has the same effect as a poorly regulated supply, increased
ripple and reduced peak output power. Use wide traces for power supply inputs and amplifier outputs to minimize
losses due to trace resistance, as well as route heat away from the device. Proper grounding improves audio
performance, minimizes crosstalk between channels and prevents switching noise from interfering with the audio
signal. Use of power and ground planes is recommended.
Place all digital components and route digital signal traces as far as possible from analog components and
traces. Do not run digital and analog traces in parallel on the same PCB layer. If digital and analog signal lines
must cross either over or under each other, ensure that they cross in a perpendicular fashion.
LM48822TL Demoboard of Materials
Table 5. LM48822TL Demoboard Bill of Materials
Designator Quantity Description
10µF ±10% 16V 500ΩTantalum Capacitor (B Case) AVX
C1 1 TPSB106K016R0500
1μF ±10% 16V X5R Ceramic Capacitor (603) Panasonic
C2 1 ECJ-1VB1C105K
2.2μF ±10% 10V X5R Ceramic Capacitor (603) Panasonic
C3, C8, C9 3 ECJ-1VB1A225K
1μF ±10% 16V X7R Ceramic Capacitor (1206) Panasonic
C4 — C7 4 ECJ-3YB1C105K
5kΩ±5% 1/10W Thick Film Resistor (603) Vishay
R1, R2 2 CRCW06035R1KJNEA
J1 1 Stereo Headphone Jack
J2 1 16-Pin Boardmount Socket 3M 8516-4500JL
JU1 1 3 Pin Header
JU2 1 2 Pin Header
LM4822TL 1 LM48822TL (16-Bump DSBGA)
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM48822 LM48822TLEVAL
OUTL
MOUNTING
SUPPORT
JU2
J2
SCL
SDA
R2
5k
R1
5k
2
4
6
8
10
12
14
16
1
3
5
7
9
11
13
15
VDD
SCL
SDA
INL+ 1 PF
INL+
B3
C4
INL- 1 PF
INL-
B4
C5
INR+ 1 PF
INR+
C3
C6
INR- 1 PF
INR-
C4
C7
VDD
VDD
A4
GND
GND
C2
VDD OUTL
OUTR
J1
HPGND
COM
HEADPHONE_JACK
JU1 1
3
2
GND
1
R
4
CRT
3
A1
5
L
2
U1
C9
2.2 PF
C8
2.2 PF
GND
A3
B2
A1
A2
D4
D1
B1
OUTR
COM
C1P
C1N
CPVSS
CPGND
C2
1 PF
C1
10 PF
C3
2.2 PF
BIAS
C1
SCL
D2
SDA
D3
LM48822TL
LM48822, LM48822TLEVAL
SNAS456C –MAY 2008–REVISED MAY 2013
www.ti.com
Demoboard Schematic
Figure 27. LM48822 Demoboard Schematic
Demonstration Board PCB Layout
Figure 28. Solder Mask Figure 29. Top Silkscreen
16 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM48822 LM48822TLEVAL
LM48822, LM48822TLEVAL
www.ti.com
SNAS456C –MAY 2008–REVISED MAY 2013
Figure 30. Top Layer Figure 31. Layer 2 (GND)
Figure 32. Layer 3 (VDD) Figure 33. Bottom Layer
Figure 34. Bottom Silkscreen
Revision History
Rev Date Description
0.1 04/15/08 Initial PDF.
0.2 04/23/08 Added the demo boards and schematic.
0.3 04/30/08 Text edits.
0.4 07/10/08 Text edits.
0.5 03/09/11 Changed the bit B7 into B6 under the SHUTDOWN FUNCTION section.
C 05/02/2013 Changed layout of National Data Sheet to TI format.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM48822 LM48822TLEVAL
PACKAGE OPTION ADDENDUM
www.ti.com 2-May-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LM48822TL/NOPB ACTIVE DSBGA YZR 16 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 GK1
LM48822TLX/NOPB ACTIVE DSBGA YZR 16 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 GK1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM48822TL/NOPB DSBGA YZR 16 250 178.0 8.4 2.08 2.08 0.76 4.0 8.0 Q1
LM48822TLX/NOPB DSBGA YZR 16 3000 178.0 8.4 2.08 2.08 0.76 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM48822TL/NOPB DSBGA YZR 16 250 210.0 185.0 35.0
LM48822TLX/NOPB DSBGA YZR 16 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 2
MECHANICAL DATA
YZR0016xxx
www.ti.com
TLA16XXX (Rev C)
0.600±0.075 D
E
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
4215051/A 12/12
D: Max =
E: Max =
1.99 mm, Min =
1.99 mm, Min =
1.93 mm
1.93 mm
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