CPC7583 Line Card Access Switch Features Description * Small 28-pin SOIC or micro-leadframe (MLP) package * MLP version provides 65% PCB area reduction over 4th generation EMRs, and 60% smaller footprint than SOIC version * Monolithic IC reliability * Low, matched, RON * Eliminates the need for zero-cross switching * Flexible switch timing for transition from ringing mode to talk mode. * Clean, bounce-free switching * Tertiary protection consisting of integrated current limiting and thermal shutdown for SLIC protection * 5 V operation with power consumption < 10.5 mW * Intelligent battery monitor * Latched logic-level inputs, no external drive circuitry required * SOIC version pin-compatible with Agere 7583 family The CPC7583 is a monolithic 10-pole line card access switch in a 28-pin SOIC or MLP package. It provides the necessary functions to replace three 2-Form-C electromechanical relays on analog line cards and combined voice and data line cards found in central office, access, and PBX equipment. The device contains solid state switches for tip and ring line break, ringing injection/ringing return, and test access. The CPC7583 requires only a +5 V supply and offers break-before-make or make-before-break switch operation using simple logic-level input control. Specify CPC7583Bx for SOIC package in tubes, CPC7583Mx for MLP package in tubes. Add -TR to the part number for tape and reel packaging. Part Number Applications * * * * * * * * Ordering Information CPC7583xA CPC7583xB CPC7583xC Central office (CO) Digital Loop Carrier (DLC) PBX Systems Digitally Added Main Line (DAML) Hybrid Fiber Coax (HFC) Fiber in the Loop (FITL) Pair Gain System Channel Banks Description With protection SCR Without protection SCR With extra logic state and protection SCR With extra logic state but without protection SCR CPC7583xD TTESTIN (TCHANTEST) +5 Vdc VDD TRING TTESTOUT (TDROPTEST) 10 12 5 8 SW7 SW5 Tip TLINE 7 X X SW9 XSW3 X 6 TBAT X SW1 Secondary Protection Ring CPC7583 23 RBAT SW2 RLINE 22 SW6 X X SW4 X X SCR and Trip Circuit SW10 SW8 X RTESTOUT 19 20 (RDROPTEST) RINGING SLIC 300 24 (min.) VREF Switch Control Logic 1 28 14 13 FGND VBAT DGND L A T C H 17 16 15 18 INTESTIN INRINGING INTESTOUT LATCH TSD VBAT RTESTIN DS-CPC7583-R2.0 9/16/2002 www.clare.com 1 CPC7583 1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Pinout Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Absolute Maximum Ratings (at 25 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 Electrical Characteristics, TA = -40 C to +85 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4.1 Power Supply Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4.2 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4.3 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4.4 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4.5 TESTOUT Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4.6 Ringing Test Return Switch, SW7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4.7 Ringing Test Switch, SW8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4.8 Test In Switches, SW9 and SW10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 Additional Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.7 Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.7.1 Truth Table for CPC7583xA and CPC7583xB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.7.2 Truth Table for CPC7583xC and CPC7583xD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Make-Before-Break Operation (Ringing to Idle/Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Break-Before-Make Operation (Ringing to Idle/Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Alternate Break-Before-Make Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 TSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.10 Temperature Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.11 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 13 13 13 13 14 14 14 14 14 14 14 15 15 3 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 MLP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 SOIC Tape Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 15 16 16 16 16 17 2 www.clare.com R2.0 9/16/2002 CPC7583 1. Specifications 1.1 Package Pinout 1.2 Pinout Description CPC7583 FGND 1 28 VBAT NC 2 27 NC NC 3 26 NC NC 4 25 NC TTESTin 5 24 RTESTin TBAT 6 23 RBAT TLINE 7 22 RLINE TRINGING 8 NC 9 21 NC 20 RRINGING TTESTout 10 19 RTESTout NC 11 18 LATCH VDD 12 17 IN TESTin TSD 13 16 INRINGING DGND 14 Rev. 2.0 9/16/2002 Pin Name Description 1 FGND 2 NC No connection 3 NC No connection Fault ground 4 NC 5 TTESTin 6 TBAT Connect to tip on SLIC side 7 TLINE Connect to tip on line side 8 9 10 No connection Connect to TESTIN bus tip lead TRINGING Connect to ringing generator return NC Not connected TTESTout Connect to TESTOUT bus tip lead 11 NC No connection 12 VDD +5 V supply 13 TSD Temperature shutdown pin. Bi-directional I/O with internal pullup to VDD. Output function indicates status of thermal shutdown circuitry. Input function can be used to set the `all off' mode using an open-drain type output. 14 DGND 15 INTESTout Digital ground 15 INTESTout Logic-level switch control input 16 INRINGING Logic-level switch control input 17 INTESTin Logic-level switch control input 18 LATCH 19 RTESTout Connect to TESTOUT bus ring lead 20 RRINGING 21 NC 22 RLINE Connect to ring on the line side 23 RBAT Connect to ring on the SLIC side 24 RTESTin Connect to TESTIN bus ring lead 25 NC No connection 26 NC No connection 27 NC No connection 28 VBAT Battery voltage supply. Must be capable of sourcing the trigger current for proper operation of the SCR. www.clare.com Data latch control, active high, transparent low Connect to ringing generator current limiting resistor No connection 3 CPC7583 1.3 Absolute Maximum Ratings (at 25 C) Parameter Minimum Maximum Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and affect its reliability. Unit Operating temperature -40 +110 C Storage temperature -40 +150 C Operating relative humidity 5 95 % Pin soldering temperature (10 seconds max) - +260 C +5 V power supply - 7 V Battery Supply - -85 V Logic input voltage - 7 V VDD +4.5 +5.0 +5.5 V Logic input to switch output isolation - 330 V VBAT1 -19 - -72 V Switch open contact isolation (SW1, SW2, SW3, SW5, SW6, SW7, SW9, SW10) - 330 V Switch open contact isolation (SW4)* - 480 V Switch open contact isolation (SW8)* - 235 V 1.4.1 Power Supply Specifications Supply Minimum Typical Maximum Unit 1 VBAT is used only for internal protection circuitry. If VBAT rises above -10 V, the device will enter the all-off state and will remain in the all-off state until the battery drops below -15 V. ESD Rating (Human Body Model) 1000 V *Ringing supply side of switch limited to 210 V with respect to ground 1.4 Electrical Characteristics, TA = -40 C to +85 C Unless otherwise specified, minimum and maximum values are production testing requirements. Typical values are characteristic of the device and are the result of engineering evaluations. Typical values are provided for information purposes only and are not part of the testing requirements. 1.4.2 Break Switches, SW1 and SW2 Parameter Test Conditions Symbol Minimum Typical Maximum Unit 1 A Off-state leakage current +25 C VSW (differential) = -320 V to gnd VSW (differential) = +260 V to -60 V +85 C VSW (differential) = -330 V to gnd VSW (differential) = +270 V to -60 V -40 C VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V 0.1 ISW - 0.3 0.1 RON +25 C +85 C -40 C RON match 4 TLINE and RLINE = 10 mA, 40 mA, RBAT and TBAT = -2 V Per on-resistance test condition of SW1, SW2 RON Magnitude RON SW1RON SW2 www.clare.com - 14.5 - 20.5 28 10.5 - 0.15 0.8 Rev. 2.0 9/16/2002 CPC7583 Parameter Test Conditions Symbol Minimum Typical Maximum Unit DC current limit - 225 80 150 - 400 425 - 2.5 - A - 0.1 - 0.3 1 A - 0.1 - - 200 - V/s Symbol Minimum Typical Maximum Unit 1 A +25 C +85 C VSW (on) = 10 V -40 C Dynamic current limit (t = <0.5 s) Break switches in on state, ringing switches off, apply 1 kV at 10/1000 s pulse, with appropriate secondary protection in place. - mA ISW Logic input to switch output isolation +25 C VSW (TLINE, RLINE) = 320 V, logic inputs = gnd +85 C VSW (TLINE, RLINE) = 330 V, logic inputs = gnd -40 C VSW (TLINE, RLINE) = 310 V, logic inputs = gnd dv/dt sensitivity - ISW 1.4.3 Ringing Return Switch, SW3 Parameter Test Conditions Off-state leakage current +25 C VSW (differential) = -320 V to gnd VSW (differential) = +260 V to -60 V +85 C VSW (differential) = -330 V to gnd VSW (differential) = +270 V to -60 V -40 C VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V 0.1 ISW - 0.3 0.1 RON +25 C +85 C TLINE = 0 mA, 10 mA RON - -40 C 60 - 85 100 45 - DC current limit +25 C +85 C VSW (on) = 10 V 70 -40 C Dynamic current limit (t = <0.5 s) 120 85 mA 210 Break switches in on state, ringing switches off, apply 1 kV at 10/1000 s pulse, with appropriate secondary protection in place. ISW - 2.5 A Logic input to switch output isolation +25 C VSW (TRING, TLINE) = 320 V, logic inputs = gnd +85 C VSW (TRING, TLINE) = 330 V, logic inputs = gnd -40 C VSW (TRING, TLINE) = 310 V, logic inputs = gnd Rev. 2.0 9/16/2002 0.1 ISW - 0.3 1 A 0.1 www.clare.com 5 CPC7583 Parameter dv/dt sensitivity Test Conditions - Symbol Minimum Typical Maximum Unit - - 200 - V/s Symbol Minimum Typical Maximum Unit 0.05 1 0.1 1 0.05 1 1.5 3 V IRINGING 0.1 0.25 mA ISW - 150 mA - - 2 A - 450 - A RON 10 15 1 A 200 - V/s Typical Maximum Unit 1 A 1.4.4 Ringing Switch, SW4 Parameter Test Conditions Off-state leakage current +25 C VSW (differential) = -255 V to +210 V VSW (differential) = +255 V to -210 V +85 C VSW (differential) = -270 V to +210 V VSW (differential) = +270 V to -210 V -40 C VSW (differential) = -245 V to +210 V VSW (differential) = +245 V to -210 V On Voltage ISW (on) = 1 mA Ringing generator current to ground during ringing VCC = 5 V, inputs set for ringing mode - On steady-state current* Inputs set for ringing mode Surge current* - Release current - RON ISW (on) = 70 mA, 80 mA ISW - A Logic input to switch output isolation +25 C VSW (RRING, RLINE) = 320 V, logic inputs = gnd +85 C VSW (RRING, RLINE) = 330 V, logic inputs = gnd -40 C VSW (RRING, RLINE) = 310 V, logic inputs = gnd dv/dt sensitivity - 0.1 ISW - 0.3 0.1 - *Secondary protection and ringing source current limiting must prevent exceeding this parameter. 1.4.5 TESTOUT Switches, SW5 and SW6 Parameter Test Conditions Symbol Minimum Off-state leakage current +25 C VSW (differential) = -320 V to gnd VSW (differential) = +260 V to -60 V +85 C VSW (differential) = -330 V to gnd VSW (differential) = +260 V to -60 V -40 C VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V 0.1 ISW - 0.3 0.1 RON +25 C +85 C RLINE and TLINE = 10 mA, 40 mA RON -40 C - 35 - 50 70 26 - DC current limit 6 www.clare.com Rev. 2.0 9/16/2002 CPC7583 Parameter Test Conditions Symbol +25 C +85 C VSW (on) = 10 V -40 C Dynamic current limit (t = <0.5 s) Break switches in on state, ringing switches off, apply 1 kV at 10/1000 s pulse, with appropriate secondary protection in place. Minimum Typical Maximum Unit - 140 - 80 100 - - 210 250 - 2.5 - A mA ISW Logic input to switch output isolation +25 C VSW (TTESTout, TLINE, RTESTout, RLINE) = 320 V, logic inputs = gnd ISW - 0.1 1 A +85 C VSW (TTESTout, TLINE, RTESTout, RLINE) = 330 V, logic inputs = gnd ISW - 0.3 1 A -40 C VSW (TTESTout, TLINE, RTESTout, RLINE) = 310 V, logic inputs = gnd ISW - 0.1 1 A dv/dt sensitivity - 200 - V/s Typical Maximum Unit 1 A - 1.4.6 Ringing Test Return Switch, SW7 Parameter Test Conditions Symbol Minimum Off-state leakage current +25 C VSW (differential) = -320 V to gnd VSW (differential) = +260 to -60 V +85 C VSW (differential) = -330 V to gnd VSW (differential) = +270 V to -60 V -40 C VSW (differential) = -310 V to gnd VSW (differential) = +250 V to -60 V 0.1 ISW - 0.3 0.1 RON +25 C +85 C TRINGING = 10 mA, 40 mA RON - -40 C 60 - 85 100 45 - DC current limit +25 C +85 C 120 VSW (on) = 10 V ISW 70 -40 C 80 - mA 1 A - V/s 210 Logic input to switch output isolation +25 C VSW (TRING, TTESTin) = 320 V, logic inputs = gnd +85 C VSW (TRING, TTESTin) = 330 V, logic inputs = gnd -40 C VSW (TRING, TTESTin) = 310 V, logic inputs = gnd dv/dt sensitivity - Rev. 2.0 9/16/2002 0.1 ISW - 0.3 0.1 - www.clare.com 200 7 CPC7583 1.4.7 Ringing Test Switch, SW8 Parameter Test Conditions Symbol Minimum Typical Maximum Unit 1 A 0.75 1.5 V RON 35 - - 450 - A 1 A 200 - V/s Typical Maximum Unit 1 A Off-state leakage current +25 C +85 C 0.05 VSW (differential) = -60 V to +175 V ISW 0.1 -40 C 0.05 On Voltage ISW(ON) = 1 mA RON ISW(ON) = 70 mA, 80 mA Release Current - - - Logic input to switch output isolation +25 C VSW (RRING, RTESTin) = 320 V, logic inputs = gnd +85 C VSW (RRING, RTESTin) = 330 V, logic inputs = gnd -40 C VSW (RRING, RTESTin) = 310 V, logic inputs = gnd dv/dt sensitivity - 0.1 ISW - 0.3 0.1 - 1.4.8 Test In Switches, SW9 and SW10 Parameter Test Conditions Symbol Minimum Off-state leakage current +25 C VSW (differential) = -320 V to gnd VSW (differential) = -60 V to +260 V +85 C VSW (differential) = -330 V to gnd VSW (differential) = -60 V to +270 V -40 C VSW (differential) = -310 V to gnd VSW (differential) = -60 V to +250 V 0.1 ISW - 0.3 0.1 RON +25 C +85 C -40 C RTESTOUT and TTESTOUT = 10 mA, 40 mA RON 35 - 50 70 26 - - 160 - 80 110 - - 210 250 - DC current limit +25 C +85 C VSW (on) = 10 V ISW -40 C mA Logic input to switch output isolation +25 C VSW (TTESTin, RTESTin) = 320 V, logic inputs = gnd +85 C VSW (TTESTin, RTESTin) = 330 V, logic inputs = gnd -40 C VSW (TTESTin, RTESTin) = 310 V, logic inputs = gnd dv/dt sensitivity - 8 0.1 ISW - 0.3 1 A - V/s 0.1 - www.clare.com 200 Rev. 2.0 9/16/2002 CPC7583 1.5 Additional Electrical Characteristics Parameter Test Conditions Symbol Minimum Typical Maximum Unit Digital input characteristics Input low voltage - VIL - - 1.5 Input high voltage - VIH 3.5 - - Input leakage current (high) VDD = 5.5 V, VBAT = -75 V, VIH = 5 V IIH - 0.1 1 Input leakage current (low) VDD = 5.5 V, VBAT = -75 V, VIL = 0 V IIL - 0.1 1 Power consumption in idle/talk and all-off states VDD = 5 V, VBAT = -48 V, measure IDD and IBAT P - 4.7 10.5 Power consumption in ringing and access states VDD = 5 V, VBAT = -48 V, measure IDD and IBAT V A Power requirements VDD current in idle/talk and all off states VDD current in ringing and access states VBAT current in idle/talk and all off states VBAT current in ringing and access states mW P 5.2 10.5 IDD - 0.9 2.0 IDD - 1.0 2.0 IBAT - 4 10 VDD = 5 V, VBAT = -48 V mA A VDD = 5V, VBAT = -48 V IBAT - 4 10 Temperature Shutdown Requirements (temperature shutdown flag is active low) Shutdown activation temperature - - 110 125 150 C Shutdown circuit hysteresis - 10 - 25 C Rev. 2.0 9/16/2002 www.clare.com 9 CPC7583 1.6 Protection Circuitry Electrical Specifications Parameter Conditions Symbol Minimum Typical Maximum Voltage drop at continu- Apply dc current limit of break ous current (50/60 Hz) switches Forward Voltage - 2.8 3.5 Voltage drop at surge current Forward Voltage - 5 - - * 60 - 35 - 110 - Unit Parameters Related to the Diodes in the Diode Bridge Apply dynamic current limit of break switches V Parameters Related to the Protection SCR (when equipped) - Surge current A Trigger current (+25 C) ITRIG Trigger current (+85 C) - ITRIG Hold current (+25 C) IHOLD Hold current (+85 C) IHOLD 60 70 - - VBAT -4 - VBAT -2 V - 1.0 A -3 - V -5 - V Gate trigger voltage IGATE = ITRIGGER Reverse leakage current VBAT = -48 V On-state voltage - - 0.5 A, t = 0.5 s VON 2.0 A, t = 0.5 s VON - mA *Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place. V BAT must be capable of sourcing ITRIGGER for the internal SCR to activate. 1.7 Truth Tables 1.7.1 Truth Table for CPC7583xA and CPC7583xB State INRINGING INTESTIN INTESTOUT Idle/Talk 0 0 0 Latch TSD1 TESTIN Switches Break Switches Ringing Test Switches Ringing Switches TESTOUT Switches Off On Off Off Off TESTout 0 0 1 Off Off Off Off On TESTin 0 1 0 On Off Off Off Off Simultaneous TESTin and TESTout 0 1 1 On Off Off Off On Ringing 1 0 0 Off Off Off On Off Ringing Generator Test 1 1 0 Off Off On Off Off Latched X X X 1 1 0 1 0 1 1 1 0 All Off X X X 0 1 or Floating X Unchanged Unchanged Unchanged Unchanged Unchanged 2 0 Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off 1If T is tied high, thermal shutdown is disabled. If T is left floating, the thermal shutdown mechanism functions normally. SD SD 2Forcing T to ground overrides the logic input pins and forces an all off state. SD 10 www.clare.com Rev. 2.0 9/16/2002 CPC7583 1.7.2 Truth Table for CPC7583xC and CPC7583xD TESTIN Switches Break Switches Ringing Test Switches Ringing Switches TESTOUT Switches 0 Off On Off Off Off 0 1 Off Off Off Off On 0 1 0 On Off Off Off Off Simultaneous TESTin and TESTout 0 1 1 On Off Off Off On Ringing 1 0 0 Off Off Off On Off Simultaneous TESTout and Ringing Generator Test 1 1 0 Off Off On Off On Latched X X X 1 1 0 1 0 X X X X State INRINGING INTESTIN INTESTOUT Idle/Talk 0 0 TESTout 0 TESTin All Off Latch 0 TSD1 1 or Floating Unchanged Unchanged Unchanged Unchanged Unchanged 02 Off Off Off Off Off Off Off Off Off Off 1 If TSD is tied high, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism functions normally. 2 Forcing TSD to ground overrides the logic input pins and forces an all off state. Rev. 2.0 9/16/2002 www.clare.com 11 CPC7583 2. Functional Description 2.1 Introduction The CPC7583 has the following states: * Idle/talk. Loop break switches SW1, and SW2 closed, all other switches open. * Ringing. Ringing switches SW3, SW4 closed, all other switches open. * TESTout. Testout switches SW5, SW6 closed, all other switches open. * Ringing generator test. SW7, SW8 closed, all other switches open. * TESTin. Testin switches SW9 and SW10 closed. * Simultaneous TESTin and TESTout. SW9, SW10, SW5, and SW6 closed, all other switches open. * Simultaneous test out and ringing generator test. SW5, SW6, SW7, and SW8 closed, all other switches open (only on the xC and xD versions). * All Off. All switches open. See "Truth Tables" on page 10 for more information. The CPC7583 offers break-before-make and makebefore-break switching with simple logic-level input control. Solid-state switch construction means no impulse noise is generated when switching during ring cadence or ring trip, eliminating the need for external zero-cross switching circuitry. State-control is via logic-level input so no additional driver circuitry is required. The line break switches SW1 and SW2 are linear switches that have exceptionally low RON and excellent matching characteristics. The ringing access switch SW4 has an open contact breakdown voltage rating of greater than 480 V. This is sufficiently high, with proper protection, to prevent breakdown in the presence of a transient fault condition (i.e., passing the transient on to the ring generator). Integrated into the CPC7583 is a diode bridge/SCR clamping circuit, current limiting, and a thermal shutdown mechanism to provide protection to the SLIC device during a fault condition. Positive and negative surges are reduced by the current limiting circuitry and hazardous potentials are diverted to ground via diodes and the integrated SCR. Power-cross transients are also reduced by the current limiting and thermal shutdown circuits. To protect the CPC7583 from an overvoltage fault condition, the use of a secondary protector is required. The secondary protector must limit the voltage seen at the TLINE and RLINE terminals to a level below the maximum breakdown voltage of the switches. To minimize the stress on the solid-state contacts, use of a 12 foldback or crowbar type secondary protector is recommended. With proper selection of the secondary protector, a line card using the CPC7583 will meet all relevant ITU, LSSGR, FCC and UL protection requirements. The CPC7583 operates from a +5 V supply only. This gives the device extremely low idle and active power dissipation and allows use with virtually any range of battery voltage. A battery voltage is also used by the CPC7583 as a reference for the integrated protection circuit. In the event of a loss of battery voltage, the CPC7583 enters the all-off state. 2.2 Switch Logic The CPC7583 provides, when switching from the ringing state to the idle/talk state, the ability to control the release timing of the ringing switches SW3 and SW4 relative to the state of the loop break switches SW1 and SW2 using simple logic-level input. This is referred to a make-before-break or break-before-make operation. When the line break switch contacts (SW1 and SW2) are closed (or made) before the ringing access switch contacts (SW3 and SW4) are opened (or broken), this is referred to make-before-break operation. Break-before-make operation occurs when the ringing access contacts (SW3 and SW4) are opened (broken) before the line break switch contacts (SW1 and SW2) are closed (made). With the CPC7583, the make-before-break and break-beforemake operations can easily be selected by applying the proper sequence of logic inputs to INTESTout, INRINGING, and INTESTin. The logic sequences for either mode of operation are given in "Make-Before-Break Operation (Ringing to Idle/ Talk Transition)" on page 13 and "Break-Before-Make Operation (Ringing to Idle/Talk Transition)" on page 13. Logic states and explanations are given in "Truth Tables" on page 10. Break-before-make operation can also be achieved using pin 13 (TSD) as an input. In "Break-Before-Make Operation (Ringing to Idle/Talk Transition)" on page 13, lines 2 and 3, it is possible to induce the switches to the all-off state by grounding pin 13 (TSD) instead of applying logic input to the pins. This has the effect of overriding the logic inputs and forcing the device to the all-off state. Hold this input state for 25 ms. During this hold period, toggle the inputs from the ringing state to the idle/talk state. After the 25 ms, release pin 13 www.clare.com Rev. 2.0 9/16/2002 CPC7583 (TSD) to return switch control to the input pins INTESTout, INRINGING, and INTESTin and the latch control pin. 2.2.1 Make-Before-Break Operation (Ringing to Idle/Talk Transition) State INRINGING INTESTIN INTESTOUT Ringing 1 0 TSD Timing 0 Floating - SW4 waiting for next zerocurrent crossing to turn off. Maximum time is one-half of ringing. In this transition Floating state, current that is limited to the dc break switch current limit value will be sourced from the ring node of the SLIC. Makebeforebreak 0 0 0 Idle/Talk 0 0 0 Latch 0 Floating Zero-cross current has occurred Break Ring Ring All Other Switches Return Access Test 1 and 2 Switch 3 Switch 4 Switches Off On On Off On Off On Off On Off Off Off 2.2.2 Break-Before-Make Operation (Ringing to Idle/Talk Transition) State INRINGING INTESTIN INTESTOUT Latch TSD Timing - Ringing 1 0 0 Floating All off 1 0 1 Hold this state for one-half of Floating ringing cycle. SW4 waiting for zero current to turn off. 0 Break Ring Ring All Other Switches Return Access Test 1 and 2 Switch 3 Switch 4 Switches Off On On Off Off Off On Off All off 1 0 1 Floating Zero current has occurred. SW4 has opened Off Off Off Off Idle/Talk 0 0 0 Floating Release break switches On Off Off Off 2.3 Alternate Break-Before-Make Operation Note that break-before-make operation can also be achieved using TSD as an input. In lines 2 and 3 of the table "Break-Before-Make Operation (Ringing to Idle/Talk Transition)" on page 13, instead of using the logic input pins to force the all-off state, force TSD to ground. This overrides the logic inputs and also forces the all off state. Hold this state for one-half of the ringing cycle. During this 25 ms all-off state, change the inputs from the power ringing state (INRING = 1, INTESTIN = 0, INTESTOUT = 0) to the idle/talk state (INRING = 0, INTESTIN = 0, INTESTOUT = 0). After the hold period, release TSD to return switch control to the input pins which will set the idle talk state. When using the CPC7583 in this mode, forcing TSD low overrides the input pins and forces an all off state. Setting TSD high allows switch control via the logic input pins and returns the thermal protection circuit to Rev. 2.0 9/16/2002 normal operation. Forcing TSD high disables the thermal shutdown mechanism and is not recommended. Therefore, to allow switch control via the logic input pins, allow TSD to float. When using TSD as an input, the two recommended states are 0 (overrides logic input pins and forces all off state) and float (allows switch control via logic input pins and the thermal shutdown mechanism is active). This requires the use of an open-collector type buffer. 2.4 Data Latch The CPC7583 has an integrated data latch. The latch operation is controlled by logic-level input pin 18 (LATCH). The data input of the latch are the input pins, while the output of the data latch is an internal node used for state control. When the LATCH control pin is at logic 0, the data latch is transparent and data www.clare.com 13 CPC7583 control signals flow directly through to state control. A change in input will be reflected in a change is switch state. When LATCH control pin is at logic 1, the data latch is active and a change in input control will not affect switch state. The switches will remain in the position they were in when the LATCH changed from logic 0 to logic 1 and will not respond to changes in input as long as the latch is at logic 1. The TSD input is not tied to the data latch. Therefore, TSD is not affected by the LATCH input and the TSD input will override state control via the inputs. 2.5 TSD Setting TSD to +5 V allows switch control using the logic inputs. This setting, however, also disables the thermal shutdown circuit and is therefore not recommended. When using logic controls via the input pins, pin 13 (TSD) should be allowed to float. As a result, the two recommended states when using pin 13 (TSD) as a control are 0, which forces the device to the all-off state, or float, which allows logic inputs to remain active. This requires the use of an open-collector type buffer. 2.6 Ringing Switch Zero-Cross Current Turn Off After the application of a logic input to turn SW4 off, the ringing switch is designed to delay the change in state until the next zero-crossing. Once on, the switch requires a zero-current cross to turn off, and therefore should not be used to switch a pure DC signal. The switch will remain in the on state no matter the logic input until the next zero crossing. These switching characteristics will reduce and possibly eliminate overall system impulse noise normally associated with ringing switches. See Clare application note AN-144, Impulse Noise Benefits of Line Card Access Switches for more information. The attributes of ringing switch SW4 may make it possible to eliminate the need for a zerocross switching scheme. A minimum impedance of 300 in series with the ringing generator is recommended. 2.7 Power Supplies Both a +5 V supply and battery voltage are connected to the CPC7583. CPC7583 switch state control is powered exclusively by the +5 V supply. As a result, the CPC7583 exhibits extremely low power dissipation during both active and idle states. The battery voltage is not used for switch control but rather as a supply for the integrated secondary protection circuitry. The integrated SCR is designed to trig14 ger when pin 6 (TBAT) or pin 23 (RBAT) drops 2 to 4 V below the voltage on pin 28 (VBAT). This trigger prevents a fault induced overvoltage event at the TBAT or RBAT nodes. 2.8 Battery Voltage Monitor The CPC7583 also uses the VBAT voltage to monitor battery voltage. If battery voltage is lost, the CPC7583 immediately enters the all-off state. It remains in this state until the battery voltage is restored. The device also enters the all-off state if the battery voltage rises above -10 V and remains in the all-off state until the battery voltage drops below -15 V. This battery monitor feature draws a small current from the battery (less than 1 A typical) and will add slightly to the device's overall power dissipation. 2.9 Protection 2.9.1 Diode Bridge/SCR The CPC7583 uses a combination of current limited break switches, a diode bridge/SCR clamping circuit, and a thermal shutdown mechanism to protect the SLIC device or other associated circuitry from damage during line transient events such as lightning. During a positive transient condition, the fault current is conducted through the diode bridge to ground via FGND. Voltage is clamped to a diode drop above ground. During a negative transient of 2 to 4 V more negative than the voltage at VBAT, the SCR conducts and faults are shunted to FGND via the SCR and diode bridge. In order for the SCR to crowbar or foldback, the on voltage (see "Protection Circuitry Electrical Specifications" on page 10) of the SCR must be less negative than the VBAT voltage. If the VBAT voltage is less negative the TLINE and RLINE voltage, or if the VBAT supply is unable to source the trigger current, the SCR will not crowbar, however it will conduct fault currents to ground. For power induction or power-cross fault conditions, the positive cycle of the transient is clamped to a diode drop above ground and the fault current directed to ground. The negative cycle of the transient will cause the SCR to conduct when the voltage exceeds the battery reference voltage by two to four volts, steering the current to ground. 2.9.2 Current Limiting function If a lightning strike transient occurs when the device in the talk/idle state, the current is passed along the line to the integrated protection circuitry and restricted by www.clare.com Rev. 2.0 9/16/2002 CPC7583 the dynamic current limit response of break switches SW1 and SW2. When a 1000V 10/1000 S pulse (GR-1089-CORE lightning) is applied to the line though a properly clamped external protector, the current seen at pin 6 (TBAT) or pin 23 (RBAT) will be a pulse with a typical magnitude of 2.5 A and a duration of less than 0.5 s. If a power-cross fault occurs with the device in the talk/ idle state, the current is passed though break switches SW1 and SW2 on to the integrated protection circuit and is limited by the dynamic DC current limit response of the two break switches. The DC current limit, specified over temperature, is between 80 mA and 425 mA, and the circuitry has a negative temperature coefficient. As a result, if the device is subjected to extended heating due to power cross fault, the measured current at pin 6 (TBAT) or pin 23 (RBAT) will decrease as the device temperature increases. If the device temperature rises sufficiently, the temperature shutdown mechanism will activate and the device will default to the all-off state. all-off state. At this point the current measured at pin 6 (TBAT) and pin 23 (RBAT) will drop to zero. Once the device enters thermal shutdown it will remain in the all-off state until the temperature of the device drops below the activation level of the thermal shutdown circuit. This will permit the device to return to normal operation. If the transient has not passed, current will flow up to the value allowed by the dynamic DC current limiting of the switches and heating will begin again, reactivating the thermal shutdown mechanism. This cycle of entering and exiting the thermal shutdown mode will continue as long as the fault condition persists. If the magnitude of the fault condition is great enough, the external secondary protector could activate and shunt all current to ground. The thermal shutdown mechanism of the CPC7583 can be disabled by applying a logic 1 to pin 13 (TSD). 2.10 Temperature Shutdown The thermal shutdown mechanism will activate when the device temperature reaches a minimum of 110 C, placing the device in the all-off state regardless of logic input. During thermal shutdown mode, pin 13 (TSD) will read 0 V. Normal output of TSD is +5 V. 2.11 External Protection Elements The CPC7583 requires only overvoltage secondary protection on the loop side of the device. The integrated protection feature described above negates the need for protection on the line side. The secondary protector limits voltage transients to levels that do not exceed the breakdown voltage or input-output isolation barrier of the CPC7583. A foldback or crowbar type protector is recommended to minimize stresses on the device. If presented with a short duration transient such as a lightning event, the thermal shutdown feature will typically not activate. But in an extended power-cross transient, the device temperature will rise and the thermal shutdown will activate forcing the switches to the Consult Clare's application note, AN-100, "Designing Surge and Power Fault Protection Circuits for Solid State Subscriber Line Interfaces" for equations related to the specifications of external secondary protectors, fused resistors and PTCs. 3. Manufacturing Information 3.1 Soldering 3.1.1 Moisture Reflow Sensitivity Clare has characterized the moisture reflow sensitivity of LCAS products using IPC/JEDEC standard J-STD020A. Moisture uptake from atmospheric humidity occurs by diffusion. During the solder reflow process, in which the component is attached to the PCB, the whole body of the component is exposed to high process temperatures. The combination of moisture uptake and high reflow soldering temperatures may lead to moisture induced delamination and cracking of the component. To prevent this, this component must be handled in accordance with IPC/JEDEC standard Rev. 2.0 9/16/2002 J-STD-020A per the labelled moisture sensitivity level (MSL), level 1 for the SOIC package, and level 3 for the MLP package. 3.1.2 Reflow Profile The maximum ramp rates, dwell times, and temperatures of the assembly reflow profile should not exceed those specified in IPC standard IPC-9502, table 2. Soldering processes are limited to 220 C component body temperature. www.clare.com 15 CPC7583 3.2 Washing Clare does not recommend ultrasonic cleaning of LCAS parts. 3.3 Mechanical Dimensions 3.3.1 MLP Package 11.0 BSC (0.4334). 0.18 BSC (0.0071) 0.18 BSC (0.0071) 0.75 BSC (0.0295) 0.33 -0.05 +0.07 (0.0130 -0.0020 +0.0028) 7.0 BSC (0.2758) 0.60 BSC (0.0236) 5.0 0.05 (0.1970 0.0020) 0.37 BSC (0.0146) TOP VIEW Pin 1 0.70 BSC (0.0276) 0.61 BSC (0.0240) 0.55 0.05 7.5 0.05 (0.2955 0.0020) 0.2 BSC (0.0079) 0.9 0.1 (0.0355 0.0039) Bottom side metallic pad BOTTOM VIEW Seating Plane 0.02 0.03 (0.0008 0.0012) Dimensions in mm (inches) Dimensions and tolerances conform to ANSI Y14.5M-1994 SIDE VIEW NOTE: For optimum solder joint size, MLP package printed-circuit board pads should extend no more than .05 mm past the chip post on the short sides, and no more than .025 mm past the chip posts on the long sides. As the metallic pad on the bottom of the MLP package is connected to the substrate of the die, Clare recommends that no printed circuit board to traces cross this area to maintain minimum creepage and clearance values. 3.3.2 SOIC Package 18.034 0.127 (0.710 0.005) 10.312 0.051 (0.406 0.003) .330 x 45o max. (.013 x 45o max.) 7.468 0.127 (0.294+/-0.005) 3o - 7o 0.813 0.102 (0.032 0.004) Dimensions in mm (inches) 2.54 0.127 (0.100+/-0.005) 1.27 typ. (0.050 typ.) 16 0.250 typ. (0.010 typ.) 0.366 min. / 0.467 max. typ. (0.014 min. / 0.018 max. typ.) www.clare.com Rev. 2.0 9/16/2002 CPC7583 3.3.3 MLP Tape Dimensions A0 6.4 R = .50 K1 B0 7.40 16.00 K0 1.4 1.4 12.00 4.00 2.00 1.50 A0 = 6.4 mm B0 = 7.4 mm K0 = 1.4 mm K1 = 1.4 mm Rev. 2.0 9/16/2002 NOTES:1. ALL DIMENSIONS ARE IN MILLIMETERS AND CARRY TOLERANCES OF EIA STANDARD 481-2. 2. THE TAPE COMPLIES WITH ALL "NOTES" FOR CONSTANT DIMENSIONS LISTED ON PAGE 5 OF EIA-481-2. www.clare.com 17 For additional information please visit www.clare.com Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set forth in Clare's Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of Clare's product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-CPC7583-R 2.0 (c) Copyright 2001, Clare, Inc. All rights reserved. Printed in USA. 9/16/2002