CPC7583BB - IXYS Corporation - Datasheet.Directory

DS-CPC7583-R2.0 9/16/2002 www.clare.com 1

Features

•

Small 28-pin SOIC or micro-leadframe (MLP) package

•MLP ver sion provides 65% PCB area reduction over

4th generation EMRs , and 60% smaller footprint than

SOIC ve rsion

•Monolithic IC reliability

•Low, matched, RON

•Eliminates the need for zero-cross switching

•Fle xible switch timing for transition from ringing

mode to talk mode .

•Clean, bounce-free switching

•Tertiary protection consisting of integrate d current

limiting and thermal shutdown for SLIC protection

•5 V operation with power consumption < 10.5 mW

•Intelligent battery monitor

•Latched logic-level inputs, no external drive circuitry

required

•SOIC ve rsion pin-compatible with Agere 7583 family

Applications

•Central office (CO)

•Digital Loop Carrier (DLC)

•PBX Systems

•Digitally Added Main Line (DAML)

•Hybrid Fiber Coax (HFC)

•Fiber in the Loop (FITL)

•P air Gain System

•Channel Banks

Description

The CPC7583 is a monolithic 10-pole line card access

s witch in a 28-pin SOIC or MLP package. It provides

the necessary functions to replace three 2-F orm-C

electromechanical relays on analog line cards and

combined v oice and data line cards found in central

office, access, and PBX equipment. The device con-

tains solid state switches for tip and ring line break,

ringing injection/ringing return, and test access . The

CPC7583 requires only a +5 V supply an d offers

break-bef or e-make or make-before-break switch oper-

ation using simple logic-level input control.

Ordering Information

Specify CPC7583Bx for SOIC package in tubes ,

CPC7583Mx f or MLP package in tubes. Add -TR

to the part number f or tape and reel pac kaging.

Part Number Description

CPC7583xA With protection SCR

CPC7583xB Without protection SCR

CPC7583xC With extra logic state and protection SCR

CPC7583xD With extra logic state but without protection

SCR

CPC7583

TLINE

RLINE

TBAT

VDD

RBAT

DGND

VBAT

FGND

VREF INTESTIN

INRINGING

INTESTOUT

TSD

LATCH

10 85

1314281

Switch

Control

Logic

SCR

and

Trip

Circuit

Secondary

Protection

+5 Vdc

Tip

Ring SLIC

XSW5 SW7

SW6

SW2

SW4

SW10

SW8

TTESTIN

(T )

CHANTEST

TTESTOUT

(T )

DROPTEST

VBAT

RINGING

300

(min.)

Ω

RTESTOUT

(R )

DROPTEST

TESTIN

TRING

SW3 SW9

SW1

Ω

CPC7583

Line Card Access Switch

CPC7583

2 www.clare.com R2.0 9/16/2002

1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Pinout Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Absolute Maximum Ratings (at 25° C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Electrical Characteristics, TA = -40° C to +85° C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4.1 Power Supply Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4.2 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4.3 Ringing Return Switch, SW3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4.4 Ringing Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4.5 TESTOUT Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4.6 Ringing Test Return Switch, SW7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4.7 Ringing Test Switch, SW8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4.8 Test In Switches, SW9 and SW10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.5 Additional Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.6 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.7 Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.7.1 Truth Table for CPC7583xA and CPC7583xB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.7.2 Truth Table for CPC7583xC and CPC7583xD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Switch Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2.1 Make-Before-Break Operation (Ringing to Idle/Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.2 Break-Before-Make Operation (Ringing to Idle/Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3 Alternate Break-Before-Make Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 TSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.6 Ringing Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.7 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.8 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.9 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.9.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.9.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.10 Temperature Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.11 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3.1 MLP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3.2 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3.3 SOIC Tape Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

CPC7583

Rev. 2.0 9/16/2002 www.clare.com 3

1. Specifications

1.1 Package Pinout 1.2 Pinout Description

CPC7583

TBAT

FGND

DGND

TTESTin

INTESTin

TTESTout

INTESTout

RTESTout

TLINE

TRINGING

VDD

VBAT

RBAT

TESTin

RLINE

RRINGING

LATCH

INRINGING

Pin Name Description

1FGND Fault ground

2 NC No connection

3 NC No connection

4 NC No connection

5TTESTin Connect to TESTIN bus tip lead

6TBAT Connect to tip on SLIC side

7TLINE Connect to tip on line side

8TRINGING Connect to ringing generator return

9 NC Not connected

10 TTESTout Connect to TESTOUT bus tip lead

11 NC No connection

12 VDD +5 V supply

13 TSD

Temperature shutdown pin. Bi-directional

I/O with internal pullup to VDD. Output func-

tion indicates status of thermal shutdown

circuitry. Input function can be used to set

the ‘all off’ mode using an open-drain type

output.

14 DGND Digital ground

15 INTESTout Logic-level switch control input

16 INRINGING Logic-level switch control input

17 INTESTin Logic-level switch control input

18 LATCH Data latch control, active high, transparent

low

19 RTESTout Connect to TESTOUT bus ring lead

20 RRINGING

Connect to ringing generator current limit-

ing resistor

21 NC No connection

22 RLINE Connect to ring on the line side

23 RBAT Connect to ring on the SLIC side

24 RTESTin Connect to TESTIN bus ring lead

25 NC No connection

26 NC No connection

27 NC No connection

28 VBAT

Battery voltage supply. Must be capable of

sourcing the trigger current for proper

operation of the SCR.

CPC7583

4 www.clare.com Rev. 2.0 9/16/2002

1.3 Absolute Maximum Ratings (at 25° C)

1.4 Electrical Characteristics, T A = -40° C to +85° C

Unless otherwise specified, minimum and maxim um

v alu es ar e production testing r equir ements. Typical

v alu es ar e char acteristic of the device and are the

result of engineering e valuations. Typical values are

provided for inf ormation purposes only and are not

part of the testing requirements.

Absolute maximum ratings are stress ratings. Stresses in

excess o f these ratings can cause per m anent damage to

the device. Functional operation of the device at these or

any other conditions beyond those indicated in the opera-

tional sections of this data sheet is not implied. Exposure of

the device to the absolute maximum ratings for an

extended period may degrade the device and affect its reli-

ability.

1.4.1 Power Supply Specifications

1.4.2 Break Switches, SW1 and SW2

Parameter Minimum Maximum Unit

Operating temperature -40 +110 °C

Storage temperature -40 +150 °C

Operating relative humidity 5 95 %

Pin soldering temperature

(10 seconds max) - +260 °C

+5 V power supply - 7 V

Battery Supply - -85 V

Logic input voltage - 7 V

Logic input to switch output

isolation -330V

Switch open contact isola-

tion (SW1, SW2, SW3,

SW5, SW6, SW7, SW9,

SW10)

-330V

Switch open contact isola-

tion (SW4)* -480V

Switch open contact isola-

tion (SW8)* -235V

*Ringing supply side of switch limited to ±210 V with respect to ground

Supply Minimum Typical Maximum Unit

VDD +4.5 +5.0 +5.5 V

VBAT

1-19 - -72 V

1VBAT is used only for internal protection circuitry. If VBAT rises above

-10 V, the device will e nter the all-off stat e and will remain in the all-off state

until the battery drops below -15 V.

ESD Rating (Human Body Model)

1000 V

Parameter Test Conditions Symbol Minimum Typical Maximum Unit

Off-state leakage current

+25° C

VSW (differential) = -320 V to gnd

VSW (differential) = +260 V to -60 V

ISW -

0.1

1µA+85° C VSW (differential) = -330 V to gnd

VSW (differential) = +270 V to -60 V 0.3

-40° C VSW (differential) = -310 V to gnd

VSW (differential) = +250 V to -60 V 0.1

RON

+25° C TLINE and RLINE = ±10 mA, ±40 mA,

RBAT and TBAT = -2 V RON

14.5 -

Ω

+85° C 20.5 28

-40° C 10.5 -

RON match Per on-resistance test condition of

SW1, SW2

Magnitude

RON SW1-

RON SW2

0.15 0.8

CPC7583

Rev. 2.0 9/16/2002 www.clare.com 5

1.4.3 Ringing Return Switch, SW3

DC current limit

+25° C

VSW (on) = ±10 V

ISW

- 225 -mA+85° C 80 150

-40° C - 400 425

Dynamic current limit

(t = <0.5 µs)

Break switches in on state, ringing

switches off, apply ±1 kV at

10/1000 µs pulse, with appropriate sec-

ondary protection in place.

-2.5- A

Logic input to switch output isolation

+25° C VSW (TLINE, RLINE) = ±320 V, logic

inputs = gnd

ISW

-0.1

1µA+85° C VSW (TLINE, RLINE) = ±330 V, logic

inputs = gnd -0.3

-40° C VSW (TLINE, RLINE) = ±310 V, logic

inputs = gnd -0.1

dv/dt sensitivity - - - 200 - V/µs

Parameter Test Conditions Symbol Minimum Typical Maximum Unit

Off-state leakage current

+25° C VSW (differential) = -320 V to gnd

VSW (differential) = +260 V to -60 V

ISW -

0.1

1µA+85° C VSW (differential) = -330 V to gnd

VSW (differential) = +270 V to -60 V 0.3

-40° C VSW (differential) = -310 V to gnd

VSW (differential) = +250 V to -60 V 0.1

RON

+25° C

TLINE = ±0 mA, ±10 mA RON -

60 -

Ω+85° C 85 100

-40° C 45 -

DC current limit

+25° C

VSW (on) = ± 10 V

ISW

- 120

mA+85° C 70 85

-40° C

210

Dynamic current limit

(t = <0.5 µs)

Break switches in on state, ringing

switches off, apply ±1 kV at

10/1000 µs pulse, with appropriate sec-

ondary protection in place.

2.5 A

Logic input to switch output isolation

+25° C VSW (TRING, TLINE) = ±320 V, logic

inputs = gnd

ISW -

0.1

1µA+85° C VSW (TRING, TLINE) = ±330 V, logic

inputs = gnd 0.3

-40° C VSW (TRING, TLINE) = ±310 V, logic

inputs = gnd 0.1

Parameter Test Conditions Symbol Minimum Typical Maximum Unit

CPC7583

6 www.clare.com Rev. 2.0 9/16/2002

1.4.4 Ringing Switch, SW4

1.4.5 TESTOUT Switches, SW5 and SW6

dv/dt sensitivity - - - 200 - V/µs

Parameter Test Conditions Symbol Minimum Typical Maximum Unit

Off-state leakage current

+25° C

VSW (differential) = -255 V to +210 V

VSW (differential) = +255 V to -210 V

ISW

0.05 1

µA+85° C

VSW (differential) = -270 V to +210 V

VSW (differential) = +270 V to -210 V 0.1 1

-40° C VSW (differential) = -245 V to +210 V

VSW (differential) = +245 V to -210 V 0.05 1

On Voltage ISW (on) = ± 1 mA -1.53V

Ringing generator cur-

rent to ground during

ringing

VCC = 5 V, inputs set for ringing mode IRINGING 0.1 0.25 mA

On steady-state current* Inputs set for ringing mode ISW - 150 mA

Surge current* - - - 2 A

Release current - - 450 - µA

RON ISW (on) = ±70 mA, ±80 mA RON 10 15 Ω

Logic input to switch output isolation

+25° C VSW (RRING, RLINE) = ±320 V, logic

inputs = gnd

ISW -

0.1

1µA+85° C VSW (RRING, RLINE) = ±330 V, logic

inputs = gnd 0.3

-40° C VSW (RRING, RLINE) = ±310 V, logic

inputs = gnd 0.1

dv/dt sensitivity - - 200 - V/µs

*Secondary protection and ringing source current limiting must prevent exceeding this par ameter.

Parameter Test Conditions Symbol Minimum Typical Maximum Unit

Off-state leakage current

+25° C

VSW (differential) = -320 V to gnd

VSW (differential) = +260 V to -60 V

ISW -

0.1

1µA+85° C

VSW (differential) = -330 V to gnd

VSW (differential) = +260 V to -60 V 0.3

-40° C

VSW (differential) = -310 V to gnd

VSW (differential) = +250 V to -60 V 0.1

RON

+25° C

RLINE and TLINE = ±10 mA, ±40 mA RON -

35 -

Ω+85° C 50 70

-40° C 26 -

DC current limit

Parameter Test Conditions Symbol Minimum Typical Maximum Unit

CPC7583

Rev. 2.0 9/16/2002 www.clare.com 7

1.4.6 Ringing Test Return Switch, SW7

+25° C

VSW (on) = ±10 V

ISW

- 140 -

mA+85° C 80 100 -

-40° C - 210 250

Dynamic current limit

(t = <0.5 µs)

Break switches in on state, ringing

switches off, apply ±1 kV at

10/1000 µs pulse, with appropriate sec-

ondary protection in place.

-2.5- A

Logic input to switch output isolation

+25° C VSW (TTESTout, TLINE, RTESTout, RLINE)

= ±320 V, logic inputs = gnd ISW -0.11µA

+85° C VSW (TTESTout, TLINE, RTESTout, RLINE)

= ±330 V, logic inputs = gnd

ISW -0.31µA

-40° C VSW (TTESTout, TLINE, RTESTout, RLINE)

= ±310 V, logic inputs = gnd

ISW -0.11µA

dv/dt sensitivity - - 200 - V/µs

Parameter Test Conditions Symbol Minimum Typical Maximum Unit

Off-state leakage current

+25° C VSW (differential) = -320 V to gnd

VSW (differential) = +260 to -60 V

ISW -

0.1

1µA+85° C VSW (differential) = -330 V to gnd

VSW (differential) = +270 V to -60 V 0.3

-40° C VSW (differential) = -310 V to gnd

VSW (differential) = +250 V to -60 V 0.1

RON

+25° C

TRINGING = ±10 mA, ±40 mA RON -

60 -

Ω+85° C 85 100

-40° C 45 -

DC current limit

+25° C

VSW (on) = ±10 V ISW 70

120

-mA+85° C 80

-40° C 210

Logic input to switch output isolation

+25° C VSW (TRING, TTESTin) = ±320 V, logic

inputs = gnd

ISW -

0.1

1µA+85° C VSW (TRING, TTESTin) = ±330 V, logic

inputs = gnd 0.3

-40° C VSW (TRING, TTESTin) = ±310 V, logic

inputs = gnd 0.1

dv/dt sensitivity - - 200 - V/µs

Parameter Test Conditions Symbol Minimum Typical Maximum Unit

CPC7583

8 www.clare.com Rev. 2.0 9/16/2002

1.4.7 Ringing Test Switch, SW8

1.4.8 Test In Switches, SW9 and SW10

Parameter Test Conditions Symbol Minimum Typical Maximum Unit

Off-state leakage current

+25° C

VSW (differential) = -60 V to +175 V ISW

0.05

1µA+85° C 0.1

-40° C 0.05

On Voltage ISW(ON) = ±1 mA - 0.75 1.5 V

RON ISW(ON) = ±70 mA, ±80 mA RON 35 - Ω

Release Current - - 450 - µA

Logic input to switch output isolation

+25° C VSW (RRING, RTESTin) = ±320 V, logic

inputs = gnd

ISW -

0.1

1µA+85° C VSW (RRING, RTESTin) = ±330 V, logic

inputs = gnd 0.3

-40° C VSW (RRING, RTESTin) = ±310 V, logic

inputs = gnd 0.1

dv/dt sensitivity - - 200 - V/µs

Parameter Test Conditions Symbol Minimum Typical Maximum Unit

Off-state leakage current

+25° C VSW (differential) = -320 V to gnd

VSW (differential) = -60 V to +260 V

ISW -

0.1

1µA+85° C

VSW (differential) = -330 V to gnd

VSW (differential) = -60 V to +270 V 0.3

-40° C

VSW (differential) = -310 V to gnd

VSW (differential) = -60 V to +250 V 0.1

RON

+25° C

RTESTOUT and TTESTOUT = ±10 mA,

±40 mA RON -

35 -

Ω+85° C 50 70

-40° C 26 -

DC current limit

+25° C

VSW (on) = ±10 V ISW

- 160 -

mA+85° C 80 110 -

-40° C - 210 250

Logic input to switch output isolation

+25° C VSW (TTESTin, RTESTin) = ±320 V, logic

inputs = gnd

ISW -

0.1

1µA+85° C VSW (TTESTin, RTESTin) = ±330 V, logic

inputs = gnd 0.3

-40° C VSW (TTESTin, RTESTin) = ±310 V, logic

inputs = gnd 0.1

dv/dt sensitivity - - 200 - V/µs

CPC7583

Rev. 2.0 9/16/2002 www.clare.com 9

1.5 Additional Electrical Characteristics

Parameter Test Conditions Symbol Minimum Typical Maximum Unit

Digital input characteristics

Input low voltage - VIL --1.5

Input high voltage - VIH 3.5 - -

Input leakage current

(high) VDD = 5.5 V, VBAT = -75 V, VIH = 5 V IIH -0.11µA

Input leakage current

(low) VDD = 5.5 V, VBAT = -75 V, VIL = 0 V IIL -0.11

Power requirements

Power consumption in

idle/talk and all-off

states

VDD = 5 V, VBAT = -48 V, measure IDD

and IBAT

P- 4.7 10.5

Power consumption in

ringing and access

states

VDD = 5 V, VBAT = -48 V, measure IDD

and IBAT

P5.2 10.5

VDD current in idle/talk

and all off states VDD = 5 V, VBAT = -48 V

IDD -0.92.0

VDD current in ringing

and access states IDD -1.02.0

VBAT current in idle/talk

and all off states VDD = 5V, VBAT = -48 V

IBAT -410

µA

VBAT current in ringing

and access states

IBAT -410

Temperature Shutdown Requirements (temperature shutdown flag is active low)

Shutdown activation

temperature - - 110 125 150 °C

Shutdown circuit hyster-

esis --10-25°C

CPC7583

10 www.clare.com Rev. 2.0 9/16/2002

1.6 Protection Circuitry Electrical Specifications

1.7 Truth Tables

1.7.1 Truth Table for CPC7583xA and CPC7583xB

Parameter Conditions Symbol Minimum Typical Maximum Unit

Parameters Related to the Diodes in the Diode Bridge

Voltage drop at continu-

ous current (50/60 Hz)

Apply ± dc current limit of break

switches

Forward

Vol tage -2.83.5

Voltage drop at surge

current

Apply ± dynamic current limit of break

switches

Forward

Vol tage -5-

Parameters Related to the Protection SCR (when equipped)

Surge current

-*A

Trigger current (+25° C) ITRIG 60 -

Trigger current (+85° C) ITRIG 35 -

Hold current (+25° C) IHOLD 110 -

Hold current (+85° C) IHOLD 60 70 -

Gate trigger voltage IGATE = ITRIGGER

§-V

BAT -4 -VBAT -2 V

Reverse leakage current VBAT = -48 V -

-1.0µA

On-state voltage

0.5 A, t = 0.5 µsVON -3 - V

2.0 A, t = 0.5 µsVON -5 - V

*Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place.

§VBAT must be capable of sourcing ITRIGGER for the internal SCR to activate.

State INRINGING INTESTIN INTESTOUT Latch TSD

1TESTIN

Switches

Break

Switches

Ringing

Test

Switches

Ringing

Switches

TESTOUT

Switches

Idle/Talk 0 0 0

1 or

Floating

Off On Off Off Off

TESTout 0 0 1 Off Off Off Off On

TESTin010 On Off Off Off Off

Simul-

taneous

TESTin

and

TESTout

011 On Off Off Off On

Ringing 1 0 0 Off Off Off On Off

Ringing

Generator

Te s t

110 OffOff

On Off Off

Latched X X X 1 Unchanged Unchanged Unchanged Unchanged Unchanged

All Off

1 0 1 0 Off Off Off Off Off

1 1 1 0 Off Off Off Off Off

XXXX

02Off Off Off Off Off

1If TSD is tied high, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism functions normally.

2Forcing TSD to ground overrides the logic input pins and forces an all off state.

CPC7583

Rev. 2.0 9/16/2002 www.clare.com 11

1.7.2 Truth Table for CPC7583xC and CPC7583xD

State INRINGING INTESTIN INTESTOUT Latch TSD

1TESTIN

Switches

Break

Switches

Ringing

Test

Switches

Ringing

Switches

TESTOUT

Switches

Idle/Talk 0 0 0

1 or

Floating

Off On Off Off Off

TESTout 0 0 1 Off Off Off Off On

TESTin010 On Off Off Off Off

Simul-

taneous

TESTin

and

TESTout

011 On Off Off Off On

Ringing 1 0 0 Off Off Off On Off

Simulta-

neous

TESTout

and Ring-

ing Gener-

ator Test

110 OffOff

On Off On

Latched X X X 1 Unchanged Unchanged Unchanged Unchanged Unchanged

All Off

1 0 1 0 Off Off Off Off Off

XXXX

02Off Off Off Off Off

1If TSD is tied high, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism functions normally.

2Forcing TSD to ground overrides the logic input pins and forces an all off state.

CPC7583

12 www.clare.com Rev. 2.0 9/16/2002

2. Functional Description

2.1 Introduction

The CPC7583 has the following states:

•Idle/talk. Loop break s witches SW1, and SW2

closed, all other switches open.

•Ringing. Ringing switches SW3, SW4 closed, all

other switches open.

•TESTout. Testout s witches SW5, SW6 closed, all

other switches open.

•Ringing generator test. SW7, SW8 closed, all

other switches open.

•TESTin. Testin s w itches SW9 and SW10 closed.

•Simulta neous TESTin and TESTout. SW9, SW10,

SW5, and SW6 closed, all other switches open.

•Simultaneous test out and ringing generator

test. SW5, SW6, SW7, and SW8 closed, all other

switches open (only on the xC and xD v ersions).

•All Off . All switches open.

See “Truth Tables” on page 10 for more information.

The CPC7583 offers break-before-make and make-

before-break switching with simple logic-lev el input

control. Solid-state s witch construction means no

impulse noise is generated when s witching during ring

cadence or ring trip, eliminat ing the need for external

zero-cross switching circuitry. State-control is via

logic-le vel input so no additional driver circuit ry is

required. The line break switches SW1 and SW2 are

linear switches that hav e exceptionally low RON and

e xcellent matching characteristics . The ringing access

switch SW4 has an open contact breakdown voltage

rating of g reat er t han 480 V. This is sufficiently high,

with proper protection, to preve nt br eakdown in the

presence of a transient fault condition (i.e . , p assing

the transient on to t he ring generato r).

Integr ated int o the CPC7583 is a diode bridge/SCR

clamping circuit, current limiting , and a th ermal shut-

down mechanism t o provide protection to the SLIC

de vice during a fault condition. Positive and negative

surges are reduced by the current limiting circuitry and

hazardous potentials are div erted to ground via diodes

and the integrat ed SCR. Power-cross tr ansients are

also reduced b y the curr ent limit ing and t hermal shut-

down circuits .

To protect the CPC7583 from an overvoltage fault

condition, the use of a secondary protector is required.

The secondary protector must limit the v oltage seen at

the TLINE and RLINE terminals to a le vel below the

maximum breakdown voltage of the switches. To min-

imize the stre ss on the solid-state contacts, use of a

f oldback or crowbar type secondary protector is rec-

ommended. With proper selection of the secondary

protector, a line card using the CPC7583 will meet all

rele vant ITU, LSSGR, FCC and UL protection require-

ments.

The CPC7583 operates from a +5 V supply only. This

gives the device e xtremely low idle and active power

dissipation and allows use with virtually any range of

battery voltag e . A battery voltage is also used by the

CPC7583 as a ref erence for the integrated protect ion

circuit. In the event of a loss of battery vo lt age , the

CPC7583 enters the all-off st ate.

2.2 Switch Logic

The CPC7583 provides , when switching from the ring-

ing state to the idle/talk state, the ability to control the

release timing of the ringing switches SW3 and SW4

relativ e to the state of the loop break s wit ches SW1

and SW2 using simple logic-level input. This is

ref erred to a make-bef ore-break or break-before-mak e

operation. When the line br eak switch contacts (SW1

and SW2) are closed (or made) before the ringing

access s wit ch contacts (SW3 a nd SW4) are opened

(or broken), this is referred to make-before-break

operation. Break-before-make operation occurs when

the ringing access contacts (SW3 and SW4) are

opened (brok en) before the line break s witch contacts

(SW1 and SW2) are closed (made). With t he

CPC7583, the make-before-break and break-before-

make operations can easily be selected by applying

the proper sequence of logic inputs to INTESTout,

INRINGING, and INTESTin.

The logic sequences for either mode of operation are

given in “Make-Before-Break Operation (Ringing to Idle/

Talk Transition)” on page 13 and “Break-Before-Make Oper-

ation (Ringing to Idle/Talk Transition)” on page 13. Logic

states and explanations are given in “Truth Tables” on

page 10.

Break-before-make operation can also be achieve d

using pin 13 (TSD) as an input. In “Break-Before-Make

Operation (Ringing to Idle/Talk Transition)” on page 13,

lines 2 and 3, it is possible to induce the s wit ches to

the all-off state by grounding pin 13 (TSD) instead of

applying logic input to the pins. This has the effect of

ov erriding the logic inputs and f orcing the de vice to the

all-off state. Hold th is input state f or 25 ms. During this

hold period, toggle the inputs from the ringing state to

the idle/talk state . After the 25 ms, release pin 13

CPC7583

Rev. 2.0 9/16/2002 www.clare.com 13

(TSD) to return switch control to the input pins INTEST-

out, INRINGING, and INTESTin and t he latch cont rol pin.

2.2.1 Make-Before-Break Operation (Ringing to Idle/Talk Transition)

2.2.2 Break-Before-Make Operation (Ringing to Idle/Talk Transition)

2.3 Alternate Brea k-Before-Make Operation

Note that break-before-make oper a tion can also be

achie v ed using TSD as an input. In lines 2 and 3 of the

table “Break-Before-Make Operation (Ringing to Idle/Talk

Transition)” on page 13, instead of using the logic input

pins to f orce the all-off state, f orce TSD to gr ound. This

overrides the logic inputs and also forces the all off

state. Hold th is st ate for one-half of the ringing cycle.

During this 25 ms all-off state, change t he inputs from

the power ringing state (INRING = 1, I N TESTIN = 0,

INTESTOUT = 0) to th e idle/ talk stat e (I NRING = 0,

INTESTIN = 0, INTESTOUT = 0). After the hold period,

release TSD to return switch control to the input pins

which will set the idle talk state.

When using the CPC7583 in this mode , forcing TSD

low overrides the input pins and f orces an all of f state .

Setting TSD high allows switch control via the logic

input pins and returns the thermal protection circuit to

normal operation. F orcing TSD high disab l es the ther-

mal shutdown mechanism and is not recommended.

Therefore, to allow switch control via the logic input

pins, allo w TSD to float.

When using TSD as an input, the two recommended

states are 0 (o verrides logic input pins and f orces all

off state) and float (allo ws s witch control via logic input

pins and the thermal shutdown mechanism is active).

This requires the use of an open- collector typ e buffer.

2.4 Data Latch

The CPC7583 has an integr at ed data latch. The lat ch

operation is controlled by logic-level input pin 18

(LATCH). The data input of the latch are t he input

pins, while the ou tput of t he data latch is an in ternal

node used for state control. When the LATCH control

pin is at logic 0, the data latch is t r ansparent and d ata

State INRINGING INTESTIN INTESTOUT Latch TSD Timing

Break

Switches

1 and 2

Ring

Return

Switch 3

Ring

Access

Switch 4

All Other

Test

Switches

Ringing 1 0 0

Floating - Off On On Off

Make-

before-

break

0 0 0 Floating

SW4 waiting for next zero-

current crossing to turn off.

Maximum time is one-half of

ringing. In this transition

state, current that is limited to

the dc break switch current

limit value will be sourced

from the ring node of the

SLIC.

On Off On Off

Idle/Talk 0 0 0 Floating Zero-cross current has

occurred On Off Off Off

State INRINGING INTESTIN INTESTOUT Latch TSD Timing

Break

Switches

1 and 2

Ring

Return

Switch 3

Ring

Access

Switch 4

All Other

Test

Switches

Ringing 1 0 0

Floating - Off On On Off

All off 1 0 1 Floating

Hold this state for one-half of

ringing cycle. SW4 waiting for

zero current to turn off.

Off Off On Off

All off 1 0 1 Floating Zero current has occurred.

SW4 has opened Off Off Off Off

Idle/Talk 0 0 0 Floating Release break switches On Off Off Off

CPC7583

14 www.clare.com Rev. 2.0 9/16/2002

control signals flow directly through to state cont rol. A

change in input will be reflected in a change is switch

state. When LATCH control pin is at logic 1, the data

latch is active and a change in input control will not

aff ect switch state. The switches will remain in the

position they were in when the LATCH changed from

logic 0 to logic 1 and will not respond to changes in

input as long as the latch is at logic 1. The TSD input is

not tied to the data latch. Therefore, TSD is no t

affected by the LATCH input and the TSD input will

override state control via the inputs.

2.5 TSD

Setting TSD to +5 V allows switch contr ol using t he

logic inputs. This setting, howe ver, also disables the

thermal shutdown circuit and is therefore not recom-

mended. When using logic cont rols via the input pins,

pin 13 (TSD) should be allo wed to float. As a result, th e

two recommended states when using pin 13 (T SD) as

a control are 0, which for ces the device to the all-off

state, or f loat, which allows logic inputs to remain

active. This requires the use of an open-collector type

buffer.

2.6 Ringing Switc h Zer o-Cr oss Current Turn Off

After the application of a logic input t o turn SW4 off,

the ringing switch is designed to delay the change in

state until the next zero-crossing. Once on, the switch

requires a zero-current cross to tu rn off, and therefore

should not be used to switch a pure DC signal. The

switch will remain in the on state no matter the logic

input until the next zero crossing. These switching

characteristics will reduce and possibl y eliminate o ver-

all system impulse noise normally associated with

ringing swit ches . See Clare applicat ion note AN-144,

Impulse Noise Benefits of Line Card Access Switches for

more inf ormation. The attributes of ringing s witch SW4

ma y make it possible to eliminate the need for a zero-

cross s wit ching scheme. A minimum impedance of

300 Ω in series with the ringing generator is recom-

mended.

2.7 Power Supp lies

Both a +5 V supply and battery v oltage are connected

to the CPC7583. CPC7583 switch state control is

pow ered exclusiv ely by the +5 V supply. As a result,

the CPC7583 e xhibits e xtremely low power dissipation

during both active and idle stat es.

The battery voltage is not used for s witch con trol but

rather as a supply for the integrated secondary protec-

tion circuitry. The integr at ed SCR is designed to trig-

ger when pin 6 (TBAT) or pin 23 (RBAT) drops 2 to 4 V

below the voltage on pin 28 (VBAT). This trigger pre-

v ents a fault induced ov ervolt age ev ent a t the T BAT or

RBAT nodes .

2.8 Battery Voltage Monit o r

The CPC7583 also uses the VBAT voltage to monitor

battery v oltage. If battery voltage is lost, the CPC7583

immediately enters the all-off st ate. It remains in this

state until the battery voltage is rest ored. The device

also enters the all-off state if t he bat tery volt age rises

above –10 V and remains in the all-off state unt il the

battery v oltag e drops below –15 V. This battery moni-

tor f eature dra ws a small current from the battery (less

than 1 µA typical) and will add slightly to t he device’s

overall power dissipation.

2.9 Protection

2.9.1 Diode Bridge/SCR

The CPC7583 uses a combination of current limited

break s witches, a diode bridge/SCR clamping circuit,

and a thermal shutdown mechanism to protect the

SLIC device or other associated circuitry from damage

during line transient e v ents such as lightning. During a

positive transient condition, the fault current is con-

ducted through the diode bridge to ground via F GND.

Voltage is clamped to a diode drop above ground.

During a negative transient of 2 to 4 V more negative

than the voltage at VBAT, the SCR conducts and faults

are shunted to FGND via the SCR and diode bridge.

In order f or the SCR to crowbar or f oldback, the on

v olt age (see “Protection Circuitry Electrical Specifica-

tions” on page 10) of the SCR must be less negative

than the VBAT voltage. I f t he VBAT voltage is less neg-

ativ e the TLINE and RLINE voltage, or if the V BAT sup-

ply is unab le to source the trigger current, the SCR will

not crowbar, however it will conduct fault currents to

ground.

F or po w er induction or po w er-cross fault conditions,

the positiv e cycle of the transient is clamped to a diode

drop above ground and the fault current directed to

ground. The negative cycle of the transie nt will ca use

the SCR to conduct when the voltage exceeds the

battery ref erence voltage by two to four volts , steering

the current to g round.

2.9.2 Current Limiting function

If a lightning strike transient occurs when the device in

the talk/idle state, the curre nt is passed along the line

to the integrat ed protection circuitry and restricted by

CPC7583

Rev. 2.0 9/16/2002 www.clare.com 15

the dynamic current limit response of br eak switches

SW1 and SW2. When a 1000V 10/1000 µS pulse

(GR-1089-CORE lightning) is applied to the line

though a properly clamped external protector, the cur-

rent seen at pin 6 (TBAT) or pin 23 (RBAT) will be a

pulse with a typical magnitude of 2.5 A and a duration

of less than 0.5 µs.

If a pow er-cross f ault occurs with the de vice in the t alk/

idle state, the current is passed though break s witches

SW1 and SW2 on to the integ rated protection circuit

and is limited by the dynamic DC current limit

response of the tw o break switches. The DC current

limit, specified over temperature, is betw een 80 mA

and 425 mA, and the circuitry has a negativ e tempera-

ture coefficient. As a res ult, if the device is subjected

to e xtended heating due to po wer cross f ault, the mea-

sured current at pin 6 (TBAT) or pin 23 (RBAT) will

decrease as the device temperature increases . If the

de vice te mper ature rises sufficiently, the temperature

shutdown mechanism will activate and the device will

default to the all-off state.

2.10 Temperature Shutdown

The thermal shutdown mechanism will activate when

the de vice temperature reaches a minimum of 110° C ,

placing the device in the all-off state regardless of

logic input. During thermal shutdown mode, pin 13

(TSD) will read 0 V. Normal output of TSD is +5 V.

If presented with a sh ort duration transient such as a

lightning e vent, the thermal shutdown feature will typi-

cally not activ ate . But in an e xt ended po wer-cross

transient, the de vice temper ature will rise and the ther-

mal shutdown will activate forcing th e switches to the

all-off state . At this point t he current measured at pin 6

(TBAT) and pin 23 (RBAT) will drop to zero. Once the

de vice enter s t hermal shutdown it will remain in the

all-off state until t he t emper ature of t he device drops

below the act ivation level of the thermal shutdown cir-

cuit. This will permit the de vice to re turn to normal

operation. If the transient has not passed, current will

flow up to the value allowed by the dynamic DC cur-

rent limiting of the switches and heating will begin

again, reactivating the thermal shutdown mechanism.

This cycle of entering and exiting the thermal shut-

down mode will contin ue as long as the fault condition

persists. If the magnitude of the f ault condit ion is great

enough, the e xternal secondary protector could acti-

v ate and shunt all current t o ground.

The thermal shutdown mechanism of the CPC7583

can be disab l ed by applying a logic 1 to pin 13 (TSD).

2.11 External Protection Elements

The CPC7583 requires only o vervolt age secondary

protection on the loop side of t he device. The inte-

grated protection featur e described abov e negates the

need f or protection on the line side. The secondary

protector limits voltage transients to lev els t hat do not

e xceed t he breakdo wn voltage or input-output isola-

tion barrier of the CPC7583. A f oldback or crowbar

type protector is recommended to minimize stresses

on the device.

Consult Clare’s application note, AN-100, “ Designing

Surge and Power Fault Protection Circuits for Solid

State Subscriber Line Interf aces” for equations related

to the specifications of external secondary protectors,

fused resistors and PTCs.

3. Manufacturing Information

3.1 Soldering

3.1.1 Moisture Reflow Sensitivity

Clare has characterized the moist ure reflow sensitivity

of LCAS products using IPC/JEDEC standar d J-STD-

020A. Moisture uptake from atmospheric humidity

occurs by diff usion. During the solder reflo w process ,

in which the component is attached to th e PCB, the

whole body of the component is exposed to high pro-

cess temperatures. The combination of moisture

uptake and high r eflo w soldering temperat ures may

lead to moisture induced delamination and cr acking of

the component. To prevent this, t his component must

be handled in accordance with IPC/JEDEC standard

J-STD-020A per the labelled mo isture sensitivit y level

(MSL), level 1 for the SOIC package, and level 3 f or

the MLP package .

3.1.2 Reflow Profile

The maximum ramp rates, dwell times, and tempera-

tures of the assemb ly reflo w profile should not exceed

those specified in IPC standard IPC-9502, table 2.

Soldering processes are limited to 220 °C component

body temperature .

CPC7583

16 www.clare.com Rev. 2.0 9/16/2002

3.2 Wa sh i ng

Clare does not recommend ultrasonic cleaning of

LCAS parts.

3.3 Mechanical D ime ns io n s

3.3.1 MLP Package

NOTE: For optim um solder joint size, MLP package

printed-circuit board pads should extend no more than

.05 mm past the chip post on t he sh ort sides, and no

more than .025 mm past the chip posts on the long

sides.

As the metallic pad on the bottom of the MLP package

is connected to the substr ate of t he die , Clare reco m-

mends that no printed circuit board to traces cross this

area to maintain minimum creepage and clearance

values.

3.3.2 SOIC Package

0.18 BSC

(0.0071)

0.18 BSC

(0.0071)

0.61 BSC

(0.0240)

0.37 BSC

(0.0146)

Pin 1

Bottom side

metallic pad

TOP VIEW

BOTTOM VIEW

SIDE VIEW

Seating Plane

Dimensions in mm (inches)

Dimensions and tolerances conform to ANSIY14.5M-1994

11.0 BSC

(0.4334).

7.0 BSC

(0.2758)

0.9 ± 0.1

(0.0355 ±0.0039)

0.02 ±0.03

(0.0008 ±0.0012)

0.2 BSC

(0.0079)

0.75 BSC

(0.0295)

0.60 BSC

(0.0236)

0.70 BSC

(0.0276)

0.33 -0.05 +0.07

(0.0130 -0.0020 +0.0028)

5.0

± 0.05

(0.1970

±0.0020)

0.55 ± 0.05 7.5 ± 0.05

(0.2955 ± 0.0020)

1.27 typ.

(0.050 typ.)

2.54 ±0.127

(0.100+/-0.005)

7.468 ±0.127

(0.294+/-0.005)

10.312 ±0.051

(0.406 ±0.003)

0.250 typ.

(0.010 typ.)

0.813 ±0.102

(0.032 ±0.004)

3 - 7

18.034 ±0.127

(0.710 ±0.005)

.330 x 45 max.

(.013 x 45 max.)

Dimensions in mm

(inches)

0.366 min. / 0.467 max. typ.

(0.014 min. / 0.018 max. typ.)

CPC7583

Rev. 2.0 9/16/2002 www.clare.com 17

3.3.3 MLP Tape Dimensions

16.00

R = .50

1.4

7.40

4.00

2.00

1.50

12.00

6.4

1.4

A0 =

B0 =

K0 =

K1 =

NOTES:1.ALL DIMENSIONS ARE IN MILLIMETERS AND CARRYTOLERANCES OF EIA

STANDARD 481-2. 2.THE TAPE COMPLIES WITH ALL "NOTES" FOR CONSTANT DIMENSIONS

LISTED ON PAGE 5 OF EIA-481-2.

6.4 mm

7.4 mm

1.4 mm

For additional information please visit www.clare.com

Clare, Inc. makes no representations or warrantie s with respect to the accura cy or completeness of the contents of this publication and reserves the right to make

changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set

forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its

products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.

The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intend ed for surgical implant into

the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a

person or severe property or environment al damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.

Specification: DS-CPC7583-R 2.0

9/16/2002