AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Features 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor AR0331 Datasheet, Rev. L For the latest datasheet, please visit www.onsemi.com Features light and high dynamic range scene performance. It is programmable through a simple two-wire serial interface. The AR0331 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, including surveillance and HD video. * Superior low-light performance * Latest 2.2 m pixel with ON Semiconductor A-PixTM technology * Full HD support at 1080P 60 fps for superior video performance * Linear or high dynamic range capture * 3.1M (4:3)and 1080P full HD (16:9) images * Optional adaptive local tone mapping (ALTM) * Interleaved T1/T2 output * Support for external mechanical shutter * Support for external LED or Xenon flash * Slow-motion video (VGA 120 fps) * On-chip phase-locked loop (PLL) oscillator * Integrated position-based color and lens shading correction * Slave mode for precise frame-rate control * Stereo/3D camera support * Statistics engine * Data interfaces: four-lane serial high-speed pixel interface (HiSPiTM) differential signaling (SLVS and HiVCM), or parallel * Auto black level calibration * High-speed context switching * Temperature sensor Table 1: * * * * * * * Typical Value Optical format 1/3-inch (5.8 mm) Note: Sensor optical format will also work with lenses designed for 1/3.2" format. Active pixels 2048(H) x 1536(V) (4:3, mode) Pixel size 2.2m x 2.2m Color filter array RGB Bayer Shutter type Electronic rolling shutter and GRR Input clock range 6 - 48 MHz Output clock maximum 148.5 Mp/s (4-lane HiSPi) 74.25 Mp/s (Parallel) Frame rate Video surveillance Stereo vision Smart vision Automation Machine vision 1080p60 video applications High dynamic range imaging The ON Semiconductor AR0331 is a 1/3-inch CMOS digital image sensor with an active-pixel array of 2048Hx1536V. It captures images in either linear or high dynamic range modes, with a rolling-shutter readout. It includes sophisticated camera functions such as in-pixel binning, windowing and both video and single frame modes. It is designed for both low 1 Serial HiSPi 10-, 12-, 14-, or 16-bit Parallel 10-, 12-bit Full resolution 30 fps 1080p 60 fps Responsivity 1.9 V/lux-sec SNRMAX 39 dB Max Dynamic range Up to 100 dB Supply voltage General Description AR0331_DS Rev. L Pub. 5/15 EN Parameter Output Applications Key Parameters I/O 1.8 or 2.8 V Digital 1.8 V Analog 2.8 V HiSPi 0.3V - 0.6V, 1.7 V - 1.9 V Power consumption (typical) <780 mW Operating temperature (ambient) -30C to + 85 C Package options 10 x 10 mm 48 pin iLCC 9.5 x 9.5 mm 63-pin iBGA (c)Semiconductor Components Industries, LLC 2015, AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Ordering Information Ordering Information Table 2: Available Part Numbers Part Number Product Description Orderable Product Attribute Description AR0331SRSC00SHCA0-DRBR 48-pin iLCC HiSPi, 0 CRA Dry Pack without Protective Film, Double Side BBAR Glass AR0331SRSC00SHCAD3-GEVK 48-pin iLCC HiSPi, 0 CRA Demo Kit 3 AR0331SRSC00SHCAD-GEVK 48-pin iLCC HiSPi, 0 CRA Demo Kit AR0331SRSC00SHCAH-GEVB 48-pin iLCC HiSPi, 0 CRA Demo Board AR0331SRSC00SUCA0-DPBR 48-pin iLCC Parallel, 0 CRA Dry Pack with Protective Film, Double Side BBAR Glass AR0331SRSC00SUCA0-DRBR 48-pin iLCC Parallel, 0 CRA Dry Pack without Protective Film, Double Side BBAR Glass AR0331SRSC00SUCAD3-GEVK 48-pin iLCC Parallel, 0 CRA Demo Kit 3 AR0331SRSC00SUCAD-GEVK 48-pin iLCC Parallel, 0 CRA Demo Kit AR0331SRSC00SUCAH-GEVB 48-pin iLCC Parallel, 0 CRA Demo Board AR0331SRSC00XUEAD3-GEVK 63-pin iBGA Demo Kit 3 AR0331SRSC00XUEAD-GEVK 63-pin iBGA Demo Kit AR0331SRSC00XUEAH-GEVB 63-pin iBGA Demo Board AR0331SRSC00XUEE0-BY-DRBR 63-pin iBGA, 0 CRA 0 Dry Pack without Protective Film, Double Side BBAR Glass AR0331SRSC00XUEE0-DPBR 63-pin iBGA, 0 CRA 0 Dry Pack with Protective Film, Double Side BBAR Glass AR0331SRSC00XUEE0-DRBR 63-pin iBGA, 0 CRA 0 Dry Pack without Protective Film, Double Side BBAR Glass AR0331SRSC00XUEE0-DRBR1 63-pin iBGA, 0 CRA 0 Dry Pack without Protective Film, Double Side BBAR Glass AR0331_DS Rev. L Pub. 5/15 EN 2 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Ordering Information AR0331_DS Rev. L Pub. 5/15 EN 3 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pixel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Pixel Output Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Pixel Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Gain Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Pedestals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 High Dynamic Range Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Sensor PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Sensor Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Subsampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Sensor Frame Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Frame Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Changing Sensor Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Two-Wire Serial Register Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Power-On Reset and Standby Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 AR0331_DS Rev. L Pub. 5/15 EN 3 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Typical Configuration: Serial Four-Lane HiSPi Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Typical Configuration: Parallel Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 48 iLCC Package, Parallel Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 48 iLCC Package, HiSPi Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 9.5 x 9.5 mm 63-Ball IBGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Imaging a Scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 HiSPi Transmitter and Receiver Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Block Diagram of DLL Timing Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Delaying the Clock with Respect to Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Delaying Data with Respect to the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Integration Control in ERS Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Example of 8.33ms Integration in 16.6ms Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 The Row Integration Time is Greater Than the Frame Readout Time . . . . . . . . . . . . . . . . . . . . . . . . . .23 Gain Stages in AR0331 Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 HDR Data Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 PLL Dividers Affecting VCO Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Sensor Dual Readout Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PLL for the Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 PLL for the Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Effect of Horizontal Mirror on Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Effect of Vertical Flip on Readout Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Horizontal Binning in the AR0331 Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Vertical Row Binning in the AR0331 Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Frame Period Measured in Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Slave Mode Active State and Vertical Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Slave Mode Example with Equal Integration and Frame Readout Periods . . . . . . . . . . . . . . . . . . . . . .38 Slave Mode Example Where the Integration Period is Half of the Frame Readout Period . . . . . . . . .39 Example of the Sensor Output of a 1928 x 1088 Frame at 60 fps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Example of the Sensor Output of a 1928 x1088 Frame at 30 fps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Example of Changing the Sensor from Context A to Context B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Frame Format with Embedded Data Lines Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Format of Embedded Statistics Output within a Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Single READ from Current Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Quantum Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 I/O Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Power Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 48 iLCC Parallel Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 48 iLCC HiSPi Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 63-Ball iBGA Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 AR0331_DS Rev. L Pub. 5/15 EN 4 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Key Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Pin Descriptions, 48 iLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Pin Descriptions, 9.5 x 9.5 mm, 63-ball iBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Output Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Configuration of the Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Recommended Sensor Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Companding Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Knee Points for Compression from 16 Bits to 12 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Bit Operation After Linearization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 PLL Parameters for the Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Example PLL Configuration for the Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 PLL Parameters for the Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Example PLL Configurations for the Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Minimum Vertical Blanking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Serial SYNC Codes Included with Each Protocol Included with the AR0331 Sensor . . . . . . . . . . . . . .40 List of Configurable Registers for Context A and Context B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 A-Law Compression Table for 12-10 bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Test Pattern Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Two-Wire Serial Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 I/O Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Operating Current Consumption in Parallel Output and Linear Mode . . . . . . . . . . . . . . . . . . . . . . . . .58 Operating Current Consumption in Parallel Output and HDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . .58 Operating Current in HiSPi (HiVCM) Output and Linear Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Operating Current in HiSPi (HiVCM) Output and HDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Operating Current in HiSPi (SLVS) Output and Linear Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Operating Current in HiSPi (SLVS) Output and HDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Channel Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Clock DLL Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Data DLL Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 AR0331_DS Rev. L Pub. 5/15 EN 5 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor General Description General Description The ON Semiconductor AR0331 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. The default mode output is a 1080presolution image at 60 frames per second (fps). In linear mode, it outputs 12-bit or 10-bit A-Law compressed raw data, using either the parallel or serial (HiSPi) output ports. In high dynamic range mode, it outputs 12-bit compressed data using parallel output. In HiSPi mode, 12- or 14-bit compressed, or 16-bit linearized data may be output. The device may be operated in video (master) mode or in single frame trigger mode. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a synchronized pixel clock in parallel mode. The AR0331 includes additional features to allow application-specific tuning: windowing and offset, auto black level correction, and on-board temperature sensor. Optional register information and histogram statistic information can be embedded in the first and last 2 lines of the image frame. The sensor is designed to operate in a wide temperature range (-30C to +85C). Functional Overview The AR0331 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 48 MHz. The maximum output pixel rate is 148.5 Mp/s, corresponding to a clock rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor. Figure 1: Block Diagram 12 ADC data Row noise correction Companding Black level correction Test pattern generator Pixel defect correction 12 Adaptive CD filter 12 bits ( HDR and Linear), 12 or 10 bits Linear 16, 14, or 12 bits Motion correction and Blue Halo filter Parallel HiSPi HDR linearization (ME or DLO) 16 Smooting filter Digital gain and pedestal AR0331_DS Rev. L Pub. 5/15 EN 6 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Functional Overview User interaction with the sensor is through the two-wire serial bus, which communicates with the array control, analog signal chain, and digital signal chain. The core of the sensor is a 3.1 Mp Active- Pixel Sensor array. The timing and control circuitry sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. The exposure is controlled by varying the time interval between reset and readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an analogto-digital converter (ADC). The output from the ADC is a 12-bit value for each pixel in the array. The ADC output passes through a digital processing signal chain (which provides further data path corrections and applies digital gain). The sensor also offers a high dynamic range mode of operation where multiple images are combined on-chip to produce a single image at 16-bit per pixel value. A compression mode is further offered to allow the 16-bit pixel value to be transmitted to the host system as a 12-bit value with close to zero loss in image quality. Typical Configuration: Serial Four-Lane HiSPi Interface VDD_IO 1.5k2 1.5k2 Digital Digital I/O Core power1 power1 VDD Master clock (6-48 MHz) EXTCLK From controller SADDR SDATA SCLK TRIGGER OE_BAR RESET_BAR HiSPi power1 VDD_SLVS Figure 2: VDD Notes: AR0331_DS Rev. L Pub. 5/15 EN VDD_SLVS VDD_PLL VAA VDD_PLL VAA VAA_PIX SLVS0_P SLVS0_N SLVS1_P SLVS1_N SLVS2_P SLVS2_N SLVS3_P SLVS3_N SLVSC_P SLVSC_N FLASH SHUTTER TEST VDD_IO PLL Analog Analog power1 power1 power1 DGND AGND Digital ground Analog ground To controller VAA_PIX 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for slower two-wire speed. 3. The parallel interface output pads can be left unconnected if the serial output interface is used. 4. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on lay- 7 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Functional Overview out and design considerations. Refer to the AR0331 demo headboard schematics for circuit recommendations. 5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. Figure 3: Typical Configuration: Parallel Pixel Data Interface 1.5k2, 1.5k2 Digital Digital core I/O power1 power1 Master clock (6-48 MHz) VDD_IO PLL Analog Analog power1 power1 power1 VDD DOUT [11:0] EXTCLK PIXCLK LINE_VALID FRAME_VALID SADDR SDATA SCLK TRIGGER OE_BAR From Controller VAA_PIX VDD_PLL VAA To controller FLASH SHUTTER RESET_BAR TEST DGND VDD_IO VDD VDD_PLL VAA VAA_PIX Digital ground Notes: AR0331_DS Rev. L Pub. 5/15 EN AGND Analog ground 1. All power supplies must be adequately decoupled. 2. ON Semiconductor recommends a resistor value of 1.5k, but a greater value may be used for slower two-wire speed. 3. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output interface is used. 4. ON Semiconductor recommends that 0.1F and 10F decoupling capacitors for each power supply are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Refer to the AR0331 demo headboard schematics for circuit recommendations. 5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized. 6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents. 7. The EXTCLK input is limited to 6-48 MHz. 8 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Functional Overview 7 6 5 4 3 2 1 48 47 46 45 44 43 E X T C LK V DD_P LL D OUT6 D OUT5 D OUT4 D OUT3 D OUT2 D OUT1 D OUT0 D GND NC 48 iLCC Package, Parallel Output D GND Figure 4: D OUT 7 NC 42 8 D OUT 8 NC 41 9 D OUT 9 V AA 40 10 D OUT 10 A GND 39 11 D OUT 11 V AA_P IX 38 12 V DD_IO V AA_P IX 37 13 P IX C LK V AA 36 14 V DD A GND 15 S CLK V AA 34 16 S DATA Reserved 33 17 R E S E T _BAR NC 32 Reserved 31 AR0331_DS Rev. L Pub. 5/15 EN FLASH T R IG G E R F R A M E _V A LID LIN E _V A LID 22 23 24 25 26 27 28 29 9 D GND TEST 21 S ADDR 20 OE_BAR NC 19 NC NC V DD_IO V DD 18 35 30 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Functional Overview Table 1: Pin Descriptions Pin Number Name Type Description 1 DOUT4 Output Parallel pixel data output. 2 DOUT5 Output Parallel pixel data output. 3 DOUT6 Output Parallel pixel data output. 4 VDD_PLL Power PLL power. 5 EXTCLK Input External input clock. 6 DGND Power Digital ground. 7 DOUT7 Output Parallel pixel data output. 8 DOUT8 Output Parallel pixel data output. Output Parallel pixel data output. 9 DOUT9 10 DOUT10 Output Parallel pixel data output. 11 DOUT11 Output Parallel pixel data output (MSB). 12 VDD_IO Power I/O supply power. 13 PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this clock. 14 VDD Power Digital power. 15 SCLK Input Two-Wire Serial clock input. 16 SDATA I/O 17 RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default. 18 VDD_IO Power I/O supply power. 19 VDD Power Digital power. 20 NC 21 NC 22 NC 23 OE_BAR Input Output enable (active LOW). 24 SADDR Input Two-Wire Serial address select. 0: 0x20. 1: 0x30 Two-Wire Serial data I/O. 25 TEST Input 26 FLASH Output 27 TRIGGER Input 28 FRAME_VALID Output Asserted when DOUT frame data is valid. 29 LINE_VALID Output Asserted when DOUT line data is valid. 30 DGND Power Digital ground Output Control for external mechanical shutter. Can be left floating if not used. Analog power. 31 Reserved 32 SHUTTER 33 Reserved Manufacturing test enable pin (connect to DGND). Flash output control. Receives slave mode VD signal for frame rate synchronization and trigger to start a GRR frame. 34 VAA Power 35 AGND Power Analog ground. 36 VAA Power Analog power. 37 VAA_PIX Power Pixel power. 38 VAA_PIX Power Pixel power. 39 AGND Power Analog ground. 40 VAA Power Analog power. 41 NC AR0331_DS Rev. L Pub. 5/15 EN 10 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Functional Overview Table 1: Pin Descriptions (continued) Pin Number Name 42 NC 43 NC Type Description 44 DGND Power Digital ground. 45 DOUT0 Output Parallel pixel data output (LSB) 46 DOUT1 Output Parallel pixel data output. 47 DOUT2 Output Parallel pixel data output. 48 DOUT3 Output Parallel pixel data output. 6 5 4 3 2 1 48 47 46 45 44 43 SLVS0_N SLVS0_P SLVS1_N SLVS1_P SLVSC_N SLVSC_P SLVS2_N SLVS2_P SLVS3_N SLVS3_P D GND 48 iLCC Package, HiSPi Output NC Figure 5: A GND 7 V DD_SLVS 8 V DD_IO 9 D GND NC 40 10 V DD NC 39 11 EXTC LK V AA 12 V DD NC 37 13 D GND V AA_P IX 36 14 V DD_IO V AA_P IX AR0331_DS Rev. L Pub. 5/15 EN 35 21 22 23 Reserved 20 V DD_PLL 19 D GND 31 FLASH A GND T R IG G E R 32 R E S E T _BAR OE_BAR V AA NC TEST NC Reserved S ADDR 18 38 S CLK V DD_IO 17 41 S DATA D GND 16 42 SHUTTER V DD 15 V AA 24 25 26 27 28 29 30 11 34 33 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Functional Overview Table 2: Pin Descriptions, 48 iLCC Pin Number Name Type Description 1 SLVSC_N Output HiSPi serial DDR clock differential N. 2 SLVS1_P Output HiSPi serial data, lane 1, differential P. 3 SLVS1_N Output HiSPi serial data, lane 1, differential N. 4 SLVS0_P Output HiSPi serial data, lane 0, differential P. 5 SLVS0_N Output HiSPi serial data, lane 0, differential N. 6 NC 7 VDD_SLVS Power 0.3V-0.6V or 1.7V - 1.9V port to HiSPi Output Driver. Set the High_VCM (R0x306E[9]) bit to 1 when configuring VDD_SLVS to 1.7 - 1.9V. 8 VDD_IO Power I/O supply power. 9 DGND Power Digital ground. 10 VDD Power Digital power. 11 EXTCLK Input External input clock. 12 VDD Power Digital power. 13 DGND 14 VDD_IO 15 SDATA I/O 16 SCLK Input Digital ground. Power I/O supply power. Two-Wire Serial data I/O. Two-Wire Serial clock input. 17 TEST 18 RESET_BAR Input Manufacturing test enable pin (connect to DGND). Asynchronous reset (active LOW). All settings are restored to factory default. 19 VDD Power Digital power. 20 DGND Power Digital ground. 21 VDD_IO Power I/O supply power. Input Two-Wire Serial address select. 0: 0x20. 1: 0x30 22 NC 23 SADDR 24 NC 25 OE_BAR 26 TRIGGER Input Output enable (active LOW). 27 FLASH Output Receives slave mode VD signal for frame rate synchronization and trigger to start a GRR frame. Flash output control. 28 DGND Power 29 VDD_PLL Power PLL power. 30 Reserved 31 AGND Power Analog ground. 32 VAA Power Analog power. 33 Reserved 34 SHUTTER Output Control for external mechanical shutter. Can be left floating if not used. 35 VAA_PIX Power Pixel power. 36 VAA_PIX Power Pixel power. 37 NC Power Analog power. 38 VAA 39 NC 40 NC AR0331_DS Rev. L Pub. 5/15 EN 12 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Functional Overview Table 2: Pin Descriptions, 48 iLCC (continued) Pin Number Name Type Description 41 VAA Power Analog power. 42 AGND Power Analog ground. 43 DGND Power Digital ground. 44 SLVS3_P Output HiSPi serial data, lane 3, differential P. 45 SLVS3_N Output HiSPi serial data, lane 3, differential N. 46 SLVS2_P Output HiSPi serial data, lane 2, differential P. 47 SLVS2_N Output HiSPi serial data, lane 2, differential N 48 SLVSC_P Output HiSPi serial DDR clock differential P. Figure 6: 9.5 x 9.5 mm 63-Ball IBGA Package 1 A 2 3 5 SLVS0_N SLVS0_P SLVS1_N SLVS2_N B VDD_PLL SLVS_CN SLVSC_P C EXTCLK VDD_ SLVS SLVS3_N D SADDR E LINE_ VALID F G H 4 SLVS3_P 6 7 8 VDD VDD NC SLVS2_P VDD VAA VAA DGND VDD AGND AGND VAA_PIX VAA_PIX SLVS1_P SDATA DGND DGND VDD FRAME_ VALID PIXCLK FLASH DGND VDD_IO NC SHUTTER DOUT8 DOUT9 DOUT10 DOUT11 DGND VDD_IO TEST Reserved (NC) DOUT4 DOUT5 DOUT6 DOUT7 DGND VDD_IO TRIGGER OE_BAR VDD_IO RESET_ BAR DOUT0 SCLK DOUT1 DOUT2 DOUT3 DGND VDD_IO Top View (Ball Down) AR0331_DS Rev. L Pub. 5/15 EN 13 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Functional Overview Table 3: Pin Descriptions, 9.5 x 9.5 mm, 63-ball iBGA Name iBGA Pin Type Description SLVS0_N A2 Output HiSPi serial data, lane 0, differential N. SLVS0_P A3 Output HiSPi serial data, lane 0, differential P. SLVS1_N A4 Output HiSPi serial data, lane 1, differential N. SLVS1_P A5 Output HiSPi serial data, lane 1, differential P. VDD_PLL B1 Power PLL power. SLVSC_N B2 Output HiSPi serial DDR clock differential N. SLVSC_P B3 Output HiSPi serial DDR clock differential P. SLVS2_N B4 Output HiSPi serial data, lane 2, differential N. SLVS2_P B5 Output HiSPi serial data, lane 2, differential P. VAA B7, B8 Power Analog power. EXTCLK C1 Input External input clock. VDD_SLVS C2 Power 0.3V-0.6V or 1.7V - 1.9V port to HiSPi Output Driver. Set the High_VCM (R0x306E[9]) bit to 1 when configuring VDD_SLVS to 1.7 - 1.9V. SLVS3_N C3 Output HiSPi serial data, lane 3, differential N. SLVS3_P C4 Output HiSPi serial data, lane 3, differential P. DGND Power VDD C5, D4, D5, E5, F5, G5, H5 A6, A7, B6, C6, D6 Power Digital power. AGND C7, C8 Power Analog ground. SADDR D1 Input Two-Wire Serial address select. 0: 0x20. 1: 0x30 SCLK D2 Input Two-Wire Serial clock input. Digital ground. SDATA D3 I/O VAA_PIX D7, D8 Power Pixel power. LINE_VALID E1 Output Asserted when DOUT line data is valid. FRAME_VALID E2 Output Asserted when DOUT frame data is valid. Two-Wire Serial data I/O. PIXCLK E3 Output Pixel clock out. DOUT is valid on rising edge of this clock. VDD_IO E6, F6, G6, H6, H7 Power I/O supply power. DOUT8 F1 Output Parallel pixel data output. DOUT9 F2 Output Parallel pixel data output. DOUT10 F3 Output Parallel pixel data output. DOUT11 F4 Output Parallel pixel data output (MSB) TEST F7 Input. Manufacturing test enable pin (connect to DGND). DOUT4 G1 Output Parallel pixel data output. DOUT5 G2 Output Parallel pixel data output. DOUT6 G3 Output Parallel pixel data output. DOUT7 G4 Output Parallel pixel data output. TRIGGER G7 Input Exposure synchronization input. OE_BAR G8 Input DOUT0 H1 Output Parallel pixel data output (LSB) DOUT1 H2 Output Parallel pixel data output. DOUT2 H3 Output Parallel pixel data output. DOUT3 H4 Output Parallel pixel data output. AR0331_DS Rev. L Pub. 5/15 EN Output enable (active LOW). 14 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Functional Overview Table 3: Pin Descriptions, 9.5 x 9.5 mm, 63-ball iBGA (continued) Name iBGA Pin Type Description RESET_BAR H8 Input Asynchronous reset (active LOW). All settings are restored to factory default. SHUTTER E8 Output Control for external mechanical shutter. Can be left floating if not used. FLASH E4 Output Flash control output. NC A8, E7 Reserved F8 AR0331_DS Rev. L Pub. 5/15 EN 15 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Pixel Data Format Pixel Data Format Pixel Array Structure While the sensor's format is 2048x1536, additional active columns and active rows are included for use when horizontal or vertical mirrored readout is enabled, to allow readout to start on the same pixel. The pixel adjustment is always performed for monochrome or color versions. The active area is surrounded with optically transparent dummy pixels to improve image uniformity within the active area. Not all dummy pixels or barrier pixels can be read out. Figure 7: Pixel Array Description 2064 16 barrier + 4 border pixels 20521 x 1536 4.51mm x 3.38 mm 1578 2 barrier + 4 border pixels 2 barrier + 4 border pixels 18 barrier + 4 border pixels Light dummy pixel Notes: AR0331_DS Rev. L Pub. 5/15 EN Active pixel 1. Maximum of 2048 columns is supported. Additional columns included for mirroring operations. 16 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Pixel Data Format Figure 8: Pixel Color Pattern Detail (Top Right Corner) Column Readout Direction Row Readout Direction Active Pixel (0,0) Array Pixel (0, 0) R G R G R G R G G B G B G B G B R G R G R G R G G B G B G B G B R G R G R G R G G B G B G B G B Default Readout Order By convention, the sensor core pixel array is shown with pixel (0,0) in the top right corner (see Figure 8). This reflects the actual layout of the array on the die. Also, the first pixel data read out of the sensor in default condition is that of pixel (0, 0). When the sensor is imaging, the active surface of the sensor faces the scene as shown in Figure 9. When the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced as shown in Figure 9. Figure 9: Imaging a Scene Lens Scene Sensor (rear view) Row Readout Order Column Readout Order AR0331_DS Rev. L Pub. 5/15 EN Pixel (0,0) 17 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Pixel Output Interfaces Pixel Output Interfaces Parallel Interface The parallel pixel data interface uses these output-only signals: * FRAME_VALID * LINE_VALID * PIXCLK * DOUT[11:0] The parallel pixel data interface is disabled by default at power up and after reset. It can be enabled by programming R0x301A. Table 5 shows the recommended settings. When the parallel pixel data interface is in use, the serial data output signals can be left unconnected. Set reset_register [bit 12 (R0x301A[12] = 1)] to disable the serializer while in parallel output mode. Output Enable Control When the parallel pixel data interface is enabled, its signals can be switched asynchronously between the driven and High-Z under pin or register control, as shown in Table 4. Table 4: Output Enable Control OE_BAR Pin Drive Pins R0x301A[6] Description 1 X 0 0 1 X Interface High-Z Interface driven Interface driven Configuration of the Pixel Data Interface Fields in R0x301A are used to configure the operation of the pixel data interface. The supported combinations are shown in Table 5. Table 5: Configuration of the Pixel Data Interface Serializer Disable R0x301 A[12] Parallel Enable R0x301 A[7] 0 0 Power up default. Serial pixel data interface and its clocks are enabled. Transitions to soft standby are synchronized to the end of frames on the serial pixel data interface. 1 1 Parallel pixel data interface, sensor core data output. Serial pixel data interface and its clocks disabled to save power. Transitions to soft standby are synchronized to the end of frames in the parallel pixel data interface. Description High Speed Serial Pixel Data Interface The High Speed Serial Pixel (HiSPi) interface uses four data lanes and one clock as output. * SLVSC_P * SLVSC_N * SLVS0_P * SLVS0_N * SLVS1_P * SLVS1_N AR0331_DS Rev. L Pub. 5/15 EN 18 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Pixel Output Interfaces * * * * SLVS2_P SLVS2_N SLVS3_P SLVS3_N The HiSPi interface supports three protocols, Streaming-S, Streaming-SP, and Packetized SP. The streaming protocols conform to a standard video application where each line of active or intra-frame blanking provided by the sensor is transmitted at the same length. The Packetized SP protocol will transmit only the active data ignoring line-to-line and frame-to-frame blanking data. These protocols are further described in the High-Speed Serial Pixel (HiSPiTM) Interface Protocol Specification V1.50.00. The HiSPi interface building block is a unidirectional differential serial interface with four data and one double data rate (DDR) clock lanes. One clock for every four serial data lanes is provided for phase alignment across multiple lanes. Figure 10 shows the configuration between the HiSPi transmitter and the receiver. Figure 10: HiSPi Transmitter and Receiver Interface Block Diagram A camera containing the HiSPi transmitter Tx PHY0 A host (DSP) containing the HiSPi receiver Dp0 Dp0 Dn0 Dn0 Dp1 Dp1 Dn1 Dn1 Dp2 Dp2 Dn2 Dn2 Dp3 Dp3 Dn3 Dn3 Cp0 Cp0 Cn0 Cn0 Rx PHY0 HiSPi Physical Layer The HiSPi physical layer is partitioned into blocks of four data lanes and an associated clock lane. Any reference to the PHY in the remainder of this document is referring to this minimum building block. The PHY will serialize 10-, 12-, 14-, or 16-bit data words and transmit each bit of data centered on a rising edge of the clock, the second on the falling edge of the clock. Figure 11 shows bit transmission. In this example, the word is transmitted in order of MSB to LSB. The receiver latches data at the rising and falling edge of the clock. AR0331_DS Rev. L Pub. 5/15 EN 19 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Pixel Output Interfaces Figure 11: Timing Diagram TxPost cp .... cn TxPre dp .... MSB dn LSB 1 UI DLL Timing Adjustment The specification includes a DLL to compensate for differences in group delay for each data lane. The DLL is connected to the clock lane and each data lane, which acts as a control master for the output delay buffers. Once the DLL has gained phase lock, each lane can be delayed in 1/8 unit interval (UI) steps. This additional delay allows the user to increase the setup or hold time at the receiver circuits and can be used to compensate for skew introduced in PCB design. Delay compensation may be set for clock and/or data lines in the hispi_timing register R0x31C0. If the DLL timing adjustment is not required, the data and clock lane delay settings should be set to a default code of 0x000 to reduce jitter, skew, and power dissipation. delay data _lane 0 AR0331_DS Rev. L Pub. 5/15 EN delay delay DATA3_DEL[2:0] DATA2_DEL[2:0] DATA1_DEL[2:0] CLOCK_DEL[2:0] Block Diagram of DLL Timing Adjustment DATA0_DEL[2:0] Figure 12: delay delay data _lane 1 clock _lane 0 data _lane 2 data _lane 3 20 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Pixel Output Interfaces Figure 13: Delaying the Clock with Respect to Data 1 UI dataN (DATAN_DEL = 000) cp (CLOCK_DEL = 000) cp (CLOCK_DEL = 001) cp (CLOCK_DEL = 010) cp (CLOCK_DEL = 011) cp (CLOCK_DEL = 100) cp (CLOCK_DEL = 101) c p (CLOCK_DEL = 110) cp (CLOCK_DEL =111) increasing CLOCK_DEL[2:0] increases clock delay Figure 14: Delaying Data with Respect to the Clock cp ( CLOCK_DEL = 000) dataN (DATAN_DEL = 000) dataN(DATAN_DEL = 001) dataN(DATAN_DEL = 010) dataN(DATAN_DEL = 011) dataN(DATAN_DEL = 100) dataN(DATAN_DEL = 101) dataN(DATAN_DEL = 110) dataN(DATAN_DEL = 111) increasing DATAN_DEL[2:0] increases data delay t DLLSTEP 1 UI HiSPi Protocol Layer The HiSPi protocol is described the HiSPi Protocol Specification document. AR0331_DS Rev. L Pub. 5/15 EN 21 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Pixel Sensitivity Serial Configuration The serial format should be configured using R0x31AC. Refer to the AR0331 Register Reference document for more detail regarding this register. The serial_format register (R0x31AE) controls which serial format is in use when the serial interface is enabled (reset_register[12] = 0). The following serial formats are supported: * 0x0304 - Sensor supports quad-lane HiSPi operation * 0x0302 - Sensor supports dual-lane HiSPi operation * 0x0301 - Sensor supports single-lane HiSPi operation Pixel Sensitivity Figure 15: Integration Control in ERS Readout Row Integration (TINTEGRATION) Row Reset (Start of Integration) Row Readout A pixel's integration time is defined by the number of clock periods between a row's reset and read operation. Both the read followed by the reset operations occur within a row period (TROW ) where the read and reset may be applied to different rows. The read and reset operations will be applied to the rows of the pixel array in a consecutive order. The coarse integration time is defined by the number of row periods (TROW ) between a row's reset and the row read. The row period is defined as the time between row read operations (see Sensor Frame Rate). TCOARSE = TROW * coarse_integration_time AR0331_DS Rev. L Pub. 5/15 EN 22 (EQ 1) (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Gain Stages Figure 16: Example of 8.33ms Integration in 16.6ms Frame TCOARSE = coarse_integration_time x TROW 8.33 ms =563 rows x 22.22 s/row Read Reset Horizontal Blanking Vertical Blanking TFRAME = frame_length_lines x TROW 16.6 ms = 750 rows x 22.22 s/row Time Vertical Blanking Figure 17: The Row Integration Time is Greater Than the Frame Readout Time TCOARSE = coarse_integration_time* TROW 20.7ms = 1390 rows *14.8us/row Read Pointer Horizontal Blanking Vertical Blanking TFRAME = Frame_length_lines * TROW Image 16.6ms = 1125 rows *14.8us/row Vertical Blanking Time Shutter Pointer Horizontal Blanking Extended Vertical Blanking 4.1ms Image The minimum frame-time is defined by the number of row periods per frame and the row period. The sensor frame-time will increase if the coarse_integration_time is set to a value equal to or greater than the frame_length_lines. Gain Stages The analog gain stages of the AR0331 sensor are shown in Figure 18. The sensor analog gain stage consists of a variable ADC reference. The sensor will apply the same analog gain to each color channel. Digital gain can be configured to separate levels for each color channel. AR0331_DS Rev. L Pub. 5/15 EN 23 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Gain Stages Figure 18: Gain Stages in AR0331 Sensor ADC Reference Digital Gain with Dithering 1x to 16x 1x, 2x, 4x, and 8x (128 steps per 6dB) The level of analog gain applied is controlled by the coarse_gain register. The recommended analog gain settings are listed in Table 6. A minimum analog gain of 1.23x is recommended. Changes to these registers should be done prior to streaming images. Table 6: Recommended Sensor Gain coarse_gain (0x3060[5:4])/ coarse_gain_cb (0x3060[13:12]) fine_gain (0x3060[3:0])/ fine_gain_cb (0x3060[11:8]) ADC Gain 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 2 2 2 3 6 7 8 9 10 11 12 13 14 15 0 2 4 6 8 10 12 14 0 4 8 12 0 1.23 1.28 1.34 1.39 1.45 1.52 1.60 1.69 1.78 1.88 2.00 2.14 2.28 2.47 2.67 2.91 3.20 3.56 4 4.56 5.34 6.41 8 Each digital gain can be configured from a gain of 0 to 15.992. The digital gain supports 128 gain steps per 6dB of gain. The format of each digital gain register is "xxxx.yyyyyyy" where "xxxx" refers an integer gain of 1 to 15 and "yyyyyyy" is a fractional gain ranging from 0/128 to 127/128. The sensor includes a digital dithering feature to reduce quantization noise resulting from using digital gain. It can be disabled by setting R0x30BA[5] to 0. The default value is 1. AR0331_DS Rev. L Pub. 5/15 EN 24 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Pedestals Pedestals There are two types of constant offset pedestals that may be adjusted at the end of the datapath. The data pedestal is a constant offset that is added to pixel values at the end of the datapath. The default offset when ALTM is disabled is 168 and is a 12-bit offset. This offset matches the maximum range used by the corrections in the digital readout path. The purpose of the data pedestal is to convert negative values generated by the digital datapath into positive output data. It is recommended that the data pedestal be set to 16 when ALTM is enabled. The data pedestal value can be changed from its default value by adjusting register R0x301E. The ALTM pedestal (R0x2450) is also located at the end of the datapath. The ALTM pedestal default offset is 0. High Dynamic Range Mode By default, the sensor powers up in HDR Mode. The HDR scheme used is multi-exposure HDR. This allows the sensor to handle up to 100dB of dynamic range. In HDR mode, the sensor sequentially captures two exposures by maintaining two separate read and reset pointers that are interleaved within the rolling shutter readout. The intermediate pixel values are stored in line buffers while waiting for the two exposure values to be present. As soon as a pixel's two exposure values are available, they are combined to create a linearized 16-bit value for each pixel's response. Depending on whether HiSPi or Parallel mode is selected, the full 16 bit value may be output, it can be compressed to 12 bits using Adaptive Local Tone Mapping (ALTM), or companded to 12 or 14 bits. Adaptive Local Tone Mapping Real- world scenes often have a very high dynamic range (HDR) that far exceeds the electrical dynamic range of the imager. Dynamic range is defined as the luminance ratio between the brightest and the darkest objects in a scene. Even though the AR0331 can capture full dynamic range images, the images are still limited by the low dynamic range of display devices. Today's typical LCD monitor has a contrast ratio around 1,000:1 while it is not atypical for an HDR image having a contrast ratio of around 250,000:1. Therefore, in order to reproduce HDR images on a low dynamic range display device, the captured high dynamic range must be compressed to the available range of the display device. This is commonly called tone mapping. The AR0331 has implemented an adaptive local tone mapping (ALTM) feature to reproduce visually appealing images that increase the local contrast and the visibility of the images. When ALTM is enabled, the gamma in the backend ISP should be set to 1 for proper display. See the AR0331 Developer Guide for more information on ALTM. AR0331_DS Rev. L Pub. 5/15 EN 25 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor High Dynamic Range Mode Companding The 16-bit linearized HDR image may be compressed to 12 bits using on-chip companding. Figure 19 illustrates the compression from 16- to 12-bits. Companding is enabled by setting R0x31D0. Table 8 shows the knee points for the different modes. Figure 19: HDR Data Compression 4500 4000 3500 3000 2500 12-bit Code Output 2000 1500 1000 500 0 0 Table 7: 10000 20000 30000 40000 16-bit Code Input 50000 60000 70000 Companding Table Segment 1 Segment 2 Segment 3 Segment 4 Input Code Range 0 to 1023 1024 to 4095 4096 to 32767 32768 to 65535 3456 to 3967 Output Code Range 0 to 1023 1024 to 2559 2560 to 3455 Companding Formula Pout = Pin Pout = (Pin - 1024)/2 + 1024 Pout = (Pin - 4096)/32 + 2560 Pout = (Pin - 32768)/64 + 3456 Decompanding Formula Pout = Pin Pout = (Pin - 1024)*2 + 1024 Pout = (Pin - 2560)*32 + 4096 Pout = (Pin - 3456)*64 + 32768 Table 9 illustrates the input and output codes as well as companding and decompanding formulas for each of the four colored segments in Figure 19. AR0331_DS Rev. L Pub. 5/15 EN 26 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor High Dynamic Range Mode Table 8: Knee Points for Compression from 16 Bits to 12 Bits T1/T2 Exposure Ratio (R1) R0x3082[3:2] P1 POUT1 = P1 P2 POUT2= (P2 - P1)/2 + 1024 P3 POUT3= (P3 - P2)/32 + 2560 PMAX POUTMAX = (PMAX - P3)/64 +3456 4x, 8x, 16x, 32x 210 1024 212 2560 215 3456 216 3968 As described in Table 8, the AR0331 companding block operates on 16-bit input only. For the exposure ratios that do not result in 16-bits, bit shifting occurs before the data enters the companding block. As a result of the bit shift, data needs to be unshifted after linearization in order to obtain the proper image. Table 9 provides the bit operation that should occur to the data after linearization. Table 9: Bit Operation After Linearization ratio_t1_t2 (R0x3082[3:2])/ ratio_t1_t2_cb (R0x3084[3:2]) Bit Shift Operation after Linearization 4x 8x 16x 32x Right shift 2 bits Right shift 1 bit No shift Left shift 1 bit HDR-Specific Exposure Settings In HDR mode, pixel values are stored in line buffers while waiting for both exposures to be available for final pixel data combination. There are 70 line buffers used to store intermediate T1 data. Due to this limitation, the maximum coarse integration time possible for a given exposure ratio is equal to 70*T1/T2 lines. For example, if R0x3082[3:2] = 2, the sensor is set to have T1/T2 ratio = 16x. Therefore the maximum number of integration lines is 70*16 = 1120 lines. If coarse integration time is greater than this, the T2 integration time will stay at 70. The sensor will calculate the ratio internally, enabling the linearization to be performed. If companding is being used, then relinearization would still follow the programmed ratio. For example if the T1/T2 ratio was programmed to 16x but coarse integration was increased beyond 1120 then one would still use the 16x relinearization formulas. An additional limitation is the maximum number of exposure lines in relation to the frame_length_lines register. In linear mode, maximum coarse_integration_time = frame_length_lines - 1. However in HDR mode, since the coarse integration time register controls T1, the max coarse integration time is frame_length_lines - 71. Putting the two criteria listed above together, the formula is as follows: maximum coarse_integration_time = minimum 70 T1 T2, frame_length_lines - 71 (EQ 2) There is a limitation of the minimum number of exposure lines, which is one row time for linear mode. In HDR mode, the minimum number of rows required is half of the ratio T1/T2. AR0331_DS Rev. L Pub. 5/15 EN 27 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Reset Motion Compensation In typical multi-exposure HDR systems, motion artifacts can be created when objects move during the T1 or T2 integration time. When this happens, edge artifacts can potentially be visible and might look like a ghosting effect. To correct this, the AR0331 has special 2D motion compensation circuitry that detects motion artifacts and corrects the image. The motion compensation feature can be enabled by setting R0x318C[14] = 1. Additional parameters are available to control the extent of motion detection and correction as per the requirements of the specific application. For more information, refer to the AR0331 Register Reference document and the AR0331 Developer Guide. Reset The AR0331 may be reset by the RESET_BAR pin (active LOW) or the reset register. Hard Reset of Logic The RESET_BAR pin can be connected to an external RC circuit for simplicity. The recommended RC circuit uses a 10k resistor and a 0.1F capacitor. The rise time for the RC circuit is 1s maximum. Soft Reset of Logic Soft reset of logic is controlled by the R0x301A Reset register. Bit 0 is used to reset the digital logic of the sensor. Furthermore, by asserting the soft reset, the sensor aborts the current frame it is processing and starts a new frame. This bit is a self-resetting bit and also returns to "0" during two-wire serial interface reads. Sensor PLL VCO Figure 20: PLL Dividers Affecting VCO Frequency EXTCLK (6-48 MHz) pre_pll_clk_div 2 (1-64) pll_multiplier 58 (32-384) FVCO The sensor contains a phase-locked loop (PLL) that is used for timing generation and control. The required VCO clock frequency is attained through the use of a pre-PLL clock divider followed by a multiplier. The PLL multiplier should be an even integer. If an odd integer (M) is programmed, the PLL will default to the lower (M-1) value to maintain an even multiplier value. The multiplier is followed by a set of dividers used to generate the output clocks required for the sensor array, the pixel analog and digital readout paths, and the output parallel and serial interfaces. Use of the PLL is required when using the HiSPi interface. AR0331_DS Rev. L Pub. 5/15 EN 28 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Sensor PLL Dual Readout Paths There are two readout paths within the sensor digital block. The sensor PLL should be configured such that the total pixel rate across both readout paths is equal to the output pixel rate. For example, if CLK_PIX is 74.25 MHz in a 4-lane HiSPi configuration, the CLK_OP should be equal to 37.125 MHz. Figure 21: Sensor Dual Readout Paths CLK_PIX A ll D igital B locks S erial O utpu t (H iS P i) P ixel A rray Pixel Rate = 2 x CLK_PIX = # data lanes x CLK_OP (HiSPi) = CLK_OP (Parallel) A ll D igital B locks CLK_PIX The sensor row timing calculation refers to each data-path individually. For example, the sensor default configuration uses 1100 clocks per row (line_length_pck) to output 1928 active pixels per row. The aggregate clocks per row seen by the receiver will be 2200 clocks (1100 x 2 readout paths). Parallel PLL Configuration Figure 22: PLL for the Parallel Interface . FVCO EXTCLK (6-48 MHz) pre_pll_clk_div 2(1-64) pll_multiplier 58(32 - 384) vt_sys_clk_div 1 (1,2,4,6,8,10 12,14,160 vt_pix_clk_div 6(4-16) CLK_OP (Max 74.25 Mp/s) CLK_PIX (Max 37.125 Mp/s) The maximum output of the parallel interface is 74.25 MPixel/s. This will limit the readout clock (CLK_PIX) to 37.125 MPixel/s. The sensor will not use the FSERIAL, FSERIAL_CLK, or CLK_OP when configured to use the parallel interface. AR0331_DS Rev. L Pub. 5/15 EN 29 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Sensor PLL Table 10: PLL Parameters for the Parallel Interface Parameter Symbol Min Max Unit External Clock EXTCLK 6 48 MHz FVCO 384 768 MHz Readout Clock CLK_PIX 37.125 Mpixel/s Output Clock CLK_OP 74.25 Mpixel/s VCO Clock Table 11: Example PLL Configuration for the Parallel Interface Parameter Value Output 445.5 MHz (Max) FVCO vt_sys_clk_div 1 vt_pix_clk_div 6 CLK_PIX 37.125 MPixel/s (= 445.5MHz / 12) CLK_OP 74.25 MPixel/s (= 445.5MHz / 6) Output pixel rate 74.25 MPixel/s Serial PLL Configuration Figure 23: PLL for the Serial Interface F V CO p re_p ll_ clk_d iv 2 (1-64) p ll_ m u ltip lie r 58 (32 - 384) vt_sys_clk_d iv 1 (1,2,4,6,8, 10,12,14,16) vt_p ix_clk_d iv 6 (4-16) o p_sys_clk_d iv o p_p ix_clk_d iv (default=1) 12 (8,10,12) CLK_PIX CLK_OP F V CO F S E RIA L The PLL must be enabled when HiSPi mode is selected. The sensor will use op_sys_clk_div and op_pix_clk_div to configure the output clock per lane (CLK_OP). The configuration will depend on the number of active lanes (1, 2, or 4) configured. To configure the sensor protocol and number of lanes, refer to "Serial Configuration" on page 22. AR0331_DS Rev. L Pub. 5/15 EN 30 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Sensor PLL Table 12: PLL Parameters for the Serial Interface Parameter Symbol Min Max Unit External Clock EXTCLK 6 48 MHz FVCO 384 768 MHz Readout Clock CLK_PIX 74.25 Mpixel/s Output Clock CLK_OP 37.125 Mpixel/s Output Serial Data Rate Per Lane FSERIAL 300 (HiSPi) 700 (HiSPi) Mbps FSERIAL_CLK 150 (HiSPi) 350(HiSPi) MHz VCO Clock Output Serial Clock Speed Per Lane Configure the serial output so that it adheres to the following rules: * The maximum data-rate per lane (FSERIAL) is 700 Mbps/lane (HiSPi). * Configure the output pixel rate per lane (CLK_OP) so that the sensor output pixel rate matches the peak pixel rate (2 x CLK_PIX). - 4-lane: 4 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 148.5 Mpixel/s) - 2-lane: 2 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 74.25 Mpixel/s) - 1-lane: 1 x CLK_OP = 2 x CLK_PIX = Pixel Rate (max: 37.125 Mpixel/s) Table 13: Example PLL Configurations for the Serial Interface 4-lane Parameter 2-lane 1-lane 16-bit 14-bit 12-bit 10-bit 12-bit 10-bit 10-bit Units 594 519.75 445.5 742.5 445.5 742.5 742.5 MHz vt_sys_clk_div 1 1 1 2 1 2 4 vt_pix_clk_div 8 7 6 5 12 10 10 FVCO op_sys_clk_div 1 1 1 2 1 2 2 op_pix_clk_div 16 14 12 10 12 10 10 FSERIAL 594 519.75 445.5 371.25 445.5 371.25 371.25 MHz FSERIAL_CLK 297 259.875 222.75 185.63 222.75 185.63 185.63 MHz CLK_PIX 74.25 74.25 74.25 74.25 37.125 37.125 18.563 Mpixel/s CLK_OP 37.125 37.125 37.125 37.125 37.125 37.125 37.125 Mpixel/s Pixel Rate 148.5 148.5 148.5 148.5 74.25 74.25 37.125 Mpixel/s Stream/Standby Control The sensor supports a soft standby mode. In this mode, the external clock can be optionally disabled to further minimize power consumption. If this is done, then the "PowerUp Sequence" on page 62 must be followed. When the external clock is disabled, the sensor will be unresponsive to register writes and other operations. Soft Standby is a low-power state that is controlled through register R0x301A[2]. The sensor will go to Standby after completion of the current frame readout. When the sensor comes back from Soft Standby, previously written register settings are still maintained. Soft Standby will not occur if the Trigger pin is held high. A specific sequence needs to be followed to enter and exit from Soft Standby. Entering Soft Standby: 1. Set R0x301A[12] = 1 if serial mode was used 2. Set R0x301A[2] = 0 and drive Trigger pin low. AR0331_DS Rev. L Pub. 5/15 EN 31 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Sensor Readout 3. Turn off external clock to further minimize power consumption Exiting Soft Standby: 1. Enable external clock if it was turned off 2. Set R0x301A[2] = 1 or drive Trigger pin high. 3. Set R0x301A[12] = 0 if serial mode is used Sensor Readout Image Acquisition Modes The AR0331 supports two image acquisition modes: * Electronic rolling shutter (ERS) mode This is the normal mode of operation. When the AR0331 is streaming, it generates frames at a fixed rate, and each frame is integrated (exposed) using the ERS. When the ERS is in use, timing and control logic within the sensor sequences through the rows of the array, resetting and then reading each row in turn. In the time interval between resetting a row and subsequently reading that row, the pixels in the row integrate incident light. The integration (exposure) time is controlled by varying the time between row reset and row readout. For each row in a frame, the time between row reset and row readout is the same, leading to a uniform integration time across the frame. When the integration time is changed (by using the two-wire serial interface to change register settings), the timing and control logic controls the transition from old to new integration time in such a way that the stream of output frames from the AR0331 switches cleanly from the old integration time to the new while only generating frames with uniform integration. See "Changes to Integration Time" in the AR0331 Register Reference. * Global reset mode This mode can be used to acquire a single image at the current resolution. In this mode, the end point of the pixel integration time is controlled by an external electromechanical shutter, and the AR0331 provides control signals to interface to that shutter. The benefit of using an external electromechanical shutter is that it eliminates the visual artifacts associated with ERS operation. Visual artifacts arise in ERS operation, particularly at low frame rates, because an ERS image effectively integrates each row of the pixel array at a different point in time. Window Control The sequencing of the pixel array is controlled by the x_addr_start, y_addr_start, x_addr_end, and y_addr_end registers. Readout Modes Horizontal Mirror When the horiz_mirror bit (R0x3040[14]) is set in the read_mode register, the order of pixel readout within a row is reversed, so that readout starts from x_addr_end + 1 and ends at x_addr_start. Figure 24 on page 33 shows a sequence of 6 pixels being read out with R0x3040[14] = 0 and R0x3040[14] = 1. AR0331_DS Rev. L Pub. 5/15 EN 32 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Sensor Readout Figure 24: Effect of Horizontal Mirror on Readout Order LINE_VALID horiz_mirror = 0 DOUT[11:0] G0[11:0] R0[11:0] G1[11:0] R1[11:0] G2[11:0] R2[11:0] horiz_mirror = 1 DOUT[11:0] G3[11:0] R2[11:0] G2[11:0] R1[11:0] G1[11:0] R0[11:0] Vertical Flip When the vert_flip bit (R0x3040[15]) is set in the read_mode register, the order in which pixel rows are read out is reversed, so that row readout starts from y_addr_end and ends at y_addr_start. Figure 30 shows a sequence of 6 rows being read out with R0x3040[15] = 0 and R0x3040[15] = 1. Figure 25: Effect of Vertical Flip on Readout Order FRAME_VALID vert_flip = 0 DOUT[11:0] Row0[11:0] Row1[11:0] Row2[11:0] Row3[11:0] Row4[11:0] Row5[11:0] vert_flip = 1 DOUT[11:0] Row6[11:0] Row5[11:0] Row4[11:0] Row3[11:0] Row2[11:0] Row1[11:0] AR0331_DS Rev. L Pub. 5/15 EN 33 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Subsampling Subsampling The AR0331 supports subsampling. Subsampling allows the sensor to read out a smaller set of active pixels by either skipping, binning, or summing pixels within the readout window. The following examples are configured to use either 2x2 or 3x3 subsampling. Figure 26: Horizontal Binning in the AR0331 Sensor lsb lsb lsb - lsb lsb lsb Horizontal binning is achieved either in the pixel readout or the digital readout. The sensor will sample the combined 2x or 3x adjacent pixels within the same color plane. Figure 27: Vertical Row Binning in the AR0331 Sensor ee- ee- Vertical row binning is applied in the pixel readout. Row binning can be configured as 2x or 3x rows within the same color plane. Pixel skipping can be configured up to 2x and 3x in both the x-direction and y-direction. Skipping pixels in the x-direction will not reduce the row time. Skipping pixels in the ydirection will reduce the number of rows from the sensor effectively reducing the frame time. Skipping will introduce image artifacts from aliasing. Refer to the AR0331 Developer Guide for details on configuring skipping, binning, and summing modes for color and monochrome operation. AR0331_DS Rev. L Pub. 5/15 EN 34 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Sensor Frame Rate Sensor Frame Rate The time required to read out an image frame (TFRAME) can be derived from the number of clocks required to output each image and the pixel clock. The frame-rate is the inverse of the frame period. fps=1/TFRAME (EQ 3) The number of clocks can be simplified further into the following parameters: * The number of clocks required for each sensor row (line_length_pck) This parameter also determines the sensor row period when referenced to the sensor readout clock. (TROW = line_length_pck x 1/CLK_PIX) * The number of row periods per frame (frame_length_lines) * An extra delay between frames used to achieve a specific output frame period (extra_delay) TFRAME=1/(CLK_PIX) x[frame_length_lines x line_length_pck + extra_delay] Figure 28: (EQ 4) Frame Period Measured in Clocks frame_length_lines = active rows + VB AR0331_DS Rev. L Pub. 5/15 EN 35 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Sensor Frame Rate Row Period (TROW) line_length_pck will determine the number of clock periods per row and the row period (TROW ) when combined with the sensor readout clock. line_length_pck includes both the active pixels and the horizontal blanking time per row. The sensor utilizes two readout paths, as seen in Figure 21 on page 29, allowing the sensor to output two pixels during each pixel clock. The minimum line_length_pck is defined as the maximum of the following three equations: ADC Readout Limitation: line_length_pck 1100 (EQ 5) Digital Readout Limitation: 1--x_addr_end - x_addr_start + 1 --------------------------------------------------------------------------3 x_odd_inc + 1 0.5 (EQ 6) Output Interface Limitations: 1--x_addr_end - x_addr_start + 1 --------------------------------------------------------------------------- + 96 2 x_odd_inc + 1 0.5 (EQ 7) Row Periods Per Frame frame_length_lines determines the number of row periods (TROW ) per frame. This includes both the active and blanking rows. The minimum vertical blanking value is defined by the number of OB rows read per frame, two embedded data rows, and two blank rows. A minimum number of idle rows equal to the T2 integration time should be added in HDR mode to allow for changes in integration time by an auto exposure algorithm. For example, if the coarse integration time is 320 lines and the exposure ratio is 16x, then the minimum vertical blanking would be 8 + 2 + 2 + 20 = 32 rows. The minimum (default) number of idle rows is 4. y_addr_end - y_addr_start + 1 Minimum frame_length_lines = --------------------------------------------------------------------------- + min_vertical_blanking y_odd_inc + 1 2 (EQ 8) The sensor is configured to output frame information in two embedded data rows by setting R0x3064[8] to 1 (default). If R0x3064[8] is set to 0, the sensor will instead output two blank rows. The data configured in the two embedded rows is defined in "Embedded Data and Statistics" on page 45. Table 14: min_vertical_blanking1 R0x3180[7:4] OB Rows 0x8 (Default) 8 OB Rows 8 OB + 8 = 16 0x4 4 OB Rows 4 OB + 8 = 12 0x2 2 OB Rows 2 OB + 8 = 10 Notes: AR0331_DS Rev. L Pub. 5/15 EN Minimum Vertical Blanking Configuration 1. min_vertical_blanking includes the default number (4) of idle rows. 36 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Slave Mode The locations of the OB rows, embedded rows, and blank rows within the frame readout are identified in Figure 29: "Slave Mode Active State and Vertical Blanking," on page 37. Slave Mode The slave mode feature of the AR0331 supports triggering the start of a frame readout from a VD signal that is supplied from an external ASIC. The slave mode signal allows for precise control of frame rate and register change updates. The VD signal is an edge triggered input to the trigger pin and must be at least 3 PIXCLK cycles wide. Figure 29: Slave Mode Active State and Vertical Blanking VD Signal Start of frame N Time Frame Valid OB Rows (2, 4, or 8 rows) Embedded Data Row (2 rows) Active Data Rows Blank Rows (2 rows) Extra Vertical Blanking (frame_length_lines - min_frame_length_lines) Extra Delay (clocks) The period between the rising edge of the VD signal and the slave mode ready state is TFRAME + 16 clocks. Slave Mode Active State End of frame N Start of frame N + 1 If the slave mode is disabled, the new frame will begin after the extra delay period is finished. The slave mode will react to the rising edge of the input VD signal if it is in an active state. When the VD signal is received, the sensor will begin the frame readout and the slave mode will remain inactive for the period of one frame time plus 16 clock periods (TFRAME + (16 / CLK_PIX)). After this period, the slave mode will re-enter the active state and will respond to the VD signal. AR0331_DS Rev. L Pub. 5/15 EN 37 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Slave Mode Figure 30: Slave Mode Example with Equal Integration and Frame Readout Periods The integration of the last row is started before the end of the programmed integration for the first row. Frame Valid Rising Edge Rising Edge Rising Edge VD Signal Slave Mode Trigger Inactive Active Rising edge of VD signal triggers the start of the frame readout. Inactive Row reset and read operations begin after the rising edge of the VD signal. Row 0 Active Row Reset (start of integration) Row Readout Programmed Integration Integration due to Slave Mode Delay Row N The Slave Mode will become "Active" after the last row period. Both the row reset and row read operations will wait until the rising edge of the VD signal.. The row shutter and read operations will stop when the slave mode becomes active and is waiting for the VD signal. The following should be considered when configuring the sensor to use the slave mode: 1. The frame period (TFRAME) should be configured to be less than the period of the input VD signal. The sensor will disregard the input VD signal if it appears before the frame readout is finished. 2. If the sensor integration time is configured to be less than the frame period, then the sensor will not have reset all of the sensor rows before it begins waiting for the input VD signal. This error can be minimized by configuring the frame period to be as close as possible to the desired frame rate (period between VD signals). AR0331_DS Rev. L Pub. 5/15 EN 38 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Slave Mode Figure 31: Slave Mode Example Where the Integration Period is Half of the Frame Readout Period The sensor read pointer will have paused at row 0 while the shutter pointer pauses at row N/2. The extra integration caused by the slave mode delay will only be seen by rows 0 to N/2. The example below is for a frame readout period of 16.6ms while the integration time is configured to 8.33ms. Frame Valid Rising Edge Rising Edge Rising Edge VD Signal Slave Mode Trigger Inactive 8.33 ms 8.33 ms Active Inactive Row reset and read operations begin after the rising edge of the Vd signal. Row 0 Active Row Reset (start of integration) Row Readout Programmed Integration Integration due to Slave Mode Delay Row N Reset operation is held during slave mode "Active" state. When the slave mode becomes active, the sensor will pause both row read and row reset operations. (Note: The row integration period is defined as the period from row reset to row read.) The frame-time should therefore be configured so that the slave mode "wait period" is as short as possible. In the case where the sensor integration time is shorter than the frame time, the "wait period" will only increase the integration of the rows that have been reset following the last VD pulse. The period between slave mode pulses must also be greater than the frame period. If the rising edge of the VD pulse arrives while the slave mode is inactive, the VD pulse will be ignored and will wait until the next VD pulse has arrived. To enter slave mode: 1. While in soft-standby, set R0x30CE[4] = 1 to enter slave mode. 2. Enable the input pins (TRIGGER) by setting R0x301A[8] = 1. 3. Enable streaming by setting R0x301A[2] = 1. 4. Apply sync-pulses to the TRIGGER input. AR0331_DS Rev. L Pub. 5/15 EN 39 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Frame Readout Frame Readout The sensor readout begins with vertical blanking rows followed by the active rows. The frame readout period can be defined by the number of row periods within a frame (frame_length_lines) and the row period (line_length_pck/clk_pix). The sensor will read the first vertical blanking row at the beginning of the frame period and the last active row at the end of the row period. Figure 32: Example of the Sensor Output of a 1928 x 1088 Frame at 60 fps The frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor. The SYNC codes represented in this diagram represent the HiSPi Streaming-SP protocol. 1/60s 1/60s Row Reset Row Read Row Reset Row Read Vertical Blanking Active Rows Row Reset Time Row Read Row Reset Row Read End of Frame Readout Start of Frame Start of Active Row HB (136 Pixels/Column) 1928 x 1088 End of Line HB (136Pixels/Column) VB (37 Rows) Serial SYNC Codes Start of Vertical Blanking VB (37 Rows) End of Frame Readout 1928 x 1088 End of Frame Frame Valid Line Valid Figure 32 aligns the frame integration and readout operation to the sensor output. It also shows the sensor output using the HiSPi Streaming-SP protocol. Different sensor protocols will list different SYNC codes. Table 15: Serial SYNC Codes Included with Each Protocol Included with the AR0331 Sensor Interface/Protocol Start of Vertical Blanking Row (SOV) Start of Frame (SOF) Start of Active Line (SOL) End of Line (EOL) End of Frame (EOF) Parallel Parallel interface uses FRAME VALID (FV) and LINE VALID (LV) outputs to denote start and end of line and frame. HiSPi Streaming-S Required Unsupported Required Unsupported Unsupported HiSPi Streaming-SP Required Required Required Unsupported Unsupported HiSPi Packetized SP Unsupported Required Required Required Required AR0331_DS Rev. L Pub. 5/15 EN 40 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Frame Readout Figure 33 illustrates how the sensor active readout time can be minimized while reducing the frame rate. 1125 VB rows were added to the output frame to reduce the 1928 x1088 frame rate from 60 fps to 30 fps without increasing the delay between the readout of the first and last active row. Figure 33: Example of the Sensor Output of a 1928 x1088 Frame at 30 fps The frame valid and line valid signals mentioned in this diagram represent internal signals within the sensor. The SYNC codes represented in this diagram represent the HiSPi Streaming-SP protocol. 1/30s Row Reset 1/30s Row Read Row Reset Row Read Vertical Blanking Active Rows Row Reset Time Row Read Row Reset Row Read End of Frame Readout End of Frame Readout Serial SYNC Codes Start of Vertical Blanking Start of Frame Start of Active Row VB (37 Rows) 1928 x 1088 H B (1236 P ixels ) End of Line End of Frame VB (37 Rows) 1928 x 1088 H B (1236 P ixels ) Frame Valid Line Valid AR0331_DS Rev. L Pub. 5/15 EN 41 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Changing Sensor Modes Changing Sensor Modes Register Changes All register writes are delayed by one frame. A register that is written to during the readout of frame n will not be updated to the new value until the readout of frame n+2. This includes writes to the sensor gain and integration registers. Real-Time Context Switching In the AR0331, the user may switch between two full register sets A and B by writing to a context switch change bit in R0x30B0[13]. When the context switch is configured to context A the sensor will reference the context A registers. If the context switch is changed from A to B during the readout of frame n, the sensor will then reference the context B coarse_integration_time registers in frame n+1 and all other context B registers at the beginning of reading frame n+2. The sensor will show the same behavior when changing from context B to context A. Table 16: List of Configurable Registers for Context A and Context B Context A Context B Register Description Address Register Description Address coarse_integration_time line_length_pck frame_length_lines row_bin col_bin fine_gain coarse_gain x_addr_start y_addr_start x_addr_end y_addr_end y_odd_inc x_odd_inc green1_gain blue_gain red_gain green2_gain global_gain operation_mode_ctrl bypass_pix_comb 0x3012 0x300C 0x300A 0x3040[12] 0x3040[13] 0x3060[3:0] 0x3060[5:4] 0x3004 0x3002 0x3008 0x3006 0x30A6 0x30A2 0x3056 0x3058 0x305A 0x305C 0x305E 0x3082 0x318E[13:12] coarse_integration_time_cb line_length_pck_cb frame_length_lines_cb row_bin_cb col_bin_cb fine_gain_cb coarse_gain_cb x_addr_start_cb y_addr_start_cb x_addr_end_cb y_addr_end_cb y_odd_inc_cb x_odd_inc_cb green1_gain_cb blue_gain_cb red_gain_cb green2_gain_cb global_gain_cb operation_mode_ctrl_cb bypass_pix_comb_cb 0x3016 0x303E 0x30AA 0x3040[10] 0x3040[11] 0x3060[11:8] 0x3060[13:12] 0x308A 0x308C 0x308E 0x3090 0x30A8 0x30AE 0x30BC 0x30BE 0x30C0 0x30C2 0x30C4 0x3084 0x318E[15:14] AR0331_DS Rev. L Pub. 5/15 EN 42 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Changing Sensor Modes Figure 34: Example of Changing the Sensor from Context A to Context B 1 /6 0 s 1 /6 0 s 1 /3 0 s V ertical B lanking A ctive R ow s T im e S ta rt o f A c tiv e R o w E n d o f F ra m e H B (136 P ixels /C olum n ) H B (136 P ixels /C olum n ) VB (37 R o w s) VB (37 R o w s) S ta rt o f F ra m e 1 9 2 8x1 0 8 8 F ra m e N 1 9 2 8x1 0 8 8 F ra m e N+ 1 In teg ratio n tim e o f co n text B m o d e im p lem en ted d u rin g read o u t o f fram e N+1 W rite co n text A to B d u rin g read o u t o f F ram e N HB (76 P ixels/Column) VB ( 37 R ow s) c S e ria l S Y N C C o d e s S ta rt o f V e rtic a l B la n k in g End of Fram e Readout End of Fram e Readout End of Fram e Readout ) 2 0 4 8x1 5 3 6 F ra m e N+ 2 C o n text B m o d e is im p lem en ted in fram e N + 2 Combi Mode To facilitate faster switching between linear and HDR modes, the AR0331 includes a Combi Mode feature. When enabled, Combi Mode loads a single (HDR) sequencer. When switching from HDR to linear modes, the sequencer remains the same, but only the T1 image is output. While not optimized for linear mode operation, it allows faster mode switching as a new sequencer load is not needed. Combi Mode is enabled by setting bit R0x30BA[8]. See the AR0331 Developer Guide for more information on Combi Mode. Compression When the AR0331 is configured for linear mode operation, the sensor can optionally compress 12-bit data to 10-bit using A-law compression. The compression is applied after the data pedestal has been added to the data. See "Pedestals" on page 25. The A-law compression is disabled by default and can be enabled by setting R0x31D0 from "0" to "1". Table 17: A-Law Compression Table for 12-10 bits Input Values Compressed Codeword Input Range 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 0 to 127 128 to 255 256 to 511 512 to 1023 1024 to 2047 2048 to 4095 0 0 0 0 0 1 0 0 0 0 1 a 0 0 0 1 a b 0 0 1 a b c 0 1 a b c d a a b c d e b b c d e f c c d e f g d d e f g h e e f g h X f f g X X X g g X X X X 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 a a a a a a b b b b b b c c c c c c d d d d d d e e e e e e f f f f f f g g g g g g h h AR0331_DS Rev. L Pub. 5/15 EN 43 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Changing Sensor Modes Temperature Sensor The AR0331 sensor has a built-in PTAT-based temperature sensor, accessible through registers, that is capable of measuring die junction temperature. The temperature sensor can be enabled by writing R0x30B4[0]=1 and R0x30B4[4]=1. After this, the temperature sensor output value can be read from R0x30B2[9:0]. The value read out from the temperature sensor register is an ADC output value that needs to be converted downstream to a final temperature value in degrees Celsius. Since the PTAT device characteristic response is quite linear in the temperature range of operation required, a simple linear function in the format of the equation below can be used to convert the ADC output value to the final temperature in degrees Celsius. Temperature = slope R0x30B2 9:0 + T 0 (EQ 9) For this conversion, a minimum of two known points are needed to construct the line formula by identifying the slope and y-intercept "T0". These calibration values can be read from registers R0x30C6 and R0x30C8, which correspond to value read at 70C and 55C respectively. Once read, the slope and y-intercept values can be calculated and used in Equation 9. For more information on the temperature sensor registers, refer to the AR0331 Register Reference. AR0331_DS Rev. L Pub. 5/15 EN 44 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Changing Sensor Modes Embedded Data and Statistics The AR0331 has the capability to output image data and statistics embedded within the frame timing. There are two types of information embedded within the frame readout. * Embedded Data: If enabled, these are displayed on the two rows immediately before the first active pixel row is displayed. * Embedded Statistics: If enabled, these are displayed on the two rows immediately after the last active pixel row is displayed. Figure 35: Frame Format with Embedded Data Lines Enabled Register Data Image HBlank Status & Statistics Data VBlank Embedded Data The embedded data contains the configuration of the image being displayed. This includes all register settings used to capture the current frame. The registers embedded in these rows are as follows: Line 1: Registers R0x3000 to R0x312F Line 2: Registers R0x3136 to R0x31BF, R0x31D0 to R0x31FF Note: All undefined registers will have a value of 0. The format of the embedded register data transmission is defined per the embedded data section of the SMIA Function Specification. In parallel mode, since the pixel word depth is 12 bits/pixel, the sensor 16-bit register data will be transferred over 2 pixels where the register data will be broken up into 8 MSB and 8 LSB. The alignment of the 8-bit data will be on the 8 MSB bits of the 12-bit pixel word. For example, if a register value of 0x1234 is to be transmitted, it will be transmitted over two, 12-bit pixels as follows: 0x120, 0x340. AR0331_DS Rev. L Pub. 5/15 EN 45 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Changing Sensor Modes Embedded Statistics The embedded statistics contain frame identifiers and histogram information of the image in the frame. This can be used by downstream auto-exposure algorithm blocks to make decisions about exposure adjustment. This histogram is divided into 244 bins with a bin spacing of 64 evenly spaced bins for digital code values 0 to 28, 120 evenly spaced bins for values 28 to 212, 60 evenly spaced bins for values 212 to 216. In HDR with a 16x exposure ratio, this approximately corresponds to the T1 and T2 exposures respectively. The statistics found in line 2 are for backwards compatibility. It is recommended that auto exposure algorithms be developed using the histogram statistics on line 1. The first pixel of each line in the embedded statistics is a tag value of 0x0B0. This signifies that all subsequent statistics data is 10 bit data aligned to the MSB of the 12-bit pixel. Figure 36 summarizes how the embedded statistics transmission looks like. It should be noted that data, as shown in Figure 36, is aligned to the MSB of each word: Figure 36: Format of Embedded Statistics Output within a Frame data_format_ code = 8'h0B # words = 10'h1EC stats line 1 data_format_ code = 8'h0B # words = 10'h00C {2'b00,frame _count MSB} {2'b00,frame _count LSB} histogram bin1 [19:0] histogram bin1 [9:0] mean [19:10] mean [9:0] lowEndMean [19:10] lowEndMean [9:0] {2'b00,frame _ID MSB} {2'b00,frame _ID LSB} histogram bin0 [19:10] histogram bin0 [9:0] histogram bin243 [19:0] histogram bin243 [9:0] 8'h07 histBegin [19:10] histBegin [9:0] histEnd [19:10] histEnd [9:0] perc_lowEnd [19:10] perc_lowEnd [9:0] norm_abs_ dev [19:10] norm_abs_ dev [9:0] 8'h07 stats line 2 8'h07 The statistics embedded in these rows are as follows: Line 1: * 0x0B0 - identifier * Register 0x303A - frame_count * Register 0x31D2 - frame ID * Histogram data - histogram bins 0-243 Line 2: * 0x0B0 (TAG) * Mean * Histogram Begin * Histogram End * Low End Histogram Mean * Percentage of Pixels Below Low End Mean * Normal Absolute Deviation AR0331_DS Rev. L Pub. 5/15 EN 46 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Changing Sensor Modes Test Patterns The AR0331 has the capability of injecting a number of test patterns into the top of the datapath to debug the digital logic. With one of the test patterns activated, any of the datapath functions can be enabled to exercise it in a deterministic fashion. Test patterns are selected by Test_Pattern_Mode register (R0x3070). Only one of the test patterns can be enabled at a given point in time by setting the Test_Pattern_Mode register according to Table 18. When test patterns are enabled the active area will receive the value specified by the selected test pattern and the dark pixels will receive the value in Test_Pattern_Green (R0x3074 and R0x3078) for green pixels, Test_Pattern_Blue (R0x3076) for blue pixels, and Test_Pattern_Red (R0x3072) for red pixels. Table 18: Test Pattern Modes Test_Pattern_Mode Test Pattern Output 0 1 2 3 256 No test pattern (normal operation) Solid color test pattern 100% Vertical Color Bars test pattern Fade-to-Gray Vertical Color Bars test pattern Walking 1s test pattern (12-bit) Solid Color When the color field mode is selected, the value for each pixel is determined by its color. Green pixels will receive the value in Test_Pattern_Green, red pixels will receive the value in Test_Pattern_Red, and blue pixels will receive the value in Test_Pattern_Blue. Vertical Color Bars When the vertical color bars mode is selected, a typical color bar pattern will be sent through the digital pipeline. Walking 1s When the walking 1s mode is selected, a walking 1s pattern will be sent through the digital pipeline. The first value in each row is 1. AR0331_DS Rev. L Pub. 5/15 EN 47 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Two-Wire Serial Register Interface Two-Wire Serial Register Interface The two-wire serial interface bus enables read/write access to control and status registers within the AR0331.The interface protocol uses a master/slave model in which a master controls one or more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK) that is an input to the sensor and is used to synchronize transfers. Data is transferred between the master and the slave on a bidirectional signal (SDATA). SDATA is pulled up to VDD_IO off-chip by a 1.5k resistor. Either the slave or master device can drive SDATA LOW--the interface protocol determines which device is allowed to drive SDATA at any given time. The protocols described in the two-wire serial interface specification allow the slave device to drive SCLKLOW; the AR0331 uses SCLK as an input only and therefore never drives it LOW. Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of lowlevel protocol elements: 1. a (repeated) start condition 2. a slave address/data direction byte 3. an (a no) acknowledge bit 4. a message byte 5. a stop condition The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a "repeated start" or "restart" condition. Stop Condition A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each SCLK clock period. SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. AR0331_DS Rev. L Pub. 5/15 EN 48 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Two-Wire Serial Register Interface Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A "0" in bit [0] indicates a WRITE, and a "1" indicates a READ. The default slave addresses used by the AR0331 are 0x20 (write address) and 0x21 (read address) in accordance with the specification. Alternate slave addresses of 0x30 (write address) and 0x31 (read address) can be selected by enabling and asserting the SADDR input. An alternate slave address can also be programmed through R0x31FC. Message Byte Message bytes are used for sending register addresses and register write data to the slave device and for retrieving register read data. Acknowledge Bit Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the SCLK clock period following the data transfer. The transmitter (which is the master when writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is LOW and must be stable while SCLK is HIGH. No-Acknowledge Bit The no-acknowledge bit is generated when the receiver does not drive SDATA LOW during the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence. Typical Sequence A typical READ or WRITE sequence begins by the master generating a start condition on the bus. After the start condition, the master sends the 8-bit slave address/data direction byte. The last bit indicates whether the request is for a read or a write, where a "0" indicates a write and a "1" indicates a read. If the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. If the request was a WRITE, the master then transfers the 16-bit register address to which the WRITE should take place. This transfer takes place as two 8-bit sequences and the slave sends an acknowledge bit after each sequence to indicate that the byte has been received. The master then transfers the data as an 8-bit sequence; the slave sends an acknowledge bit at the end of the sequence. The master stops writing by generating a (re)start or stop condition. If the request was a READ, the master sends the 8-bit write slave address/data direction byte and 16-bit register address, the same way as with a WRITE request. The master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. The master generates an acknowledge bit after each 8-bit transfer. The slave's internal register address is automatically incremented after every 8 bits are transferred. The data transfer is stopped when the master sends a no-acknowledge bit. AR0331_DS Rev. L Pub. 5/15 EN 49 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Two-Wire Serial Register Interface Single READ from Random Location This sequence (Figure 37) starts with a dummy WRITE to the 16-bit address that is to be used for the READ. The master terminates the WRITE by generating a restart condition. The master then sends the 8-bit read slave address/data direction byte and clocks out one byte of register data. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. Figure 37 shows how the internal register address maintained by the AR0331 is loaded and incremented as the sequence proceeds. Figure 37: Single READ from Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] S = start condition P = stop condition Sr = restart condition A = acknowledge A = no-acknowledge A Reg Address, M Reg Address[7:0] A Sr Slave Address 1 A M+1 Read Data A P slave to master master to slave Single READ from Current Location This sequence (Figure 38) performs a read using the current value of the AR0331 internal register address. The master terminates the READ by generating a no-acknowledge bit followed by a stop condition. The figure shows two independent READ sequences. Figure 38: Single READ from Current Location Previous Reg Address, N S Slave Address AR0331_DS Rev. L Pub. 5/15 EN 1 A Read Data N+1 A Read Data 50 N+2 A Read Data N+L-1 A Read Data N+L A P (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Two-Wire Serial Register Interface Sequential READ, Start from Random Location This sequence (Figure 39) starts in the same way as the single READ from random location (Figure 37). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte READs until "L" bytes have been read. Figure 39: Sequential READ, Start from Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] M+1 Read Data A M+2 A Read Data Reg Address, M Reg Address[7:0] A Sr Slave Address M+L-2 M+3 Read Data M+L-1 Read Data A 1 A M+1 M+L Read Data A A A P Sequential READ, Start from Current Location This sequence (Figure 40) starts in the same way as the single READ from current location (Figure 38). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte READs until "L" bytes have been read. Figure 40: Sequential READ, Start from Current Location Previous Reg Address, N S Slave Address 1 A N+1 Read Data A N+2 Read Data A N+L-1 Read Data A N+L Read Data A P Single WRITE to Random Location This sequence (Figure 41) begins with the master generating a start condition. The slave address/data direction byte signals a WRITE and is followed by the HIGH then LOW bytes of the register address that is to be written. The master follows this with the byte of write data. The WRITE is terminated by the master generating a stop condition. Figure 41: Single WRITE to Random Location Previous Reg Address, N S AR0331_DS Rev. L Pub. 5/15 EN Slave Address 0 A Reg Address[15:8] A 51 Reg Address, M Reg Address[7:0] A Write Data M+1 A P A (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Two-Wire Serial Register Interface Sequential WRITE, Start at Random Location This sequence (Figure 42) starts in the same way as the single WRITE to random location (Figure 41). Instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte WRITEs until "L" bytes have been written. The WRITE is terminated by the master generating a stop condition. Figure 42: Sequential WRITE, Start at Random Location Previous Reg Address, N S Slave Address 0 A Reg Address[15:8] M+1 Write Data AR0331_DS Rev. L Pub. 5/15 EN M+2 A Write Data A Reg Address, M Reg Address[7:0] M+3 A Write Data M+L-2 Write Data A 52 M+1 A M+L-1 A Write Data M+L A P A (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Spectral Characteristics Spectral Characteristics Figure 43: Quantum Efficiency 65 60 Red 55 Quantum Efficiency (%) 50 G re e n 45 40 Blu e 35 30 25 20 15 10 5 0 350 450 550 650 750 850 950 1050 1150 Wavelength (nm) AR0331_DS Rev. L Pub. 5/15 EN 53 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Electrical Specifications Electrical Specifications Unless otherwise stated, the following specifications apply under the following conditions: VDD = 1.8V - 0.10/+0.15; VDD_IO = VDD_PLL = VAA = VAA_PIX = 2.8V 0.3V; VDD_SLVS = 0.4V - 0.1/+0.2; TA = -30C to +85C; output load = 10pF; frequency = 74.25 MHz; HiSPi off. Two-Wire Serial Register Interface The electrical characteristics of the two-wire serial register interface (SCLK, SDATA) are shown in Figure 44 and Table 19. Figure 44: Two-Wire Serial Bus Timing Parameters SDATA tLOW tf tf tSU;DAT tr tHD;STA tr tBUF SCLK tHD;STA S tHD;DAT Note: Table 19: tSU;STA tHIGH tSU;STO Sr P S Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued. Two-Wire Serial Bus Characteristics fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25C Standard Mode Parameter Symbol Fast Mode Min Max Min Max Unit SCL 0 100 0 400 KHz tHD;STA 4.0 - 0.6 - S 4.7 - 1.3 - S f SCLK Clock Frequency Hold time (repeated) START condition After this period, the first clock pulse is generated LOW period of the SCLK clock t HIGH period of the SCLK clock tHIGH LOW 4.0 - 0.6 - S Set-up time for a repeated START condition t SU;STA 4.7 - 0.6 - S Data hold time tHD;DAT 04 3.455 06 0.95 S Data set-up time t - nS 7 SU;DAT 250 - 100 6 Rise time of both SDATA and SCLK signals t r - 1000 20 + 0.1Cb 300 nS Fall time of both SDATA and SCLK signals tf - 300 20 + 0.1Cb7 300 nS SU;STO 4.0 - 0.6 - S tBUF 4.7 - 1.3 - S Cb - 400 - 400 pF Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line AR0331_DS Rev. L Pub. 5/15 EN t 54 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Electrical Specifications Table 19: Two-Wire Serial Bus Characteristics (continued) f EXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25C Standard Mode Parameter Serial interface input pin capacitance SDATA max load capacitance SDATA pull-up resistor Notes: Fast Mode Symbol Min Max Min Max Unit CIN_SI - 3.3 - 3.3 pF CLOAD_SD - 30 - 30 pF 1.5 4.7 1.5 4.7 K RSD 2 1. 2. 3. 4. This table is based on I C standard (v2.1 January 2000). Philips Semiconductor. Two-wire control is I2C-compatible. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK. 5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF. I/O Timing By default, the AR0331 launches pixel data, FV, and LV with the rising edge of PIXCLK. The expectation is that the user captures DOUT[11:0], FV, and LV using the falling edge of PIXCLK. See Figure 45 below and Table 20 on page 56 for I/O timing (AC) characteristics. Figure 45: I/O Timing Diagram tR RP tF FP 90% 90% 10% 10% t EXTCLK EXTCLK t CP PIXCLK t PD t PD Data[11:0] LINE_VALID/ FRAME_VALID Pxl _0 Pxl _1 Pxl _2 Pxl _n t PLH t PFL t PFH t PLL FRAME_VALID leads LINE_VALID by 6 PIXCLKs. FRAME_VALID trails LINE_VALID by 6 PIXCLKs. *PLL disabled for tCP AR0331_DS Rev. L Pub. 5/15 EN 55 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Electrical Specifications Table 20: Symbol f EXTCLK1 t EXTCLK1 t R Condition Input clock frequency Input clock period Input clock rise time Typ Max Unit 6 - 48 MHz 20.8 - 166 ns - 3 - ns Input clock fall time - 3 - ns Pixclk rise time - 4 - ns ns FP (PIX JITTER) Pixclk fall time - 4 - Clock duty cycle 40 50 60 Jitter on PIXCLK - 1 11.3 t CP f Min RP t t Definition t F t I/O Timing Characteristics PIXCLK tPD tPFH tPLH tPFL tPLL CLOAD CIN EXTCLK to PIXCLK propagation delay Nominal voltages, PLL Disabled - PIXCLK frequency Default, Nominal Voltages 6 PIXCLK to data valid Default, Nominal Voltages - PIXCLK to FV HIGH Default, Nominal Voltages PIXCLK to LV HIGH % ns - ns 74.25 MHz 2.3 - ns - 1.5 - ns Default, Nominal Voltages - 2.3 - ns PIXCLK to FV LOW Default, Nominal Voltages - 1.5 - ns PIXCLK to LV LOW Default, Nominal Voltages - 2 - ns Output load capacitance - <10 - pF Input pin capacitance - 2.5 - pF Note: AR0331_DS Rev. L Pub. 5/15 EN I/O timing characteristics are measured under the following conditions: - Temperature is 25C ambient - 10pF load 56 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Electrical Specifications DC Electrical Characteristics The DC electrical characteristics are shown in the tables below. Table 21: DC Electrical Characteristics Symbol Definition Condition Min Typ Max Unit VDD Core digital voltage 1.7 1.8 1.95 V VDD_IO I/O digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 V Analog voltage 2.5 2.8 3.1 V VAA_PIX VAA Pixel supply voltage 2.5 2.8 3.1 V VDD_PLL PLL supply voltage 2.5 2.8 3.1 V VDD_SLVS HiSPi supply voltage 0.3 0.4 0.6 V VIH Input HIGH voltage VDD_IO*0.7 - - V VIL Input LOW voltage - - VDD_IO*0.3 V 20 - - A IIN Input leakage current No pull-up resistor; VIN = VDD_IO or DGND VOH Output HIGH voltage VDD_IO-0.3 - - V VOL Output LOW voltage - - 0.4 V IOH Output HIGH current At specified VOH -22 - - mA IOL Output LOW current At specified VOL - - 22 mA Caution Table 22: Stresses greater than those listed in Table 14 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Absolute Maximum Ratings Symbol Definition Condition Min Max Unit VDD_MAX Core digital voltage -0.3 2.4 V VDD_IO_MAX I/O digital voltage -0.3 4 V VAA_MAX VAA_PIX VDD_PLL VDD_SLVS_MAX tST Analog voltage -0.3 4 V Pixel supply voltage -0.3 4 V PLL supply voltage -0.3 4 V HiSPi I/O digital voltage -0.3 2.4 V Storage temperature -40 85 C Note: AR0331_DS Rev. L Pub. 5/15 EN Exposure to absolute maximum rating conditions for extended periods may affect reliability. 57 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Electrical Specifications Table 23: Operating Current Consumption in Parallel Output and Linear Mode Symbol Min Typ Max Unit Digital operating current Streaming, 2048x1536 20 fps IDD1 - 122 137 mA I/O digital operating current Streaming, 2048x1536 20 fps IDD_IO - 25 30 mA Analog operating current Streaming, 2048x1536 20 fps IAA - 32 38 mA Pixel supply current Streaming, 2048x1536 20 fps IAA_PIX - 7 12 mA PLL supply current Streaming, 2048x1536 20 fps IDD_PLL - 8 12 mA Definition Condition Digital operating current Streaming, 1080p30 IDD1 - 122 137 mA I/O digital operating current Streaming, 1080p30 IDD_IO - 25 30 mA Analog operating current Streaming, 1080p30 IAA - 35 40 mA Pixel supply current Streaming, 1080p30 IAA_PIX - 7 12 mA PLL supply current Streaming, 1080p30 IDD_PLL - 8 12 mA Notes: Table 24: 1. Operating currents are measured at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8V VDD = VDD_IO = 1.8V PLL Enabled and PIXCLK = 74.25 Mhz TA = 25C Operating Current Consumption in Parallel Output and HDR Mode Definition Condition Symbol Min Typ Max Unit Digital operating current Streaming, 2048x1536 20 fps IDD - 156 173 mA I/O digital operating current Streaming, 2048x1536 20 fps IDD_IO - 30 35 mA Analog operating current Streaming, 2048x1536 20 fps IAA - 50 65 mA Pixel supply current Streaming, 2048x1536 20 fps IAA_PIX - 9 14 mA PLL supply current Streaming, 2048x1536 20 fps IDD_PLL - 8 12 mA Digital operating current Streaming, 1080p30 IDD - 161 184 mA IDD_IO - 30 35 mA IAA - 54 70 mA Streaming, 1080p30 IAA_PIX - 9 14 mA Streaming, 1080p30 IDD_PLL - 8 12 mA I/O digital operating current Streaming, 1080p30 Analog operating current Streaming, 1080p30 Pixel supply current PLL supply current Notes: AR0331_DS Rev. L Pub. 5/15 EN 1. Operating currents are measured at the following conditions: VAA = VAA_PIX = VDD_PLL = 2.8V VDD = VDD_IO = 1.8V PLL Enabled and PIXCLK = 74.25 Mhz TA = 25C 58 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Electrical Specifications Table 25: Operating Current in HiSPi (HiVCM) Output and Linear Mode Definition Condition Symbol Min Typ Max Unit Digital Operating Current Streaming, 2048x1536 30fps IDD - 252 278 mA Analog Operating Current Streaming, 2048x1536 30fps IAA - 27 35 mA - 5 10 mA Pixel Supply Current Streaming, 2048x1536 30fps IAA_PIX PLL Supply Current Streaming, 2048x1536 30fps IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 2048x1536 30fps IDD_SLVS - 22 26 mA mA Digital Operating Current Streaming, 1080p60 IDD - 276 302 Analog Operating Current Streaming, 1080p60 IAA - 37 45 mA Pixel Supply Current Streaming, 1080p60 IAA_PIX - 7 12 mA PLL Supply Current Streaming, 1080p60 IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 1080p60 IDD_SLVS - 22 26 mA Unit Notes: Table 26: 1. Operating currents are measured at the following conditions: VAA=VAA_PIX= VDD_PLL=2.8V VDD =VDD_IO= 1.8V VDD_SLVS = 1.8V PLL Enabled and PIXCLK=74.25Mhz TA = 25C Operating Current in HiSPi (HiVCM) Output and HDR Mode Definition Condition Symbol Min Typ Max Digital Operating Current Analog Operating Current Streaming, 2048x1536 30fps IDD - 317 358 mA Streaming, 2048x1536 30fps IAA - 45 55 mA Pixel Supply Current Streaming, 2048x1536 30fps IAA_PIX - 8 13 mA PLL Supply Current Streaming, 2048x1536 30fps IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 2048x1536 30fps IDD_SLVS - 22 26 mA Digital Operating Current Streaming, 1080p60 - 323 358 mA IDD Analog Operating Current Streaming, 1080p60 IAA - 55 70 mA Pixel Supply Current Streaming, 1080p60 IAA_PIX - 9 14 mA PLL Supply Current Streaming, 1080p60 IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 1080p60 IDD_SLVS - 24 28 mA Notes: AR0331_DS Rev. L Pub. 5/15 EN 1. Operating currents are measured at the following conditions: VAA=VAA_PIX= VDD_PLL=2.8V VDD = VDD_IO= 1.8V VDD_SLVS = 1.8V PLL Enabled and PIXCLK=74.25MHz TA = 25C 59 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Electrical Specifications Table 27: Operating Current in HiSPi (SLVS) Output and Linear Mode Definition Condition Symbol Min Typ Max Unit Digital Operating Current Streaming, 2048x1536 30fps IDD - 252 278 mA Analog Operating Current Streaming, 2048x1536 30fps IAA - 27 35 mA - 5 10 mA Pixel Supply Current Streaming, 2048x1536 30fps IAA_PIX PLL Supply Current Streaming, 2048x1536 30fps IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 2048x1536 30fps IDD_SLVS - 9 13 mA mA Digital Operating Current Streaming, 1080p60 IDD - 276 302 Analog Operating Current Streaming, 1080p60 IAA - 37 45 mA Pixel Supply Current Streaming, 1080p60 IAA_PIX - 7 12 mA PLL Supply Current Streaming, 1080p60 IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 1080p60 IDD_SLVS - 9 13 mA Unit Notes: Table 28: 1. Operating currents are measured at the following conditions: VAA=VAA_PIX= VDD_PLL=2.8V VDD =VDD_IO= 1.8V VDD_SLVS = 0.4V PLL Enabled and PIXCLK=74.25Mhz TA = 25C Operating Current in HiSPi (SLVS) Output and HDR Mode Definition Condition Symbol Min Typ Max Digital Operating Current Analog Operating Current Streaming, 2048x1536 30fps IDD - 317 358 mA Streaming, 2048x1536 30fps IAA - 45 55 mA Pixel Supply Current Streaming, 2048x1536 30fps IAA_PIX - 8 13 mA PLL Supply Current Streaming, 2048x1536 30fps IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 2048x1536 30fps IDD_SLVS - 9 13 mA Digital Operating Current Streaming, 1080p60 - 323 358 mA IDD Analog Operating Current Streaming, 1080p60 IAA - 55 70 mA Pixel Supply Current Streaming, 1080p60 IAA_PIX - 9 14 mA PLL Supply Current Streaming, 1080p60 IDD_PLL - 8 12 mA SLVS Supply Current Streaming, 1080p60 IDD_SLVS - 9 13 mA Notes: AR0331_DS Rev. L Pub. 5/15 EN 1. Operating currents are measured at the following conditions: VAA=VAA_PIX= VDD_PLL=2.8V VDD = VDD_IO= 1.8V VDD_SLVS = 0.4V PLL Enabled and PIXCLK=74.25MHz TA = 25C 60 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Electrical Specifications HiSPi Electrical Specifications The ON Semiconductor AR0331 sensor supports both SLVS and HiVCM HiSPi modes. Please refer to the High-Speed Serial Pixel (HiSPi) Interface Physical Layer Specification v2.00.00 for electrical definitions, specifications, and timing information. The VDD_SLVS supply in this datasheet corresponds to VDD_TX in the HiSPi Physical Layer Specification. Similarly, VDD is equivalent to VDD_HiSPi as referenced in the specification. The DLL as implemented on AR0331 is limited in the number of available delay steps and differs from the HiSPi specification as described in this section. Table 29: Channel Skew Measurement Conditions: VDD_HiSPi = 1.8V;VDD_HiSPi_TX = 0.8V; Data Rate =480 Mbps; DLL set to 0 Data Lane Skew in Reference to Clock Table 30: tCHSKEW1PHY -150 ps Clock DLL Steps Measurement Conditions: VDD_HiSPi = 1.8V;VDD_HiSPi_TX = 0.8V; Data DLL set to 0 Clock DLL Step 1 2 3 4 5 Step Delay at 660 Mbps Eye_opening at 660 Mbps 0.25 0.85 0.375 0.78 0.5 0.71 0.625 0.71 0.75 0.69 UI UI Note: Table 31: The Clock DLL Steps 6 and 7 are not recommended by ON Semiconductor for the AR0331. Data DLL Steps Measurement Conditions: VDD_HiSPi = 1.8V;VDD_HiSPi_TX = 0.8V; Clock DLL set to 0 Data DLL Step 1 2 4 6 Step Delay at 660 Mbps Eye opening at 660 Mbps 0.25 0.79 0.375 0.84 0.625 0.71 0.875 0.61 UI UI Note: AR0331_DS Rev. L Pub. 5/15 EN The Data DLL Steps 3, 5, and 7 are not recommended by ON Semiconductor for the AR0331. 61 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Power-On Reset and Standby Timing Power-On Reset and Standby Timing Power-Up Sequence The recommended power-up sequence for the AR0331 is shown in Figure 46. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Turn on VDD_PLL power supply. 2. After 100s, turn on VAA and VAA_PIX power supply. 3. After 100s, turn on VDD_IO power supply. 4. After 100s, turn on VDD power supply. 5. After 100s, turn on VDD_SLVS power supply. 6. After the last power supply is stable, enable EXTCLK. 7. Assert RESET_BAR for at least 1ms. The parallel interface will be tri-stated during this time. 8. Wait 150000 EXTCLKs (for internal initialization into software standby. 9. Configure PLL, output, and image settings to desired values. 10. Wait 1ms for the PLL to lock. 11. Set streaming mode (R0x301a[2] = 1). Figure 46: Power Up VDD_PLL (2.8) VAA_PIX VAA (2.8) t0 t1 VDD_IO (1.8/2.8) t2 VDD (1.8) t3 VDD_SLVS (0.4) EXTCLK t4 RESET_BAR tx t5 Software Standby Internal Initialization Hard Reset Table 32: t6 PLL Lock Streaming Power-Up Sequence AR0331_DS Rev. L Pub. 5/15 EN Definition Symbol Minimum Typical Maximum Unit VDD_PLL to VAA/VAA_PIX3 VAA/VAA_PIX to VDD_IO VDD_IO to VDD VDD to VDD_SLVS Xtal settle time t0 t1 t2 t3 tx 0 0 0 0 - 100 100 100 100 301 - - - - - S S S S mS 62 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Power-On Reset and Standby Timing Table 32: Power-Up Sequence (continued) Definition Hard Reset Internal Initialization PLL Lock Time Notes: AR0331_DS Rev. L Pub. 5/15 EN Symbol Minimum 2 t4 t5 t6 1 150000 1 Typical Maximum Unit - - - - - - mS EXTCLKS mS 1. Xtal settling time is component-dependent, usually taking about 10 - 100 mS. 2. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the RC time must include the all power rail settle time and Xtal settle time. 3. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the others. If the case happens that VDD_PLL is powered after other supplies then sensor may have functionality issues and will experience high current draw on this supply. 63 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Power-On Reset and Standby Timing Power-Down Sequence The recommended power-down sequence for the AR0331 is shown in Figure 47. The available power supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA, VAA_PIX) must have the separation specified below. 1. Disable streaming if output is active by setting standby R0x301a[2] = 0 2. The soft standby state is reached after the current row or frame, depending on configuration, has ended. 3. Turn off VDD_SLVS. 4. Turn off VDD. 5. Turn off VDD_IO 6. Turn off VAA/VAA_PIX. 7. Turn off VDD_PLL. Figure 47: Power Down VDD_SLVS (0.4) t0 VDD (1.8) t1 V DD_IO (1.8/2.8) t2 VAA_PIX VAA (2.8) t3 VDD_PLL (2.8) EXTCLK t4 Power Down until next Power up cycle Table 33: Power-Down Sequence Definition Minimum Typical Maximum Unit VDD_SLVS to VDD t0 0 - - s VDD to VDD_IO t1 0 - - s VDD_IO to VAA/VAA_PIX t2 0 - - s VAA/VAA_PIX to VDD_PLL t3 0 - - s PwrDn until Next PwrUp Time t4 100 - - ms Note: AR0331_DS Rev. L Pub. 5/15 EN Symbol t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged. 64 (c)Semiconductor Components Industries, LLC, 2015. AR0331_DS Rev. L Pub. 5/15 EN Package Dimensions Figure 48: 48 iLCC Parallel Package Outline Drawing (c)Semiconductor Components Industries, LLC, 2015 1. All dimensions are in millimeters. Dimensions in () are for reference only. 2 Encapsulant: Epoxy 3 Substrate material: Plastic laminate 0.5 thickness 4 Lid material: Borosilicate glass 0.4 +- 0.04 thickness. 5 Lead finish: Gold plating, 0.5 microns minimum thickness. 6 Image sensor die: 0.2mm thickness. 7 Maximum rotation of optical area relative to package edges: 1. Maximum tilt of optical area relative to substrate plane D : 25 m. Maximum tilt of cover glass relative to optical area plane E : 50 m. 8. Double side AR coating: 420 - 850 nm R < 1% applied to glass. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Package Dimensions 65 Notes: AR0331_DS Rev. L Pub. 5/15 EN Figure 49: 48 iLCC HiSPi Package Outline Drawing (c)Semiconductor Components Industries, LLC, 2015 1. All dimensions are in millimeters. Dimensions in () are for reference only. 2 Encapsulant: Epoxy 3 Substrate material: Plastic laminate 0.5 thickness 4 Lid material: Borosilicate glass 0.4 +- 0.04 thickness. 5 Lead finish: Gold plating, 0.5 microns minimum thickness. 6 Image sensor die: 0.2mm thickness. 7 Maximum rotation of optical area relative to package edges: 1. Maximum tilt of optical area relative to substrate plane D : 25 m. Maximum tilt of cover glass relative to optical area plane E : 50 m. 8. Double side AR coating: 420 - 850 nm R < 1% applied to glass. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Package Dimensions 66 Notes: AR0331_DS Rev. L Pub. 5/15 EN Figure 50: 63-Ball iBGA Package Outline Drawing (c)Semiconductor Components Industries, LLC, 2015 1. All dimensions are in millimeters. Dimensions in () are for reference only. 2 Encapsulant: Epoxy 3 Substrate material: Plastic laminate 0.25 thickness 4 Lid material: Borosilicate glass 0.4 +- 0.04 thickness. 5 Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). Dimensions apply to solder balls post reflow. Solder ball is O0.5 on a O0.4 SMD ball pad. 6 Image sensor die: 0.2mm thickness. 7 Maximum rotation of optical area relative to package edges: 1. Maximum tilt of optical area relative to substrate plane D : 25 m. Maximum tilt of cover glass relative to optical area plane E : 50 m. 8. Double side AR coating: 420 - 850 nm R < 1% applied to glass. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Package Dimensions 67 Notes: AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Revision History Revision History Rev. L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/1/15 * Updated "Ordering Information" on page 2 Rev. K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/25/15 * Removed Confidential marking * Updated format of Table of Contents Rev. J. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/19/15 * Updated to ON Semiconductor template Rev. H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/27/14 * Updated Figure 1: "Block Diagram," on page 6 * Updated Figure 6: "9.5 x 9.5 mm 63-Ball IBGA Package," on page 13 * Updated Table 3, "Pin Descriptions, 9.5 x 9.5 mm, 63-ball iBGA," on page 14 * Updated Figure 32: "Example of the Sensor Output of a 1928 x 1088 Frame at 60 fps," on page 40 * Updated Figure 33: "Example of the Sensor Output of a 1928 x1088 Frame at 30 fps," on page 41 * Updated Figure 34: "Example of Changing the Sensor from Context A to Context B," on page 43 * Updated Table 33, "Power-Down Sequence," on page 64 * Updated Figure 48: "48 iLCC Parallel Package Outline Drawing," on page 65 * Updated Figure 49: "48 iLCC HiSPi Package Outline Drawing," on page 66 * Updated Figure 50: "63-Ball iBGA Package Outline Drawing," on page 67 * Updated corporate address on last page Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3/24/14 * Updated Figure 4: "48 iLCC Package, Parallel Output," on page 9 * Applied updated Aptina template Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8/29/12 * Updated Figure 6: "9.5 x 9.5 mm 63-Ball IBGA Package," on page 13 * Updated "Pixel Sensitivity" on page 22 (Deleted last sentence in section) * Added Table 7, "Companding Table," on page 26 * Updated Figure 48: "48 iLCC Parallel Package Outline Drawing," on page 65 * Updated Figure 49: "48 iLCC HiSPi Package Outline Drawing," on page 66 * Updated Figure 50: "63-Ball iBGA Package Outline Drawing," on page 67 Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/13/12 * Updated the external reference clock frequency range from 6-74.25MHz to 6-48MHz (in Table 1 and various other locations). * Updated Table 3, "Available Part Numbers," on page 2 * Updated title of Table 3, "Pin Descriptions, 9.5 x 9.5 mm, 63-ball iBGA," on page 14 * Changed recommended data pedestal setting from 0 to 16 when ALTM is enabled (p25) * Removed statement that register values are preserved on a soft reset (p28) * Updated Figure 22: "PLL for the Parallel Interface," on page 29 * Updated Figure 23: "PLL for the Serial Interface," on page 30 * Updated Table 14, "Minimum Vertical Blanking Configuration," on page 36 AR0331_DS Rev. L Pub. 5/15 EN 68 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Revision History * Updated the Trigger pulse timing for slave mode from TFRAME - 16 clocks to TFRAME + 16 clocks (Figure 29: "Slave Mode Active State and Vertical Blanking," on page 37). * Updated Figure 45: "I/O Timing Diagram," on page 55 * Restored revision history that got deleted from Rev. D Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/21/11 * Updated Active Pixels, HiSPi Supply Voltage, Power Consumption, and Package Options in Table 1, "Key Parameters," on page 1 * Updated "General Description" on page 1 * Updated "General Description" on page 6 * Updated "Functional Overview" on page 6 * Updated Figure 1: "Block Diagram," on page 6 * Added Note 7 to Figure 3: "Typical Configuration: Parallel Pixel Data Interface," on page 8 * Updated VDD_SLVS description in Table 2, "Pin Descriptions, 48 iLCC," on page 12 * Changed titles of Figure 6: "9.5 x 9.5 mm 63-Ball IBGA Package," on page 13 and Table 3, "Pin Descriptions, 9.5 x 9.5 mm, 63-ball iBGA," on page 14 * Updated VDD_SLVS description in Table 3, "Pin Descriptions, 9.5 x 9.5 mm, 63-ball iBGA," on page 14 * Updated "Pixel Array Structure" on page 16 * Added Note 1 to Figure 7: "Pixel Array Description," on page 16 * Updated Table 4, "Output Enable Control," on page 18 * Updated ""Parallel Interface" on page 18" * Updated "DLL Timing Adjustment" on page 20 * Updated Figure 12: "Block Diagram of DLL Timing Adjustment," on page 20 * Updated "HiSPi Protocol Layer" on page 21 * Updated "Serial Configuration" on page 22 * Added "Pixel Sensitivity" heading before Figure 15: "Integration Control in ERS Readout," on page 22 * Updated "Gain Stages" on page 23 * Updated Figure 15: "Integration Control in ERS Readout," on page 22 * Deleted "Positional Gain Adjustments (PGA) on page 18" * Updated Table 6, "Recommended Sensor Gain," on page 24 * Removed "Table 9, "Recommended Registers to Configure Sensor Gain Table" on page 24 * Updated "Pedestals" on page 25 * Updated "High Dynamic Range Mode" on page 25 * Updated "Adaptive Local Tone Mapping" on page 25 * Updated "Companding" on page 26 * Updated "HDR-Specific Exposure Settings" on page 27 * Removed "Clocks" on page 28 * Updated "VCO" on page 28 * Removed Figure 17: "Row Read and Row Reset Showing Fine Integration" on page 23 * Removed Equation 3 on page 23 * Updated "Dual Readout Paths" on page 29 * Updated "Parallel PLL Configuration" on page 29 * Updated "Serial PLL Configuration" on page 30 * Updated Figure 23: "PLL for the Serial Interface," on page 30 AR0331_DS Rev. L Pub. 5/15 EN 69 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Revision History * Updated Table 12, "PLL Parameters for the Serial Interface," on page 31 * Added 14-bit column to 4-lane section in Table 13, "Example PLL Configurations for the Serial Interface," on page 31 * Updated "Stream/Standby Control" on page 31 * Updated "Image Acquisition Modes" on page 32 * Updated "Horizontal Mirror" on page 32 * Updated "Subsampling" on page 34 * Updated "Row Period (TROW )" on page 36 * Updated "Row Periods Per Frame" on page 36 * Updated "Slave Mode" on page 37 * Updated Note for Table 14, "Minimum Vertical Blanking Configuration," on page 36 * Updated "Combi Mode" on page 43 * Updated "Temperature Sensor" on page 44 * Updated "Embedded Statistics" on page 46 * Added Note to Table 20, "I/O Timing Characteristics," on page 56 * Updated "HiSPi Electrical Specifications" on page 61 * Updated Table 23, "Operating Current Consumption in Parallel Output and Linear Mode," on page 58 * Updated Table 24, "Operating Current Consumption in Parallel Output and HDR Mode," on page 58 * Updated Table 25, "Operating Current in HiSPi (HiVCM) Output and Linear Mode," on page 59 * Updated Table 26, "Operating Current in HiSPi (HiVCM) Output and HDR Mode," on page 59 * Added Table 27, "Operating Current in HiSPi (SLVS) Output and Linear Mode," on page 60 * Added Table 28, "Operating Current in HiSPi (SLVS) Output and HDR Mode," on page 60 * Updated Note for Table 30, "Clock DLL Steps," on page 61 * Updated Note for Table 31, "Data DLL Steps," on page 61 * Updated "Power-Up Sequence" on page 62 * Added Note to pin 48 of Figure 48: "48 iLCC Parallel Package Outline Drawing," on page 65 * Added Figure 49: "48 iLCC HiSPi Package Outline Drawing," on page 66 Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/8/11 * Updated "Features" on page 1 * Updated Table 3, "Available Part Numbers," on page 2 * Updated Table 5, "Configuration of the Pixel Data Interface," on page 18 * Updated "Gain Stages" on page 23 * Updated Table 6, "Recommended Sensor Gain," on page 24 * Changed title of "Data Pedestals" to "Pedestals" on page 25 and updated * Updated "VCO" on page 28 * Updated Table 13, "Example PLL Configurations for the Serial Interface," on page 31 * Updated "Horizontal Mirror" on page 32 * Updated "Vertical Flip" on page 33 * Updated "Slave Mode" on page 37 AR0331_DS Rev. L Pub. 5/15 EN 70 (c)Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor Revision History * Updated Table 15, "Serial SYNC Codes Included with Each Protocol Included with the AR0331 Sensor," on page 40 * Added "Combi Mode" on page 43 * Added "Spectral Characteristics" on page 53 * Updated Table 23, "Operating Current Consumption in Parallel Output and Linear Mode," on page 58 * Updated Table 24, "Operating Current Consumption in Parallel Output and HDR Mode," on page 58 * Updated Table 25, "Operating Current in HiSPi (HiVCM) Output and Linear Mode," on page 59 * Updated Table 26, "Operating Current in HiSPi (HiVCM) Output and HDR Mode," on page 59 Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/8/11 * Updated "Features" on page 1 * Updated Figure 2: "Typical Configuration: Serial Four-Lane HiSPi Interface," on page 7 * Updated Figure 3: "Typical Configuration: Parallel Pixel Data Interface," on page 8 * Updated Table 3, "Available Part Numbers," on page 2 * Updated Table 1, "Pin Descriptions," on page 10 * Updated Table 2, "Pin Descriptions, 48 iLCC," on page 12 * Updated Table 3, "Pin Descriptions, 9.5 x 9.5 mm, 63-ball iBGA," on page 14 * Added "Pixel Output Interfaces" on page 18 * Added "The Correction Function" on page 18 * Updated "Serial Configuration" on page 22 * Updated Table 6, "Recommended Sensor Gain," on page 24 * Updated Table 8, "Knee Points for Compression from 16 Bits to 12 Bits," on page 27 * Added Table 9, "Bit Operation After Linearization," on page 27 with introductory text above it * Updated Table 20, "I/O Timing Characteristics," on page 56 * Updated Figure 48: "48 iLCC Parallel Package Outline Drawing," on page 65 * Updated Figure 50: "63-Ball iBGA Package Outline Drawing," on page 67 * Updated corporate address on last page Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/26/11 * Initial release A-Pix is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC's product/patent coverage may be accessed at www.onsemi.com/site/pdf/ Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. AR0331_DS Rev. L Pub. 5/15 EN 71 (c)Semiconductor Components Industries, LLC, 2015 .