General Purpose Transistor
NPN Silicon
MAXIMUM RATINGS
Rating Symbol Value Unit
Collector–Emitter Voltage VCEO 32 Vdc
Collector–Base Voltage VCBO 60 Vdc
Emitter–Base V oltage VEBO 5.0 Vdc
Collector Current — Continuous IC800 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR–5 Board(1)
TA = 25°C
Derate above 25°C
PD225
1.8
mW
mW/°C
Thermal Resistance, Junction to Ambient RJA 556 °C/W
Total Device Dissipation
Alumina Substrate,(2) TA = 25°C
Derate above 25°C
PD300
2.4
mW
mW/°C
Thermal Resistance, Junction to Ambient RJA 417 °C/W
Junction and Storage Temperature TJ, Tstg –55 to +150 °C
DEVICE MARKING
BCW65ALT1 = EA
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Collector–Emitter Breakdown Voltage
(IC = 10 mAdc, IB = 0) V(BR)CEO 32 — — Vdc
Collector–Emitter Breakdown Voltage
(IC = 10 Adc, VEB = 0) V(BR)CES 60 — — Vdc
Emitter–Base Breakdown Voltage
(IE = 10 Adc, IC = 0) V(BR)EBO 5.0 — — Vdc
Collector Cutoff Current
(VCE = 32 Vdc, IE = 0)
(VCE = 32 Vdc, IE = 0, TA = 150°C)
ICES —
——
—20
20 nAdc
µAdc
Emitter Cutoff Current
(VEB = 4.0 Vdc, IC = 0) IEBO — — 20 nAdc
1. FR–5 = 1.0 0.75 0.062 in.
2. Alumina = 0.4 0.3 0.024 in. 99.5% alumina.
ON Semiconductor
Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 1 1Publication Order Number:
BCW65ALT1/D
BCW65ALT1
12
3
CASE 318–08, STYLE 6
SOT–23 (TO–236AB)
COLLECTOR
3
1
BASE
2
EMITTER
BCW65ALT1
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2
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Continued)
Characteristic Symbol Min Typ Max Unit
ON CHARACTERISTICS
DC Current Gain
(IC = 100 µAdc, VCE = 10 Vdc)
(IC = 10 mAdc, VCE = 1.0 Vdc)
(IC = 100 mAdc, VCE = 1.0 Vdc)
(IC = 500 mAdc, VCE = 2.0 Vdc)
hFE 35
75
100
35
—
—
—
—
—
220
250
—
—
Collector–Emitter Saturation Voltage
(IC = 500 mAdc, IB = 50 mAdc)
(IC = 100 mAdc, IB = 10 mAdc)
VCE(sat) —
—0.7
0.3 —
—
Vdc
Base–Emitter Saturation Voltage
(IC = 500 mAdc, IB = 50 mAdc) VBE(sat) — — 2.0 Vdc
SMALL–SIGNAL CHARACTERISTICS
Current–Gain — Bandwidth Product
(IC = 20 mAdc, VCE = 10 Vdc, f = 100 MHz) fT100 — — MHz
Output Capacitance
(VCB = 10 Vdc, IE = 0, f = 1.0 MHz) Cobo — — 12 pF
Input Capacitance
(VEB = 0.5 Vdc, IC = 0, f = 1.0 MHz) Cibo — — 80 pF
Noise Figure
(VCE = 5.0 Vdc, IC = 0.2 mAdc, RS = 1.0 kΩ, f = 1.0 kHz, BW = 200 Hz) NF — — 10 dB
SWITCHING CHARACTERISTICS
Turn–On Time
(IB1 = IB2 = 15 mAdc) ton — — 100 ns
Turn–Off Time
(IC = 150 mAdc, RL = 150 Ω)toff — — 400 ns
BCW65ALT1
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3
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT–23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature o f the die, RθJA, the thermal resistance from t h e
device junction to ambient, and the operating temperature,
TA. Using the values provided on the data sheet for the
SOT–23 package, PD can be calculated as follows:
PD = TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 225 milliwatts.
PD = 150°C – 25°C
556°C/W = 225 milliwatts
The 556°C/W for the SOT–23 package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts.
There are other alternatives to achieving higher power
dissipation from the SOT–23 package. Another alternative
would be to use a ceramic substrate or an aluminum core
board such as Thermal Clad. Using a board material such
as Thermal Clad, an aluminum core board, the power
dissipation can be doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•Always preheat the device.
•The delta temperature between the preheat and soldering
should be 100°C or less.*
•When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
•The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
•When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
•After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
•Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
BCW65ALT1
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4
PACKAGE DIMENSIONS
CASE 318–08
ISSUE AF
SOT–23 (TO–236)
DJ
K
L
A
C
BS
H
GV
3
12
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B0.0472 0.0551 1.20 1.40
C0.0350 0.0440 0.89 1.11
D0.0150 0.0200 0.37 0.50
G0.0701 0.0807 1.78 2.04
H0.0005 0.0040 0.013 0.100
J0.0034 0.0070 0.085 0.177
K0.0140 0.0285 0.35 0.69
L0.0350 0.0401 0.89 1.02
S0.0830 0.1039 2.10 2.64
V0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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BCW65ALT1/D
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