LT116 6
1
1166fa
For more information www.linear.com/LT1166
TYPICAL APPLICATION
FEATURES DESCRIPTION
Power Output Stage
Automatic Bias System
The LT
®
1166 is a bias generating system for controlling
class AB output current in high powered amplifiers. When
connected with external transistors, the circuit becomes
a unity-gain voltage follower. The LT1166 is ideally suited
for driving power MOSFET devices because it eliminates
all quiescent current adjustments and critical transistor
matching. Multiple output stages using the LT1166 can
be paralleled to obtain higher output current.
Thermal runaway of the quiescent point is eliminated
because the bias system senses the current in each power
transistor by using a small external sense resistor. A high
speed regulator loop controls the amount of drive applied
to each power device. The LT1166 can be biased from a
pair of resistors or current sources and because it oper-
ates on the drive voltage to the output transistors, it oper-
ates on any supply voltage.
Unity Gain Buffer Amp Driving 1Ω Load
APPLICATIONS
n Set Class AB Bias Currents
n Eliminates Adjustments
n Eliminates Thermal Runaway of IQ
n Corrects for Device Mismatch
n Simplifies Heat Sinking
n Programmable Current Limit
n May Be Paralleled for Higher Current
n Small SO-8 or PDIP Package
n Biasing Power MOSFETs
n High Voltage Amplifiers
n Shaker Table Amplifiers
n Audio Power Amplifiers
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and C-Load
is a trademark of Analog Devices, Inc. All other trademarks are the property of their respective
owners.
Figure 1. Unity Gain Buffer with Current Limit
7
3
6
ILIM+
VOUT
ILIM–
LT1166
VTOP
VBOTTOM
1µF
1µF
1k
1k
R3
100Ω
RSENSE–
0.33Ω
RSENSE+
0.33Ω
1Ω
VOUT
4 IBOTTOM = 15mA
1 ITOP = 15mA
300pF
R2
100Ω
300pF
IRF9530
IRF530
2N2222
R4
100Ω 47Ω
MPS2222
+
220µF
2N2907
R1
100Ω
MPS2907
+
220µF
15V
–15V
5.6k
VIN
V
IN
4.3k 2
1166 • F01
SENSE–5
SENSE+8
47Ω
0V
0V
OUTPUT
INPUT
1166 • TA01
LT116 6
2
1166fa
For more information www.linear.com/LT1166
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Supply Current (Pin 1 or Pin 4) ..............................75mA
Differential Voltage (Pin 2 to Pin 3) ........................... ±6V
Output Short-Circuit Duration (Note 1) .........Continuous
Specified Temperature Range (Note 2) ........ 0°C to 70°C
Operating Temperature Range .................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Junction Temperature (Note 3) ............................. 150°C
Lead Temperature (Soldering, 10 sec) ...................300°C
(Note 1)
1
2
3
4
8
7
6
5
TOP VIEW
VTOP
VIN
VOUT
V
BOTTOM
SENSE+
ILIM+
ILIM–
SENSE–
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
+1
TJMAX = 150°C, θJA = 100°C/W (N8)
TJMAX = 150°C, θJA = 150°C/W (S8)
ORDER INFORMATION
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Pin 1 = 2V, Pin 4 = –2V, Operating current 15mA and RIN = 20k, unless
otherwise specified.
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1166CN8#PBF LT1166CN8#TRPBF 1166 8-LEAD PDIP 0°C to 70°C
LT1166CS8#PBF LT1166CS8#TRPBF 1166 8-LEAD PLASTIC SO 0°C to 70°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LT1166#orderinfo
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Offset Voltage Operating Current 15mA to 50mA l50 250 mV
Input Bias Current Operating Current 15mA to 50mA (Note 4) l2 10 µA
Input Resistance Operating Current 15mA to 50mA (Note 5) l2 15 MΩ
VAB (Top) Measure Pin 8 to Pin 3, No Load 14 20 26 mV
VAB (Bottom) Measure Pin 5 to Pin 3, No Load –14 –20 –26 mV
Voltage Compliance Operating Current = 50mA (Notes 6, 9) l±2 ±10 V
Current Compliance Operating Voltage = ±2V l±4 ±50 mA
Transconductance
gmCC2
gmEE2
gmCC10
gmEE10
(Note 7)
Pin 1 = 2V, Pin 4 = –2V
Pin 1 = 2V, Pin 4 = –2V
Pin 1 = 10V, Pin 4 = –10V
Pin 1 = 10V, Pin 4 = –10V
l
l
l
l
0.08
0.08
0.09
0.09
0.100
0.100
0.125
0.125
0.13
0.13
0.16
0.16
mho
mho
mho
mho
PSRRCC (Note 8) 19 dB
PSRREE (Note 8) 19 dB
Current Limit Voltage Operating Current 15mA to 50mA
Pin 7 Voltage to Pin 3
Pin 6 Voltage to Pin 3
l
l
1.0
–1.0
1.3
–1.3
1.5
–1.5
V
V
LT116 6
3
1166fa
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ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Commercial grade parts are designed to operate over the
temperature range of –40°C to 85°C but are neither tested nor guaranteed
beyond 0°C to 70°C. Industrial grade parts specified and tested over
–40°C and 85°C are available on special request, consult factory.
Note 3: TJ calculated from the ambient temperature TA and the power
dissipation PD according to the following formulas:
LT1166CN8: TJ = TA + (PD • 100°C/W)
LT1166CS8: TJ = TA + (PD • 150°C/W)
Note 4: ITOP = IBOTTOM
Note 5: The input resistance is typically 15MΩ when the loop is closed.
When the loop is open (current limit) the input resistance drops to 200Ω
referred to Pin 3.
Note 6: Maximum TJ can be exceeded with 50mA operating current and
simultaneous 10V and –10V (20V total).
Note 7: Apply ±200mV to Pin 2 and measure current change in Pin 1
and 4. Pin 3 is grounded.
Note 8:
Note 9: For Linear Operation, Pin 1 must not be less than 2V or more than
10V from Pin 3. Similarly, Pin 4 must not be less than 2V or more than
10V from Pin 3.
PSRR
CC
= gm
CC2
– gm
CC10
gm
CC2
PSRR
EE = gmEE2 – gmEE10
gmEE2
TYPICAL PERFORMANCE CHARACTERISTICS
Input Bias Current vs
Current Source Mismatch
Output Offset Voltage vs
Current Source Mismatch
Output Offset Voltage vs
Temperature
Input Bias Current vs Temperature Output Voltage vs Input Voltage
Open-Loop Voltage Gain vs
Frequency
CURRENT SOURCE MISMATCH (%)
–10
INPUT BIAS CURRENT (µA)
–5.0 0 5.0
10
LT1166 • TPC01
150
100
50
0
–50
–100
–150 –7.5 –2.5 2.5 7.5
ITOP = IBOTTOM = 50mA
ITOP = IBOTTOM = 4mA
TEMPERATURE (°C)
–50
INPUT BIAS CURRENT (µA)
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0 050 75
LT1166 • TPC04
–25 25 100
125
RL = ∞
ITOP = IBOTTOM = 15mA
RIN = 4.3k
ITOP AND IBOTTOM MISMATCH (mA)
–1.0
OUTPUT OFFSET VOLTAGE (mV)
1.0
LT1166 • TPC02
–0.5 00.5
800
600
400
200
0
–200
–400
–600
–800
–0.75 –0.25 0.25 0.75
ITOP = IBOTTOM = 50mA
RIN = 20k
RIN = 2k
INPUT VOLTAGE (V)
–10
OUTPUT VOLTAGE SWING (V)
10
8
6
4
2
0
–2
–4
–6
–8
–10 6
LT1166 • TPC05
–6–8 –4 0 4 8
–2 2
10
RIN = 4.3k
C1 = C2 = 500pF
RL = 10Ω
SEE FIGURE 8
ITOP = IBOTTOM = 12mA
RTOP = RBOTTOM = 1k
TEMPERATURE (°C)
–50
55
50
45
40
35
30 25 75
–25 0 50 100
RL = ∞
ITOP = IBOTTOM = 15mA
RIN = 4.3k
FREQUENCY (MHz)
GAIN (dB)
30
25
20
15
10
5
0
–5
–10
–15
–20
0.001 0.1 1
10
LT1166 • TPC06
0.01
VS = ±15V
RIN = 4.3k
ITOP = IBOTTOM = 12mA
C1 = C2 = 500pF
SEE FIGURE 8
RL = ∞
RL =10Ω
LT116 6
4
1166fa
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TYPICAL PERFORMANCE CHARACTERISTICS
Closed-Loop Voltage Gain vs
Frequency
Voltage Across Sense Resistors
vs Temperature
Current Limit Pin Voltage vs
Temperature
Input Transconductance vs
Supply Voltage
Total Harmonic Distortion vs
Frequency
Sense Pin Voltage Referenced to
VOUT vs Load Current
FREQUENCY (MHz)
GAIN (dB)
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
0.001 0.1 1
10
LT1166 • TPC07
0.01
VS = ±15V
RIN = 4.3k
ITOP = IBOTTOM = 12mA
C1 = C2 = 500pF
SEE FIGURE 8
RL = ∞
RL =10Ω
SUPPLY VOLTAGE (V)
0
INPUT TRANSCONDUCTANCE (mhos)
0.120
0.110
0.100
0.090
0.080
–0.080
–0.090
–0.100
–0.110
–0.120 8
LT1166 • TPC10
21 3 5 7 9
4610
VIN = 200mV
RL = 0
RIN = 0
125°C
25°C
–55°C
125°C
–55°C
25°C
gmCC
gmEE
TEMPERATURE (°C)
–50
VOLTAGE DROP ACROSS SENSE RESISTORS (mV)
24
22
20
18
16
–16
–18
–20
–22
–24 050 75
LT1166 • TPC08
–25 25 100
125
SENSE+
SENSE–
FREQUENCY (kHz)
0.1
TOTAL HARMONIC DISTORTION (%)
1
0.01 1 10
100
LT1166 • TPC11
0.01
0.1
10
RL = 10Ω
PO = 1W
SEE FIGURE 8
TEMPERATURE (°C)
–50
I
LIM
PIN VOLTAGE REFERENCED TO V
OUT
(V)
1.25
1.20
1.15
–1.15
–1.20
–1.25 050 75
LT1166 • TPC09
–25 25 100
125
PIN 7 TO PIN 3
PIN 6 TO PIN 3
VIN = ±1.5V
LOAD CURRENT (mA)
10864202468
10
SENSE PIN VOLTAGE REFERENCED TO V
OUT
(mV)
LT1166 • TPC12
1000
100
10
1
RSENSE = 100Ω
VBOTTOM VTOP
SINKING SOURCING
LT116 6
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1166fa
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PIN FUNCTIONS
VTOP (Pin 1): Pin 1 establishes the top side drive voltage
for the output transistors. Operating supply current enters
Pin 1 and a portion biases internal circuitry; Pin 1 current
should be greater than 4mA. Pin 1 voltage is internally
clamped to 12V with respect to VOUT and the pin current
should be limited to 75mA maximum.
VIN (Pin 2): Pin 2 is the input to a unity gain buffer
which drives VOUT (Pin 3). During a fault condition
(short-circuit) the input impedance drops to 200Ω and
the input current must be limited to 5mA or VIN to VOUT
limited to less than ±6V.
VOUT (Pin 3): Pin 3 of the LT1166 is the output of a volt-
age control loop that maintains the output voltage at the
input voltage.
VBOTTOM (Pin 4): Pin 4 establishes the bottom side drive
voltage for the output transistors. Operating supply cur-
rent exits this pin; Pin 4 current should be greater than
4mA. Pin 4 voltage is internally clamped to –12V with
respect to VOUT and the pin current should be limited to
75mA maximum.
SENSE– (Pin 5): The Sense– pin voltage is established
by the current control loop and it controls the output qui-
escent current in the bottom side power device. Limit the
maximum differential voltage between Pin 5 and Pin 3 to
±6V during fault conditions.
ILIM– (Pin 6): The negative side current limit, limits the
voltage at VBOTTOM to VOUT during a negative fault condi-
tion. The maximum reverse voltage on Pin 6 with respect
to VOUT is 6V.
I
LIM+
(Pin 7): The positive side current limit, limits the
voltage at VTOP to VOUT during a positive fault condition.
The maximum reverse voltage on Pin 7 with respect to
VOUT is –6V.
SENSE+ (Pin 8): The Sense+ pin voltage is established by
the current control loop and it controls the output qui-
escent current in the top side power device. Limit the
maximum differential voltage between Pin 8 and Pin 3 to
±6V during fault conditions.
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1166fa
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APPLICATIONS INFORMATION
VAB+
VAB–
1k
1k
1Ω
1Ω
8
1
3
5
4
VO
V–
V
+
Q7
× 10
Q8
× 10
Q9
× 1
Q10
× 1
RB
1k
RT
1k
–
+
–
+
M2
VTOP
VBOTTOM
IREF
IREF
10
SHUNT
REGULATOR
1166 • F02
M1
1Ω
1Ω
R1
R2
1
3
4
VO
V–
V
+
Q11
Q12
Q1
Q2
RB
1k
RT
1k
M2
VTOP
VBOTTOM
1166 • F03
Q4
× 32
Q6
× 32
Q3
× 1
Q5
× 1
CEXT1
VIN
RIN
CEXT2
2
M1
Overvoltage Protection
The supplies V
TOP
(Pin 1) and V
BOTTOM
(Pin 4) have clamp
diodes that turn on when they exceed ±12V. These diodes
act as ESD protection and serve to protect the LT1166
when used with large power MOS devices that produce
high VGS voltage. Current into Pin 1 or Pin 4 should be
limited to ±75mA maximum.
Multiplier Operation
Figure 2 shows the current multiplier circuit internal to
the LT1166 and how it works in conjunction with power
output transistors. The supply voltages VT (top) and VB
(bottom) of the LT1166 are set by the required “on” volt-
age of the power devices. A reference current IREF sets
a constant VBE7 and VBE8. This voltage is across emitter
base of Q9 and Q10 which are 1/10 the emitter area of
Q7 and Q8. The expression for this current multiplier is:
VBE7 + VBE8 = VBE9 + VBE10
or in terms of current:
(IC9)(IC10) = (IREF)2/100 = Constant
The product of I
C9
and I
C10
is constant. These currents are
mirrored and set the voltage on the (+) inputs of a pair of
internal op amps. The feedback of the op amps force the
same voltage on the (–) inputs and these voltages then
appear on the sense resistors in series with the power
devices. The product of the two currents in the power
devices is constant, as one increases the other decreases.
The excellent logging nature of Q9 and Q10 allows this
relation to hold over many decades in current.
The total current in Q7 and Q8 is actually the sum of IREF
and a small error current from the shunt regulator. During
high output current conditions the error current from the
regulator decreases. Current conducted by the regulator
also decreases allowing VT or VB to increase by an amount
needed to drive the power devices.
Driving the Input Stage
Figure 3 shows the input transconductance stage of the
LT1166 that provides a way to drive VT and VB. When a
positive voltage V
IN
is applied to R
IN
, a small input current
flows into R2 and the emitter of Q2. This effect causes
VO to follow VIN within the gain error of the amplifier. The
input current is then mirrored by Q3/Q4 and current sup-
plied to Q4’s collector is sourced by power device M1.
The signal current in Q4’s emitter is absorbed by external
resistor RB and this causes VB to rise by the same amount
Figure 2. Constant Product Generator Figure 3. Input Stage Driving Gates
LT116 6
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1166fa
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APPLICATIONS INFORMATION
as VIN. Similarly for VT, when positive voltage is applied to
R
IN
, current that was flowing in R1 and Q1 is now supplied
through RIN. This effect reduces the current in mirror Q5/
Q6. The reduced current has the effect of reducing the
drop on RT, and VT rises to make VO track VIN.
The open-loop voltage gain VO/(VIN – VPIN2) can be
increased by replacing RT and RB with current sources.
The effect of this is to increase the voltage gain VOUT/ VIN
from approximately 0.8 to 1 (see Typical Performance
Characteristics curves). The use of current sources
instead of resistors greatly increases loop gain and this
compensates for the nonlinearity of the output stage
resulting in much lower distortion.
Frequency Compensation and Stability
The input transconductance is set by the input resistor
RIN and the 32:1 current mirrors Q3/Q4 and Q5/Q6. The
resistors R1 and R2 are small compared to the value of
RIN. Current in RIN appears 32 times larger in Q4 or Q6,
which drive external compensation capacitors CEXT1 and
CEXT2. These two input signal paths appear in parallel to
give an input transconductance of:
gm = 16/RIN
The gain bandwidth is:
GBW = 16
2π(RIN)(CEXT
)
Depending on the speed of the output devices, typical
values are RIN = 4.3k and CEXT1 = CEXT2 = 500pF giving
a –3dB bandwidth of 1.2MHz (see Typical Performance
Characteristics curves).
To prevent instability it is important to provide good sup-
ply bypassing as shown in Figure 1. Large supply bypass
capacitors (220µF) and short power leads can eliminate
instabilities at these high current levels. The 100Ω resis-
tors (R2 and R3) in series with the gates of the output
devices stop oscillations in the 100MHz region as do the
100Ω resistors R1 and R4 in Figure 1.
Driving Capacitive Loads
Ideally, amplifiers have enough phase margin that they
don’t oscillate but just slow down with capacitive loads.
Practically, amplifiers that drive significant power require
some isolation from heavy capacitive loads to prevent
oscillation. This isolation is normally an inductor in series
with the output of the amplifier. A 1µH inductor in parallel
with a 10Ω resistor is sufficient for many applications.
Setting Output AB Bias Current
Setting the output AB quiescent current requires no
adjustments. The internal op amps force VAB = ±20mV
between each Sense (Pins 5 and 8) to the Output (Pin 3).
At quiescent levels the output current is set by:
IAB = 20mV/RSENSE
The LT1166 does not require a heat sink or mounting
on the heat sink for thermal tracking. The temperature
coefficient of V
AB
is approximately 0.3%/°C and is set
by the junction temperature of the LT1166 and not the
temperature of the power transistors.
Output Offset Voltage and Input Bias Current
The output offset voltage is a function of the value of RIN
and the mismatch between external current sources ITOP
and I
BOTTOM
(see the Typical Performance Characteristics
curves). Any error in ITOP and IBOTTOM match is reduced
by the 32:1 input current mirror, but is multiplied by the
input resistor RIN.
Current Limit
The voltage to activate the current limit is ±1.3V. The sim-
plest way to protect the output transistors is to connect
the Current Limit pins 6 and 7 to the Sense pins 5 and
8. A current limit of 1.3A can be set by using 1Ω sense
resistors. To keep the current limit circuit from oscillating
in hard limit, it is necessary to add an RC (1k and 1µF)
between the Sense pin and the ILIM as shown in Figure 1.
The sense resistors can be tapped up or down to increase
or decrease the current limit without changing AB bias
current in the power transistors. Figure 4 demonstrates
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1166fa
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APPLICATIONS INFORMATION
how tapping the sense resistors gives twice the limit cur-
rent or one half the limit current.
Foldback current limit can be added to the normal or
“square” current limit by including two resistors (30k typi-
cal) from the power supplies to the ILIM pins as shown in
Figure 5. With square current limit the maximum output
current is independent of the voltage across the power
devices. Foldback limit simply makes the output current
dependent on output voltage. This scheme puts dissipa-
tion limits on the output devices. The larger the voltage
across the power device, the lower the available output
current. This is represented in Figure 6, Output Voltage
vs Output Current for the circuit of Figure 5.
Driving the Shunt Regulator
It is possible to current drive the shunt regulator directly
without driving the input transconductance stage. This
has the advantage of higher speed and eliminates the
need to compensate the gm stage. With Pin 2 floating,
the LT1166 can be placed inside a feedback loop and
driven through the biasing current sources. The input
transconductance stage remains biased but has no effect
on circuit operation. The RL in Figure 7 is used to modu-
late the op amp supply current with input signal. This op
amp functions as a V-to-I with the supply leads acting as
current source outputs. The load resistor and the posi-
tive input of the op amp are connected to the output of
the LT1166 for feedback to set AV = 1V/V. The capacitor
CF eliminates output VOS due to mismatch between ITOP
and IBOTTOM, and it also forms a pole at DC and a zero at
1/RFCF. The zero frequency is selected to give a –1V/V
gain in the op amp before the phase of the MOSFETs
degenerate the stability of the loop.
Figure 5. Unity Gain Buffer Amp with Foldback Current Limit
Figure 4. Tapping Current Limit Resistors
Figure 6. Output Current vs Output Voltage
8
7
3
6
5
SENSE+
ILIM+
VOUT
ILIM–
SENSE–
LT1166
VTOP
VBOTTOM
0.5Ω
0.5Ω
1Ω
VOUT
V
+
V
–
4
1
VIN
V
IN
RIN 2
1166 • F04
1Ω
(2)(ILIM)
(1/2)(ILIM
)
8
7
3
6
5
SENSE+
ILIM+
VOUT
ILIM–
SENSE–
LT1166
VTOP
VBOTTOM
1µF
1µF
1k
1k
100Ω
10Ω
10Ω
30k
30k
V
OUT
4
1
100Ω
IRFR9024
IRFR024
15V
–15V
VIN
5.1k 2
1166 • F05
+
330pF
330pF
20mA
20mA
mA
OUTPUT VOLTAGE (V)
–10
OUTPUT CURRENT (mA)
200
160
120
80
40
0
–40
–80
–120
–160
–200 6
LT1166 • F06
–6–8 –4 0 4 8
–2 2
10
SQUARE ILIM+
SQUARE ILIM–
FOLDBACK ILIM+
FOLDBACK ILIM–
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APPLICATIONS INFORMATION
APPLICATION CIRCUITS
Bipolar Buffer
Similar to the unity gain buffer in Figure 1, the LT1166 can
be used to bias bipolar transistors as shown in Figure 8.
The minimum operating voltage for the LT1166 is ±2V,
so it is necessary to bias the part with adequate voltage
from the output stage. The simplest way to do this is to
use Darlington drivers and series diodes. There are no
thermal tracking circuits or adjustments necessary and
the LT1166 does not need to be mounted on the heat sink
with the power devices. RTOP and RBOTTOM can be used
to replace ITOP and IBOTTOM; see Typical Characteristics
curves.
Figure 7. Current Source Drive Figure 8. Bipolar Buffer Amp
8
7
3
6
5
SENSE+
ILIM+
VOUT
ILIM–
SENSE–
LT1166
VTOP
VBOTTOM
1Ω
1Ω
V
OUT
4
1
M2
M1
V+
V–
VIN
V
IN
RIN
2
1166 • F07
IT
IB
–
+
RL
RF
CF
8
7
3
6
5
SENSE+
ILIM+
VOUT
ILIM–
SENSE–
LT1166
VTOP
VBOTTOM
100Ω
1Ω
1Ω
150Ω
150Ω
10Ω
VOUT
4
IBOT =
15mA
1
ITOP =
15mA 100Ω
2N2222
47Ω
100Ω
2N2222
+
220µF
2N2907
47Ω
100Ω
2N2907
+
220µF
–15V
15V
5.6k
VIN
V
IN
4.7k 2
1166 • F08
500pF
TIP29
2N2222
IN4001
IN4001
500pF
TIP30
2N2907
RTOP
RBOTTOM
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APPLICATIONS INFORMATION
7
3
6
ILIM+
VOUT
ILIM–
LT1166
VT
VBOT
100Ω
0.33Ω
0.33Ω
1Ω
4
15mA
1
15mA
100Ω
MPS2222
110Ω
110Ω
5.1k
5.1k
+
440µF
15V
–15V
VIN
39k 2
1166 • F09
300pF
300pF
MPS2907
IRF530
IRF9530
1µF
1µF
1k
1k
LT1004-2.5
LT1004
2.5
–
+
CF
500pF 0.1µF
0.1µF
1k LT1360
76
4
3
2
909Ω
500pF
100Ω
+
440µF
SENSE+
SENSE–
8
5
V
IN
V
OUT
0V
0V
OUTPUT
INPUT
1166 • F10
0V
0V
OUTPUT
INPUT
1166 • F11
Figure 10. Power Amp Driving 1Ω Load Figure 11. Power Amp at 6A Current Limit
Figure 9. Power Op Amp AV = 10
Adding Voltage Gain
The circuit in Figure 9 adds voltage gain to the circuit in
Figure 1. At low frequency the LT1166 is in the feedback
loop of the LT1360 so the gain error and the VOS are
reduced and the closed-loop gain is 10V/ V.
LT116 6
11
1166fa
For more information www.linear.com/LT1166
APPLICATIONS INFORMATION
1A Adjustable Voltage Reference
The circuit in Figure 12 uses the LT1166 in a feedback
loop with the LT1431 to make a voltage reference with
an “attitude.” This 5V reference can drive ±1A and main-
tain 0.4% tolerance at the output. If other output voltages
are desired, external resistors can be used instead of the
LT1431’s internal 5k resistors.
HIGH VOLTAGE APPLICATION CIRCUITS
In order to use op amps in high voltage applications it is
necessary to use techniques that confine the amplifier’s
common mode voltage to its output. The following appli-
cations utilize amplifiers operating in suspended-supply
operation (Figure 13). See “Linear Technology Magazine”
Volume IV Number 2 for a discussion of suspended sup-
plies. The gain setting resistors used in suspended-sup-
ply operation must be tight tolerance or the gain will be
wrong. For example: with 1% resistors the gain can be as
far off as 75%, but with 0.1% resistors that error is cut to
less than 5%. Using the values shown in Figure 13, the
formula for computing the gain is:
A
V =
= –11.22
R8(R9 + R10)
(R8 • R9) – (R7 • R10)
Figure 13. Op Amp in Suspended-Supply Operation
Figure 12. ±1A, 5V Voltage Reference
8
7
3
6
5
SENSE+
ILIM+
VOUT
ILIM–
SENSE–
LT1166
VTOP
VBOTTOM
100Ω
1Ω
1Ω
5k
5k
4
1
100Ω
12V
VIN
2k
1387
65
4
1166 • F12
1µF
1µF
1k
1k
100Ω
100Ω
12V
12V
220µF
+
5V
OUT
2
1k
COLV+
2.5V
REF
RTOP RMID
GND/SENSE–
GND
FORCE
–
+
LT1431 IRF9530
IRF530
OUT
1166 • F13
–
+
R8
1k
R7
10k
R9
9.1k
R10
1k
IN
LT116 6
12
1166fa
For more information www.linear.com/LT1166
APPLICATIONS INFORMATION
Parallel Operation
Parallel operation is an effective way to get more out-
put power by connecting multiple power drivers. All that
is required is a small ballast resistor to ensure current
sharing between the drivers and an isolation inductor to
keep the drivers apart at high frequency. In Figure 14 one
power slice can deliver ±6A at 100VPK, or 300W RMS
into 16Ω. The addition of another slice boosts the power
output to 600W RMS into 8Ω and the addition of two
or more drivers theoretically raises the power output to
1200W RMS into 4Ω. Due to IR loss across the sense
resistors, the FET RON resistance at 10A, and some sag-
ging of the power supply, the circuit of Figure 14 actu-
ally delivers 350W RMS into 8Ω. Performance photos
and a THD vs frequency plot are included in Figure 15
through 18. Frequency compensation is provided by the
2k input resistor, 180µH inductor and the 1nF compensa-
tion capacitors. The common node in the auxiliary power
supplies is connected to amplifier output to generate the
floating ±15V supplies.
Figure 14. 350W Shaker Table Amplifier
8
7
3
6
5
SENSE+
ILIM+
VOUT
ILIM–
SENSE–
LT1166
VTOP
VBOTTOM R11
100Ω
R4
0.22Ω
R17
0.22Ω
R3
0.22
4
1
R2
100Ω
2N3904
R12
100Ω
R1
100Ω
VIN
RIN
2k 2
1166 • F14
1nF
1nF
2N3906
IRF230
C1
1µF
C2
1µF
R5
1k
R6
1k
–
+
LT1360
7
6
4
3
2
100V
–100V
L1**
0.4µH
L3***
1.5µH
180µH
FB
FB
POWER SLICE
POWER SLICE
R8*
1k
R7*
10k
R15
390Ω
R10*
1k
R9*
9.1k
C4
0.1µF
LT1004-2.5
LT1004-2.5
15V
–15V
V
IN
R13
200Ω
C3
3300pF
R16
390Ω
+
10µF
+
10µF
R14
1k
1Ω
10A
FAST-BLOW
VOUT
+
C5
220µF
25V
+
C6
220µF
25V
C7
1000µF
35V
C8
1000µF
35V –15V
15V
~
~
+
–
110V
AC
DIODE
BRIDGE
+
+
7815
7915
0.1% RESISTORS
4 TURNS T37-52 (MICROMETALS)
6 TURNS T80-52 (MICROMETALS)
*
**
***
–12.5V
12.5V
IRF9240
AUXILARY SUPPLIES
LT116 6
13
1166fa
For more information www.linear.com/LT1166
APPLICATIONS INFORMATION
100W Audio Power Amplifier
The details of a low distortion audio amplifier are shown in
Figure 19. The LT1360, designated U1, was chosen for its
good CMRR and is operated in suspended-supply mode at
a closed-loop gain of –26.5V/V. The ±15V supplies of U1
are effectively bootstrapped by the output at point D and
are generated as shown in Figure 14. A 3VP-P signal at VIN
will cause an 80VPP output at point A. Resistors 7 to 10
set the gain of –26.5V/V of U1, while C1 compensates for
the additional pole generated by the CMRR of U1. The rest
of the circuit (point A to point D) is an ultralow distortion
unity-gain buffer.
The main component in the unity-gain buffer is U4
(LT1166). This controller performs two important func-
tions, first it modifies the DC voltage between the gates of
M1 and M2 by keeping the product of the voltage across
R20 and R21 constant. Its secondary role is to perform
current limit, protecting M1 and M2 during short-circuit.
The function of U3 is to drive the gates of M1 and M2.
This amplifier’s real output is not point C as it appears, but
rather the Power Supply pins. Current through R6 is used
to modulate the supply current and thus provide drive to
VTOP and VBOTTOM. Because the output impedance of U3
(through its supply pins) is very high, it is not able to drive
the capacitive inputs of M1 and M2 with the combination
of speed and accuracy needed to have very low distortion
at 20kHz. The purposes of U2 are to drive the gate capaci-
tance of M1 and M2 through its low output impedance and
to reduce the nonlinearty of the M1 and M2 transconduc-
tance. R24, C4 set a frequency above which U2 no longer
looks after U3 and U4, but just looks after itself as its gain
goes through unity. R1/R2 and C2/C3 are compensation
components for the CMRR feedthough. Curves showing
the performance of the amplifier are shown in Figures 20
through 22.
Figure 18. THD vs Frequency
Figure 16. Clipping at 1kHz, RL = 8Ω
Figure 15. 0.3% THD at 10kHz, PO = 350W, RL = 8Ω Figure 17. 2kHz Square-Wave, CL = 1µF
1166 • F15
1166 • F17
1166 • F16
FREQUENCY (Hz)
10
0.01
TOTAL HARMONIC DISTORTION (%)
0.1
1.0
1k
100k
100 10k
LT1166 • F18
PO = 350W
RL = 8Ω
LT116 6
14
1166fa
For more information www.linear.com/LT1166
APPLICATIONS INFORMATION
Figure 19. 100W Audio Amplifier
8
7
3
6
5
SENSE+
ILIM+
VOUT
ILIM–
SENSE–
U4
LT1166
VTOP
VBOTTOM
R21
0.22Ω
R20
0.22Ω
4
1
R18
100Ω
R14
500Ω
R17
500Ω
VIN
2
1166 • F18
M1
IRF530
M2
IRF9530
C10
1µF
C11
1µF
R19
1k
R22
1k
–
+
U3
LT1360
7
6
4
2
3
L1
1µH
R4
1k
LT1009-2.5
LT1009-2.5
R23
10Ω
V
OUT
C14
0.1µF C15
22µF
+
C6
22µF
+
–50V
C12
0.1µF
C13
22µF
+
50V
C7
0.01µF
R5
3.3k
C5
3300pF
R16
30Ω
C9
0.01µF
R13
30Ω
R15
100Ω
+
–15V**
2N3904
R12
100Ω
C8
22µF
+
+
–15V**
2N3906
R11
100Ω
R3
10k
–
+
U2
LT1363
7
6
4
3
2
C2
470pF
R2
100Ω
R1
100Ω
C4
20pF
C3
470pF
C
B
A
R24
2.4k
–
+
7
6
4
2
3
U1
LT1360
R10*
1k
R8*
1k
R9*
9.6k
R7*
10k
C1
10pF
D
* 0.1% RESISTORS
** SEE POWER SUPPLY OF FIGURE 13
R6
160Ω
VIN
LT116 6
15
1166fa
For more information www.linear.com/LT1166
APPLICATIONS INFORMATION
1166 • F20
R
L 8Ω
f = 8kHz
1166 • F21
R
L 8Ω
f = 20kHz
FREQUENCY (Hz)
10
0.001
TOTAL HARMONIC DISTORTION (%)
0.01
0.1
1k
100k
100 10k
LT1166 • F22
RL = 8Ω
POWER OUT = 100W
Figure 20. Square Wave Response Into 8Ω Figure 21. 100W 20kHz Sine Wave and Its Distortion
Figure 22. THD vs Frequency
LT116 6
16
1166fa
For more information www.linear.com/LT1166
SIMPLIFIED SCHEMATIC
VAB+
VAB–
1k
1k
R1
200Ω
R2
200Ω
8
7
1
3
2
5
6
4
Q7
× 10
Q8
× 10
Q9
× 1
Q10
× 1
–
+
–
+
Q11
Q12
Q1
Q2
IREF
IREF
10
SHUNT
REGULATOR
1166 • SS
Q4
× 32
Q3
× 1
Q6
× 32
Q5
× 1
VTOP
SENSE+
V
BOTTOM
SENSE–
ILIM–
VOUT
ILIM+
V
IN
LT116 6
17
1166fa
For more information www.linear.com/LT1166
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT1166#packaging for the most recent package drawings.
N8 REV I 0711
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.130 ±.005
(3.302 ±0.127)
.020
(0.508)
MIN
.018 ±.003
(0.457 ±0.076)
.120
(3.048)
MIN
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
( )
1 2 34
87 65
.255 ±.015*
(6.477 ±0.381)
.400*
(10.160)
MAX
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
N Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)
LT116 6
18
1166fa
For more information www.linear.com/LT1166
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT1166#packaging for the most recent package drawings.
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 REV G 0212
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030
±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610 Rev G)
LT116 6
19
1166fa
For more information www.linear.com/LT1166
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 06/17 Updated Order Information.
Corrected pin numbers for U1 and U3.
2
14
LT116 6
20
1166fa
LINEAR TECHNOLOGY CORPORATION 1995
LT 0617 REV A • PRINTED IN USA
www.linear.com/LT1166
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
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LT1210 1A/40MHz Current Feedback Amplifier C-Load Op Amp with Shutdown and 700V/µs Slew Rate
LT1270A 10A High Efficiency Switching Regulator Use as Battery Boost Converter
LT1360 50MHz, 800V/µs Op Amp ±15V, Ideal for Driving Capacitive Loads
LT1363 70MHz, 800V/µs Op Amp ±15V, Very High Speed, C-Load