SLIS038A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
Copyright 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
•Low rDS(on) . . . 0.23 Ω Typ
•High Voltage Output ...60 V
•Extended ESD Capability . . . 4000 V
•Pulsed Current ...11.25 A Per Channel
•Fast Commutation Speed
description
The TPIC5403 is a monolithic gate-protected
power DMOS array that consists of four
independent electrically isolated N-channel
enhancement-mode DMOS transistors. Each
transistor features integrated high-current zener
diodes (ZCXa and ZCXb) to prevent gate damage
in the event that an overstress condition occurs.
These zener diodes also provide up to 4000 V of
ESD protection when tested using the
human-body model of a 100-pF capacitor in series
with a 1.5-kΩ resistor.
The TPIC5403 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation
over the case temperature range of −40°C to 125°C.
schematic
D1
DRAIN3
D3
Z1 Z3
Z2 Z4
GND
GATE3
DRAIN4
GATE4
SOURCE3
DRAIN1
GATE1
SOURCE1
DRAIN2
GATE2
Q1
Q2 Q4
Q3
D2 D4
1, 2
3
5, 6
11, 12
10
7, 8
23, 24
22
19, 20
13, 14
15
17, 18
SOURCE2 SOURCE4
4, 9, 16, 21
ZC2b
ZC2a
ZC1b
ZC1a
ZC3b
ZC3a
ZC4b
ZC4a
NOTE A: For correct operation, no terminal may be taken below GND.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DRAIN1
DRAIN1
GATE1
GND
SOURCE1
SOURCE1
SOURCE2
SOURCE2
GND
GATE2
DRAIN2
DRAIN2
DRAIN3
DRAIN3
GATE3
GND
SOURCE3
SOURCE3
SOURCE4
SOURCE4
GND
GATE4
DRAIN4
DRAIN4
DW PACKAGE
(TOP VIEW)
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SLIS038A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Drain-to-source voltage, VDS 60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source-to-GND voltage 100 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drain-to-GND voltage 100 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-to-source voltage range, VGS −9 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current, each output, TC = 25°C 2.25 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current, TC = 25°C 2.25 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, Imax, TC = 25°C (see Note 1 and Figure 15) 11.25 A. . . . . . . . . . . . . . . . .
Continuous gate-to-source zener diode current, TC = 25°C ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed gate-to-source zener diode current, TC = 25°C ±500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-pulse avalanche energy, EAS, TC = 25°C (see Figures 4, 15, and 16) 17.2 mJ. . . . . . . . . . . . . . . . . . .
Continuous total power dissipation, TC = 25°C (see Figure 15) 1.39 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ −40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms, duty cycle = 2%
SLIS038A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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electrical characteristics, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(BR)DSX Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 60 V
VGS(th) Gate-to-source threshold voltage ID = 1 mA,
See Figure 5 VDS = VGS,1.5 1.75 2.2 V
V(BR)GS Gate-to-source breakdown voltage IGS = 250 µA 18 V
V(BR)SG Source-to-gate breakdown voltage ISG = 250 µA 9 V
V(BR) Reverse drain-to-GND breakdown voltage (across
D1, D2, D3, and D4) Drain-to-GND current = 250 µA 100 V
VDS(on) Drain-to-source on-state voltage ID = 2.25 A,
See Notes 2 and 3 VGS = 10 V, 0.5 0.62 V
VF(SD) Forward on-state voltage, source-to-drain IS = 2.25 A,
VGS = 0 (Z1, Z2, Z3, Z4),
See Notes 2 and 3 and Figure 12 0.9 1.1 V
VFForward on-state voltage, GND-to-drain ID = 2.25 A (D1, D2, D3, D4),
See Notes 2 and 3 2.5 V
IDSS
Zero-gate-voltage drain current
VDS = 48 V,
TC = 25°C 0.05 1
A
IDSS Zero-gate-voltage drain current
VDS = 48 V,
VGS = 0 TC = 125°C 0.5 10 µA
IGSSF Forward gate current, drain short circuited to source VGS = 15 V, VDS = 0 20 200 nA
IGSSR Reverse gate current, drain short circuited to
source VSG = 5 V, VDS = 0 10 100 nA
Ilkg
Leakage current, drain-to-GND
VDGND = 48 V
TC = 25°C 0.05 1
A
Ilkg Leakage current, drain-to-GND VDGND = 48 V TC = 125°C 0.5 10 µA
rDS(on)
Static drain-to-source on-state resistance
VGS = 10 V,
ID = 2.25 A,
TC = 25°C 0.23 0.27
Ω
rDS(on) Static drain-to-source on-state resistance
ID = 2.25 A,
See Notes 2 and 3
and Figures 6 and 7 TC = 125°C 0.35 0.4 Ω
gfs Forward transconductance VDS = 15 V, ID = 1.125 A,
See Notes 2 and 3 and Figure 9 1.6 2.1 S
Ciss Short-circuit input capacitance, common source 200 250
Coss Short-circuit output capacitance, common source V
DS
= 25 V,
f = 1 MHz,
V
GS
= 0,
See Figure 11
100 175
pF
Crss Short-circuit reverse-transfer capacitance,
common source
VDS = 25 V,
f = 1 MHz,
VGS = 0,
See Figure 11 60 75
pF
NOTES: 2. Technique should limit TJ − TC to 10°C maximum.
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain and GND-to-drain diode characteristics, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
trr
Reverse-recovery time
I = 1.125 A,
V = 48 V,
Z1, Z2, Z3, and Z4 80
ns
trr Reverse-recovery time IS = 1.125 A,
VGS = 0,
VDS = 48 V,
di/dt = 100 A/µs,
D1, D2, D3, and D4 160 ns
QRR
Total diode charge
S
V
GS
= 0,
See Figures 1 and 14
DS
di/dt = 100 A/
µ
s,
Z1, Z2, Z3, and Z4 0.12
C
QRR Total diode charge
See Figures 1 and 14
D1, D2, D3, and D4 0.5 µC
SLIS038A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
resistive-load switching characteristics, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(on) Turn-on delay time 32 55
td(off) Turn-off delay time
VDD = 25 V,
RL = 20
Ω
,
tr1 = 10 ns,
27 50
ns
tr2 Rise time
VDD = 25 V,
tf1 = 10 ns,
RL = 20 Ω,
See Figure 2
tr1 = 10 ns,
14 30 ns
tf2 Fall time
tf1 = 10 ns,
See Figure 2
7 15
QgTotal gate charge
VDS = 48 V,
ID = 1.125 A,
VGS = 10 V,
6.6 8
Qgs(th) Threshold gate-to-source charge VDS = 48 V,
See Figure 3
ID = 1.125 A, VGS = 10 V, 0.6 0.7 nC
Qgd Gate-to-drain charge
See Figure 3
2.8 3.2
nC
LDInternal drain inductance 5
nH
LSInternal source inductance 5
nH
RgInternal gate resistance 0.25 Ω
thermal resistance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RθJA Junction-to-ambient thermal resistance See Notes 4 and 7 90 °C/W
RθJB Junction-to-board thermal resistance See Notes 5 and 7 49 °C/W
RθJP Junction-to-pin thermal resistance See Notes 6 and 7 28 °C/W
NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink
5. Package mounted on a 24 inch2, 4-layer FR4 printed-circuit board
6. Package mounted in intimate contact with infinite heatsink
7. All outputs with equal power
SLIS038A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
IRM†
Reverse di/dt = 100 A/µs
trr(SD)
†IRM = maximum recovery current
25% of IRM†
VDS = 48 V
VGS = 0
TJ = 25°C
Z1 − Z4‡
Time − ns
− Source-to-Drain Diode Current − AIS
0 50 100 150 200 250 300
0
− 0.75
− 1.5
− 2.25
− 3
− 3.75
− 4.25
1.5
0.75
350 400 450 500
Shaded Area = QRR
‡The above waveform is representative of D1, D2, D3, and D4 in shape only.
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
Pulse Generator
50 Ω
Rgen
50 Ω
VGS
VDD = 25 V
DUT
VDS
TEST CIRCUIT
VDD
VDS(on)
tf2
td(on) tr2
td(off)
VOLTAGE WAVEFORMS
VGS
VDS
RL
CL 30 pF
(see Note A)
tf1
tr1
10 V
0 V
NOTE A: CL includes probe and jig capacitance.
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
SLIS038A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
Qg
10 V
VOLTAGE WAVEFORM
Qgd
Time
Gate Voltage
VGS
12-V
Battery 0.2 µF50 kΩ
0.3 µF
Current
Regulator
DUT
Same Type
as DUT
0IG = 100 µA
IG Current-
Sampling Resistor ID Current-
Sampling Resistor
VDD
TEST CIRCUIT
Qgs(th)
VDS
Figure 3. Gate-Charge Test Circuit and Voltage Waveform
VDD = 25 V
159 µH
ID
twtav
IAS
V(BR)DSX = 60 V Min
VOLTAGE AND CURRENT WAVEFORMS
0 V
0 V
0 V
ID
VDS
DUT
VDS
TEST CIRCUIT
(see Note A)
(see Note B)
Pulse Generator
50 Ω
Rgen
50 Ω
VGS
VGS
15 V
NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration (tw) is increased until peak current IAS = 11.25 A.
Energy test level is defined as EAS +
IAS V(BR)DSX tav
2+17.2 mJ.
Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms
SLIS038A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS
1
0.5
0
− Gate-to-Source Threshold Voltage − V
1.5
2
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
2.5
−40 −20 0 20 40 60 80 100 120 140 160
ID = 1 mA
ID = 100 µA
ÁÁ
ÁÁ
ÁÁ
VGS(th)
T
J
− Junction Temperature − °C
0.4
0.2
0
− Static Drain-to-Source
0.6
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
−40 −20 0 20 40 60 80 100 120 140 160
VGS = 10 V
ÁÁ
ÁÁ
ÁÁ
ÁÁ
rDS(on)
T
J
− Junction Temperature − °C
On-State Resistance −Ω
VGS = 15 V
ID = 2.25 A
VDS = VGS
Figure 5 Figure 6
0.1
0.5
0.1 1 10 100
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
− Static Drain-to-Source
ÁÁ
ÁÁ
ÁÁ
ÁÁ
rDS(on)
On-State Resistance −Ω
VGS = 10 V
VGS = 15 V
TJ = 25°C
ID − Drain Current − A
5
4
2
1
0
9
3
0123456
− Drain Current − A
7
6
8
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
10
78910
VGS = 6 V
VGS = 4 V
VGS = 15 V VGS = 10 V
ÁÁ
ÁÁ
ID
VDS − Drain-to-Source Voltage − V
0.2
0.3
0.4
∆VGS = 0.4 V
TJ = 25°C
(unless otherwise
noted)
Figure 7 Figure 8
PRODUCT PREVIEW
SLIS038A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS
25
15
5
0
Percentage of Units − %
35
45
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
50
40
30
20
10
1.975
2
2.025
2.050
2.075
2.1
2.125
2.150
2.175
2.2
2.225
gfs − Forward Transconductance − S
5
4
2
1
0
9
3
0123456
7
6
8
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
10
78910
TJ = 40°C
TJ = 25°C
TJ = 75°C
TJ = 125°C
TJ = 150°C
− Drain Current − A
ÁÁ
ÁÁ
ID
VGS − Gate-to-Source Voltage − V
VDS = 15 V
ID = 1.125 A
TJ = 25°C
Total Number of Units = 688
Figure 9 Figure 10
200
160
80
40
0
360
120
0 4 8 12162024
280
240
320
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
400
28 32 36 40
Ciss
Coss
Crss
VGS = 0
f = 1MHz
TJ = 25°C
Ciss @ 0 V = 301 pF
Coss @ 0 V = 384 pF
Crss @ 10 V = 144 pF
VDS − Drain-to-Source Voltage − V
1
10
0.1 1
− Source-to-Drain Diode Current − A
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
10
0.1
ISD
VSD − Source-to-Drain Voltage − V
TJ = 125°C
TJ = 150°C
TJ = 25°C
TJ = 75°C
TJ = 40°C
VGS = 0
C − Capacitance − pF
Figure 11 Figure 12
SLIS038A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS
30
20
10
0012
− Drain-to-Source Voltage − V
40
50
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
60
34 675
6
4
2
0
8
10
12
VDD = 20 V
VDD = 48 V
ID = 1.125 A
TJ = 25°C
See Figure 3
VDS
VGS
Qg − Gate Charge − nC
VDD = 30 V
VDD = 20 V
− Gate-to-Source Voltage − V
Figure 13
100
75
25
00 100 200 300
− Reverse-Recovery Time − ns
125
150
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
175
400 500 600
50
Z1, Z2, Z3, and Z4
trr
VDS = 48 V
VGS = 0
IS = 1.125 A
TJ = 25°C
See Figure 1
D1, D2, D3, and D4
Reverse di/dt − A/µs
Figure 14
SLIS038A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
THERMAL INFORMATION
Figure 15
10
1
0.1
100
0.1 1 10 100
− Maximum Drain Current − A
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
500 µs†
1 ms†
10 ms†
RθJP‡
RθJA§
1 µs†
TC = 25°C
ID
VDS − Drain-to-Source Voltage − V
†Less than 2% duty cycle
‡Device mounted in intimate contact with infinite heatsink.
§Device mounted on FR4 printed circuit board with no heatsink.
DC Conditions
Figure 16
10
100
0.01 0.1
− Maximum Peak Avalanche Current − A
MAXIMUM PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
100
1
IAS
tav − Time Duration of Avalanche − ms
TC = 25°C
TC = 125°C
See Figure 4
1.0 10
SLIS038A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
THERMAL INFORMATION
DW PACKAGE†
JUNCTION-TO-BOARD THERMAL RESISTANCE
vs
PULSE DURATION
†Device mounted on 24in2, 4-layer FR4 printed-circuit board with no heatsink.
NOTE A: ZθJB(t) = r(t) RθJB
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc
JBθC/W
°
− Junction-to-Board Thermal Resistance −
R
tw − Pulse Duration − s
10
100
0.0001 0.001
1
0.1 0.01 0.1 1 100
tw
tc
ID
0
d = 0.02
d = 0.01
Single Pulse
10
d = 0.2
d = 0.5
DC Conditions
d = 0.1
d = 0.05
Figure 17
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPIC5403DW OBSOLETE SOIC DW 24 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
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Addendum-Page 1
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