UC3842T UC3843T
UC3844T UC3845T
Septe mbe r 20 01
HIGH PERFORMANCE CURRENT MOD E PWM CONTRO LLER
.TRIMMED OSCILLATOR FOR PRECISE FRE-
QUENCY CO NT ROL
.OSCILLATOR FREQUENCY GUARANTEED
AT 250kHz
.CURRENT MODE OP ER A TION TO 500kHz
.AUTOMATIC FEED FORWARD COMPENSA-
TION
.LATCHING PWM FOR CYCLE-BY-CYCLE
CURRENT LIMITING
.INTERNALLY TRIMMED REFERENCE WITH
UNDERVOLTAGE LOCKOUT
.HIGH CURRENT TOTE M P OLE OU TPUT
.UNDERVOLTAGE LOCKOUT WITH HYSTER-
ESIS
.LOW STAR T-UP AND OPERATING CU RRENT
DESCRIPTION
The UC384XT family of control ICs provides the
necessary features to implement off-line or DC to
DC fixed frequency current mode control schemes
with a minimal external parts count. Internally imple-
men ted cir cuits i nclude a trimm ed oscil lator fo r pre-
cise DUTY CYCLE CONTROL under voltage lock-
out featuring start-up current less than 0.5mA, a pre-
cision reference trimmed for accuracy at the error
amp input, logic to insure la tche d operation, a PW M
comparator which also provides current limit control,
and a totem pole output stage designed to source
or sink high peak current. The output stage, suitable
for driving N-Channel MOSFETs, is low in the off-
state.
Differenc es between members of this family are the
under-voltage lockout thr esholds and maximum duty
cycle ranges. The UC3842T and UC3844T have
UVLO thresholds of 16V (on) and 10V (off), ideally
suited to off-line applications The corresponding
thres holds for the UC3843T and UC3845T are 8.5 V
and 7.9 V. The UC3842T and UC3843T can oper ate
to duty cycles approaching 100% . A range of zero to
< 50 % is obtained by the UC3844T and UC3845T by
the addition of an internal toggle flip flop which blanks
the output off every other clock c ycle.
BLOCK DIAGRAM (toggle fl ip flop used only in UC3844T and UC3845 T)
UVLO
S/R 5V
REF
34V
INTERNAL
BIAS
VREF GOOD
LOGIC
2.50V
T
S
R
OSC
R1V
CURRENT
SENSE
COMPARATOR
2R
+
-PWM
LATCH
7
5
4
2
1
3
8
6
ERROR AMP.
Vi
GROUND
RT/CT
VFB
COMP
CURRENT
SENSE
VREF
5V 50mA
OUTPUT
D95IN331
Minidip
®
SO8
1/15
*All voltages are with re spect to pin 5, al l curren ts ar e positi ve into t he specif ied te rminal.
PIN CONNECTION (top view)
COMP
VFB
ISENSE
RT/CTGROUND
OUTPUT
Vi
VREF
1
3
2
4
6
5
7
8
D95IN332
Minidip/SO8
ORDERING NUMBERS
SO8 Minidip
UC3842TD
UC3843TD
UC3844TD
UC3845TD
UC3842TN
UC3843TN
UC3844TN
UC3845TN
ABSOL UTE M AXIMUM RA TINGS
Symbol Parameter Value Unit
ViSupply Voltage (low impedance source) 30 V
ViSupply Voltage (Ii < 30mA) Self Limiting
IOOutp ut Cur re nt ±1A
EOOutput Energy (capacitive load) 5 µJ
Analog Inputs (pins 2, 3) – 0.3 to 5.5 V
Error Amplifier Output Sink Current 10 mA
Ptot Power Dissipation at Tamb ≤ 25 °C (Minidip) 1.25 W
Ptot Power Dissipation at Tamb ≤ 25 °C (SO8) 800 mW
Tstg Storage Temperature Range – 65 to 150 °C
TLLead Temperature (soldering 10s) 300 °C
PIN F U NCTIO NS
No Function Description
1 COMP This pin is the Error Amplifier output and is made available for loop compensation.
2V
FB This is the inverting input of the Error Amplifier. It is normally connected to the switching
power supply output through a resistor divider.
3I
SENSE A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
4R
T
/CTThe oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor RT to Vref and cpacitor C T to ground. Operation to 500kHz is possible.
5 GROUND This pin is the combined control circuitry and power ground.
6 OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced
and sunk by this pin.
7V
CC This pin is the positive supply of the control IC.
8V
ref This is the reference output. It provides charging current for capacitor C T through resistor R T.
UC3842T - UC 3843T - UC 3844T - UC3845T
2/15
ELECT RICAL C HARACTE RISTIC S ( [note 1] Unless otherwi se stated, these s pec ifications apply for
0 < Tamb < 105° C; V i = 15V (note 5); RT = 10K; CT = 3.3nF)
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
REFERENCE SECTION
∆VREF Line Regulation 12V ≤ Vi ≤ 25V 220mV
∆
V
REF Load Regulation 1 ≤ Io ≤ 20mA 325mV
∆
V
REF/∆TTemperature Stability (Note 2) 0.2 mV/°C
Total Output Variation Line, Load, Temperature 4.85 5.15 V
eNOutput Noise Voltage 10Hz ≤ f ≤ 10KHz Tj = 25°C
(note 2) 50 µV
Long Term Stability Tamb = 125°C, 1000Hrs (note 2) 525mV
I
SC Output Short Circuit -30 -100 -180 mA
OSCILLATOR SECTION
fOSC Frequency Tj = 25°C
TA = Tlow to Thigh
TJ = 25°C (RT = 6.2k, CT = 1n F)
49
48
225
52
–
250
55
56
275
KHz
KHz
KHz
∆fOSC/∆VFrequen cy Cha nge wit h V olt. VCC = 12V to 25V – 0.2 1 %
∆fOSC/∆TFrequency Change with Temp. TA = Tlow to Thigh –1–%
V
OSC Oscillator Voltage Swing (peak to peak) – 1.6 – V
Idischg Discharge Current (VOSC =2V) TA = Tlow to Thigh 7.3–8.8mA
ERROR AMP SECTION
V2Input Voltage VPIN1 = 2.5V 2.42 2.50 2.58 V
IbInput Bias C urrent VFB = 5V -0.1 -2 µA
AVOL 2V ≤ Vo ≤ 4V 65 90 dB
BW Unity Gain Bandwidth TJ = 25° C 0.7 1 MHz
PSRR Pow er Supply Rejec. Ratio 12V ≤ Vi ≤ 25V 60 70 dB
IoOutput Sink Current VPIN2 = 2.7V VPIN1 = 1.1V 2 12 m A
IoOutput Source Current VPIN2 = 2.3V VPIN1 = 5V -0.5 -1 m A
VOUT High VPIN2 = 2.3V;
RL = 15KΩ to Ground 5 6.2 V
VOUT Low VPIN2 = 2.7V;
RL = 15KΩ to Pin 8 0.8 1.1 V
CURRENT SENSE SECTION
GVGain (note 3 & 4) 2.85 3 3.15 V/V
V3Maximum Input Signal VPIN1 = 5V (note 3) 0.9 1 1.1 V
SVR Supply Voltage Rejection 12 ≤ Vi ≤ 25V (note 3) 70 dB
IbInput Bias C urrent -2 -10 µA
Delay to Output 100 300 ns
THERMAL D ATA
Symbol Description Minidip SO8 Unit
Rth j- a mb Thermal Resistance Junction-ambient. max. 100 150 °C/W
U3842T - UC 3843T - UC3844T - UC3845T
3/15
Notes : 1. Max packa ge power d issipati on l imits must be respe cte d; low duty cycle pul se t echniq ues are used durin g t est mai ntain Tj as
close to Tamb as po ssib le.
2. These param et ers, alth ough guaranteed, are not 1 00% t est ed in product i on.
3. Paramet er m easured at tri p poi nt of la tch wit h V PIN2 = 0.
4. Ga in de fined as :
∆ VPIN1
A = ; 0 ≤ VPIN3 ≤ 0.8 V
∆ VPIN3
5. Adj ust Vi above th e sta rt th reshold bef ore set t i ng at 15 V .
ELE CTRIC AL CHARAC TE RI S TI CS ( co ntinued)
Symbol Parameter Test Conditions Value Unit
Min. Typ. Max.
OUTPUT SECTION
VOL Output Low Level ISINK = 20mA 0.1 0.4 V
ISINK = 200mA 1.6 2.2 V
VOH Output High Level ISOURCE = 20mA 13 13.5 V
ISOURCE = 200mA 12 13.5 V
VOLS UVLO Saturation VCC = 6V; ISINK = 1mA 0.1 1.1 V
trRise Time Tj = 25°C CL = 1nF (2) 50 150 ns
tfFall Time Tj = 25°C CL = 1nF (2) 50 150 ns
UNDER-VOLTAGE LOCKOUT SECTION
Start Threshold UC3842T/4T 15 16 17 V
UC3843T/5T 7.8 8.4 9.0 V
Min Operating Voltage
After Turn-on UC3842T/4T 9 10 11 V
UC3843T/5T 7.0 7.6 8.2 V
PWM SECTION
Maximum Duty Cy cle UC3842T/3T 94 96 100 %
UC3844T/5T 47 48 50 %
Minimum Duty Cycle 0%
TOTAL STANDBY CURRENT
Ist Start-up Current Vi = 6.5V for UC3843T/45T 0.3 0.5 m A
Vi = 14V for UC3842T/44T 0.3 0.5 m A
IiOperating Supply Current VPIN2 = VPIN3 = 0V 12 17 mA
Viz Zener Voltage Ii = 25mA 30 36 V
UC3842T - UC 3843T - UC 3844T - UC3845T
4/15
Figure 1: Open L oop T e st Circuit .
R
T
A2N2222
4.7KΩ
1KΩ
ERROR AMP.
ADJUST
4.7KΩ5KΩ
I
SENSE
ADJUST
100KΩCOMP
V
FB
I
SENSE
R
T
/C
T
1
2
3
4
C
T
7
6
5
8
V
REF
V
i
OUTPUT
GROUND
0.1µF
0.1µF
V
REF
V
i
OUTPUT
GROUND
1W
1KΩ
D95IN343
D.U.T.
High peak currents associated with capacitive loads
necessitate careful grounding techniques. Timing
and bypass capacitors should be connected close
to pi n 5 i n a single poi nt gr oun d. The transis to r and
5 KΩ potentiometer are used to sample the oscillator
wav ef or m a nd ap ply an adjustabl e ra m p to pin 3 .
10K 20K 30K 50K 100K 200K 300K 500K f
OSC
(KHz)
1
2
5
10
20
50
D95IN333
C
T
=10nF
C
T
=5nF
C
T
=2nF
C
T
=1nF
C
T
=500pF
C
T
=200pF
C
T
=100pF
V
i
=15V
T
A
=25˚C
RT
(KΩ)
0.8
Figure 2: Timing Resistor vs. Oscillator Fre-
quency
10K 20K 30K 50K 100K 200K 300K 500K fOSC(KHz)
1
2
3
5
10
20
30
50
%
C
T
=10nF
C
T
=5nF
C
T
=2nF
C
T
=1nF
C
T
=500pF
C
T
=200pF
C
T
=100pF
D95IN334
V
i
=15V
T
A
=25˚C
Figure 3: Output Dead-Time vs. Oscillator Fre-
quency
U3842T - UC 3843T - UC3844T - UC3845T
5/15
-55 -25 0 25 50 75 100 T
A
(˚C)
7.0
7.5
8.0
8.5
I
dischg
(mA)
D95IN335
V
i
=15V
V
OSC
=2V
Figure 4: Oscillator Discharge Current vs. Tem-
perature.
1235
40
50
60
70
80
90
D
max
(%)
0.8 R
T
(KΩ)
D95IN336
V
i
=15V
C
T
=3.3nF
T
A
=25˚C
I
dischg
=7.5mA
I
dischg
=8.8mA
Figure 5: Maximum Output Duty Cycle vs. Tim-
ing Resistor.
10 100 1K 10K 100K 1M f(Hz)
-20
0
20
40
60
80
(dB)
180
150
120
90
60
30
φ
D95IN337
V
i
=15V
V
O
=2V to 4V
R
L
=100K
T
A
=25˚C
Gain
Phase
Figure 6: Error Amp Open-Loop Gain and
Phase vs. Frequency.
0246V
O
(V)
0.0
0.2
0.4
0.6
0.8
1.0
V
th
(V)
D95IN338
V
i
=15V
T
A
=-40˚C
T
A
=125˚C
T
A
=25˚C
Figure 7: Current Sense Input Threshold vs. Er-
ror Amp Output Voltage.
0 20406080100I
ref(mA)
D95IN339
0
10
20
30
40
50
60 Vi=15V
TA=-40˚C
TA=125˚C
TA=25˚C
Figure 8: Reference Voltage Change vs.
Source Current.
-55 -25 0 25 50 75 100 T
A
(˚C)
D95IN340
50
60
70
80
90
100
I
SC
(mA) V
i
=15V
R
L
≤0.1Ω
Figure 9: Reference Short Circuit Current vs.
Temperature.
UC3842T - UC 3843T - UC 3844T - UC3845T
6/15
0 200 400 600 I
O
(mA)
0
1
2
3
-2
-1
V
sat
(V)
D95IN341
V
i
=15V
80µs Pulsed Load 120Hz Rate
T
A
=-40˚C
T
A
=25˚C
V
i
T
A
=-40˚C T
A
=25˚C
GND
Sink Saturation
(Load to V
i
)
Source Saturation
(Load to Ground)
Figure 10: Output Saturation Voltagevs. Load
Current.
0102030V
i
(V)
0
5
10
15
20
I
i
(mA)
UCX843/45
UCX842/44
R
T
=10K
C
T
=3.3nF
V
FB
=0V
I
Sense
=0V
T
A
=25˚C
D95IN342
Figure 11: Supply Current vs. Supply Voltage.
Figure 12: Output Waveform. Figure 13: Output Cross Conduct ion
5V REG
OSCILLATOR
PWM
CLOCK
8
4
5
6
RT
CT
GND
OUTPUT
7
Vi
ID
CT
OUTPUT
LARGE RT/SMALL CT
CT
OUTPUT
SMALL RT/LARGE CT
D95IN344
Figure 14: Oscillator and Output Waveforms.
Vi =15 V
CL = 1.0nF
TA = 25°C
90%
10%
50ns/DIV
Vi =30V
CL = 15pF
TA = 25°C
VO
ICC
100ns/DIV
100mA/DIV
20V/DIV
U3842T - UC 3843T - UC3844T - UC3845T
7/15
Figure 15 : Error A m p C onf ig ura t ion.
Z
i
Z
f
1mA
2
1
V
FB
COMP
2.5V
D95IN345
+
-
Figure 16 : Under V ol t age Lo c ko ut .
UC3842T
UC3844T UC3843T
UC3845T
16V 8.4V
10V 7.6V
V
ON
V
OFF
V
i
ON/OFF COMMAND
TO REST OF IC
7
<0.5mA
<17mA
I
CC
V
CC
V
OFF
V
ON
D99IN1058
Figure 17 : Curre nt Se ns e Cir c uit .
ERROR
AMPL. 2R
R1V
CURRENT
SENSE
COMPARATOR
1
CURRENT
SENSE
COMP
CR
S
R3
5
GND
I
S
D95IN347
Peak c ur re nt (i s) is det er m ine d by th e form u la
1.0 V
IS max ≈RS
A small RC filt er ma y b e re quir ed to sup pres s s w it ch tran si ent s .
Duri ng UVLO, the Output i s low
UC3842T - UC 3843T - UC 3844T - UC3845T
8/15
Figure 18 : Slop e Com pensation T ec hni ques.
RS
R1
ISRSLOPE CT
RT
VREG 8
RT/CT
ISENSE
4
35
GND RS
R1
IS
RSLOPE CT
RT
VREG 8
RT/CT
ISENSE
4
35
GND
D99IN1059
UC3842T UC3842T
Figure 19 : Isolat ed M OS F E T Drive and Current Transformer Se ns ing.
7
6
COMP/LATCH
ISOLATION
BOUNDARY
D95IN349
5.0Vref
V
CC
+
-
+
-
Q
S
R
+
-
3R
R
S
N
S
C
V
in
Q1
N
P
V
GS
Waveforms
+
0+
0
-- 50% DC 25% DC
I
pk
= V
(pin 1)
-1.4
3R
S
N
S
N
P
()
U3842T - UC 3843T - UC3844T - UC3845T
9/15
Figure 20 : Latched Shutdown.
D95IN350
BIAS
+
-EA
R
+
OSC
2N
3905
2N
3903
1mA
R
R
2R
1
2
8
4
SCR must be selected for a holding current of less than 0.5mA at T
A(min)
.
The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10K.
5
D95IN351
+
-EA
R
i
+
1mA
R
d
R
2R
5
C
f
R
f
1
2
From V
O
2.5V
+
-EA
R
P
+
1mA
R
d
R
2R
5
C
f
R
f
1
2
From V
O
2.5V
Error Amp compensation circuit for stabilizing any current-mode topology except
for boost and flyback converters operating with continuous inductor current.
C
P
R
i
Error Amp compensation circuit for stabilizing current-mode boost and flyback
topologies operating with continuous inductor current.
Figure 21: Error Amplifier Compensation
UC3842T - UC 3843T - UC 3844T - UC3845T
10/15
D99IN1060
+
-
+
RA
1
7
f =
R
BIAS
OSC
C
6
VREF
RRB
+
-
+
-EA R
2R
R
S
Q
84
5
2
3
5K
5K
5K NE555
8
4
2
1
5
TO ADDITIONAL
UC384XT
1.44
(RA + 2RB)C Dmax = RB
RA + 2RB
Figure 23: External Duty Cycle Clamp and Multi Unit Synchronization.
D95IN352
+
-EA
+
R
2R
5
R
T
1
2
EXTERNAL
SYNC INPUT
The diode clamp is required if the Sync amplitude is large enough to cause
the bottom side of C
T
to go more than 300mV below ground
R
BIAS
OSC
C
T
0.01µF
47Ω
4
8
V
REF
R
Figure 22: External Clock Synchronization.
U3842T - UC 3843T - UC3844T - UC3845T
11/15
D95IN354
+
R
BIAS
OSC
C
R
+
-
+
-EA R
2R
R
S
Q
8
4
2
1
5
1mA
1V
+
-
5V
ref
1MΩ
Figure 24: Soft-Start Cir cuit
D95IN355
+
R
BIAS
OSC
C
R
+
-
+
-EA R
2R
R
S
Q
8
4
2
1
5
1mA
1V
+
-
5V
ref
R2
R1
V
Clamp
+
-
Comp/Latch
7
R
S
V
CC
Q1
V
in
7
6
5
BC109
V
CLAMP
=
·
R
1
R
1
+ R
2
where 0 <V
CLAMP
<1V I
pk(max)
= V
CLAMP
R
S
Figure 25: Sof t-Start and Error Amplifier Output Duty Cyc le Clamp.
UC3842T - UC 3843T - UC 3844T - UC3845T
12/15
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.069
a1 0.1 0.25 0.004 0.010
a2 1.65 0.065
a3 0.65 0.85 0.026 0.033
b 0.35 0.48 0.014 0.019
b1 0.19 0.25 0.007 0.010
C 0.25 0.5 0.010 0.020
c1 45° (typ.)
D (1) 4.8 5.0 0.189 0.197
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 3.81 0.150
F (1) 3.8 4.0 0.15 0.157
L 0.4 1.27 0.016 0.050
M 0.6 0.024
S8° (max.)
(1) D and F do not include mold flash or protrusions. Mold flash or
potrusions shall not exceed 0.15mm (.006inch).
SO8
OUTLINE AND
MECHANICAL DATA
U3842T - UC 3843T - UC3844T - UC3845T
13/15
Minidip
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 3.32 0.131
a1 0.51 0.020
B 1.15 1.65 0.045 0.065
b 0.356 0.55 0.014 0.022
b1 0.204 0.304 0.008 0.012
D 10.92 0.430
E 7.95 9.75 0.313 0.384
e 2.54 0.100
e3 7.62 0.300
e4 7.62 0.300
F 6.6 0.260
I 5.08 0.200
L 3.18 3.81 0.125 0.150
Z 1.52 0.060
OUTLINE AND
MECHANICAL DATA
UC3842T - UC 3843T - UC 3844T - UC3845T
14/15
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the conse-
quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMi-
croelectronics products are not authorized for use as critical components in life support devices or systems without express written
approval of STMicr oelectroni cs. T he ST logo is a register ed tradem ark of STMic roelec tronics
© 2001 ST Microelec troni cs – Prin ted in Italy – All R ights Res erved
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U3842T - UC 3843T - UC3844T - UC3845T
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