CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
36-Mbit QDR® II SRAM Two-Word
Burst Architecture
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document Number: 001-57825 Rev. *O Revised January 3, 2018
36-Mbit QDR® II SRAM Two-Word Burst Architectur e
Features
Separate independent read and write data ports
Supports concurrent transactions
333 MHz clock for high bandwidth
Two-word burst on all accesses
Double data rate (DDR) Interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR® II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
Available in × 9, × 18, and × 36 configurations
Full data coherency, providing most current data
Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
Supports both 1.5 V and 1.8 V I/O supply
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free Packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
Phase locked loop (PLL) for accurate data placement
Configurations
CY7C1425KV18 – 4M × 9
CY7C1412KV18 – 2M × 18
CY7C1414KV18 – 1M × 36
Functional Description
The CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18
are 1.8 V synchronous pipelined SRAMs, equipped with QDR II
architecture. QDR II architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II architecture has separate data inputs and
data outputs to completely eliminate the need to “turnaround” the
data bus that exists with common I/O devices. Access to each
port is through a common address bus. Addresses for read and
write addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR II read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with two 9-bit
words (CY7C1425KV18), 18-bit words (CY7C1412KV18), or
36-bit words (CY7C1414KV18) that burst sequentially into or out
of the device. Because data can be transferred into and out of
the device on every rising edge of both input clocks (K and K and
C and C), memory bandwidth is maximized while simplifying
system design by eliminating bus turnarounds.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Description 333 MHz 300 MHz 250 MHz Unit
Maximum operating frequency 333 300 250 MHz
Maximum operating current × 9 730 680 590 mA
× 18 750 700 610
× 36 910 850 730
Document Number: 001-57825 Rev. *O Page 2 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Logic Block Diagram – CY7C1425KV18
2M x 9 Array
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
9
21
18
9
BWS[0]
VREF
Write Add. Decode
Write
Reg
9
A(20:0)
21
CQ
CQ
DOFF
Q[8:0]
9
9
Write
Reg
C
C
2M x 9 Array
9
Logic Block Diagram – CY7C1412KV18
1M x 18 Array
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
20
36
18
BWS[1:0]
VREF
Write Add. Decode
Write
Reg
18
A(19:0)
20
CQ
CQ
DOFF
Q[17:0]
18
18
Write
Reg
C
C
1M x 18 Array
18
Document Number: 001-57825 Rev. *O Page 3 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Logic Block Diagram – CY7C1414KV18
512K x 36 Array
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
19
72
36
BWS[3:0]
VREF
Write Add. Decode
Write
Reg
36
A(18:0)
19
CQ
CQ
DOFF
Q[35:0]
36
36
Write
Reg
C
C
512K x 36 Array
36
Document Number: 001-57825 Rev. *O Page 4 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Contents
Pin Configurations ...........................................................5
Pin Definitions ..................................................................7
Functional Overview ........................................................8
Read Operations .........................................................8
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
Concurrent Transactions ............................................. 9
Depth Expansion .........................................................9
Programmable Impedance .......................................... 9
Echo Clocks ................................................................ 9
PLL ..............................................................................9
Application Example ......................................................10
Truth Table ......................................................................11
Write Cycle Descriptions ...............................................11
Write Cycle Descriptions ...............................................12
Write Cycle Descriptions ...............................................12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port .......................................................13
Performing a TAP Reset ...........................................13
TAP Registers ........................................................... 13
TAP Instruction Set ...................................................13
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ......................................16
TAP Electrical Characteristics ......................................16
TAP AC Switching Characteristics ............................... 17
TAP Timing and Test Conditions ..................................18
Identification Register Definitions ................................19
Scan Register Sizes .......................................................19
Instruction Codes ........................................................... 19
Boundary Scan Order .................................................... 20
Power Up Sequence in QDR II SRAM ........................... 21
Power Up Sequence ................................................. 21
PLL Constraints ......................................................... 21
Maximum Ratings ........................................................... 22
Operating Range ............................................................. 22
Neutron Soft Error Immunity ......................................... 22
Electrical Characteristics ............................................... 22
DC Electrical Characteristics ..................................... 22
AC Electrical Characteristics ..................................... 24
Capacitance .................................................................... 24
Thermal Resistance ........................................................ 24
AC Test Loads and Waveforms ..................................... 24
Switching Characteristics .............................................. 25
Switching Waveforms .................................................... 27
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagram ............................................................ 29
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC® Solutions ...................................................... 33
Cypress Developer Community ................................. 33
Technical Support ..................................................... 33
Document Number: 001-57825 Rev. *O Page 5 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Pin Configurations
The pin configurations for CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow. [1]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1425KV18 (4M × 9)
12345678910 11
ACQ NC/72M A WPS NC K NC/144M RPS AACQ
BNC NC NC A NC/288M K BWS0ANCNCQ4
CNC NC NC VSS AAAV
SS NC NC D4
DNC D5 NC VSS VSS VSS VSS VSS NC NC NC
ENC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3
FNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
GNC D6 Q6 VDDQ VDD VSS VDD VDDQ NC NC NC
HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC NC VDDQ VDD VSS VDD VDDQ NC Q2 D2
KNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
LNC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1
MNC NC NC VSS VSS VSS VSS VSS NC NC D1
NNC D8 NC VSS AAAV
SS NC NC NC
PNC NC Q8 A A C A A NC D0 Q0
RTDOTCKAAACAAATMSTDI
Note
1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-57825 Rev. *O Page 6 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
CY7C1412KV18 (2M × 18)
12345678910 11
ACQ NC/144M A WPS BWS1KNC/288M RPS ANC/72MCQ
BNC Q9 D9 A NC K BWS0ANCNCQ8
CNC NC D10 VSS AAAV
SS NC Q7 D8
DNC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
ENC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
FNC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
GNC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
KNC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
LNC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
MNC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
NNC D17 Q16 VSS AAAV
SS NC NC D1
PNC NC Q17 A A C A A NC D0 Q0
RTDOTCKAAACAAATMSTDI
CY7C1414KV18 (1M × 36)
12345678910 11
ACQ NC/288M NC/72M WPS BWS2KBWS1RPS A NC/144M CQ
BQ27 Q18 D18 A BWS3KBWS
0AD17Q17Q8
CD27 Q28 D19 VSS AAAV
SS D16 Q7 D8
DD28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
EQ29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6
FQ30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
GD30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5
HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JD31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4
KQ32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3
LQ33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
MD33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
ND34 D26 Q25 VSS AAAV
SS Q10 D9 D1
PQ35 D35 Q26 A A C A A Q9 D0 Q0
RTDOTCKAAACAAATMSTDI
Pin Configurations (continued)
The pin configurations for CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow. [1]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
Document Number: 001-57825 Rev. *O Page 7 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Pin Definitions
Pin Name I/O Pin Description
D[x:0] Input-
synchronous
Data input signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1425KV18 D[8:0]
CY7C1412KV18 D[17:0]
CY7C1414KV18 D[35:0]
WPS Input-
synchronous
Write port select active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
BWS0,
BWS1,
BWS2,
BWS3
Input-
synchronous
Byte write select 0, 1, 2, and 3 active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the
write operations. Bytes not written remain unaltered.
CY7C1425KV18 BWS0 controls D[8:0].
CY7C1412KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1414KV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select
ignores the corresponding byte of data and it is not written into the device.
A Input-
synchronous
Address inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks during
active read and write operations. These address inputs are multiplexed for both read and write
operations. Internally, the device is organized as 4M × 9 (2 arrays each of 2M × 9) for CY7C1425KV18,
2M × 18 (2 arrays each of 1M × 18) for CY7C1412KV18, and 1M × 36 (2 arrays each of 512K × 36) for
CY7C1414KV18. Therefore, only 21 address inputs are needed to access the entire memory array of
CY7C1425KV18, 20 address inputs for CY7C1412KV18, and 19 address inputs for CY7C1414KV18.
These inputs are ignored when the appropriate port is deselected.
Q[x:0] Output-
synchronous
Data output signals. These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of the C and C clocks during read operations, or K and K when in single
clock mode. When the read port is deselected, Q[x:0] are automatically tristated.
CY7C1425KV18 Q[8:0]
CY7C1412KV18 Q[17:0]
CY7C1414KV18 Q[35:0]
RPS Input-
synchronous
Read port select active LOW. Sampled on the rising edge of positive input clock (K). When active, a
read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tristated following the next rising edge
of the C clock. Each read access consists of a burst of two sequential transfers.
C Input clock Positive input clock for output data. C is used in conjunction with C to clock out the read data from
the device. Use C and C together to deskew the flight times of various devices on the board back to the
controller. See Application Example on page 10 for further details.
CInput clock Negative input clock for output data. C is used in conjunction with C to clock out the read data from
the device. Use C and C together to deskew the flight times of various devices on the board back to the
controller. See Application Example on page 10 for further details.
K Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
KInput clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
CQ Echo clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in Switching Characteristics on page 25.
CQ Echo clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the Switching Characteristics on page 25.
Document Number: 001-57825 Rev. *O Page 8 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Functional Overview
The CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18
are synchronous pipelined burst SRAMs with a read port and a
write port. The read port is dedicated to read operations and the
write port is dedicated to write operations. Data flows into the
SRAM through the write port and flows out through the read port.
These devices multiplex the address inputs to minimize the
number of address pins required. By having separate read and
write ports, the QDR II completely eliminates the need to turn
around the data bus and avoids any possible data contention,
thereby simplifying system design. Each access consists of two
9-bit data transfers in the case of CY7C1425KV18, two 18-bit
data transfers in the case of CY7C1412KV18, and two 36-bit
data transfers in the case of CY7C1414KV18 in one clock cycle.
This device operates with a read latency of one and half cycles
when DOFF pin is tied HIGH. When DOFF pin is set LOW or
connected to VSS then the device behaves in QDR I mode with
a read latency of one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input timing is
referenced from the rising edge of the input clocks (K and K) and
all output timing is referenced to the output clocks (C and C, or
K and K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the output clocks (C and C, or K and K when in
single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C1412KV18 is described in the following sections. The
same basic descriptions apply to CY7C1425KV18, and
CY7C1414KV18.
Read Operations
The CY7C1412KV18 is organized internally as two arrays of
1M × 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address is latched on the rising edge of the K clock. The address
presented to the address inputs is stored in the read address
register. Following the next K clock rise, the corresponding
lowest order 18-bit word of data is driven onto the Q[17:0] using
C as the output timing reference. On the subsequent rising edge
of C, the next 18-bit data word is driven onto the Q[17:0]. The
requested data is valid 0.45 ns from the rising edge of the output
clock (C and C or K and K when in single clock mode).
Synchronous internal circuitry automatically tristates the outputs
following the next rising edge of the output clocks (C/C). This
enables for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF Input PLL turn off active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the operation with the PLL turned off differs from those listed in this data sheet. For normal operation,
connect this pin to a pull up through a 10 K or less pull-up resistor. The device behaves in QDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR I timing.
TDO Output TDO pin for JTAG.
TCK Input TCK pin for JTAG.
TDI Input TDI pin for JTAG.
TMS Input TMS pin for JTAG.
NC N/A Not connected to the die. Can be tied to any voltage level.
NC/72M Input Not connected to the die. Can be tied to any voltage level.
NC/144M Input Not connected to the die. Can be tied to any voltage level.
NC/288M Input Not connected to the die. Can be tied to any voltage level.
VREF Input-
reference
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
VDD Power supply Power supply inputs to the core of the device.
VSS Ground Ground for the device.
VDDQ Power supply Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name I/O Pin Description
Document Number: 001-57825 Rev. *O Page 9 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D[17:0] is latched and stored into the
lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
presented to D[17:0] is also stored into the write data register,
provided BWS[1:0] are both asserted active. The 36 bits of data
are then written into the memory array at the specified location.
When deselected, the write port ignores all inputs after the
pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C1412KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate byte write select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the byte write select input during the
data portion of a write enables the data stored in the device for
that byte to remain unaltered. This feature is used to simplify
read, modify, or write operations to a byte write operation.
Concurrent Transactions
The read and write ports on the CY7C1412KV18 operate
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. The user can start reads and writes in the same clock cycle.
If the ports access the same location at the same time, the SRAM
delivers the most recent information associated with the
specified address location. This includes forwarding data from a
write cycle that was initiated on the previous K clock rise.
Depth Expansion
The CY7C1412KV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to enable the SRAM to adjust its output
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350 , with VDDQ =1.5 V. The
output impedance is adjusted every 1024 cycles upon power-up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR II to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are
synchronized to the output clock of the QDR II. In the single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K. The timing for the echo clocks is shown in
Switching Characteristics on page 25.
PLL
These chips use a PLL which is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
20 s of stable clock. The PLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in QDR I mode (with one cycle latency and a longer
access time).
Document Number: 001-57825 Rev. *O Page 10 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Application Example
Figure 2 shows two QDR II used in an application.
Figure 2. Application Example (Width Expansion)
D[x:0]
ARPS
WPS BWS KK
Q[x:0]
ZQ
SRAM#1 CQ/CQ
D[x:0]
ARPS
WPS BWS KK
Q[x:0]
ZQ
SRAM#2 CQ/CQ
DATA IN[2x:0]
DATA OUT [2x:0]
ADDRESS
RPS
WPS
BWS
CLKIN1/CLKIN1
CLKIN2/CLKIN2
SOURCE K
SOURCE K
FPGA / ASIC
RQ RQ
CCCC
DELAYED K
DELAYED K
Document Number: 001-57825 Rev. *O Page 11 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Truth Table
The truth table for CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow. [2, 3, 4, 5, 6, 7]
Operation KRPS WPS DQ DQ
Write cycle:
Load address on the rising edge of K;
input write data on K and K rising edges.
L–H X L D(A + 0) at K(t) D(A + 1) at K(t)
Read cycle:
Load address on the rising edge of K;
wait one and a half cycle; read data on C and C rising edges.
L–H L X Q(A + 0) at C(t + 1) Q(A + 1) at C(t + 2)
NOP: No operation L–H H H D = X
Q = high Z
D = X
Q = high Z
Standby: Clock stopped Stopped X X Previous state Previous state
Write Cycle Descriptions
The write cycle description table for CY7C1412KV18 follow. [2, 8]
BWS0BWS1KKComments
L L L–H During the data portion of a write sequence
CY7C1412KV18 both bytes (D[17:0]) are written into the device.
L L L–H During the data portion of a write sequence:
CY7C1412KV18 both bytes (D[17:0]) are written into the device.
L H L–H During the data portion of a write sequence:
CY7C1412KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L H L–H During the data portion of a write sequence
CY7C1412KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H L L–H During the data portion of a write sequence
CY7C1412KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H L L–H During the data portion of a write sequence
CY7C1412KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H H L–H No data is written into the devices during this portion of a write operation.
H H L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Is based on a write cycle that was initiated in accordance with the Truth Table. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as
long as the setup and hold requirements are achieved.
Document Number: 001-57825 Rev. *O Page 12 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Write Cycle Descriptions
The write cycle description table for CY7C1425KV18 follow. [9, 10]
BWS0K K Comments
L L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
H L–H No data is written into the device during this portion of a write operation.
H L–H No data is written into the device during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1414KV18 follow. [9, 10]
BWS0BWS1BWS2BWS3K K Comments
L L L L L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L L L L L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L H H H L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L H H H L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H L H H L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H L H H L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H H L H L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H L H L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H H L L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H L L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H H L–H No data is written into the device during this portion of a write operation.
H H H H L–H No data is written into the device during this portion of a write operation.
Notes
9. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
10. Is based on a write cycle that was initiated in accordance with the Truth Table on page 11. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a
write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-57825 Rev. *O Page 13 of 33
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8 V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull-up resistor. TDO
must be left unconnected. Upon power-up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
Test Access Port
Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram on page 15. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 19).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and is performed when the SRAM is operating. At power
up, the TAP is reset internally to ensure that TDO comes up in a
high Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions are serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 16. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to enable
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are
used to capture the contents of the input and output ring.
The Boundary Scan Order on page 20 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 19.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 19. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Document Number: 001-57825 Rev. *O Page 14 of 33
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CY7C1414KV18
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a high Z state until the next command is supplied during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP may then try to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
high Z condition.
This bit is set by entering the SAMPLE/PRELOAD or EXTEST
command, and then shifting the desired bit into that cell, during
the Shift-DR state. During Update-DR, the value loaded into that
shift-register cell latches into the preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is pre-set LOW to enable the output
when the device is powered up, and also when the TAP controller
is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-57825 Rev. *O Page 15 of 33
CY7C1425KV18
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CY7C1414KV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [11]
TEST-LOGIC
RESET
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
10
10
0
0
1
0
1
1
0
1
0
0
1
1
0
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
Note
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-57825 Rev. *O Page 16 of 33
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CY7C1414KV18
TAP Controller Block Diagram
0
012..29
3031
Boundary Scan Register
Identification Register
012..
.
.108
012
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI TDO
TCK
TMS
TAP Electrical Characteristics
Over the Operating Range
Parameter [12, 13, 14] Description Test Conditions Min Max Unit
VOH1 Output HIGH voltage IOH =2.0 mA 1.4 V
VOH2 Output HIGH voltage IOH =100 A1.6V
VOL1 Output LOW voltage IOL = 2.0 mA 0.4 V
VOL2 Output LOW voltage IOL = 100 A–0.2V
VIH Input HIGH voltage 0.65 × VDD VDD + 0.3 V
VIL Input LOW voltage –0.3 0.35 × VDD V
IXInput and output load current GND VI VDD –5 5 A
Notes
12. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 22.
13. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 1.5 V (Pulse width less than tCYC/2).
14. All voltage referenced to Ground.
Document Number: 001-57825 Rev. *O Page 17 of 33
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CY7C1414KV18
TAP AC Switching Characteristics
Over the Operating Range
Parameter [15, 16] Description Min Max Unit
tTCYC TCK clock cycle time 50 ns
tTF TCK clock frequency 20 MHz
tTH TCK clock HIGH 20 ns
tTL TCK clock LOW 20 ns
Setup Times
tTMSS TMS setup to TCK clock rise 5 ns
tTDIS TDI setup to TCK clock rise 5 ns
tCS Capture setup to TCK rise 5 ns
Hold Times
tTMSH TMS hold after TCK clock rise 5 ns
tTDIH TDI hold after clock rise 5 ns
tCH Capture hold after clock rise 5 ns
Output Times
tTDOV TCK clock LOW to TDO valid 10 ns
tTDOX TCK clock LOW to TDO invalid 0 ns
Notes
15. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
16. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 001-57825 Rev. *O Page 18 of 33
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TAP Timing and Test Conditions
Figure 3 shows the TAP timing and test conditions. [17]
Figure 3. TAP Timing and Test Conditions
t
TL
t
TH
(a)
TDO
C
L
= 20 pF
Z
0
= 50
GND
0.9V
50
1.8V
0V
ALL INPUT PULSES
0.9V
Test Clock
Test Mode Select
TCK
TMS
Test Data In
TDI
Test Data Out
t
TCYC
t
TMSH
t
TMSS
t
TDIS
t
TDIH
t
TDOV
t
TDOX
TDO
Note
17. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 001-57825 Rev. *O Page 19 of 33
CY7C1425KV18
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Identification Register Definitions
Instruction Field Value Description
CY7C1425KV18 CY7C1412KV18 CY7C1414KV18
Revision number (31:29) 000 000 000 Version number.
Cypress device ID (28:12) 11010011010001111 11010011010010111 11010011010100111 Defines the type of
SRAM.
Cypress JEDEC ID (11:1) 00000110100 00000110100 00000110100 Allows unique
identification of SRAM
vendor.
ID register presence (0) 1 1 1 Indicates the presence
of an ID register.
Scan Register Sizes
Register Name Bit Size
Instruction 3
Bypass 1
ID 32
Boundary scan 109
Instruction Codes
Instruction Code Description
EXTEST 000 Captures the input and output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a high Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-57825 Rev. *O Page 20 of 33
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Boundary Scan Order
Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID
0 6R 28 10G 56 6A 84 1J
16P299G575B852J
2 6N 30 11F 58 5A 86 3K
3 7P 31 11G 59 4A 87 3J
47N 329F 605C 882K
5 7R 33 10F 61 4B 89 1K
6 8R 34 11E 62 3A 90 2L
7 8P 35 10E 63 2A 91 3L
8 9R 36 10D 64 1A 92 1M
9 11P 37 9E 65 2B 93 1L
10 10P 38 10C 66 3B 94 3N
11 10N 39 11D 67 1C 95 3M
12 9P 40 9C 68 1B 96 1N
13 10M 41 9D 69 3D 97 2M
14 11N 42 11B 70 3C 98 3P
15 9M 43 11C 71 1D 99 2N
16 9N 44 9B 72 2C 100 2P
17 11L 45 10B 73 3E 101 1P
18 11M 46 11A 74 2D 102 3R
19 9L 47 10A 75 2E 103 4R
20 10L 48 9A 76 1E 104 4P
21 11K 49 8B 77 2F 105 5P
22 10K 50 7C 78 3F 106 5N
23 9J 51 6C 79 1G 107 5R
24 9K 52 8A 80 1F 108 Internal
25 10J 53 7A 81 3G
26 11J 54 7B 82 2G
27 11H 55 6B 83 1H