(R) DSP201 DSP202 DSP-Compatible Single/Dual DIGITAL-TO-ANALOG CONVERTERS FEATURES DESCRIPTION ZERO-CHIP INTERFACE TO DSP ICs: AD, AT&T, MOTOROLA, TI The DSP201 and DSP202 are high performance digital-to-analog converters designed for simplicity of use with modern digital signal processing ICs. Both are complete with all interface logic for use directly with DSP ICs, and provide analog output voltages updated at up to 500kHz. SINGLE CHANNEL: DSP201 DUAL CHANNEL: DSP202 Two Serial Inputs or Cascade from Single 32-Bit Word UPDATE RATE TO 500kHz DYNAMIC SPECIFICATIONS: Signal/(Noise + Distortion) = 90dB; THD = -92dB USER SELECTABLE 16-BIT OR 18-BIT DATA WORDS Convert Command The DSP201 offers a single complete voltage output channel, accepting either 16 bits or 18 bits of input data, and can be driven by 16-bit, 24-bit, or 32-bit serial ports. The DSP202 offers two complete voltage output channels, with either two separate input ports, or a mode to drive both output channels from a single 32-bit word. Both the DSP201 and DSP202 are packaged in standard, low-cost 28-pin plastic DIP packages. Each is offered in two performance grades to match application requirements. Latch Enable 18-Bit DAC Reset Select Sync Format Control Logic Select Word Length (16/18) Analog Voltage Output Channel A Reference Channel A Data In Sync Bit Clock 18-Bit DAC Analog Voltage Output Channel B Channel B Data In Channel B on DSP202 Only Cascade International Airport Industrial Park * Mailing Address: PO Box 11400 Tel: (520) 746-1111 * Twx: 910-952-1111 * Cable: BBRCORP * * Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd. * Tucson, AZ 85706 Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132 (c) PDS-1067C 1991 Burr-Brown Corporation Printed in U.S.A. July, 1993 SPECIFICATIONS ELECTRICAL TA = 0C to 70C, Output Update Frequency, fS, = 400kHz, VA+ = VD+ = +5V, VA- = VD- = -5V, unless otherwise specified. DSP201JP DSP202JP PARAMETER CONDITIONS MIN TYP RESOLUTION DSP201KP DSP202KP MAX MIN TYP 18 DYNAMIC RANGE ANALOG OUTPUT Voltage Range Impedance Current Slew Rate Settling Time to 0.006% for Full-Scale Step THROUGHPUT SPEED (1) Update Rate DSP202 in Cascade Mode AC ACCURACY (2, 3) Signal to (Noise + Distortion) Ratio Total Harmonic Distortion Channel Separation on DSP202 DC ACCURACY Integral Nonlinearity Error Differential Nonlinearity Error Bipolar Zero Error (5) Bipolar Zero Error Drift Bipolar Zero Mismatch (5) Gain Error Gain Error Drift Gain Error Mismatch Digital Feedthrough Power Supply Sensitivity 108 3 0.1 8 15 2.5 RL = 375 RL = 375 RL = 1.5k, CL = 100pF RL = 1.5k, CL = 100pF CASC = LOW on DSP202 CASC = HIGH 500 300 fOUT = 1kHz fOUT = 1kHz (-60dB) fOUT = 10kHz fOUT = 1kHz fOUT = 1kHz to 100kHz 82 86 30 86 -90 105 80 0.006 0.006 10 20 5 1 100 1 -105 -60 -60 DSP202 Channels ENABLE = HIGH -5.1 < VA-, VD- < -4.9 +4.9 <VA+, VD+ < +5.1 DIGITAL OUTPUTS VOL VOH POWER SUPPLIES Rated Voltage VA+ VA- VD+ VD- Current IA+ IA- ID+ ID- Power Consumption TEMPERATURE RANGE Specification Storage UNITS * Bits * dB * * * * V mA V/s s * * DSP202 Channels DIGITAL INPUTS Format Coding Logic Levels VIL VIH Data Transfer Clock Frequency Duty Cycle MAX 88 86 -85 kHz kHz 90 32 90 -92 * 0.004 0.004 * * * * * * * * * 3 3 -88 * * dB(4) dB dB dB dB % % mV ppm FSR/C mV % ppm/C % dB dB dB Serial; MSB first; 16/18-bit and Cascaded Binary Twos Complement IIL = 10A IIH = 10A 0 +2.4 40 IOL = 4mA IOH = 4mA 50 0 +2.4 +4.75 -5.25 +4.75 -5.25 +5 -5 +5 -5 18 17 13 25 365 0 -40 +0.8 +5 * * 12 60 * * +0.4 +5 * * +5.25 -4.75 +5.25 -4.75 * * * * * * * * * * * * * 450 +70 +125 * * * * * V V * * MHz % * * V V * * * * V V V V * mA mA mA mA mW * * oC oC NOTES: (1) The data transfer clock must be at least 24 times the update rate for the standard mode, and 40 times the update rate in the DSP202 Cascade Mode. (2) All dynamic specifications are based on 2048-point FFTs. (3) Data for the 1kHz test is bandlimited to 0 to 20kHz. Data for the 10kHz test is bandlimited to 0 to 40kHz. (4) All specifications in dB are referred to a full-scale output, 3Vp-p. (5) Adjustable to zero with external potentiometer. (R) DSP201/202 2 TYPICAL PERFORMANCE CURVES TA = +25C; Update Frequency, fS = 400kHz; VA+ = VD+ = +5V; VA- = VD- = 5V; SWL = HIGH; CASC = LOW; Output Bandwidth Limited to 20kHz; unless otherwise noted. SIGNAL-TO-(NOISE + DISTORTION) RATIO vs TEMPERATURE AND AMPLITUDE DYNAMIC PERFORMANCE vs TEMPERATURE -80 Signal-to-(Noise +Distortion) Ratio (dB) 80 85 -85 Signal-to-(Noise + Distortion) (SINAD) 90 -90 Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious Free Dynamic Range (SFDR) 100 -50 -25 -95 -100 0 25 50 75 80 f OUT = 1kHz, -20dB 70 60 50 40 f OUT = 1kHz, -60dB 30 20 10 0 -50 -25 0 50 75 Ambient Temperature (C) TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY SIGNAL-TO-(NOISE + DISTORTION) vs OUTPUT UPDATE RATE f OUT = 0dB Output not band-limited. -60 -70 -80 -90 -100 2 20 100 80 f OUT = 0dB Output not band-limited. 85 90 200 0.4 4 Output Frequency (kHz) 40 400 Output Update Rate (kHz) BIPOLAR ZERO ERROR AND GAIN ERROR vs TEMPERATURE INTEGRAL AND DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE (For Worst-Case Codes.) 0.020 10 0.3 Gain Error Bipolar Zero Error (mV) Absolute Value of Error (%) 25 Ambient Temperature (C) Signal-to-(Noise + Distortion) Ratio (dB) Total Harmonic Distortion (dB) f OUT = 1kHz, 0dB 90 100 -50 0.2 100 0.015 Differential Non-Linearity 0.010 0.005 5 0.2 Bipolar Zero Error 0 0.1 -5 0 Integral Non-Linearity 0.0 -10 -50 -25 0 25 50 75 100 -0.1 -50 -25 0 25 50 75 Gain Error (% of 6V Full Scale Range) 95 THD (dB) SINAD, SNR and SFDR (dB) f OUT = 1kHz, 3Vp-p 100 Ambient Temperature (C) Ambient Temperature (C) The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. (R) 3 DSP201/202 TYPICAL PERFORMANCE CURVES (CONT) TA = +25C; Update Frequency, fS = 400kHz; VA+ = VD+ = +5V; VA- = VD- = 5V; SWL = HIGH; CASC = LOW; Output Bandwidth Limited to 20kHz; unless otherwise noted. POWER SUPPLY REJECTION vs SUPPLY RIPPLE FREQUENCY OUTPUT VOLTAGE SETTLING TIME -35 R L = 1.5k C L = 100pF 0.01 Supply Ripple Rejection (dB) Accuracy (% of 6V Full Scale Range) 0.1 +Full Scale to -Full Scale Transition -Full Scale to +Full Scale Transition -45 -55 VA + = VD + -65 VA - = VD - -75 0.001 0 1 2 3 4 5 6 7 8 9 10 0.1 Settling Time (s) 1 10 100 Supply Ripple Frequency (kHz) INTERMODULATION DISTORTION vs TEMPERATURE Intermodulation Distortion (dB) -85 ELECTROSTATIC DISCHARGE SENSITIVITY f OUT 1 + fOUT 2 = 0dB f OUT 1 = 9.5kHz f OUT 2 = 11.5kHz -90 The DSP201 and DSP202 are ESD (electrostatic discharge) sensitive devices, and normal standard precautions should be taken. Permanent damage may occur on unconnected devices subject to high energy electrostatic fields. When not in use, devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed. -95 -100 -105 -50 -25 0 25 50 75 100 ABSOLUTE MAXIMUM RATINGS Ambient Temperature (C) VA+ to Analog Common ...................................................................... +7V VA- to Analog Common ...................................................................... -7V VD+ to Digital Common ..................................................................... +7V VD- to Digital Common ....................................................................... -7V Analog Common to Digital Common ................................................... 1V Control Inputs to Digital Common ............................... -0.5 to VD + 0.5V Maximum Junction Temperature ..................................................... 150oC Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) ............................................... +300oC Thermal Resistance, JA: Plastic DIP ............................................ 50oC/W PACKAGE INFORMATION MODEL PACKAGE DSP201JP DSP201KP DSP202JP DSP202KP 28-Pin 28-Pin 28-Pin 28-Pin Plastic Plastic Plastic Plastic DIP DIP DIP DIP PACKAGE DRAWING NUMBER(1) 215 215 215 215 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MODEL DSP201JP DSP201KP DSP202JP DSP202KP NUMBER OF CHANNELS SIGNAL-TO(NOISE + DIST.) RATIO, dB min 1 1 2 2 82 88 82 88 1-24 (R) DSP201/202 4 25-99 100+ DSP201 PIN CONFIGURATION VA - AGND 1 28 AGND 2 27 DGND 3 26 VA + 4 25 VPOT 24 MSB 23 VOS 22 AGND 5 VD + DSP201 PIN ASSIGNMENTS 6 DSP201 VD + 7 RESET 8 21 VOUT PIN # NAME 1 2 3 4 5 6 7 VA- AGND 8 RESET 9 SSF Select Sync Format In. Tie HIGH for use with Motorola and TI DSP ICs. Tie LOW for use with AT&T DSP ICs. 10 SWL Select Word Length In. If HIGH, DSP201 accepts first 16 bits of data. If LOW, DSP201 accepts first 18 bits of data. 11 SYNC Data Synchronization Output. Active HIGH when SSF is HIGH, active LOW when SSF is LOW. Data Transfer Clock Input. VD+ VD+ SSF 9 20 VD - SWL 10 19 DGND SYNC 11 18 DGND XCLK 12 17 ENABLE 12 XCLK SIN 13 16 DGND 13 SIN 14 15 CONV 14 15 DESCRIPTION -5V Analog Power. No Internal Connection. No Internal Connection. Analog Ground. No Internal Connection. +5V Digital Power. +5V Digital Power. Reset. If LOW, DAC output will be 0V after two convert commands, and will remain there as long as the Reset input is LOW. If HIGH, normal operation proceeds. Two convert commands are required after Reset goes from LOW to HIGH before the output will relate to the input word. Serial Data In. MSB first, Binary Two's Complement format. No Internal Connection. CONV Convert Command In. DAC is updated on falling edge, and initiates clocking new data in. 16 DGND Digital Ground. 17 ENABLE 18 19 20 21 22 23 24 25 26 27 28 DGND DGND VD- VOUT AGND VOS MSB VPOT VA+ DGND AGND Latch Enable In. If LOW, DAC output will be latched with new data word on falling edge of Convert Command. If HIGH, Convert Commands will be ignored. Digital Ground. Digital Ground. -5V Digital Power. Voltage Out. Analog Ground. VOS Adjust In. MSB Adjust In. Trim Reference Out for MSB adjustment. +5V Analog Power. Digital Ground. Analog Ground. (R) 5 DSP201/202 DSP202 PIN ASSIGNMENTS DSP202 PIN CONFIGURATION VA - 1 28 AGND MSBB 2 27 DGND VOSB 3 26 VA + AGNDB 4 25 VPOT VOUTB 5 24 MSBA VD + 6 23 VOSA 22 AGNDA DSP202 VD + 7 RESET 8 21 VOUTA SSF 9 20 VD - SWL 10 19 DGND SYNC 11 18 DGND XCLK 12 17 ENABLE SINA 13 16 CASC SINB 14 15 CONV (R) DSP201/202 6 PIN # NAME DESCRIPTION 1 2 3 4 5 6 7 VA- MSBB VOSB AGNDB VOUTB VD+ VD+ -5V Analog Power. Channel B MSB Adjust In. Channel B VOS Adjust In. Channel B Analog Ground. Channel B Voltage Out. +5V Digital Power. +5V Digital Power. 8 RESET Reset. If LOW, DAC output will be 0V after two Convert Commands, and will remain there as long as the Reset input is LOW. If HIGH, normal operation proceeds. Two Convert Commands are required after Reset goes from LOW to HIGH before the output will relate to the input word. 9 SSF Select Sync Format In. Tie HIGH for use with Motorola and TI DSP ICs. Tie LOW for use with AT&T DSP ICs. 10 SWL Select Word Length In. If HIGH, DSP202 accepts first 16 bits of data. If LOW, DSP202 accepts first 18 bits of data. Must be HIGH if CASC is HIGH. 11 SYNC Data Synchronization Output. Active HIGH when SSF is HIGH, active LOW when SSF is LOW. 12 XCLK Data Transfer Clock Input. 13 SINA Channel A Serial Data In. MSB first, Binary Two's Complement format. In Cascade Mode, connect to SINB and to DSP IC output. 14 SINB Channel B Serial Data In. MSB first, Binary Two's Complement format. In Cascade Mode, connect to SINA and to DSP IC output. 15 CONV Convert Command In. DAC is updated on falling edge, and initiates clocking new data in. 16 CASC Select Cascade Mode In. If HIGH, DSP202 accepts a 32-bit word, and uses the first 16 bits to update channel A, and the second 16 bits to update channel B. In Cascade Mode, SINA and SINB are connected together. If CASC is LOW, data is strobed into both channels on each clock cycle. 17 ENABLE Latch Enable In. If LOW, DAC output will be latched with new data word on falling edge of Convert Command. If HIGH, Convert Commands will be ignored. 18 19 20 21 22 23 24 25 26 27 28 DGND DGND VD- VOUTA AGNDA VOSA MSBA VPOT VA+ DGND AGND Digital Ground. Digital Ground. -5V Digital Power. Channel A Voltage Out. Channel A Analog Ground. Channel A VOS Adjust In. Channel A MSB Adjust In. Trim Reference Out for MSB adjustments. +5V Analog Power. Digital Ground. Analog Ground. THEORY OF OPERATION BASIC OPERATION The DSP201 and DSP202 are basic voltage output digitalto-analog converters with complete logic interface circuitry for ease of use with standard digital signal processing ICs. Data words are transmitted from the DSP IC on its serial port, leaving the DSP IC parallel ports free for digital communication. DATA FORMAT AND OUTPUT LEVELS The DSP201 and DSP202 are pipelined internally. When the user gives a convert command at time t, two actions are initiated. First, the data stored in the internal shift registers following the previous convert command (at t - 1) is used to update the output D/A converters immediately. Second, the DSP201 or DSP202 transmits a synchronization pulse to the DSP IC and starts clocking new data into the shift register using the system Bit Clock. This data is then used to update the D/As when the t + 1 convert command is received. As with all standard D/As, the output ranges from negative full scale (-3V) to 1 LSB below positive full scale (+3V - 1LSB). The bipolar output amplifiers are designed to drive 375 loads at full speed and accuracy. The DSP201 and DSP202 accept serial data, MSB first, in standard Binary Two's Complement format. The length of the data words can be selected as shown below, and the D/A output level generated by a specific input code is shown in Table I. UPDATING THE OUTPUT With ENABLE (pin 17) LOW, the falling edge of a Convert Command arriving on CONV (pin 15) will immediately update the D/A outputs with the data stored in the internal shift registers following the previous Convert Command. The Convert Command can be asynchronous to any other signals or clocks without reducing accuracy, although system accuracy is often enhanced by synchronizing digital signals. Both the DSP201 and DSP202 are 18-bit D/As internally. On-chip logic can be programmed to use 18-bits of data to update the D/A outputs, or can be programmed to update the D/A based on 16-bit data words. Additionally, the logic in the DSP202 can accept a 32-bit data word (the Cascade Mode), and update both D/A channels simultaneously with 16 bits each. All of these modes can be hard-wired or logiccontrolled externally, so that no extra overhead on the part of the DSP IC is required. For a full-scale change in the input code, the output will typically settle to within 0.006% of its final level within 2.5s. The slew rate of the output amplifier is typically 15V/ s, for a full power bandwidth close to 800kHz. All of the specifications and typical performance curves are achieved with a full 400kHz update rate, unless otherwise specified. The DSP201 and DSP202 are guaranteed operational to a full 500kHz update rate, which exceeds the maximum Bit Clock rate for most standard DSP ICs. In the 16-bit modes, the DSP201 and DSP202 will append zeros to the 16-bits transferred to each of the internal D/As, which are full 18-bit converters. The 18-bit word-length mode can be used with DSP ICs programmed for either 24bit or 32-bit output words, in which case the DSP201 or DSP202 will clock in the first 18-bits of data after the synchronization pulse, and ignore additional information on the serial line. When programmed to accept 16-bit words, the DSP201 and DSP202 can be used with DSP ICs programmed to output 16-, 24-, or 32-bit words, and will ignore additional information after the first 16 bits on the serial line. DATA TRANSFER Data is transmitted serially to the DSP201 or DSP202, and is clocked into the internal shift registers on the rising edge of the external Data Transfer Clock or Bit Clock (XCLK input on pin 12.) This clock can be as fast as 12MHz. The Data Transfer Clock can tolerate duty cycles from 40% to 60%. The DSP201 and DSP202 are complete voltage output D/A converters, with on-chip references and output amplifiers to drive 3V into 375 loads. State-of-the-art bipolar technologies are used in the D/A section to maximize the output update rate, to maximize dynamic performance, and to eliminate glitch problems. Advanced plastic packaging methods makes this performance attainable economically. As indicated in the timing diagrams in Figure 1, either 16or 18-bits of data will be clocked into the DSP201 or DSP202, or 32-bits will be clocked into the DSP202 in the INPUT CODE OUTPUT VOLTAGE BINARY 16-BIT MODE AND DSP202 CASCADE MODE HEX 18-BIT MODE 16-BIT MODE AND DSP202 CASCADE MODE 18-BIT MODE 0111...1111 0000...0000 1111...1111 1000...0000 7FFF 0000 FFFF 8000 1FFFF 00000 3FFFF 20000 +2.999908V 0V -92V -3.000000V 2.999977V 0V -23V -3.000000V 91.6V 22.9V Theoretical LSB Size TABLE I. Output Voltage vs Input Code. (R) 7 DSP201/202 FIGURE 1. DSP201 and DSP202 Timing. (R) DSP201/202 8 t9 t8 (2) SINA/B CONV XCLK (CASC = HIGH) t2 t1 t10 Bit 16 (LSB) Bit 16 50 50 50 20 Bit 17 (3) 0 2 t1 15 15 ns ns t1 t1 ns ns ns ns ns ns ns ns UNITS Bit 16 (LSB) Bit 18 (3) (LSB) Channel B Data MAX Bit 1 (MSB) 83 50 24 40 t1 +40 Channel A Data Bit 2 t4 Bit 2 MIN t11 t11 XCLK period; Duty Cycle 50% 10% Convert Command LOW Time Convert Period (CASC = LOW on DSP202) Convert Period (CASC = HIGH on DSP202 SYNC Active Delay after Convert Falling Edge) SYNC LOW to HIGH Delay from XCLK Rising; CL = 50pF SYNC HIGH to LOW Delay from XCLK Rising; CL = 50pF ENABLE Setup before Convert Falling Edge(1) ENABLE Hold after Convert Falling Edge(1) RESET Setup before Convert Falling Edge SINA/B Data Setup before XCLK Rising SINA/B Data Hold after XCLK Rising Bit 1 (MSB) t10 Bit 1 (MSB) DESCRIPTION t6 t7 t3 NOTES: (1) Normally tied LOW so that previously transmitted data is used to update DAC output on falling edge of CONV. ENABLE HIGH prevents the DAC from being updated. (2) RESET must be held LOW for two complete Convert Command cycles, and ENABLE must be LOW. (3) Optional data bits. Clocked into DAC register only if SWL is LOW. t1 t2 t3 t4 t5 t6 t7 t8 t9 t8 t10 t11 INTERVAL DSP202 Cascade Mode (CASC = HIGH) (CASC = LOW on DSP202) t8 (1) SINA/B RESET ENABLE t7 SYNC (SSF = LOW) t5 t6 t2 t1 SYNC (SSF = HIGH) CONV XCLK t2 t2 DSP202 CASCADE MODE If CASC on the DSP202 (pin 16) is HIGH, the Cascade Mode is implemented. In this mode, SINA (pin 13) and SINB (pin 14) are strapped together and connected to the serial output port of an appropriate DSP IC or other data word source. A Convert Command initiates the transfer of a 32-bit word to the DSP202. Cascade Mode, but internal digital overhead requires additional Data Transfer Clock cycles before a new Convert Command can be sent. The minimum time between Convert Commands is 24 times the Data Transfer Clock period for either the DSP201 or the DSP202 in standard modes, and 40 times the Data Transfer clock period for the DSP202 in the Cascade Mode. There is no maximum time between Convert Commands. In the Cascade Mode, care must be taken to make sure SWL (pin 10) is HIGH. These additional clock cycles are used to set up the internal shift registers and logic, and are included in the specifications for maximum update rate. This means a 12MHz Bit Clock can achieve the maximum specified update rate of 500kHz. LATCH ENABLE If ENABLE (pin 17) is LOW, the D/A outputs will be latched with new data on the falling edge of the Convert Command. Taking ENABLE HIGH causes the DSP201 or DSP202 to ignore Convert Commands. With ENABLE HIGH when a Convert Command arrives at time t, data latched in the internal shift register after the Convert Command at t - 1 is not latched to the D/As, but a new synchronization pulse is still generated and the data in the shift register is overwritten. This feature allows multiple DSP201s or DSP202s to share a single DSP IC and still be independently updated. DATA SYNCHRONIZATION The DSP201 and DSP202 have internal logic to generate a synchronization pulse (SYNC on pin 11) to signal the host processor to transmit data. The synchronization pulse is sent when a Convert Command is received, and the SYNC output changes on the rising edge of XCLK. Timing is shown in Figure 1. The synchronization pulse can be programmed to be either active High or active Low, depending on the logic level input on SSF (Select Sync Format on pin 9.) If SSF is LOW, SYNC will be normally HIGH, and will transmit a LOW pulse after a Convert Command is received. If SSF is HIGH, SYNC will be normally LOW, and will transmit a HIGH pulse after a Convert Command is received. The SYNC pulse will be as wide as one clock cycle on the Data Transfer Clock input on XCLK (pin 12.) RESET Taking RESET (pin 8) LOW will cause the D/As to output 0V after two Convert Commands are received. The two Convert Commands clear out the internal shift registers, and data input on the serial input lines will be ignored while RESET is low. This facilitates designing an analog output system that goes into a known, benign state either at powerup, after fault conditions or during a calibration cycle. ENABLE (pin 17) must be LOW when resetting the DSP201 or DSP202 outputs to 0V. SELECTING WORD LENGTH If the Select Word Length input (SWL, pin 10) is HIGH, the DSP201 or DSP202 will accept 16 bits of data after a Convert Command, with the timing shown in Figure 1. After these 16 bits, additional data on SIN (DSP201 pin 13) or SINA and SINB (DSP202 pins 13 and 14) will be ignored. Transparent to the user, the internal shift register will append two zeroes to the 16-bit data words before updating the D/As on the next Convert Command. After RESET is taken HIGH, two Convert Commands are required before the output will relate to the input data. Also, ENABLE must be LOW for the data to be latched to the D/As. The first Convert Command again latches the outputs at 0V, and the second Convert Command drives the output to the level determined by the data clocked in after the first Convert Command. If SWL is LOW, the DSP201 or DSP202 will clock 18 bits of data into the internal shift register after a Convert Command, with the timing shown in Figure 1. Subsequent data on SIN (DSP201 pin 13) or SINA and SINB (DSP202 pins 13 and 14) will be ignored. A RESET command after power up is not required for proper operation of the DSP201 or DSP202. LAYOUT CONSIDERATIONS Because of the high resolution, linearity and speed of the DSP201 and DSP202, system design problems such as ground path resistance, contact resistance and power supply quality become very important. In the 16-bit mode, an increment of 1 LSB will change the D/A output by approximately 91.6V (the 6V full scale range divided by 216), while an LSB in the 18-bit mode will change the output approximately 22.9V (6V/218). GROUNDS To achieve the maximum performance from the DSP201 or DSP202, care should be taken to minimize the effect of current flows in the system grounds that may corrupt the output voltages generated by the D/As. Pin 22 on the DSP201 and pins 4 and 22 on the DSP202 are the most The DSP201 and DSP202 analog performance is tested in production using the 16-bit mode (with SWL HIGH), and the typical performance curves were generated using the 16bit mode. Verification is made during final test that the 18bit mode functions, but the extra resolution of these last two bits is not used when testing the analog performance. (R) 9 DSP201/202 critical internal grounds, and care should be taken especially at these points to make them as close as possible to the same potential as the system analog ground. The design of the DSP201 and DSP202 insures that these pins will have minimal current flowing through them. a current switching D/A architecture, and the current from this is internally amplified to produce a 3V output range. Negative full scale output thus results from having all of the internal current switches turned off. Offset on the DSP201 and DSP202 should not be confused with the delta from 0V with an input code of 0000...0000 (0000 hex for 16-bit Modes, 00000 hex for 18-bit Modes). This is often described as bipolar zero error, and includes the effects of both offset and gain error. Internally, power currents are directed to the digital grounds (pins 18, 19, and 27) for internal digital currents, which are primarily switching currents, and to the analog grounds (pin 28, plus pin 4 on the DSP201) for analog currents, which are primarily from the internal current switches and the output amplifier. Pin 16 on the DSP201 is used internally as a logic level, and injects essentially no current into the ground. To trim the offsets, first latch the D/As with 1000...0000 (8000 hex or 20000 hex). Then adjust the offset adjustment pots to produce an output of -3.000000V. Wherever possible, it is strongly recommended that separate analog and digital ground planes be used. With an LSB level of 92V in 16-bit modes, and one quarter of that in 18-bit modes, the currents switched in a typical DSP system (processor, memory, etc.) can easily corrupt the output accuracy of the D/A's unless great care is taken to analyze and design for current flows. ADJUSTING THE MSB WEIGHT The MSB adjustment circuitry shown in Figure 2 for the DSP201 and in Figure 4 for the DSP202 basically change the weight of the MSB by adding to or subtracting from the current controlled by the internal MSB switch. Depending on the application, the MSB adjustments can be made in one of three different ways to optimize the system performance using the DSP201 or DSP202. For dynamic performance, the MSB can be adjusted to minimize distortion of either a full-scale or low level sine-wave output. For applications stressing differential linearity, the 0000...0000 (0000 hex or 00000 hex) to 1000...0000 (FFFF hex or 3FFFF hex) transition can be trimmed to change the output of the D/As precisely 1 LSB (92V in the 16-bit Mode or 23V in the 18-bit Mode.) POWER SUPPLY DECOUPLING All of the supplies should be decoupled to the appropriate grounds using tantalum capacitors in parallel with ceramic capacitors, as shown in Figures 2 and 3. For optimum performance of any high resolution D/A, all of the supplies need to be as clean as possible. If separate digital and analog supplies are available in a system, care should be taken to insure that the difference between the analog and the digital supplies is not more than 0.5V for more than a few hundred milliseconds, as may occur at power-on. To adjust for minimum distortion of full-scale sinewaves, strobe the inputs to the DSP201 or DSP202 with codes representing ideal full scale sine waves, then trim the MSB adjustment circuit to minimize distortion, as measured by either a distortion analyzer or by digitizing the output with an appropriate A/D and running FFT analyses. Separate -5V analog and digital supplies are not needed. These pins are kept separate internally to minimize coupling. Drive pin 20 from the -5V analog supply, and make sure that the decoupling shown in Figure 2 or 3 are placed as close as possible to the D/As. In many audio applications, it is more appropriate to adjust for minimum distortion with low level sinewave outputs. This minimizes zero-crossover error, which can be a concern in high-end audio systems. To do this, strobe the inputs to the DSP201 or DSP202 with codes representing ideal low-level sine waves (-60dB from full scale works well), and then trim the MSB adjustment circuit to minimize distortion, again using a distortion analyzer or FFT analyses to check the results of the trims. CALIBRATION AND ADJUSTMENT OPTIONAL EXTERNAL OFFSET AND MSB TRIMS All of the specifications for the DSP201 and DSP202, plus the typical performance curves, are based on the performance of these D/As without external trims. In most applications, external trims are not required. If external trims are not used, pins 23, 24, and 25 on the DSP201 should be left open, as should pins 2, 3, 23, 24 and 25 on the DSP202. These pins should not be decoupled with capacitors or tied to any specific potential, or the noise on the D/A outputs may increase. The MSB adjustment circuits can also be used to trim the D/A outputs directly for the transition from 0000...0000 (0000 hex or 00000 hex) to 1111...1111 (FFFF hex or 3FFFF hex), eliminating differential linearity error at the major carry. Ideally, this transition of the digital input code should cause the D/A outputs to change 92V in the 16-bit Mode or 23V in the 18-bit Mode. A simple way to make this adjustment is to continually load alternately the codes 1111...1111 (FFFF hex or 3FFFF hex) and 0000...0000 (0000 hex or 00000 hex) into the DSP201 or DSP202. An amplifier with sufficient gain can then drive an oscilloscope input, and the transition output step can be adjusted. ADJUSTING OFFSET Where required by specific applications, offsets can be trimmed using the circuits in Figure 2 (DSP201) or Figure 3 (DSP202.) As with all standard D/As, offset on the DSP201 and DSP202 means the difference of the output from the ideal negative full scale value. The DSP201 and DSP202 use (R) DSP201/202 10 GAIN ERROR Gain error on the DSP201 or DSP202 cannot be directly adjusted. If required in a specific application, gain can be trimmed out at the system level by adjusting the gain used in an output amplifier stage, such as would be used in any active output filter. In this case, the bipolar zero error should be adjusted first as discussed above. Then, the gain on the output amplifier should be adjusted to minimize the deviation from ideal for -Full Scale (1000...000; 8000 hex or 20000 hex) and +Full Scale (0111...1111; 7FFF hex or 1FFFF hex.) An alternative for calibrating on a bench is to tie SIN (DSP201 pin 13) or SINA and SINB (DSP202 pins 13 and 14) HIGH, and provide a Bit Clock and periodic Convert Commands. This loads 1111...1111 (FFFFHEX or 3FFFFHEX), driving the output to 1LSB below 0V. Then periodically bring RESET (pin 8) LOW for at least two Convert Commands, which is the equivalent of loading all 0s, so the output is 0V. Now the output can be adjusted for an ideal transition step. ADJUSTING BIPOLAR ZERO ERROR If it is important in a specific application to adjust bipolar zero error, the user should first adjust the MSB trim circuits, and then use the offset adjust circuits to adjust the outputs to 0V with input codes of all 0s (0000...0000; 0000 hex or 00000 hex.) In this case, it is not possible to also trim offset at -Full Scale, as described above. DSP201 1 -5V + 2.2F VA - AGND 28 0.01F 0.01F 2 +5V 27 3 4 + 2.2F AGNDB VA + 26 VPOT 25 MSB Adjust 100k -5V 100k 5 MSB 24 Offset Adjust 100k +5V -5V 3.3k +5V + 2.2F 6 VD + VOS 23 7 VD + AGND 22 0.01F 8 9 21 VD - 20 -5V 0.01F 10 DGND 19 11 DGND 18 12 17 13 16 14 15 + 2.2F FIGURE 2. DSP201 Power Supply Connections and Optional Adjust Circuits. (R) 11 DSP201/202 DSP202 Channel B Offset Adjust 100k -5V -5V 1 + +5V 3.3k 2.2F AGND VA - 28 0.01F 2 27 3 VOSB 4 AGNDB VA + +5V 26 25 5 + 0.01F 2.2F Channel A Offset Adjust 100k -5V 24 +5V 3.3k +5V + 2.2F 6 VD + VOSA 23 7 VD + AGNDA 22 0.01F 8 21 VD - 9 -5V 20 10 DGND 19 11 DGND 18 12 17 13 16 14 15 0.01F + 2.2F FIGURE 3. DSP202 Power Supply Connections and Optional Offset Voltage Adjustment. DSP202 MSB Adjust Channel B 100k 1 -5V 28 100k 2 27 MSBB 3 MSB Adjust Channel A 100k 26 4 VPOT -5V 25 100k 5 MSBA 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 FIGURE 4. DSP202 Optional MSB Adjust Circuit. (R) DSP201/202 24 12 APPLICATIONS COMPLETE ANALOG INPUT/OUTPUT SYSTEM The DSP201 or DSP202 can be paired with the Burr-Brown DSP101 or DSP102 analog-to-digital converter to provide both analog input and analog output for a complete digital signal processing system. The DSP101 and DSP102 are respectively single and dual channel 200kHz sampling A/Ds with easy to use interfacing logic that complement the DSP201 and DSP202. Figure 6 shows a single channel analog input and output system based on a DSP201 and a DSP101, and the minimal connections required to interface to a DSP IC. A pair of channels can be implemented using a single DSP202 and a single DSP102, either with two separate DSP ICs, with a single DSP IC with dual serial input and output channels, or a single DSP IC capable of 32bit words in the Cascade Mode. USING PARALLEL PORTS WITH THE DSP201 OR DSP202 Figure 5 shows a circuit for converting parallel outputs into the serial data stream required by the DSP201, and meets the requirements for timing signals. Doubling this circuit allows the DSP202 to be driven from a 32-bit parallel port. In most applications, this circuit can be easily incorporated into gate arrays or other programmed logic circuits already used in the system, since the extra gate count is not high. DEGLITCHING Particularly in high resolution D/A converters, changing input codes may cause glitching on the output that excessively corrupts the dynamic purity of an output signal. The DSP201 and DSP202 are designed to minimize output glitching, and all of the performance specifications and typical performance curves are based on tests with no extra deglitching circuitry. In particular, the guaranteed Signal-to(Noise + Distortion) performance would be impossible to attain with any significant glitching. For maximum flexibility in system design, the DSP201 or DSP202 D/As can be updated at a different rate than the conversion rate used on the DSP101 or DSP102 A/Ds, and either or both of these rates can be asynchronous to the clocks used with the DSP IC. 74LS374 D0 D1 D2 D3 D4 D5 D6 D7 MSB 18 17 14 13 8 7 4 3 8D 7D 6D 5D 4D 3D 2D 1D 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q CK OE 11 74LS166 19 16 15 12 9 6 5 2 14 12 11 10 5 4 3 2 15 1 H G F E D C B A S/L SI C 1 7 DSP201 QH CI 6 74LS374 D8 D9 D10 D11 D12 D13 D14 D15 LSB 8D 7D 6D 5D 4D 3D 2D 1D 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q CK OE 11 WR PORTAO 4 74LS32 6 SYNC SIN XCLK VOUT CONV SSF SWL 21 3V Analog Output +5V CL 9 +5V 18 17 14 13 8 7 4 3 11 13 12 15 9 10 13 TTL Bit Clock 74LS166 19 16 15 12 9 6 5 2 14 12 11 10 5 4 3 2 15 1 H G F E D C B A S/L SI C 1 7 QH CI 6 13 CL 9 +5V 74LS04 1 2 5 FIGURE 5. Driving the DSP201 from a 16-Bit Parallel Port. (R) 13 DSP201/202 TTL Bit Clock Digital Signal Processor IC DSP101* XCLK 2 VIN SOUT 16 CLKR 20 DSP201 12 XCLK DATA IN XCLK 13 DATA OUT SIN VOUT 21 3V Analog Output 2.75V Analog Input SYNC SSF 15 12 SYNC 11 SYNC *SSF *SSF **SWL CONV 21 DSP PROCESSOR DSP32C, DSP16 DSP56001 DSP56001 TMS320C25/C30 ADSP2101/2105 SERIAL I/O WORD Active Low Active High Active High Active High Active High SSF 10 SWL 15 Conversion Rate Generator SYNC FORMAT SYNC 9 16 24 16 16 16 Bits Bits Bits Bits Bits CONV *SSF **SWL LOW HIGH HIGH HIGH HIGH HIGH LOW HIGH HIGH HIGH *See Burr-Brown DSP101/102 product data sheet for full description of this ADC. FIGURE 6. Analog Input and Analog Output System. DSP #1 TTL Bit Clock DSP202 TXCLK SYNC DATA DSP #2 Sync Format Input TXCLK Data Length SYNC DATA +5V 12 XCLK 11 SYNC 13 SINA 14 SINB 15 CONV 16 CASC 9 SSF 10 SWL 17 ENABLE 8 VOUTA VOUTB DSP32C DSP16 DSP56001 in 16-bit Mode DSP56001 in 24-bit Mode TMS320C25 FIGURE 7. DSP202 with Dual DSP ICs. (R) DSP201/202 14 5 3V Analog Output from DSP #1 3V Analog Output from DSP #2 RESET DIGITAL SIGNAL PROCESSOR Conversion Rate Generator 21 SYNC FORMAT Logic 0 Logic 1 Logic 1 Logic 1 DATA LENGTH 16-Bit, 16-Bit, 16-Bit, 24-Bit, 16-Bit, Logic Logic Logic Logic Logic 1 1 1 0 1 USING DSP201 AND DSP202 WITH TEXAS INSTRUMENTS DSP ICS Figures 6 thru 12 show various ways to use the DSP201 and DSP202 with DSP ICs from the Texas Instruments TMS320Cxx series. For simplicity, all of these circuits are based on using the TMS320Cxx in the mode where SSF (Select Synch Format, pin 9) is tied HIGH, so that there is an active High synchronization pulse generated by the DSP201 or DSP202 after receiving a Convert Command. The synchronization pulse can be changed to active Low simply by making SSF LOW, where appropriate, without changing basic operation of the D/As. The timing for either synchronization mode is shown in Figure 1. throughput rate on the system. Figure 11 makes use of the 32-bit word length mode in the TMS320C30 and the Cascade Mode on both the DSP202 and the DSP102 to provide two full analog I/O channels over a single serial I/O port on the TMS320C30. Thus, up to four complete, separate analog I/O channels could be operated using a single TMS320C30, by making use of the second serial port. Figure 12 shows how to use a TMS320C25 to update the analog output of the DSP201. USING DSP201 AND DSP202 WITH MOTOROLA DSP ICS Figure 13 shows how to use the DSP201 with a Motorola DSP56001. Using the DSP202 requires using two DSP56001s, as indicated in Figure 7. In all cases, the DSP201 and DSP202 expect to receive the data with the MSB first, and the TMS320Cxx needs to be programmed for this. The DSP56001 needs to be programmed for transmission of the MSB bit first with SYNC in the Bit Mode. If the DSP56001 is programmed for 16-bit data words, SWL (pin 10) on the DSP201 or DSP202 needs to be tied HIGH to select the 16-bit Mode. In the DSP56001 24-bit mode, the DSP201 or DSP202 can be programmed to accept data lengths of 16-bits (with SWL HIGH) or 18-bits (with SWL LOW), and will ignore the trailing bits on the serial line. Figure 6 shows a circuit for using the TMS320C25 to generate a complete analog input and analog output system using the DSP201 plus the Burr-Brown DSP101 A/D. Figure 7 shows how to use two TMS320C25 chips to drive the two channels of the DSP202. The TMS320C30 has dual serial I/O ports, which can be used to drive the dual inputs on the DSP202, as shown in Figure 8. This circuit can maximize the update rate for the channels. Since the TMS320C30 can also output 32-bit words, both channels of the DSP202 can be updated from a single serial output port on the TMS320C30, using the cascade mode as shown in Figure 9. For use with the Motorola DSP56001, SSF (pin 9) on the DSP201 or DSP202 needs to be tied HIGH. This will cause the DSP201 or DSP202 to transmit an appropriate active High synchronization pulse on SYNC (pin 11) after a Convert Command is received by the DSP201 or DSP202. Timing is shown in Figure 1. Figures 10 and 11 show complete two-channel analog input and analog output systems consisting of three basic chips, the TMS320C30 plus a DSP202 dual D/A and a BurrBrown DSP102 dual A/D. Figure 10 makes use of the dual serial I/O ports on the TMS320C30, and is shown with the DSP202 in the 16-bit Mode, which maximizes the possible Even though the DSP201 or DSP202 require a minimum of 24 Bit Clock pulses between convert commands, the maximum update rate for the D/As using a 5MHz Bit Clock will still be over 200kHz (5MHz / 24 = 208.3kHz.) TTL Bit Clock TMS320C30 DSP202 12 CLKX - 0 CLKX - 1 DX - 0 13 14 DX - 1 XCLK SINA SINB VOUTA VOUTB 11 FSX - 0 21 5 3V Analog Output Channel A 3V Analog Output Channel B SYNC FSX - 1 +5V 9 +5V 10 16 Conversion Rate Generator 15 SSF SWL CASC CONV NOTE: (1) Serial output is 16-bit MSB first. FIGURE 8. Using DSP202 with TMS320C30's Dual SIO. (R) 15 DSP201/202 TTL Bit Clock TMS320C30 DSP202 12 CLKX XCLK 11 FSX SYNC 13 DX SINA 14 SINB 15 Conversion Rate Generator +5V 16 +5V 9 +5V 10 VOUTB 21 3V Analog Output Channel A 5 3V Analog Output Channel B CONV CASC SSF SWL 17 +5V VOUTA ENABLE 8 RESET NOTE: Program TMS320C30 for 32-bit mode. FIGURE 9. Using DSP202 with TMS320C30 in Cascade Mode. TTL Bit Clock DSP102* XCLK 2.75V Analog Input Channel A 2 VINA SOUTA SOUTB SYNC 2.75V Analog Input Channel B 25 VINB SSF CASC CONV DSP202 TMS320C30 16 CLKR-0 CLKR-1 DR-0 20 17 DR-1 15 FSR-0 FSR-1 12 12 CLKR-0 CLKR-1 DX-0 13 14 DX-1 11 FSX-0 FSX-1 +5V 22 21 +5V +5V 9 10 16 15 Conversion Rate Generator XCLK SINA VOUTA 21 3V Analog Output Channel A SINB SYNC VOUTB 5 3V Analog Output Channel B SSF SWL CASC CONV NOTES: (1) Sample rate on DSP102 and DSP202 may differ. (2) Analog Devices ADSP2101 may be used. SPORT1 and SPORT2 are used for serial MSB first communication. *See Burr-Brown DSP101/102 product data sheet for full description of this ADC. FIGURE 10. Two-Channel Analog Input and Output System with TMS320C30. (R) DSP201/202 16 TTL Bit Clock DSP102* 16 XCLK 2.75V Analog Input Channel A 2 VINA SOUTA 17 25 VINB 12 SSF 22 CASC 13 DX-0 DR-0 14 NC 15 SYNC 12 CLKX-0 CLKR-0 20 SOUTB 2.75V Analog Input Channel B DSP202 TMS320C30 11 FSX-0 FSR-0 SINA VOUTA 21 3V Analog Output Channel A 5 3V Analog Output Channel B SINB SYNC VOUTB +5V 9 +5V +5V 21 CONV XCLK 10 +5V 16 +5V 15 Conversion Rate Generator SSF SWL CASC CONV NOTES: (1) Program TMS320C30 for 32-bit mode. (2) Sample rate on DSP102 and DSP202 may differ. (3) DSP32C may also be used in this mode, with SSF pins tied LOW. *See Burr-Brown DSP101/DSP102 product data sheet for full description of this ADC. FIGURE 11. Two-Channel Analog Input and Output System with TMS320C30 in Cascade Mode. TTL Bit Clock TMS320C25 DSP201 SSI Port 12 XCLK CLKX 11 SYNC FSX 13 SIN DX 15 +5V SWL ENABLE 8 +5V 3V Analog Output SSF 10 17 Conversion Rate Generator 21 CONV 9 +5V VOUT RESET NOTE: FSX is programmed for external mode. FIGURE 12. Using DSP201 with TMS320C25. TTL Bit Clock DSP56001 SSI Port SSK SS2 DSP201 TXC 12 FSR (Bit) 11 13 STD 15 +5V (2) 9 10 17 Conversion Rate Generator +5V 8 XCLK SYNC SIN VOUT 21 3V Analog Output CONV SSF SWL ENABLE RESET NOTES: (1) DSP56001 programmed for MSB bit first. (2) For 16-bit data connect SWL to Logic 1; For 24-bit data connect SWL to Logic 0. FIGURE 13. Using DSP201 with DSP56001. (R) 17 DSP201/202 ADSP2105 TTL Bit Clock DSP201 12 SCLK1 13 DT1(1) XCLK SIN VOUT 11 TFS1 +5V +5V Conversion Rate Generator 9 10 15 21 3V Analog Output SYNC SSF SWL CONV NOTE: (1) 16-bit MSB first data. FIGURE 14. Using DSP201 with ADSP-2105. USING DSP201 AND DSP202 WITH ADI DSP ICS D/As will output an appropriate active Low synchronization pulse after a Convert Command is received. When using the DSP201 or DSP202 with the ADSP2101 or ADSP2105, the processors need to be programmed to transmit the data with the MSB first. Figures 15 and 17 show the DSP32C and DSP16 respectively used with the DSP201 in the 16-bit Mode to generate a single analog output channel. With a 12MHz Bit Clock and the 24 Bit Clock cycles required by the DSP201 and DSP202 between Convert Commands, the output of Figure 15 can be updated at a full 500kHz (12MHz/24 = 500kHz.) Figure 14 shows the connections required to generate an analog output channel using an ADSP2105 with the DSP201. The same basic circuit can also be used to connect a DSP201 to the ADSP2101. Figure 16 shows how to drive two analog output channels from a single 32-bit serial port on the DSP32C, using the Cascade Mode on the DSP202. With a 12MHz Bit Clock and the 40 Bit Clock cycles required between Convert Commands by the DSP for internal logic overhead, this circuit can update two separate analog outputs at 300kHz each from a single serial port (12MHz/40 = 300kHz.) Figure 6 indicates how to build a complete analog input and analog output system using either the ADSP2101 or ADSP2105 with a DSP201 and a Burr-Brown DSP101 A/D. The two serial ports on the ADSP2101 can also be used with the DSP202 to make two complete analog output channels as noted in footnote 2 of Figure 10. Figure 6 indicates how to build a complete analog input and analog output system using a DSP32C or DSP16 with a DSP201 and a Burr-Brown DSP101 A/D. USING DSP201 AND DSP202 WITH AT&T DSP ICS Figures 15, 16 and 17 show how to use the DSP201 and DSP202 with the DSP16 and DSP32C in different modes. The DSP IC needs to be programmed to transmit data with the MSB first, and the DSP201 or DSP202 needs to have SSF (Select Sync Format on pin 9) tied LOW so that the Figure 7 shows a two channel analog output system using a single DSP202 with two DSP32Cs or two DSP16s. (R) DSP201/202 18 TTL Bit Clock DSP32C DSP201 SIO 12 OCK XCLK 11 OLD SYNC 13 DO SIN 15 OEN SWL 17 ENABLE 8 +5V 3V Analog Output SSF 10 Conversion Rate Generator 21 CONV 9 +5V VOUT RESET NOTES: DSP32C programmed for MSB bit first. Data length 16 bit. External OCK, ILD. FIGURE 15. Using DSP201 with DSP32C with 16-Bit Data Words. TTL Bit Clock DSP202 DSP32C SIO 12 OCK 11 OLD 13 DO 14 OEN 15 +5V 16 9 Conversion Rate Generator +5V 10 17 8 +5V XCLK SYNC SINA VOUTA SINB VOUTB 21 5 3V Analog Output Channel A 3V Analog Output Channel B CONV CASC SSF SWL ENABLE RESET NOTES: (1) DSP32C programmed for MSB bit first. (2) Data length 32 bits. External OCK, ILD. FIGURE 16. Using DSP202 with DSP32C in Cascade Mode. TTL Bit Clock DSP16 DSP201 SIO 12 OCK 11 OLD 13 DO XCLK SYNC SIN VOUT 21 3V Analog Output OEN 9 +5V Conversion Rate Generator 10 15 SSF SWL CONV NOTE: (1) DSP16 programmed for MSB bit first 16-bit data. FIGURE 17. Using DSP201 with DSP16. (R) 19 DSP201/202