ASM2I9940L Low Voltage 1:18 Clock Distribution Chip Functional Description The ASM2I9940L is a 1:18 low Voltage Clock distribution chip with 2.5 V or 3.3 V LVCMOS output capabilities. The device features the capability to select either a differential LVPECL or LVCMOS compatible input. The 18 outputs are 2.5 V or 3.3 V LVCMOS compatible and feature the drive strength to drive 50 W series or parallel terminated transmission lines. With output-to-output skews of 150 pS, the ASM2I9940L is ideal as a clock distribution chip for the most demanding of Synchronous systems. The 2.5 V outputs also make the device ideal for supplying clocks for a high performance microprocessor based design. With low output impedance (20 W), in both the HIGH and LOW logic states, the output buffers of the ASM2I9940L are ideal for driving series terminated transmission lines. With a 20 W output impedance the ASM2I9940L has the capability of driving two series terminated lines from each output. This gives the device an effective fanout of 1:36. The differential LVPECL inputs of the ASM2I9940L allow the device to interface directly with a LVPECL fanout buffer to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock input. All inputs of the ASM2I9940L have internal pullup/pulldown resistor, so they can be left open if unused. The ASM2I9940L is a single or dual supply device. The device power supply offers a high degree of flexibility. The device can operate with a 3.3 V core and 3.3 V output, a 3.3 V core and 2.5 V outputs as well as a 2.5 V core and 2.5 V outputs. The 32-lead LQFP Package was chosen to optimize performance, board space and cost of the device. The 32-lead LQFP Package has a 7 x 7 mm2 body size with conservative 0.8 mm pin spacing. http://onsemi.com MARKING DIAGRAM LQFP-32 CASE 873A 2I9940L A WL YY WW G 2I9940L AWLYYWWG = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. Features * LVPECL or LVCMOS Clock Input * 2.5 V LVCMOS Outputs for Intel(R) Pentium(R) II * * * * Microprocessor Support 150 pS Maximum Output-to-Output Skew Maximum Output Frequency of 250 MHz 32 Lead LQFP Package Dual or Single Supply Device: (c) Semiconductor Components Industries, LLC, 2011 May, 2011 - Rev. 0 Dual VCC Supply Voltage, 3.3 V Core and 2.5 V Output Single 3.3 V VCC Supply Voltage for 3.3 V Outputs Single 2.5 V VCC Supply Voltage for 2.5 V I/O Pin and Function compatible to MPC940L, MPC9109, CY29940 and CY29940-1 These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant * * 1 Publication Order Number: ASM2I9940L/D ASM2I9940L PECL_CLK 0 PECL_CLK Q0 LVCMOS_CLK 1 16 LVCMOS_CLK_Sel Q1-Q16 (Internal Pulldown) Q17 Q6 Q7 Q8 VCCI Q9 Q10 Q11 GND Figure 1. Block Diagram 24 23 22 21 20 19 18 17 GNDO 25 16 VCCO Q5 26 15 Q12 Q4 27 14 Q13 Q3 28 13 Q14 VCC0 29 12 GNDO Q2 30 11 Q15 Q1 31 10 Q16 Q0 32 9 Q17 7 8 VCCI VCCO 5 6 PECL_CLK 4 PECL_CLK GNDI 3 LVCMOS_CLK_Sel 2 LVCMOS_CLK 1 GNDO ASM2I9940L Figure 2. Pin Diagram Table 1. FUNCTION TABLE Table 2. POWER SUPPLY VOLTAGES LVCMOS_CLK_Sel Input Supply Pin Voltage Level 0 1 PECL_CLK LVCMOS_CLK VCCI VCCO 2.5 V or 3.3 V $ 5% 2.5 V or 3.3 V $ 5% http://onsemi.com 2 ASM2I9940L Table 3. PIN CONFIGURATIONS Pin # Pin Name I/O Type 5 6 PECL_CLK PECL_CLK Input LVPECL LVPECL Clock Inputs Function 3 LVCMOS_CLK Input LVCMOS LVCMOS Clock Input 4 LVCMOS_CLK_Sel Input LVCMOS Selects either LVPECL or LVCMOS input as Clock Source 32, 31, 30, 28, 27, 26, 24, 23, 22, 20, 19, 18, 15, 14, 13, 11, 10, 9 Q0 - Q17 Output LVCMOS Clock Outputs 2 GNDI Supply Core Negative Power Supply 1, 12, 17, 25 GNDO Supply Output Negative Power Supply 7, 21 VCCI Supply Core Positive Power Supply 8, 16, 29 VCCO Supply Output Positive Power Supply Table 4. ABSOLUTE MAXIMUM RATINGS Symbol Min Max Unit Supply Voltage -0.3 3.6 V VI Input Voltage -0.3 VCC + 0.3 V IIN Input Current $20 mA 125 C 260 C 2 kV VCC TStor Ts TDV Parameter Storage Temperature Range -40 Max. Soldering Temperature (10 sec) Static Discharge Voltage (As per JEDEC STD22-A114-B) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. DC CHARACTERISTICS (TA = 0C to 70C, VCCI = 3.3 V $ 5%, VCCO = 3.3 V $ 5%) Symbol Characteristic Condition Min Typ Unit VCCI V 0.8 V VIH Input HIGH Voltage CMOS_CLK VIL Input LOW Voltage CMOS_CLK VPP Peak-to-Peak Input Voltage PECL_CLK 500 1000 mV Common Mode Range PECL_CLK VCCI - 1.4 VCCI - 0.6 V VCMR 2.4 Max VOH Output HIGH Voltage IOH = -20 mA VOL Output LOW Voltage IOL = 20 mA IIN Input Current CIN Input Capacitance Cpd Power Dissipation Capacitance ZOUT ICC 2.4 per output Output Impedance 18 Maximum Quiescent Supply Current http://onsemi.com 3 V 0.5 V $200 mA 4.0 pF 10 pF 23 28 W 0.5 1.0 mA ASM2I9940L Table 6. AC CHARACTERISTICS (TA = 0C to 70C, VCCI = 3.3 V $ 5%, VCCO = 3.3 V $ 5%) Symbol Characteristic Condition Fmax Maximum Input Frequency tPLH Propagation Delay PECL_CLK v 150 MHz CMOS_CLK v 150 MHz tPLH Propagation Delay PECL_CLK > 150 MHz CMOS_CLK > 150 MHz tsk(o) Output-to-output Skew PECL_CLK CMOS_CLK tsk(pp) Part-to-Part Skew tsk(pp) (Note 1) Min Typ Max Unit 250 MHz 2.0 1.7 2.7 2.5 3.4 3.0 nS 2.0 1.8 2.9 2.5 3.7 3.2 nS (Note 1) 150 150 pS PECL_CLK 150 MHz CMOS_CLK 150 MHz (Notes 1 and 2) 1.5 1.3 nS Part-to-Part Skew PECL_CLK > 150 MHz CMOS_CLK > 150 MHz (Notes 1 and 2) 1.8 1.5 nS tsk(pp) Part-to-Part Skew PECL_CLK CMOS_CLK (Notes 1 and 3) 850 750 pS DC Output Duty Cycle fCLK < 134 MHz fCLK v 250 MHz Input DC = 50% Input DC = 50% 45 40 55 60 % tr, tf Output Rise/Fall Time 0.5 - 2.4 V 0.3 1.1 nS 50 50 1. Tested using standard input levels, Production tested @ 150 MHz. 2. Across temperature and voltage ranges, includes output skew. 3. For a specific temperature and voltage, includes output skew. Table 7. DC CHARACTERISTICS (TA = 0C to 70C, VCCI = 3.3 V $ 5%, VCCO = 2.5 V $ 5%) Symbol Characteristic Condition VIH Input HIGH Voltage CMOS_CLK VIL Input LOW Voltage CMOS_CLK VPP Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK VCMR Output HIGH Voltage IOH = -12 mA VOL Output LOW Voltage IOL = 12 mA Input Current CIN Input Capacitance Cpd Power Dissipation Capacitance ZOUT ICC Typ Max Unit VCCI V 0.8 V 500 1000 mV VCCI - 1.4 VCCI - 0.6 V 2.4 VOH IIN Min per output 1.8 V $200 mA pF 10 pF 23 Maximum Quiescent Supply Current 0.5 4 V 4.0 Output Impedance http://onsemi.com 0.5 W 1.0 mA ASM2I9940L Table 8. AC CHARACTERISTICS (TA = 0C to 70C, VCCI = 3.3 V $ 5%, VCCO = 2.5 V $ 5%) Symbol Characteristic Condition Fmax Maximum Input Frequency tPLH Propagation Delay PECL_CLK v 150 MHz CMOS_CLK v 150 MHz tPLH Propagation Delay PECL_CLK > 150 MHz CMOS_CLK > 150 MHz tsk(o) Output-to-output Skew PECL_CLK CMOS_CLK tsk(pp) Part-to-Part Skew tsk(pp) (Note 4) Min Typ Max Unit 250 MHz 2.0 1.7 2.8 2.5 3.5 3.0 nS 2.0 1.8 2.9 2.5 3.8 3.3 nS (Note 4) 150 150 pS PECL_CLK 150 MHz CMOS_CLK 150 MHz (Notes 4 and 5) 1.5 1.3 nS Part-to-Part Skew PECL_CLK > 150 MHz CMOS_CLK > 150 MHz (Notes 4 and 5) 1.8 1.5 nS tsk(pp) Part-to-Part Skew PECL_CLK CMOS_CLK (Notes 4 and 6) 850 750 pS DC Output Duty Cycle fCLK < 134 MHz fCLK v 250 MHz Input DC = 50% Input DC = 50% 45 40 55 60 % tr, tf Output Rise/Fall Time 0.5 - 1.8 V 0.3 1.2 nS 50 50 4. Tested using standard input levels, Production tested @ 150 MHz. 5. Across temperature and voltage ranges, includes output skew. 6. For a specific temperature and voltage, includes output skew. Table 9. DC CHARACTERISTICS (TA = 0C to 70C, VCCI = 2.5 V $ 5%, VCCO = 2.5 V $ 5%) Symbol Characteristic Condition VIH Input HIGH Voltage CMOS_CLK VIL Input LOW Voltage CMOS_CLK VPP Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK VCMR Output HIGH Voltage IOH = -12 mA VOL Output LOW Voltage IOL = 12 mA Input Current CIN Input Capacitance Cpd Power Dissipation Capacitance ZOUT ICC Typ Max Unit VCCI V 0.8 V 500 1000 mV VCCI - 1.0 VCCI - 0.6 V 2.0 VOH IIN Min 1.8 per output Output Impedance 18 Maximum Quiescent Supply Current http://onsemi.com 5 V 0.5 V $200 mA 4.0 pF 10 pF 23 28 W 0.5 1.0 mA ASM2I9940L Table 10. AC Characteristics (TA = 0C to 70C, VCCI = 2.5 V $ 5%, VCCO = 2.5 V $ 5%) Symbol Characteristic Condition Fmax Maximum Input Frequency tPLH Propagation Delay PECL_CLK v 150 MHz CMOS_CLK v 150 MHz tPLH Propagation Delay PECL_CLK > 150 MHz CMOS_CLK > 150 MHz tsk(o) Output-to-output Skew Within one bank PECL_CLK CMOS_CLK tsk(pp) Part-to-Part Skew tsk(pp) (Note 7) Min Typ Max Unit 200 MHz 2.6 2.3 4.0 3.1 5.2 4.0 nS 2.8 2.3 3.8 3.1 5.0 4.0 nS (Note 7) 200 200 pS PECL_CLK 150 MHz CMOS_CLK 150 MHz (Notes 7 and 8) 2.6 1.7 nS Part-to-Part Skew PECL_CLK > 150 MHz CMOS_CLK > 150 MHz (Notes 7 and 8) 2.2 1.7 nS tsk(pp) Part-to-Part Skew PECL_CLK CMOS_CLK (Notes 7 and 9) 1.2 1.0 nS DC Output Duty Cycle fCLK < 134 MHz fCLK v 200 MHz Input DC = 50% Input DC = 50% 45 40 55 60 % tr, tf Output Rise/Fall Time 0.5 - 1.8 V 0.3 1.2 nS 50 50 7. Tested using standard input levels, Production tested @ 150 MHz. 8. Across temperature and voltage ranges, includes output skew. 9. For a specific temperature and voltage, includes output skew. ASM2I9940L Z0=50 Pulse Generator Z=50 Z0 =50 RT =50 RT =50 VTT VTT Figure 3. LVCMOS_CLK ASM2I9940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V Differential Pulse Generator Z=50 ASM2I9940L Z0=50 Z0=50 RT = 50 RT=50 VTT V TT Figure 4. PECL_CLK ASM2I9940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V http://onsemi.com 6 ASM2I9940L PECL_CLK VCMR VPP PECL_CLK VCC VCC /2 tPD Q GND Figure 5. Propagation Delay (tPD) Test Reference VCC LVCMOS_CLK VCC /2 GND VCC VCC /2 Q GND tPD Figure 6. LVCMOS Propagation Delay (tPD) Test Reference VCC VCC VCC /2 VCC /2 GND GND tP VOH VCC /2 T0 GND tSK(O) DC (tP /T0 100%) The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 8. Output-to-Output Skew tSK(O) Figure 7. Output Duty Cycle (DC) VCC = 3.3V V CC = 2.5V tF 2.4 1.8V 0.55 0.6V VCC = 3.3V VCC = 2.5V tR 1.7V 0.8 0.7V tR tF Figure 9. Output Transition Time Test Reference 2.0 Figure 10. Input Transition Time Test Reference http://onsemi.com 7 ASM2I9940L Power Consumption of the ASM2I9940L and Thermal Management Where ICCQ is the static current consumption of the ASM2I9940L, CPD is the power dissipation capacitance per output, (M)SCL represents the external capacitive output load, N is the number of active outputs (N is always 12 in case of the ASM2I9940L). The ASM2I9940L supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, SCL is zero for controlled transmission line systems and can be eliminated from Equation 1. Using parallel termination output termination results in Equation 2 for power dissipation. In Equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used SCL is zero in Equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Where Rqja is the thermal impedance of the package (junction-to-ambient) and TA is the ambient temperature. According to Table 11, the junction temperature can be used to estimate the long-term device reliability. Further, combining Equation 1 and Equation 2 results in a maximum operating frequency for the ASM2I9940L in a series terminated transmission line system, Equation 4. The ASM2I9940L AC specification is guaranteed for the entire operating frequency range up to 250 MHz. The ASM2I9940L power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the ASM2I9940L die junction temperature and the associated device reliability. Table 11. DIE JUNCTION TEMPERATURE AND MTBF Junction Temperature (C) MTBF (Years) 100 20.4 110 9.1 120 4.2 130 2.0 Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the ASM2I9940L needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the ASM2I9940L is represented in Equation 1. P TOT + S C @ V M I CCQ ) V CC @ f CLOCK @ N @ C PD ) P TOT + V CC @ I CCQ ) V CC @ f CLOCK @ N @ C PD ) S C ) S DC M P L L (eq. 1) CC VCC * VOH ) 1 * DC Q @ IOL @ V OL Q @ I OH (eq. 2) T J + T A ) P TOT @ R qJA f CLOCKMAX + 1 C PD @ N @ V CC 2 @ TJ,MAX should be selected according to the MTBF system requirements and Table 11. Rqja can be derived from Table 12. The Rqja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. T JMAX * T A R qJA (eq. 3) * I CCQ @ V CC (eq. 4) Table 12. THERMAL PACKAGE IMPEDANCE OF THE 32LQFP Convection, LFPM Rthja (1P2S board), C/W Rthja (2P2S board), C/W Still air 86 61 100 lfpm 76 56 200 lfpm 71 54 300 lfpm 68 53 400 lfpm 66 52 500 lfpm 60 49 http://onsemi.com 8 ASM2I9940L corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3 V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. If the calculated maximum frequency is below 250 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the ASM2I9940L. The charts were calculated for a maximum tolerable die junction temperature of 110C (120C), ORDERING INFORMATION Part Number ASM2I9940LG-32LT Marking Package Temperature Shipping 2I9940L 32-pin LQFP Pb-Free -40C to +85C 250 Units / Tray http://onsemi.com 9 ASM2I9940L 4X 32 25 0.20 (0.008) AB T-U Z BASE METAL 1 -U- -T- B B1 EE EE EE P F DETAIL Y 17 8 N AE V V1 AE J DETAIL Y 9 -Z- 9 M A D 0.20 (0.008) A1 -T-, -U-, -Z- 32 LEAD LQFP CASE 873A-02 ISSUE C AC T-U Z PACKAGE DIMENSIONS 4X 0.20 (0.008) AC T-U Z S1 8X S DETAIL AD G SECTION AE-AE M_ R C E -AB- 0.10 (0.004) AC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. H DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.450 0.750 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.018 0.030 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF W K X DETAIL AD Q_ 0.250 (0.010) -AC- GAUGE PLANE SEATING PLANE Pentium is a registered trademark of Intel Corporation. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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