Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5604P
Rev. 8, 07/2012
© Freescale, Inc., 2008–2012. All rights reserved.
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
MPC5604P
144 LQFP
20 mm x 20 mm
100 LQFP
14 mm x 14 mm
• Up to 64 MHz, single issue, 32-bit CPU core complex
(e200z0h)
— Compliant with Power Architecture embedded
category
— Variable Length Encoding (VLE)
• Memory organization
— Up to 512 KB on-chip code flash memory with ECC
and erase/program controller
— Optional 64 (4 × 16) KB on-chip data flash memory
with ECC for EEPROM emulation
— Up to 40 KB on-chip SRAM with ECC
• Fail safe protection
— Programmable watchdog timer
— Non-maskable interrupt
— Fault collection unit
• Nexus L2+ interface
• Interrupts
— 16-channel eDMA controller
— 16 priority level controller
• General purpose I/Os individually programmable as input,
output or special function
• 2 general purpose eTimer units
— 6 timers each with up/down count capabilities
— 16-bit resolution, cascadable counters
— Quadrature decode with rotation direction flag
— Double buffer input capture and output compare
• Communications interfaces
— 2 LINFlex channels (LIN 2.1)
— 4 DSPI channels with automatic chip select
generation
— 1 FlexCAN interface (2.0B Active) with 32 message
objects
— 1 safety port based on FlexCAN with 32 message
objects and up to 7.5 Mbit/s capability; usable as
second CAN when not used as safety port
— 1 FlexRay™ module (V2.1) with selectable dual or
single channel support, 32 message objects and up to
10 Mbit/s
• Two 10-bit analog-to-digital converters (ADC)
— 2 × 15 input channels, 4 channels shared between the
two ADCs
— Conversion time < 1 µs including sampling time at
full precision
— Programmable Cross Triggering Unit (CTU)
— 4 analog watchdogs with interrupt capability
• On-chip CAN/UART bootstrap loader with Boot Assist
Module (BAM)
•1 FlexPWM unit
— 8 complementary or independent outputs with ADC
synchronization signals
— Polarity control, reload unit
— Integrated configurable dead time unit and inverter
fault input pins
— 16-bit resolution, up to 2 × fCPU
— Lockable configuration
• Clock generation
— 4–40 MHz main oscillator
— 16 MHz internal RC oscillator
— Software controlled FMPLL capable of speeds as fast
as 64 MHz
• Voltage supply
— 3.3 V or 5 V supply for I/Os and ADC
— On-chip single supply voltage regulator with external
ballast transistor
• Operating temperature ranges: –40 to 125 °C or –40
to 105 °C
Qorivva MPC5604P
Microcontroller Data Sheet
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale2
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.5 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.5.1 High performance e200z0 core processor. . . . . .7
1.5.2 Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . .8
1.5.3 Enhanced direct memory access (eDMA) . . . . . .8
1.5.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.5.5 Static random access memory (SRAM). . . . . . . .9
1.5.6 Interrupt controller (INTC) . . . . . . . . . . . . . . . . . .9
1.5.7 System status and configuration module
(SSCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.5.8 System clocks and clock generation . . . . . . . . .10
1.5.9 Frequency-modulated phase-locked loop
(FMPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
1.5.10 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5.11 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . 11
1.5.12 Periodic interrupt timer (PIT) . . . . . . . . . . . . . . . 11
1.5.13 System timer module (STM) . . . . . . . . . . . . . . . 11
1.5.14 Software watchdog timer (SWT) . . . . . . . . . . . . 11
1.5.15 Fault collection unit (FCU) . . . . . . . . . . . . . . . . .12
1.5.16 System integration unit – Lite (SIUL) . . . . . . . . .12
1.5.17 Boot and censorship . . . . . . . . . . . . . . . . . . . . .12
1.5.18 Error correction status module (ECSM). . . . . . .13
1.5.19 Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . .13
1.5.20 Controller area network (FlexCAN) . . . . . . . . . .13
1.5.21 Safety port (FlexCAN) . . . . . . . . . . . . . . . . . . . .14
1.5.22 FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.5.23 Serial communication interface module
(LINFlex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.5.24 Deserial serial peripheral interface (DSPI) . . . .15
1.5.25 Pulse width modulator (FlexPWM) . . . . . . . . . .16
1.5.26 eTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.5.27 Analog-to-digital converter (ADC) module . . . . .17
1.5.28 Cross triggering unit (CTU) . . . . . . . . . . . . . . . .18
1.5.29 Nexus development interface (NDI). . . . . . . . . .18
1.5.30 Cyclic redundancy check (CRC) . . . . . . . . . . . .19
1.5.31 IEEE 1149.1 JTAG controller . . . . . . . . . . . . . . .19
1.5.32 On-chip voltage regulator (VREG). . . . . . . . . . .19
2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . .20
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.2.1 Power supply and reference voltage pins . . . . .21
2.2.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.2.3 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . 38
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 39
3.4 Recommended operating conditions . . . . . . . . . . . . . . 42
3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46
3.5.1 Package thermal characteristics . . . . . . . . . . . 46
3.5.2 General notes for specifications at maximum
junction temperature . . . . . . . . . . . . . . . . . . . . 47
3.6 Electromagnetic interference (EMI) characteristics . . . 48
3.7 Electrostatic discharge (ESD) characteristics . . . . . . . 48
3.8 Power management electrical characteristics . . . . . . . 49
3.8.1 Voltage regulator electrical characteristics . . . . 49
3.8.2 Voltage monitor electrical characteristics . . . . . 52
3.9 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . 53
3.10 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . 55
3.10.1 NVUSRO register. . . . . . . . . . . . . . . . . . . . . . . 55
3.10.2 DC electrical characteristics (5 V) . . . . . . . . . . 55
3.10.3 DC electrical characteristics (3.3 V) . . . . . . . . . 57
3.10.4 Input DC electrical characteristics definition . . 58
3.10.5 I/O pad current specification. . . . . . . . . . . . . . . 59
3.11 Main oscillator electrical characteristics . . . . . . . . . . . 64
3.12 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 65
3.13 16 MHz RC oscillator electrical characteristics . . . . . . 67
3.14 Analog-to-digital converter (ADC) electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.14.1 Input impedance and ADC accuracy . . . . . . . . 68
3.14.2 ADC conversion characteristics . . . . . . . . . . . . 72
3.15 Flash memory electrical characteristics. . . . . . . . . . . . 74
3.16 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
3.16.1 Pad AC specifications . . . . . . . . . . . . . . . . . . . 75
3.17 AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . 76
3.17.1 RESET pin characteristics . . . . . . . . . . . . . . . . 76
3.17.2 IEEE 1149.1 interface timing . . . . . . . . . . . . . . 78
3.17.3 Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.17.4 External interrupt timing (IRQ pin) . . . . . . . . . . 83
3.17.5 DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 90
4.1.1 144 LQFP mechanical outline drawing . . . . . . 90
4.1.2 100 LQFP mechanical outline drawing . . . . . . 92
5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Appendix AAbbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 3
1 Introduction
1.1 Document overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5603P/4P series of
microcontroller units (MCUs). It also describes the device features and highlights important electrical and physical
characteristics. For functional characteristics, refer to the device reference manual.
1.2 Description
This 32-bit system-on-chip (SoC) automotive microcontroller family is the latest achievement in integrated automotive
application controllers. It belongs to an expanding range of automotive-focused products designed to address chassis
applications—specifically, electrical hydraulic power steering (EHPS) and electric power steering (EPS)—as well as airbag
applications.
This family is one of a series of next-generation integrated automotive microcontrollers based on the Power Architecture
technology.
The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture
embedded category. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power
consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported
with software drivers, operating systems and configuration code to assist with users implementations.
1.3 Device comparison
Table 1 provides a summary of different members of the MPC5604P family and their features to enable a comparison among
the family members and an understanding of the range of functionality offered within this family.
Table 1. MPC5604P device comparison
Feature MPC5603P MPC5604P
Code flash memory (with ECC) 384 KB 512 KB
Data flash memory / EE option (with ECC) 64 KB (optional feature)
SRAM (with ECC) 36 KB 40 KB
Processor core 32-bit e200z0h
Instruction set VLE (variable length encoding)
CPU performance 0–64 MHz
FMPLL (frequency-modulated phase-locked loop)
module
2
INTC (interrupt controller) channels 147
PIT (periodic interrupt timer) 1 (includes four 32-bit timers)
eDMA (enhanced direct memory access) channels 16
FlexRay1Optional feature
FlexCAN (controller area network) 22,3
Safety port Yes (via second FlexCAN module)
FCU (fault collection unit) Yes
CTU (cross triggering unit) Yes
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale4
1.4 Block diagram
Figure 1 shows a top-level block diagram of the MPC5604P MCU.
eTimer 2 (16-bit, 6 channels)
FlexPWM (pulse-width modulation) channels 8 (capturing on X-channels)
ADC (analog-to-digital converter) 2 (10-bit, 15-channel4)
LINFlex 2
DSPI (deserial serial peripheral interface) 4
CRC (cyclic redundancy check) unit Yes
JTAG controller Yes
Nexus port controller (NPC) Yes (Level 2+)
Supply Digital power supply 3.3 V or 5 V single supply with external transistor
Analog power supply 3.3 V or 5 V
Internal RC oscillator 16 MHz
External crystal oscillator 4–40 MHz
Packages 100 LQFP
144 LQFP
Temperature Standard ambient temperature –40 to 125 °C
132 message buffers, selectable single or dual channel support
2Each FlexCAN module has 32 message buffers.
3One FlexCAN module can act as a Safety Port with a bit rate as high as 7.5 Mbit/s.
4Four channels shared between the two ADCs
Table 1. MPC5604P device comparison (continued)
Feature MPC5603P MPC5604P
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 5
Figure 1. MPC5604P block diagram
e200z0 Core
32-bit
general
purpose
registers
Special
purpose
registers
Integer
execution
unit
Exception
handler
Variable
length
encoded
instructions
Instruction
unit
Load/store
unit
Branch
prediction
unit
JTAG
1.2 V regulator
control
XOSC
16 MHz
RC oscillator
FMPLL_0
(System)
Nexus port
controller
Interrupt
controller
eDMA
16 channels
Master Master
Instruction
32-bit
Master
Data
32-bit
SRAM
(with ECC)
Slave Slave
Crossbar switch (XBAR, AMBA 2.0 v6 AHB)
Peripheral bridge
FCU
Legend:
ADC Analog-to-digital converter
BAM Boot assist module
CRC Cyclic redundancy check
CTU Cross triggering unit
DSPI Deserial serial peripheral interface
ECSM Error correction status module
eDMA Enhanced direct memory access
eTimer Enhanced timer
FCU Fault collection unit
Flash Flash memory
FlexCAN Controller area network
FlexPWM Flexible pulse width modulation
FMPLL Frequency-modulated phase-locked loop
INTC Interrupt controller
JTAG JTAG controller
LINFlex Serial communication interface (LIN support)
MC_CGM Clock generation module
MC_ME Mode entry module
MC_PCU Power control unit
MC_RGM Reset generation module
PIT Periodic interrupt timer
SIUL System integration unit Lite
SRAM Static random-access memory
SSCM System status and configuration module
STM System timer module
SWT Software watchdog timer
WKPU Wakeup unit
XOSC External oscillator
XBAR Crossbar switch
Slave
External ballast
Code Flash
(with ECC)
Data Flash
(with ECC)
Nexus 2+
eDMA
16 channels
FlexPWM
CTU
4×
2×
DSPI
2×
FlexCAN
LINFlex
Safety port
PIT
STM
SWT
MC_RGM
MC_CGM
MC_ME
BAM
SIUL
eTimer (6 ch)
FMPLL_1
(FlexRay, MotCtrl)
FlexRay
SSCM
1.2 V Rail VREG
WKPU
CRC
Shared
Channels
Channels
10-bit 10-bit
0–10
0–10
channels
11–14
ADC_1ADC_0
ECSM
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale6
Table 2. MPC5604P series block summary
Block Function
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter
Boot assist module (BAM) Block of read-only memory containing VLE code which is executed according to
the boot mode of the device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Controller area network (FlexCAN) Supports the standard CAN communications protocol
Cross triggering unit (CTU) Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Crossbar switch (XBAR) Supports simultaneous connections between two master ports and three slave
ports; supports a 32-bit address bus width and a 32-bit data bus width
Cyclic redundancy check (CRC) CRC checksum generator
Deserial serial peripheral interface
(DSPI)
Provides a synchronous serial interface for communication with external devices
Enhanced direct memory access
(eDMA)
Performs complex data transfers with minimal intervention from a host processor
via “n” programmable channels
Enhanced timer (eTimer) Provides enhanced programmable up/down modulo counting
Error correction status module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
External oscillator (XOSC) Provides an output clock used as input reference for FMPLL_0 or as reference
clock for specific modules depending on system needs
Fault collection unit (FCU) Provides functional safety to the device
Flash memory Provides non-volatile storage for program code, constants and variables
Frequency-modulated
phase-locked loop (FMPLL)
Generates high-speed system clocks and supports programmable frequency
modulation
Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests
JTAG controller Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINFlex controller Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with minimum load on CPU
Mode entry module (MC_ME) Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control unit,
reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Periodic interrupt timer (PIT) Produces periodic interrupts and triggers
Peripheral bridge (PBRIDGE) Interface between the system bus and on-chip peripherals
Power control unit (MC_PCU) Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 7
1.5 Feature details
1.5.1 High performance e200z0 core processor
The e200z0 Power Architecture core provides the following features:
• High performance e200z0 core processor for managing peripherals and interrupts
• Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU
• Harvard architecture
• Variable length encoding (VLE), allowing mixed 16-bit and 32-bit instructions
— Results in smaller code size footprint
— Minimizes impact on performance
• Branch processing acceleration using lookahead instruction buffer
• Load/store unit
— 1 cycle load latency
— Misaligned access support
— No load-to-use pipeline bubbles
• Thirty-two 32-bit general purpose registers (GPRs)
• Separate instruction bus and load/store bus Harvard architecture
• Hardware vectored interrupt support
• Reservation instructions for implementing read-modify-write constructs
• Long cycle time instructions, except for guarded loads, do not increase interrupt latency
• Extensive system development support through Nexus debug port
• Non-maskable interrupt support
Pulse width modulator (FlexPWM) Contains four PWM submodules, each of which is capable of controlling a single
half-bridge power stage and two fault input channels
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the device
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status and configuration
module (SSCM)
Provides system configuration and status data (such as memory size and status,
device mode and security status), device identification data, debug status port
enable and selection, and bus and peripheral abort enable/disable
System timer module (STM) Provides a set of output compare events to support AUTOSAR1 and operating
system tasks
System watchdog timer (SWT) Provides protection from runaway code
Wakeup unit (WKPU) Supports up to 18 external sources that can generate interrupts or wakeup
events, 1 of which can cause non-maskable interrupt requests or wakeup events
1AUTOSAR: AUTomotive Open System ARchitecture (see http://www.autosar.org)
Table 2. MPC5604P series block summary (continued)
Block Function
MPC5604P Microcontroller Data Sheet, Rev. 8
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1.5.2 Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four master ports and three slave ports. The
crossbar supports a 32-bit address bus width and a 32-bit data bus width.
The crossbar allows for two concurrent transactions to occur from any master port to any slave port; but one of those transfers
must be an instruction fetch from internal flash memory. If a slave port is simultaneously requested by more than one master
port, arbitration logic will select the higher priority master and grant it ownership of the slave port. All other masters requesting
that slave port will be stalled until the higher priority master completes its transactions. Requesting masters will be treated with
equal priority and will be granted access to a slave port in round-robin fashion, based upon the ID of the last master to be granted
access.
The crossbar provides the following features:
• 4 master ports:
— e200z0 core complex Instruction port
— e200z0 core complex Load/Store Data port
—eDMA
—FlexRay
• 3 slave ports:
— Flash memory (code flash and data flash)
—SRAM
— Peripheral bridge
• 32-bit internal address, 32-bit internal data paths
• Fixed Priority Arbitration based on Port Master
• Temporary dynamic priority elevation of masters
1.5.3 Enhanced direct memory access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data
movements via 16 programmable channels, with minimal intervention from the host processor. The hardware micro architecture
includes a DMA engine which performs source and destination address calculations, and the actual data movement operations,
along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation
is utilized to minimize the overall block size.
The eDMA module provides the following features:
• 16 channels support independent 8, 16 or 32-bit single value or block transfers
• Supports variable sized queues and circular queues
• Source and destination address registers are independently configured to either post-increment or to remain constant
• Each transfer is initiated by a peripheral, CPU, or eDMA channel request
• Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block
transfer
• DMA transfers possible between system memories, DSPIs, ADC, FlexPWM, eTimer and CTU
• Programmable DMA channel multiplexer for assignment of any DMA source to any available DMA channel with as
many as 30 request sources
• eDMA abort operation through software
1.5.4 Flash memory
The MPC5604P provides as much as 576 KB of programmable, non-volatile, flash memory. The non-volatile memory (NVM)
can be used for instruction and/or data storage. The flash memory module interfaces the system bus to a dedicated flash memory
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 9
array controller. It supports a 32-bit data bus width at the system bus port, and a 128-bit read data interface to flash memory.
The module contains four 128-bit wide prefetch buffers. Prefetch buffer hits allow no-wait responses. Normal flash memory
array accesses are registered and are forwarded to the system bus on the following cycle, incurring two wait-states.
The flash memory module provides the following features:
• As much as 576 KB flash memory
— 8 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 3×128 KB) code flash
— 4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash
— Full Read While Write (RWW) capability between code and data flash
• Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch buffers can be configured to
prefetch code or data or both)
• Typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page buffer miss at 64 MHz
• Hardware managed flash memory writes handled by 32-bit RISC Krypton engine
• Hardware and software configurable read and write access protections on a per-master basis
• Configurable access timing allowing use in a wide range of system frequencies
• Multiple-mapping support and mapping-based block access timing (up to 31 additional cycles) allowing use for
emulation of other memory types.
• Software programmable block program/erase restriction control
• Erase of selected block(s)
• Read page sizes
— Code flash memory: 128 bits (4 words)
— Data flash memory: 32 bits (1 word)
• ECC with single-bit correction, double-bit detection for data integrity
— Code flash memory: 64-bit ECC
— Data flash memory: 64-bit ECC
• Embedded hardware program and erase algorithm
• Erase suspend, program suspend and erase-suspended program
• Censorship protection scheme to prevent flash memory content visibility
• Hardware support for EEPROM emulation
1.5.5 Static random access memory (SRAM)
The MPC5604P SRAM module provides up to 40 KB of general-purpose memory.
ECC handling is done on a 32-bit boundary and is completely software compatible with MPC55xx family devices with an
e200z6 core and 64-bit wide ECC.
The SRAM module provides the following features:
• Supports read/write accesses mapped to the SRAM from any master
• Up to 40 KB general purpose SRAM
• Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory
• Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait state for 8- and 16-bit writes if back to back
with a read to same memory block
1.5.6 Interrupt controller (INTC)
The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt requests, suitable for statically
scheduled hard real-time systems. The INTC handles 147 selectable-priority interrupt sources.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale10
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR has to be executed. It also provides a wide number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority
ceiling protocol (PCP) for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so
that all tasks which share the same resource can not preempt each other.
The INTC provides the following features:
• Unique 9-bit vector for each separate interrupt source
• 8 software triggerable interrupt sources
• 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
• Ability to modify the ISR or task priority: modifying the priority can be used to implement the Priority Ceiling Protocol
for accessing shared resources.
• 2 external high priority interrupts directly accessing the main core and I/O processor (IOP) critical interrupt mechanism
1.5.7 System status and configuration module (SSCM)
The system status and configuration module (SSCM) provides central device functionality.
The SSCM includes these features:
• System configuration and status
— Memory sizes/status
— Device mode and security status
— Determine boot vector
— Search code flash for bootable sector
— DMA status
• Debug status port enable and selection
• Bus and peripheral abort enable/disable
1.5.8 System clocks and clock generation
The following list summarizes the system clock and clock generation on the MPC5604P:
• Lock detect circuitry continuously monitors lock status
• Loss of clock (LOC) detection for PLL outputs
• Programmable output clock divider (1, 2, 4, 8)
• FlexPWM module and eTimer module can run on an independent clock source
• On-chip oscillator with automatic level control
• Internal 16 MHz RC oscillator for rapid start-up and safe mode: supports frequency trimming by user application
1.5.9 Frequency-modulated phase-locked loop (FMPLL)
The FMPLL allows the user to generate high speed system clocks from a 4–40 MHz input clock. Further, the FMPLL supports
programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all
software configurable.
The PLL has the following major features:
• Input clock frequency: 4–40 MHz
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 11
• Maximum output frequency: 64 MHz
• Voltage controlled oscillator (VCO)—frequency 256–512 MHz
• Reduced frequency divider (RFD) for reduced frequency operation without forcing the PLL to relock
• Frequency-modulated PLL
— Modulation enabled/disabled through software
— Triangle wave modulation
• Programmable modulation depth (±0.25% to ±4% deviation from center frequency): programmable modulation
frequency dependent on reference frequency
• Self-clocked mode (SCM) operation
1.5.10 Main oscillator
The main oscillator provides these features:
• Input frequency range: 4–40 MHz
• Crystal input mode or oscillator input mode
• PLL reference
1.5.11 Internal RC oscillator
This device has an RC ladder phase-shift oscillator. The architecture uses constant current charging of a capacitor. The voltage
at the capacitor is compared by the stable bandgap reference voltage.
The RC oscillator provides these features:
• Nominal frequency 16 MHz
• ±5% variation over voltage and temperature after process trim
• Clock output of the RC oscillator serves as system clock source in case loss of lock or loss of clock is detected by the
PLL
• RC oscillator is used as the default system clock during startup
1.5.12 Periodic interrupt timer (PIT)
The PIT module implements these features:
• 4 general purpose interrupt timers
• 32-bit counter resolution
• Clocked by system clock frequency
• Each channel can be used as trigger for a DMA request
1.5.13 System timer module (STM)
The STM module implements these features:
• One 32-bit up counter with 8-bit prescaler
• Four 32-bit compare channels
• Independent interrupt source for each channel
• Counter can be stopped in debug mode
1.5.14 Software watchdog timer (SWT)
The SWT has the following features:
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale12
• 32-bit time-out register to set the time-out period
• Programmable selection of system or oscillator clock for timer operation
• Programmable selection of window mode or regular servicing
• Programmable selection of reset or interrupt on an initial time-out
• Master access protection
• Hard and soft configuration lock bits
• Reset configuration inputs allow timer to be enabled out of reset
1.5.15 Fault collection unit (FCU)
The FCU provides an independent fault reporting mechanism even if the CPU is malfunctioning.
The FCU module has the following features:
• FCU status register reporting the device status
• Continuous monitoring of critical fault signals
• User selection of critical signals from different fault sources inside the device
• Critical fault events trigger 2 external pins (user selected signal protocol) that can be used externally to reset the device
and/or other circuitry (for example, safety relay or FlexRay transceiver)
• Faults are latched into a register
1.5.16 System integration unit – Lite (SIUL)
The MPC5604P SIUL controls MCU pad configuration, external interrupt, general purpose I/O (GPIO), and internal peripheral
multiplexing.
The pad configuration block controls the static electrical characteristics of I/O pins. The GPIO block provides uniform and
discrete input/output control of the I/O pins of the MCU.
The SIU provides the following features:
• Centralized general purpose input output (GPIO) control of as many as 80 input/output pins and 26 analog input-only
pads (package dependent)
• All GPIO pins can be independently configured to support pull-up, pull down, or no pull
• Reading and writing to GPIO supported both as individual pins and 16-bit wide ports
• All peripheral pins (except ADC channels) can be alternatively configured as both general purpose input or output pins
• ADC channels support alternative configuration as general purpose inputs
• Direct readback of the pin value is supported on all pins through the SIUL
• Configurable digital input filter that can be applied to some general purpose input pins for noise elimination: as many
as 4 internal functions can be multiplexed onto 1 pin
1.5.17 Boot and censorship
Different booting modes are available in the MPC5604P: booting from internal flash memory and booting via a serial link.
The default booting scheme uses the internal flash memory (an internal pull-down is used to select this mode). Optionally, the
user can boot via FlexCAN or LINFlex (using the boot assist module software).
A censorship scheme is provided to protect the content of the flash memory and offer increased security for the entire device.
A password mechanism is designed to grant the legitimate user access to the non-volatile memory.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 13
1.5.17.1 Boot assist module (BAM)
The BAM is a block of read-only one-time programmed memory and is identical for all MPC560xP devices that are based on
the e200z0h core. The BAM program is executed every time the device is powered on if the alternate boot mode has been
selected by the user.
The BAM provides the following features:
• Serial bootloading via FlexCAN or LINFlex
• Ability to accept a password via the used serial communication channel to grant the legitimate user access to the
non-volatile memory
1.5.18 Error correction status module (ECSM)
The ECSM provides a myriad of miscellaneous control functions regarding program-visible information about the platform
configuration and revision levels, a reset status register, a software watchdog timer, wakeup control for exiting sleep modes,
and information on platform memory errors reported by error-correcting codes and/or generic access error information for
certain processor cores.
The Error Correction Status Module supports a number of miscellaneous control functions for the platform. The ECSM includes
these features:
• Registers for capturing information on platform memory errors if error-correcting codes (ECC) are implemented
• For test purposes, optional registers to specify the generation of double-bit memory errors are enabled on the
MPC5604P.
The sources of the ECC errors are:
• Flash memory
•SRAM
1.5.19 Peripheral bridge (PBRIDGE)
The PBRIDGE implements the following features:
• Duplicated periphery
• Master access privilege level per peripheral (per master: read access enable; write access enable)
• Write buffering for peripherals
• Checker applied on PBRIDGE output toward periphery
• Byte endianess swap capability
1.5.20 Controller area network (FlexCAN)
The MPC5604P MCU contains one controller area network (FlexCAN) module. This module is a communication controller
implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used
primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in
the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FlexCAN module contains 32 message
buffers.
The FlexCAN module provides the following features:
• Full implementation of the CAN protocol specification, version 2.0B
— Standard data and remote frames
— Extended data and remote frames
— Up to 8-bytes data length
— Programmable bit rate up to 1 Mbit/s
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale14
• 32 message buffers of up to 8-bytes data length
• Each message buffer configurable as Rx or Tx, all supporting standard and extended messages
• Programmable loop-back mode supporting self-test operation
• 3 programmable mask registers
• Programmable transmit-first scheme: lowest ID or lowest buffer number
• Time stamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
• Maskable interrupts
• Independent of the transmission medium (an external transceiver is assumed)
• High immunity to EMI
• Short latency time due to an arbitration scheme for high-priority messages
• Transmit features
— Supports configuration of multiple mailboxes to form message queues of scalable depth
— Arbitration scheme according to message ID or message buffer number
— Internal arbitration to guarantee no inner or outer priority inversion
— Transmit abort procedure and notification
• Receive features
— Individual programmable filters for each mailbox
— 8 mailboxes configurable as a six-entry receive FIFO
— 8 programmable acceptance filters for receive FIFO
• Programmable clock source
— System clock
— Direct oscillator clock to avoid PLL jitter
1.5.21 Safety port (FlexCAN)
The MPC5604P MCU has a second CAN controller synthesized to run at high bit rates to be used as a safety port. The CAN
module of the safety port provides the following features:
• Identical to the FlexCAN module
• Bit rate as fast as 7.5 Mbit/s at 60 MHz CPU clock using direct connection between CAN modules (no physical
transceiver required)
• 32 message buffers of up to 8 bytes data length
• Can be used as a second independent CAN module
1.5.22 FlexRay
The FlexRay module provides the following features:
• Full implementation of FlexRay Protocol Specification 2.1
• 32 configurable message buffers can be handled
• Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate
• Message buffers configurable as Tx, Rx or RxFIFO
• Message buffer size configurable
• Message filtering for all message buffers based on FrameID, cycle count and message ID
• Programmable acceptance filters for RxFIFO message buffers
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 15
1.5.23 Serial communication interface module (LINFlex)
The LINFlex (local interconnect network flexible) on the MPC5604P features the following:
• Supports LIN Master mode, LIN Slave mode and UART mode
• LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications
• Handles LIN frame transmission and reception without CPU intervention
• LIN features
— Autonomous LIN frame handling
— Message buffer to store Identifier and as much as 8 data bytes
— Supports message length as long as 64 bytes
— Detection and flagging of LIN errors (sync field, delimiter, ID parity, bit framing, checksum, and time-out)
— Classic or extended checksum calculation
— Configurable Break duration as long as 36-bit times
— Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)
— Diagnostic features: Loop back; Self Test; LIN bus stuck dominant detection
— Interrupt-driven operation with 16 interrupt sources
• LIN slave mode features
— Autonomous LIN header handling
— Autonomous LIN response handling
• UART mode
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word length (8-bit or 9-bit words)
— Error detection and flagging
— Parity, Noise and Framing errors
— Interrupt-driven operation with four interrupt sources
— Separate transmitter and receiver CPU interrupt sources
— 16-bit programmable baud-rate modulus counter and 16-bit fractional
— 2 receiver wake-up methods
1.5.24 Deserial serial peripheral interface (DSPI)
The deserial serial peripheral interface (DSPI) module provides a synchronous serial interface for communication between the
MPC5604P MCU and external devices.
The DSPI modules provide these features:
• Full duplex, synchronous transfers
• Master or slave operation
• Programmable master bit rates
• Programmable clock polarity and phase
• End-of-transmission interrupt flag
• Programmable transfer baud rate
• Programmable data frames from 4 to 16 bits
• Up to 20 chip select lines available
— 8 on DSPI_0
— 4 each on DSPI_1, DSPI_2 and DSPI_3
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale16
• 8 clock and transfer attributes registers
• Chip select strobe available as alternate function on one of the chip select pins for deglitching
• FIFOs for buffering as many as 5 transfers on the transmit and receive side
• Queueing operation possible through use of the eDMA
• General purpose I/O functionality on pins when not used for SPI
1.5.25 Pulse width modulator (FlexPWM)
The pulse width modulator module (PWM) contains four PWM submodules, each capable of controlling a single half-bridge
power stage. There are also four fault channels.
This PWM is capable of controlling most motor types: AC induction motors (ACIM), permanent magnet AC motors (PMAC),
both brushless (BLDC) and brush DC motors (BDC), switched (SRM) and variable reluctance motors (VRM), and stepper
motors.
The FlexPWM block implements the following features:
• 16-bit resolution for center, edge-aligned, and asymmetrical PWMs
• Maximum operating clock frequency of 120 MHz
• PWM outputs can operate as complementary pairs or independent channels
• Can accept signed numbers for PWM generation
• Independent control of both edges of each PWM output
• Synchronization to external hardware or other PWM supported
• Double buffered PWM registers
— Integral reload rates from 1 to 16
— Half cycle reload capability
• Multiple ADC trigger events can be generated per PWM cycle via hardware
• Write protection for critical registers
• Fault inputs can be assigned to control multiple PWM outputs
• Programmable filters for fault inputs
• Independently programmable PWM output polarity
• Independent top and bottom deadtime insertion
• Each complementary pair can operate with its own PWM frequency and deadtime values
• Individual software-control for each PWM output
• All outputs can be programmed to change simultaneously via a “Force Out” event
• PWMX pin can optionally output a third PWM signal from each submodule
• Channels not used for PWM generation can be used for buffered output compare functions
• Channels not used for PWM generation can be used for input capture functions
• Enhanced dual-edge capture functionality
• eDMA support with automatic reload
• 2 fault inputs
• Capture capability for PWMA, PWMB, and PWMX channels not supported
1.5.26 eTimer
The MPC5604P includes two eTimer modules. Each module provides six 16-bit general purpose up/down timer/counter units
with the following features:
• Maximum operating clock frequency of 120 MHz
• Individual channel capability
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 17
— Input capture trigger
— Output compare
— Double buffer (to capture rising edge and falling edge)
— Separate prescaler for each counter
— Selectable clock source
— 0–100% pulse measurement
— Rotation direction flag (Quad decoder mode)
• Maximum count rate
— External event counting: max. count rate = peripheral clock/2
— Internal clock counting: max. count rate = peripheral clock
• Counters are:
— Cascadable
— Preloadable
• Programmable count modulo
• Quadrature decode capabilities
• Counters can share available input pins
• Count once or repeatedly
• Pins available as GPIO when timer functionality not in use
1.5.27 Analog-to-digital converter (ADC) module
The ADC module provides the following features:
Analog part:
• 2 on-chip AD converters
— 10-bit AD resolution
— 1 sample and hold unit per ADC
— Conversion time, including sampling time, less than 1 µs (at full precision)
— Typical sampling time is 150 ns min. (at full precision)
— Differential non-linearity error (DNL) ±1 LSB
— Integral non-linearity error (INL) ±1.5 LSB
—TUE <3LSB
— Single-ended input signal up to 5.0 V
— The ADC and its reference can be supplied with a voltage independent from VDDIO
— The ADC supply can be equal or higher than VDDIO
— The ADC supply and the ADC reference are not independent from each other (they are internally bonded to the
same pad)
— Sample times of 2 (default), 8, 64, or 128 ADC clock cycles
Digital part:
• 2 × 13 input channels including 4 channels shared between the 2 converters
• 4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in
the appropriate ADC result location,
• 2 modes of operation: Normal mode or CTU control mode
• Normal mode features
— Register-based interface with the CPU: control register, status register, 1 result register per channel
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale18
— ADC state machine managing 3 request flows: regular command, hardware injected command, software injected
command
— Selectable priority between software and hardware injected commands
— 4 analog watchdogs comparing ADC results against predefined levels (low, high, range)
— DMA compatible interface
• CTU control mode features
— Triggered mode only
— 4 independent result queues (2 × 16 entries, 2 × 4 entries)
— Result alignment circuitry (left justified; right justified)
— 32-bit read mode allows to have channel ID on one of the 16-bit part
— DMA compatible interfaces
1.5.28 Cross triggering unit (CTU)
The cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without CPU
load during the PWM period and with minimized CPU load for dynamic configuration.
It implements the following features:
• Double buffered trigger generation unit with as many as eight independent triggers generated from external triggers
• Trigger generation unit configurable in sequential mode or in triggered mode
• Each Trigger can be appropriately delayed to compensate the delay of external low pass filter
• Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation
• Double buffered ADC command list pointers to minimize ADC-trigger unit update
• Double buffered ADC conversion command list with as many as 24 ADC commands
• Each trigger has the capability to generate consecutive commands
• ADC conversion command allows to control ADC channel from each ADC, single or synchronous sampling,
independent result queue selection
1.5.29 Nexus development interface (NDI)
The NDI (Nexus Development Interface) block provides real-time development support capabilities for the MPC5604P Power
Architecture based MCU in compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied for
MCUs without requiring external address and data pins for internal visibility. The NDI block is an integration of several
individual Nexus blocks that are selected to provide the development support interface for this device. The NDI block interfaces
to the host processor and internal busses to provide development support as per the IEEE-ISTO 5001-2003 Class 2+ standard.
The development support provided includes access to the MCU’s internal memory map and access to the processor’s internal
registers during run time.
The Nexus Interface provides the following features:
• Configured via the IEEE 1149.1
• All Nexus port pins operate at VDDIO (no dedicated power supply)
• Nexus 2+ features supported
— Static debug
— Watchpoint messaging
— Ownership trace messaging
— Program trace messaging
— Real time read/write of any internally memory mapped resources through JTAG pins
— Overrun control, which selects whether to stall before Nexus overruns or keep executing and allow overwrite of
information
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 19
— Watchpoint triggering, watchpoint triggers program tracing
• Auxiliary Output Port
— 4 MDO (Message Data Out) pins
— MCKO (Message Clock Out) pin
—2 MSEO
(Message Start/End Out) pins
—EVTO
(Event Out) pin
• Auxiliary Input Port
—EVTI
(Event In) pin
1.5.30 Cyclic redundancy check (CRC)
The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The CRC module features:
• Support for CRC-16-CCITT (x25 protocol):
—x16 + x12 + x5 + 1
• Support for CRC-32 (Ethernet protocol):
—x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
• Zero wait states for each write/read operations to the CRC_CFG and CRC_INP registers at the maximum frequency
1.5.31 IEEE 1149.1 JTAG controller
The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while remaining transparent
to system logic when not in test mode. All data input to and output from the JTAGC block is communicated in serial format.
The JTAGC block is compliant with the IEEE standard.
The JTAG controller provides the following features:
• IEEE Test Access Port (TAP) interface with 4 pins (TDI, TMS, TCK, TDO)
• Selectable modes of operation include JTAGC/debug or normal system operation.
• A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
— BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD
• A 5-bit instruction register that supports the additional following public instructions:
— ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_ONCE
• 3 test data registers: a bypass register, a boundary scan register, and a device identification register.
• A TAP controller state machine that controls the operation of the data registers, instruction register and associated
circuitry.
1.5.32 On-chip voltage regulator (VREG)
The on-chip voltage regulator module provides the following features:
• Uses external NPN (negative-positive-negative) transistor
• Regulates external 3.3 V /5.0 V down to 1.2 V for the core logic
• Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale20
2 Package pinouts and signal descriptions
2.1 Package pinouts
The LQFP pinouts are shown in the following figures.
Figure 2. 144-pin LQFP pinout (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
NMI
A[6]
D[1]
F[4]
F[5]
VDD_HV_IO0
VSS_HV_IO0
F[6]
MDO[0]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
C[3]
VSS_LV_COR0
VDD_LV_COR0
F[7]
F[8]
VDD_HV_IO1
VSS_HV_IO1
F[9]
F[10]
F[11]
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[6]
VSS_LV_COR3
VDD_LV_COR3
A[4]
VPP_TEST
F[12]
D[14]
G[3]
C[14]
G[2]
C[13]
G[4]
D[12]
G[6]
VDD_HV_FL
VSS_HV_FL
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
G[5]
A[2]
G[7]
C[12]
G[8]
C[11]
G[9]
D[11]
G[10]
D[10]
G[11]
A[1]
A[0]
D[7]
G[0]
E[1]
E[3]
C[1]
E[4]
B[7]
E[5]
C[2]
E[6]
B[8]
E[7]
E[2]
VDD_HV_ADC0
VSS_HV_ADC0
B[9]
B[10]
B[11]
B[12]
VDD_HV_ADC1
VSS_HV_ADC1
D[15]
E[8]
B[13]
E[9]
B[15]
E[10]
B[14]
E[11]
C[0]
E[12]
E[0]
BCTRL
VDD_LV_REGCOR
VSS_LV_REGCOR
VDD_HV_REG
A[15]
A[14]
C[6]
G[1]
D[2]
F[3]
B[6]
F[2]
A[13]
F[1]
A[9]
F[0]
VSS_LV_COR2
VDD_LV_COR2
C[8]
D[4]
D[3]
VSS_HV_IO3
VDD_HV_IO3
D[0]
C[15]
C[9]
A[12]
E[15]
A[11]
E[14]
A[10]
E[13]
B[3]
F[14]
B[2]
F[15]
F[13]
C[10]
B[1]
B[0]
144 LQFP
Note: Availability of port pin alternate functions depends on product selection.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 21
Figure 3. 100-pin LQFP pinout (top view)
2.2 Pin description
The following sections provide signal descriptions and related information about the functionality and configuration of the
MPC5604P devices.
2.2.1 Power supply and reference voltage pins
Table 3 lists the power supply and reference voltage for the MPC5604P devices.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
NMI
A[6]
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
C[3]
VSS_LV_COR0
VDD_LV_COR0
VDD_HV_IO1
VSS_HV_IO1
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[6]
VSS_LV_COR3
VDD_LV_COR3
A[4]
VPP_TEST
D[14]
C[14]
C[13]
D[12]
VDD_HV_FL
VSS_HV_FL
D[13]
VSS_LV_COR1
VDD_LV_COR1
A[3]
VDD_HV_IO2
VSS_HV_IO2
TDO
TCK
TMS
TDI
A[2]
C[12]
C[11]
D[11]
D[10]
A[1]
A[0]
D[7]
E[1]
C[1]
B[7]
C[2]
B[8]
E[2]
VDD_HV_ADC0
VSS_HV_ADC0
B[9]
B[10]
B[11]
B[12]
VDD_HV_ADC1
VSS_HV_ADC1
D[15]
B[13]
B[15]
B[14]
C[0]
E[0]
BCTRL
VDD_LV_REGCOR
VSS_LV_REGCOR
VDD_HV_REG
A[15]
A[14]
C[6]
D[2]
B[6]
A[13]
A[9]
VSS_LV_COR2
VDD_LV_COR2
C[8]
D[4]
D[3]
VSS_HV_IO3
VDD_HV_IO3
D[0]
C[15]
C[9]
A[12]
A[11]
A[10]
B[3]
B[2]
C[10]
B[1]
B[0]
100 LQFP
Note: Availability of port pin alternate functions depends on product selection.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale22
Table 3. Supply pins
Supply Pin
Symbol Description 100-pin 144-pin
VREG control and power supply pins. Pins available on 100-pin and 144-pin package.
BCTRL Voltage regulator external NPN ballast base control pin 47 69
VDD_HV_REG (3.3 V
or 5.0 V)
Voltage regulator supply voltage 50 72
VDD_LV_REGCOR 1.2 V decoupling pins for core logic and regulator feedback.
Decoupling capacitor must be connected between this pins
and VSS_LV_REGCOR.
48 70
VSS_LV_REGCOR 1.2 V decoupling pins for core logic and regulator feedback.
Decoupling capacitor must be connected between this pins
and VDD_LV_REGCOR.
49 71
ADC_0/ADC_1 reference and supply voltage. Pins available on 100-pin and 144-pin package.
VDD_HV_ADC01ADC_0 supply and high reference voltage 33 50
VSS_HV_ADC0 ADC_0 ground and low reference voltage 34 51
VDD_HV_ADC1 ADC_1 supply and high reference voltage 39 56
VSS_HV_ADC1 ADC_1 ground and low reference voltage 40 57
Power supply pins (3.3 V or 5.0 V). All pins available on 144-pin package.
Five pairs (VDD; VSS) available on 100-pin package.
VDD_HV_IO02Input/Output supply voltage — 6
VSS_HV_IO02Input/Output ground — 7
VDD_HV_IO1 Input/Output supply voltage 13 21
VSS_HV_IO1 Input/Output ground 14 22
VDD_HV_IO2 Input/Output supply voltage 63 91
VSS_HV_IO2 Input/Output ground 62 90
VDD_HV_IO3 Input/Output supply voltage 87 126
VSS_HV_IO3 Input/Output ground 88 127
VDD_HV_FL Code and data flash supply voltage 69 97
VSS_HV_FL Code and data flash supply ground 68 96
VDD_HV_OSC Crystal oscillator amplifier supply voltage 16 27
VSS_HV_OSC Crystal oscillator amplifier ground 17 28
Power supply pins (1.2 V). All pins available on 100-pin and 144-pin package.
VDD_LV_COR0 1.2 V Decoupling pins for core logic. Decoupling capacitor
must be connected between these pins and the nearest
VSS_LV_COR pin.
12 18
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 23
2.2.2 System pins
Table 3 and Table 4 contain information on pin functions for the MPC5604P devices. The pins listed in Table 4 are
single-function pins. The pins shown in Table 5 are multi-function pins, programmable via their respective Pad Configuration
Register (PCR) values.
VSS_LV_COR0 1.2 V Decoupling pins for core logic. Decoupling capacitor
must be connected between these pins and the nearest
VDD_LV_COR pin.
11 17
VDD_LV_COR1 1.2 V Decoupling pins for core logic. Decoupling capacitor
must be connected between these pins and the nearest
VSS_LV_COR pin.
65 93
VSS_LV_COR1 1.2 V Decoupling pins for core logic. Decoupling capacitor
must be connected between these pins and the nearest
VDD_LV_COR pin.
66 94
VDD_LV_COR2 1.2 V Decoupling pins for core logic. Decoupling capacitor
must be connected between these pins and the nearest
VSS_LV_COR pin.
92 131
VSS_LV_COR2 1.2 V Decoupling pins for core logic. Decoupling capacitor
must be connected between these pins and the nearest
VDD_LV_COR pin.
93 132
VDD_LV_COR3 1.2 V Decoupling pins for on-chip PLL modules. Decoupling
capacitor must be connected between this pin and
VSS_LV_COR3.
25 36
VSS_LV_COR3 1.2 V Decoupling pins for on-chip PLL modules. Decoupling
capacitor must be connected between this pin and
VDD_LV_COR3.
24 35
1Analog supply/ground and high/low reference lines are internally physically separate, but are shorted via a
double-bonding connection on VDD_HV_ADCx/VSS_HV_ADCx pins.
2Not available on 100-pin package.
Table 4. System pins
Symbol Description Direction
Pad speed1Pin
SRC = 0 SRC = 1 100-pin 144-pin
Dedicated pins. Available on 100-pin and 144-pin package.
MDO[0] Nexus Message Data Output—line 0 Output only Fast — 9
NMI Non-Maskable Interrupt Input only Slow — 1 1
XTAL Analog output of the oscillator amplifier
circuit; needs to be grounded if oscillator
is used in bypass mode
———1829
Table 3. Supply pins (continued)
Supply Pin
Symbol Description 100-pin 144-pin
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale24
2.2.3 Pin muxing
Table 5 defines the pin list and muxing for the MPC5604P devices.
Each row of Table 5 shows all the possible ways of configuring each pin, via alternate functions. The default function assigned
to each pin after reset is the ALT0 function.
MPC5604P devices provide four main I/O pad types, depending on the associated functions:
•Slow pads are the most common, providing a compromise between transition time and low electromagnetic emission.
•Medium pads provide fast enough transition for serial communication channels with controlled current to reduce
electromagnetic emission.
•Fast pads provide maximum speed. They are used for improved NEXUS debugging capability.
•Symmetric pads are designed to meet FlexRay requirements.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.
For more information, see the data sheet’s “Pad AC Specifications” section.
EXTAL • Analog input of oscillator amplifier
circuit, when oscillator not in bypass
mode
• Analog input for clock generator when
oscillator in bypass mode
———1930
TMS JTAG state machine control Bidirectional Slow Fast 59 87
TCK JTAG clock Input only Slow — 60 88
TDI Test Data In Input only Slow Medium 58 86
TDO Test Data Out Output only Slow Fast 61 89
Reset pin, available on 100-pin and 144-pin package.
RESET Bidirectional reset with Schmitt trigger
characteristics and noise filter
Bidirectional Medium — 20 31
Test pin, available on 100-pin and 144-pin package.
VPP_TEST Pin for testing purpose only. To be tied to
ground in normal operating mode.
———74107
1SCR values refer to the value assigned to the Slew Rate Control bits of the pad configuration register.
Table 4. System pins (continued)
Symbol Description Direction
Pad speed1Pin
SRC = 0 SRC = 1 100-pin 144-pin
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 25
Table 5. Pin muxing
Port
pin
Pad
configuration
register (PCR)
Alternate
function1,2 Functions Peripheral3I/O
direction4
Pad speed5Pin No.
SRC = 0 SRC = 1
100-pin
144-pin
Port A (16-bit)
A[0] PCR[0] ALT0
ALT1
ALT2
ALT3
—
GPIO[0]
ETC[0]
SCK
F[0]
EIRQ[0]
SIUL
eTimer_0
DSPI_2
FCU_0
SIUL
I/O
I/O
O
O
I
Slow Medium 51 73
A[1] PCR[1] ALT0
ALT1
ALT2
ALT3
—
GPIO[1]
ETC[1]
SOUT
F[1]
EIRQ[1]
SIUL
eTimer_0
DSPI_2
FCU_0
SIUL
I/O
I/O
O
O
I
Slow Medium 52 74
A[2]6PCR[2] ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[2]
ETC[2]
—
A[3]
SIN
ABS[0]
EIRQ[2]
SIUL
eTimer_0
—
FlexPWM_0
DSPI_2
MC_RGM
SIUL
I/O
I/O
—
O
I
I
I
Slow Medium 57 84
A[3]6PCR[3] ALT0
ALT1
ALT2
ALT3
—
—
GPIO[3]
ETC[3]
CS0
B[3]
ABS[2]
EIRQ[3]
SIUL
eTimer_0
DSPI_2
FlexPWM_0
MC_RGM
SIUL
I/O
I/O
I/O
O
I
I
Slow Medium 64 92
A[4]6PCR[4] ALT0
ALT1
ALT2
ALT3
—
—
GPIO[4]
ETC[0]
CS1
ETC[4]
FAB
EIRQ[4]
SIUL
eTimer_1
DSPI_2
eTimer_0
MC_RGM
SIUL
I/O
I/O
O
I/O
I
I
Slow Medium 75 108
A[5] PCR[5] ALT0
ALT1
ALT2
ALT3
—
GPIO[5]
CS0
ETC[5]
CS7
EIRQ[5]
SIUL
DSPI_1
eTimer_1
DSPI_0
SIUL
I/O
I/O
I/O
O
I
Slow Medium 8 14
A[6] PCR[6] ALT0
ALT1
ALT2
ALT3
—
GPIO[6]
SCK
—
—
EIRQ[6]
SIUL
DSPI_1
—
—
SIUL
I/O
I/O
—
—
I
Slow Medium 2 2
A[7] PCR[7] ALT0
ALT1
ALT2
ALT3
—
GPIO[7]
SOUT
—
—
EIRQ[7]
SIUL
DSPI_1
—
—
SIUL
I/O
O
—
—
I
Slow Medium 4 10
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale26
A[8] PCR[8] ALT0
ALT1
ALT2
ALT3
—
—
GPIO[8]
—
—
—
SIN
EIRQ[8]
SIUL
—
—
—
DSPI_1
SIUL
I/O
—
—
—
I
I
Slow Medium 6 12
A[9] PCR[9] ALT0
ALT1
ALT2
ALT3
—
GPIO[9]
CS1
—
B[3]
FAULT[0]
SIUL
DSPI_2
—
FlexPWM_0
FlexPWM_0
I/O
O
—
O
I
Slow Medium 94 134
A[10] PCR[10] ALT0
ALT1
ALT2
ALT3
—
GPIO[10]
CS0
B[0]
X[2]
EIRQ[9]
SIUL
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
I/O
I/O
O
I/O
I
Slow Medium 81 118
A[11] PCR[11] ALT0
ALT1
ALT2
ALT3
—
GPIO[11]
SCK
A[0]
A[2]
EIRQ[10]
SIUL
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
I/O
I/O
O
O
I
Slow Medium 82 120
A[12] PCR[12] ALT0
ALT1
ALT2
ALT3
—
GPIO[12]
SOUT
A[2]
B[2]
EIRQ[11]
SIUL
DSPI_2
FlexPWM_0
FlexPWM_0
SIUL
I/O
O
O
O
I
Slow Medium 83 122
A[13] PCR[13] ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[13]
—
B[2]
—
SIN
FAULT[0]
EIRQ[12]
SIUL
—
FlexPWM_0
—
DSPI_2
FlexPWM_0
SIUL
I/O
—
O
—
I
I
I
Slow Medium 95 136
A[14] PCR[14] ALT0
ALT1
ALT2
ALT3
—
GPIO[14]
TXD
ETC[4]
—
EIRQ[13]
SIUL
Safety Port_0
eTimer_1
—
SIUL
I/O
O
I/O
—
I
Slow Medium 99 143
A[15] PCR[15] ALT0
ALT1
ALT2
ALT3
—
—
GPIO[15]
—
ETC[5]
—
RXD
EIRQ[14]
SIUL
—
eTimer_1
—
Safety Port_0
SIUL
I/O
—
I/O
—
I
I
Slow Medium 100 144
Table 5. Pin muxing (continued)
Port
pin
Pad
configuration
register (PCR)
Alternate
function1,2 Functions Peripheral3I/O
direction4
Pad speed5Pin No.
SRC = 0 SRC = 1
100-pin
144-pin
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 27
Port B (16-bit)
B[0] PCR[16] ALT0
ALT1
ALT2
ALT3
—
GPIO[16]
TXD
ETC[2]
DEBUG[0]
EIRQ[15]
SIUL
FlexCAN_0
eTimer_1
SSCM
SIUL
I/O
O
I/O
—
I
Slow Medium 76 109
B[1] PCR[17] ALT0
ALT1
ALT2
ALT3
—
—
GPIO[17]
—
ETC[3]
DEBUG[1]
RXD
EIRQ[16]
SIUL
—
eTimer_1
SSCM
FlexCAN_0
SIUL
I/O
—
I/O
—
I
I
Slow Medium 77 110
B[2] PCR[18] ALT0
ALT1
ALT2
ALT3
—
GPIO[18]
TXD
—
DEBUG[2]
EIRQ[17]
SIUL
LIN_0
—
SSCM
SIUL
I/O
O
—
—
I
Slow Medium 79 114
B[3] PCR[19] ALT0
ALT1
ALT2
ALT3
—
GPIO[19]
—
—
DEBUG[3]
RXD
SIUL
—
—
SSCM
LIN_0
I/O
—
—
—
I
Slow Medium 80 116
B[6] PCR[22] ALT0
ALT1
ALT2
ALT3
—
GPIO[22]
CLKOUT
CS2
—
EIRQ[18]
SIUL
MC_CGL
DSPI_2
—
SIUL
I/O
O
O
—
I
Slow Medium 96 138
B[7] PCR[23] ALT0
ALT1
ALT2
ALT3
—
—
GPIO[23]
—
—
—
AN[0]
RXD
SIUL
—
—
—
ADC_0
LIN_0
Input only — — 29 43
B[8] PCR[24] ALT0
ALT1
ALT2
ALT3
—
—
GPIO[24]
—
—
—
AN[1]
ETC[5]
SIUL
—
—
—
ADC_0
eTimer_0
Input only — — 31 47
B[9] PCR[25] ALT0
ALT1
ALT2
ALT3
—
GPIO[25]
—
—
—
AN[11]
SIUL
—
—
—
ADC_0 / ADC_1
Input only — — 35 52
Table 5. Pin muxing (continued)
Port
pin
Pad
configuration
register (PCR)
Alternate
function1,2 Functions Peripheral3I/O
direction4
Pad speed5Pin No.
SRC = 0 SRC = 1
100-pin
144-pin
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale28
B[10] PCR[26] ALT0
ALT1
ALT2
ALT3
—
GPIO[26]
—
—
—
AN[12]
SIUL
—
—
—
ADC_0 / ADC_1
Input only — — 36 53
B[11] PCR[27] ALT0
ALT1
ALT2
ALT3
—
GPIO[27]
—
—
—
AN[13]
SIUL
—
—
—
ADC_0 / ADC_1
Input only — — 37 54
B[12] PCR[28] ALT0
ALT1
ALT2
ALT3
—
GPIO[28]
—
—
—
AN[14]
SIUL
—
—
—
ADC_0 / ADC_1
Input only — — 38 55
B[13] PCR[29] ALT0
ALT1
ALT2
ALT3
—
—
GPIO[29]
—
—
—
AN[0]
RXD
SIUL
—
—
—
ADC_1
LIN_1
Input only — — 42 60
B[14] PCR[30] ALT0
ALT1
ALT2
ALT3
—
—
—
GPIO[30]
—
—
—
AN[1]
ETC[4]
EIRQ[19]
SIUL
—
—
—
ADC_1
eTimer_0
SIUL
Input only — — 44 64
B[15] PCR[31] ALT0
ALT1
ALT2
ALT3
—
—
GPIO[31]
—
—
—
AN[2]
EIRQ[20]
SIUL
—
—
—
ADC_1
SIUL
Input only — — 43 62
Port C (16-bit)
C[0] PCR[32] ALT0
ALT1
ALT2
ALT3
—
GPIO[32]
—
—
—
AN[3]
SIUL
—
—
—
ADC_1
Input only — — 45 66
C[1] PCR[33] ALT0
ALT1
ALT2
ALT3
—
GPIO[33]
—
—
—
AN[2]
SIUL
—
—
—
ADC_0
Input only — — 28 41
Table 5. Pin muxing (continued)
Port
pin
Pad
configuration
register (PCR)
Alternate
function1,2 Functions Peripheral3I/O
direction4
Pad speed5Pin No.
SRC = 0 SRC = 1
100-pin
144-pin
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 29
C[2] PCR[34] ALT0
ALT1
ALT2
ALT3
—
GPIO[34]
—
—
—
AN[3]
SIUL
—
—
—
ADC_0
Input only — — 30 45
C[3] PCR[35] ALT0
ALT1
ALT2
ALT3
—
GPIO[35]
CS1
ETC[4]
TXD
EIRQ[21]
SIUL
DSPI_0
eTimer_1
LIN_1
SIUL
I/O
O
I/O
O
I
Slow Medium 10 16
C[4] PCR[36] ALT0
ALT1
ALT2
ALT3
—
GPIO[36]
CS0
X[1]
DEBUG[4]
EIRQ[22]
SIUL
DSPI_0
FlexPWM_0
SSCM
SIUL
I/O
I/O
I/O
—
I
Slow Medium 5 11
C[5] PCR[37] ALT0
ALT1
ALT2
ALT3
—
—
GPIO[37]
SCK
—
DEBUG[5]
FAULT[3]
EIRQ[23]
SIUL
DSPI_0
—
SSCM
FlexPWM_0
SIUL
I/O
I/O
—
—
I
I
Slow Medium 7 13
C[6] PCR[38] ALT0
ALT1
ALT2
ALT3
—
GPIO[38]
SOUT
B[1]
DEBUG[6]
EIRQ[24]
SIUL
DSPI_0
FlexPWM_0
SSCM
SIUL
I/O
I/O
O
—
I
Slow Medium 98 142
C[7] PCR[39] ALT0
ALT1
ALT2
ALT3
—
GPIO[39]
—
A[1]
DEBUG[7]
SIN
SIUL
—
FlexPWM_0
SSCM
DSPI_0
I/O
—
O
—
I
Slow Medium 9 15
C[8] PCR[40] ALT0
ALT1
ALT2
ALT3
—
GPIO[40]
CS1
—
CS6
FAULT[2]
SIUL
DSPI_1
—
DSPI_0
FlexPWM_0
I/O
O
—
O
I
Slow Medium 91 130
C[9] PCR[41] ALT0
ALT1
ALT2
ALT3
—
GPIO[41]
CS3
—
X[3]
FAULT[2]
SIUL
DSPI_2
—
FlexPWM_0
FlexPWM_0
I/O
O
—
I/O
I
Slow Medium 84 123
C[10] PCR[42] ALT0
ALT1
ALT2
ALT3
—
GPIO[42]
CS2
—
A[3]
FAULT[1]
SIUL
DSPI_2
—
FlexPWM_0
FlexPWM_0
I/O
O
—
O
I
Slow Medium 78 111
Table 5. Pin muxing (continued)
Port
pin
Pad
configuration
register (PCR)
Alternate
function1,2 Functions Peripheral3I/O
direction4
Pad speed5Pin No.
SRC = 0 SRC = 1
100-pin
144-pin
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale30
C[11] PCR[43] ALT0
ALT1
ALT2
ALT3
GPIO[43]
ETC[4]
CS2
CS0
SIUL
eTimer_0
DSPI_2
DSPI_3
I/O
I/O
O
I/O
Slow Medium 55 80
C[12] PCR[44] ALT0
ALT1
ALT2
ALT3
GPIO[44]
ETC[5]
CS3
CS1
SIUL
eTimer_0
DSPI_2
DSPI_3
I/O
I/O
O
O
Slow Medium 56 82
C[13] PCR[45] ALT0
ALT1
ALT2
ALT3
—
—
GPIO[45]
ETC[1]
—
—
EXT_IN
EXT_SYNC
SIUL
eTimer_1
—
—
CTU_0
FlexPWM_0
I/O
I/O
—
—
I
I
Slow Medium 71 101
C[14] PCR[46] ALT0
ALT1
ALT2
ALT3
GPIO[46]
ETC[2]
EXT_TGR
—
SIUL
eTimer_1
CTU_0
—
I/O
I/O
O
—
Slow Medium 72 103
C[15] PCR[47] ALT0
ALT1
ALT2
ALT3
—
—
GPIO[47]
CA_TR_EN
ETC[0]
A[1]
EXT_IN
EXT_SYNC
SIUL
FlexRay_0
eTimer_1
FlexPWM_0
CTU_0
FlexPWM_0
I/O
O
I/O
O
I
I
Slow Symmetric 85 124
Port D (16-bit)
D[0] PCR[48] ALT0
ALT1
ALT2
ALT3
GPIO[48]
CA_TX
ETC[1]
B[1]
SIUL
FlexRay_0
eTimer_1
FlexPWM_0
I/O
O
I/O
O
Slow Symmetric 86 125
D[1] PCR[49] ALT0
ALT1
ALT2
ALT3
—
GPIO[49]
—
ETC[2]
EXT_TRG
CA_RX
SIUL
—
eTimer_1
CTU_0
FlexRay_0
I/O
—
I/O
O
I
Slow Medium 3 3
D[2] PCR[50] ALT0
ALT1
ALT2
ALT3
—
GPIO[50]
—
ETC[3]
X[3]
CB_RX
SIUL
—
eTimer_1
FlexPWM_0
FlexRay_0
I/O
—
I/O
I/O
I
Slow Medium 97 140
D[3] PCR[51] ALT0
ALT1
ALT2
ALT3
GPIO[51]
CB_TX
ETC[4]
A[3]
SIUL
FlexRay_0
eTimer_1
FlexPWM_0
I/O
O
I/O
O
Slow Symmetric 89 128
Table 5. Pin muxing (continued)
Port
pin
Pad
configuration
register (PCR)
Alternate
function1,2 Functions Peripheral3I/O
direction4
Pad speed5Pin No.
SRC = 0 SRC = 1
100-pin
144-pin
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 31
D[4] PCR[52] ALT0
ALT1
ALT2
ALT3
GPIO[52]
CB_TR_EN
ETC[5]
B[3]
SIUL
FlexRay_0
eTimer_1
FlexPWM_0
I/O
O
I/O
O
Slow Symmetric 90 129
D[5] PCR[53] ALT0
ALT1
ALT2
ALT3
GPIO[53]
CS3
F[0]
SOUT
SIUL
DSPI_0
FCU_0
DSPI_3
I/O
O
O
O
Slow Medium 22 33
D[6] PCR[54] ALT0
ALT1
ALT2
ALT3
—
GPIO[54]
CS2
SCK
—
FAULT[1]
SIUL
DSPI_0
DSPI_3
—
FlexPWM_0
I/O
O
I/O
—
I
Slow Medium 23 34
D[7] PCR[55] ALT0
ALT1
ALT2
ALT3
—
GPIO[55]
CS3
F[1]
CS4
SIN
SIUL
DSPI_1
FCU_0
DSPI_0
DSPI_3
I/O
O
O
O
I
Slow Medium 26 37
D[8] PCR[56] ALT0
ALT1
ALT2
ALT3
—
GPIO[56]
CS2
—
CS5
FAULT[3]
SIUL
DSPI_1
—
DSPI_0
FlexPWM_0
I/O
O
—
O
I
Slow Medium 21 32
D[9] PCR[57] ALT0
ALT1
ALT2
ALT3
GPIO[57]
X[0]
TXD
—
SIUL
FlexPWM_0
LIN_1
—
I/O
I/O
O
—
Slow Medium 15 26
D[10] PCR[58] ALT0
ALT1
ALT2
ALT3
GPIO[58]
A[0]
CS0
—
SIUL
FlexPWM_0
DSPI_3
—
I/O
O
I/O
—
Slow Medium 53 76
D[11] PCR[59] ALT0
ALT1
ALT2
ALT3
GPIO[59]
B[0]
CS1
SCK
SIUL
FlexPWM_0
DSPI_3
DSPI_3
I/O
O
O
I/O
Slow Medium 54 78
D[12] PCR[60] ALT0
ALT1
ALT2
ALT3
—
GPIO[60]
X[1]
—
—
RXD
SIUL
FlexPWM_0
—
—
LIN_1
I/O
I/O
—
—
I
Slow Medium 70 99
D[13] PCR[61] ALT0
ALT1
ALT2
ALT3
GPIO[61]
A[1]
CS2
SOUT
SIUL
FlexPWM_0
DSPI_3
DSPI_3
I/O
O
O
O
Slow Medium 67 95
Table 5. Pin muxing (continued)
Port
pin
Pad
configuration
register (PCR)
Alternate
function1,2 Functions Peripheral3I/O
direction4
Pad speed5Pin No.
SRC = 0 SRC = 1
100-pin
144-pin
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale32
D[14] PCR[62] ALT0
ALT1
ALT2
ALT3
—
GPIO[62]
B[1]
CS3
—
SIN
SIUL
FlexPWM_0
DSPI_3
—
DSPI_3
I/O
O
O
—
I
Slow Medium 73 105
D[15] PCR[63] ALT0
ALT1
ALT2
ALT3
—
GPIO[63]
—
—
—
AN[4]
SIUL
—
—
—
ADC_1
Input only — — 41 58
Port E(16-bit)
E[0] PCR[64] ALT0
ALT1
ALT2
ALT3
—
GPIO[64]
—
—
—
AN[5]
SIUL
—
—
—
ADC_1
Input only — — 46 68
E[1] PCR[65] ALT0
ALT1
ALT2
ALT3
—
GPIO[65]
—
—
—
AN[4]
SIUL
—
—
—
ADC_0
Input only — — 27 39
E[2] PCR[66] ALT0
ALT1
ALT2
ALT3
—
GPIO[66]
—
—
—
AN[5]
SIUL
—
—
—
ADC_0
Input only — — 32 49
E[3] PCR[67] ALT0
ALT1
ALT2
ALT3
—
GPIO[67]
—
—
—
AN[6]
SIUL
—
—
—
ADC_0
Input only — — — 40
E[4] PCR[68] ALT0
ALT1
ALT2
ALT3
—
GPIO[68]
—
—
—
AN[7]
SIUL
—
—
—
ADC_0
Input only — — — 42
E[5] PCR[69] ALT0
ALT1
ALT2
ALT3
—
GPIO[69]
—
—
—
AN[8]
SIUL
—
—
—
ADC_0
Input only — — — 44
Table 5. Pin muxing (continued)
Port
pin
Pad
configuration
register (PCR)
Alternate
function1,2 Functions Peripheral3I/O
direction4
Pad speed5Pin No.
SRC = 0 SRC = 1
100-pin
144-pin
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 33
E[6] PCR[70] ALT0
ALT1
ALT2
ALT3
—
GPIO[70]
—
—
—
AN[9]
SIUL
—
—
—
ADC_0
Input only — — — 46
E[7] PCR[71] ALT0
ALT1
ALT2
ALT3
—
GPIO[71]
—
—
—
AN[10]
SIUL
—
—
—
ADC_0
Input only — — — 48
E[8] PCR[72] ALT0
ALT1
ALT2
ALT3
—
GPIO[72]
—
—
—
AN[6]
SIUL
—
—
—
ADC_1
Input only — — — 59
E[9] PCR[73] ALT0
ALT1
ALT2
ALT3
—
GPIO[73]
—
—
—
AN[7]
SIUL
—
—
—
ADC_1
Input only — — — 61
E[10] PCR[74] ALT0
ALT1
ALT2
ALT3
—
GPIO[74]
—
—
—
AN[8]
SIUL
—
—
—
ADC_1
Input only — — — 63
E[11] PCR[75] ALT0
ALT1
ALT2
ALT3
—
GPIO[75]
—
—
—
AN[9]
SIUL
—
—
—
ADC_1
Input only — — — 65
E[12] PCR[76] ALT0
ALT1
ALT2
ALT3
—
GPIO[76]
—
—
—
AN[10]
SIUL
—
—
—
ADC_1
Input only — — — 67
E[13] PCR[77] ALT0
ALT1
ALT2
ALT3
—
GPIO[77]
SCK
—
—
EIRQ[25]
SIUL
DSPI_3
—
—
SIUL
I/O
I/O
—
—
I
Slow Medium — 117
E[14] PCR[78] ALT0
ALT1
ALT2
ALT3
—
GPIO[78]
SOUT
—
—
EIRQ[26]
SIUL
DSPI_3
—
—
SIUL
I/O
O
—
—
I
Slow Medium — 119
Table 5. Pin muxing (continued)
Port
pin
Pad
configuration
register (PCR)
Alternate
function1,2 Functions Peripheral3I/O
direction4
Pad speed5Pin No.
SRC = 0 SRC = 1
100-pin
144-pin
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale34
E[15] PCR[79] ALT0
ALT1
ALT2
ALT3
—
—
GPIO[79]
—
—
—
SIN
EIRQ[27]
SIUL
—
—
—
DSPI_3
SIUL
I/O
—
—
—
I
I
Slow Medium — 121
Port F (16-bit)
F[0] PCR[80] ALT0
ALT1
ALT2
ALT3
—
GPIO[80]
DBG0
CS3
—
EIRQ[28]
SIUL
FlexRay_0
DSPI_3
—
SIUL
I/O
O
O
—
I
Slow Medium — 133
F[1] PCR[81] ALT0
ALT1
ALT2
ALT3
—
GPIO[81]
DBG1
CS2
—
EIRQ[29]
SIUL
FlexRay_0
DSPI_3
—
SIUL
I/O
O
O
—
I
Slow Medium — 135
F[2] PCR[82] ALT0
ALT1
ALT2
ALT3
GPIO[82]
DBG2
CS1
—
SIUL
FlexRay_0
DSPI_3
—
I/O
O
O
—
Slow Medium — 137
F[3] PCR[83] ALT0
ALT1
ALT2
ALT3
GPIO[83]
DBG3
CS0
—
SIUL
FlexRay_0
DSPI_3
—
I/O
O
I/O
—
Slow Medium — 139
F[4] PCR[84] ALT0
ALT1
ALT2
ALT3
GPIO[84]
MDO[3]
—
—
SIUL
NEXUS_0
—
—
I/O
O
—
—
Slow Fast — 4
F[5] PCR[85] ALT0
ALT1
ALT2
ALT3
GPIO[85]
MDO[2]
—
—
SIUL
NEXUS_0
—
—
I/O
O
—
—
Slow Fast — 5
F[6] PCR[86] ALT0
ALT1
ALT2
ALT3
GPIO[86]
MDO[1]
—
—
SIUL
NEXUS_0
—
—
I/O
O
—
—
Slow Fast — 8
F[7] PCR[87] ALT0
ALT1
ALT2
ALT3
GPIO[87]
MCKO
—
—
SIUL
NEXUS_0
—
—
I/O
O
—
—
Slow Fast — 19
F[8] PCR[88] ALT0
ALT1
ALT2
ALT3
GPIO[88]
MSEO1
—
—
SIUL
NEXUS_0
—
—
I/O
O
—
—
Slow Fast — 20
Table 5. Pin muxing (continued)
Port
pin
Pad
configuration
register (PCR)
Alternate
function1,2 Functions Peripheral3I/O
direction4
Pad speed5Pin No.
SRC = 0 SRC = 1
100-pin
144-pin
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 35
F[9] PCR[89] ALT0
ALT1
ALT2
ALT3
GPIO[89]
MSEO0
—
—
SIUL
NEXUS_0
—
—
I/O
O
—
—
Slow Fast — 23
F[10] PCR[90] ALT0
ALT1
ALT2
ALT3
GPIO[90]
EVTO
—
—
SIUL
NEXUS_0
—
—
I/O
O
—
—
Slow Fast — 24
F[11] PCR[91] ALT0
ALT1
ALT2
ALT3
—
GPIO[91]
—
—
—
EVTI
SIUL
—
—
—
NEXUS_0
I/O
—
—
—
I
Slow Medium — 25
F[12] PCR[92] ALT0
ALT1
ALT2
ALT3
GPIO[92]
ETC[3]
—
—
SIUL
eTimer_1
—
—
I/O
I/O
—
—
Slow Medium — 106
F[13] PCR[93] ALT0
ALT1
ALT2
ALT3
GPIO[92]
ETC[4]
—
—
SIUL
eTimer_1
—
—
I/O
I/O
—
—
Slow Medium — 112
F[14] PCR[94] ALT0
ALT1
ALT2
ALT3
GPIO[94]
TXD
—
—
SIUL
LIN_1
—
—
I/O
O
—
—
Slow Medium — 115
F[15] PCR[95] ALT0
ALT1
ALT2
ALT3
—
GPIO[95]
—
—
—
RXD
SIUL
—
—
—
LIN_1
I/O
—
—
—
I
Slow Medium — 113
Port G (12-bit)
G[0] PCR[96] ALT0
ALT1
ALT2
ALT3
—
GPIO[96]
F[0]
—
—
EIRQ[30]
SIUL
FCU_0
—
—
SIUL
I/O
O
—
—
I
Slow Medium — 38
G[1] PCR[97] ALT0
ALT1
ALT2
ALT3
—
GPIO[97]
F[1]
—
—
EIRQ[31]
SIUL
FCU_0
—
—
SIUL
I/O
O
—
—
I
Slow Medium — 141
G[2] PCR[98] ALT0
ALT1
ALT2
ALT3
GPIO[98]
X[2]
—
—
SIUL
FlexPWM_0
—
—
I/O
I/O
—
—
Slow Medium — 102
Table 5. Pin muxing (continued)
Port
pin
Pad
configuration
register (PCR)
Alternate
function1,2 Functions Peripheral3I/O
direction4
Pad speed5Pin No.
SRC = 0 SRC = 1
100-pin
144-pin
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale36
G[3] PCR[99] ALT0
ALT1
ALT2
ALT3
GPIO[99]
A[2]
—
—
SIUL
FlexPWM_0
—
—
I/O
O
—
—
Slow Medium — 104
G[4] PCR[100] ALT0
ALT1
ALT2
ALT3
GPIO[100]
B[2]
—
—
SIUL
FlexPWM_0
—
—
I/O
O
—
—
Slow Medium — 100
G[5] PCR[101] ALT0
ALT1
ALT2
ALT3
GPIO[101]
X[3]
—
—
SIUL
FlexPWM_0
—
—
I/O
I/O
—
—
Slow Medium — 85
G[6] PCR[102] ALT0
ALT1
ALT2
ALT3
GPIO[102]
A[3]
—
—
SIUL
FlexPWM_0
—
—
I/O
O
—
—
Slow Medium — 98
G[7] PCR[103] ALT0
ALT1
ALT2
ALT3
GPIO[103]
B[3]
—
—
SIUL
FlexPWM_0
—
—
I/O
O
—
—
Slow Medium — 83
G[8] PCR[104] ALT0
ALT1
ALT2
ALT3
—
GPIO[104]
—
—
—
FAULT[0]
SIUL
—
—
—
FlexPWM_0
I/O
—
—
—
I
Slow Medium — 81
G[9] PCR[105] ALT0
ALT1
ALT2
ALT3
—
GPIO[105]
—
—
—
FAULT[1]
SIUL
—
—
—
FlexPWM_0
I/O
—
—
—
I
Slow Medium — 79
G[10] PCR[106] ALT0
ALT1
ALT2
ALT3
—
GPIO[106]
—
—
—
FAULT[2]
SIUL
—
—
—
FlexPWM_0
I/O
—
—
—
I
Slow Medium — 77
G[11] PCR[107] ALT0
ALT1
ALT2
ALT3
—
GPIO[107]
—
—
—
FAULT[3]
SIUL
—
—
—
FlexPWM_0
I/O
—
—
—
I
Slow Medium — 75
1ALT0 is the primary (default) function for each port after reset.
Table 5. Pin muxing (continued)
Port
pin
Pad
configuration
register (PCR)
Alternate
function1,2 Functions Peripheral3I/O
direction4
Pad speed5Pin No.
SRC = 0 SRC = 1
100-pin
144-pin
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 37
2Alternate functions are chosen by setting the values of the PCR[PA] bitfields inside the SIU module.
PCR[PA] = 00 ALT0; PCR[PA] = 01 ALT1; PCR[PA] = 10 ALT2; PCR[PA] = 11 ALT3. This is intended to
select the output functions; to use one of the input-only functions, the PCR[IBE] bit must be written to ‘1’, regardless
of the values selected in the PCR[PA] bitfields. For this reason, the value corresponding to an input only function is
reported as “—”.
3Module included on the MCU.
4Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by
setting the values of the PSMI[PADSELx] bitfields inside the SIUL module.
5Programmable via the SRC (Slew Rate Control) bits in the respective Pad Configuration Register.
6Weak pull down during reset.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale38
3 Electrical characteristics
3.1 Introduction
This section contains device electrical characteristics as well as temperature and power considerations.
This microcontroller contains input protection against damage due to high static voltages. However, it is advisable to take
precautions to avoid application of any voltage higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This can be done by the
internal pull-up or pull-down resistors, which are provided by the device for most general purpose pins.
The following tables provide the device characteristics and its demands on the system.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller
Characteristics is included in the Symbol column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” for System Requirement is included in the Symbol column.
CAUTION
All of the following parameter values can vary depending on the application and must be
confirmed during silicon characterization or silicon reliability trial.
3.2 Parameter classification
The electrical parameters are guaranteed by various methods. To give the customer a better understanding, the classifications
listed in Table 6 are used and the parameters are tagged accordingly in the tables where appropriate.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
Table 6. Parameter classifications
Classification tag Tag description
P Those parameters are guaranteed during production testing on each individual device.
C Those parameters are achieved by the design characterization by measuring a statistically
relevant sample size across process variations.
T Those parameters are achieved by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D Those parameters are derived mainly from simulations.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 39
3.3 Absolute maximum ratings
Table 7. Absolute maximum ratings1
Symbol Parameter Conditions
Value
Unit
Min Max2
VSS SR Device ground — 0 0 V
VDD_HV_IOx3SR 3.3 V / 5.0 V input/output supply
voltage with respect to ground (VSS)
—–0.3 6.0V
VSS_HV_IOx SR Input/output ground voltage with
respect to ground (VSS)
—–0.1 0.1V
VDD_HV_FL SR 3.3 V / 5.0 V code and data flash
supply voltage with respect to ground
(VSS)
—–0.3 6.0V
Relative to
VDD_HV_IOx
VDD_HV_IOx + 0.3
VSS_HV_FL SR Code and data flash ground with
respect to ground (VSS)
—–0.1 0.1V
VDD_HV_OSC SR 3.3 V / 5.0 V crystal oscillator
amplifier supply voltage with respect
to ground (VSS)
—–0.3 6.0V
Relative to
VDD_HV_IOx
VDD_HV_IOx + 0.3
VSS_HV_OSC SR 3.3 V / 5.0 V crystal oscillator
amplifier reference voltage with
respect to ground (VSS)
—–0.1 0.1V
VDD_HV_REG SR 3.3 V / 5.0 V voltage regulator supply
voltage with respect to ground (VSS)
—–0.3 6.0V
Relative to
VDD_HV_IOx
VDD_HV_IOx + 0.3
VDD_HV_ADC04SR 3.3 V / 5.0 V ADC_0 supply and high
reference voltage with respect to
ground (VSS)
VDD_HV_REG <
2.7 V
–0.3 VDD_HV_REG +
0.3
V
VDD_HV_REG >
2.7 V
6.0
VSS_HV_ADC0 SR ADC_0 ground and low reference
voltage with respect to ground (VSS)
—–0.1 0.1V
VDD_HV_ADC14SR 3.3 V / 5.0 V ADC_0 supply and high
reference voltage with respect to
ground (VSS)
VDD_HV_REG <
2.7 V
–0.3 VDD_HV_REG +
0.3
V
VDD_HV_REG >
2.7 V
6.0
VSS_HV_ADC1 SR ADC_1 ground and low reference
voltage with respect to ground (VSS)
—–0.1 0.1V
TVDD SR Slope characteristics on all VDD
during power up5 with respect to
ground (VSS)
— 3.0 500 x 103
(0.5 [V/µs])
V/s
VIN SR Voltage on any pin with respect to
ground (VSS_HV_IOx) with respect to
ground (VSS)
—–0.3 6.0V
Relative to
VDD_HV_IOx
VDD_HV_IOx +0.
3
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale40
Figure 4 shows the constraints of the different power supplies.
VINAN0 SR ADC0 and shared ADC0/1 analog
input voltage6
VDD_HV_REG >
2.7 V
VSS_HV_ADV0
0.3
VDD_HV_ADV0 +
0.3 V
VDD_HV_REG <
2.7 V VSS_HV_ADV0 VDD_HV_ADV0 V
VINAN1 SR ADC1 analog input voltage7
VDD_HV_REG >
2.7 V
VSS_HV_ADV1
0.3
VDD_HV_ADV1 +
0.3 V
VDD_HV_REG <
2.7 V VSS_HV_ADV1 VDD_HV_ADV1 V
IINJPAD SR Injected input current on any pin
during overload condition
— –10 10 mA
IINJSUM SR Absolute sum of all injected input
currents during overload condition
— –50 50 mA
IVDD_LV SR Low voltage static current sink
through VDD_LV
—— 155mA
TSTG SR Storage temperature — –55 150 °C
TJSR Junction temperature under bias — –40 150 °C
1Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
2Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device
stress have not yet been determined.
3The difference between each couple of voltage supplies must be less than 300 mV,
|VDD_HV_IOy – VDD_HV_IOx | < 300 mV.
4The difference between ADC voltage supplies must be less than 100 mV, |VDD_HV_ADC1 – VDD_HV_ADC0| < 100 mV.
5Guaranteed by device validation
6Not allowed to refer this voltage to VDD_HV_ADV1, VSS_HV_ADV1
7Not allowed to refer this voltage to VDD_HV_ADV0, VSS_HV_ADV0
Table 7. Absolute maximum ratings1 (continued)
Symbol Parameter Conditions
Value
Unit
Min Max2
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 41
Figure 4. Power supplies constraints (–0.3 V VDD_HV_IOx 6.0 V)
The MPC5604P supply architecture allows of having ADC supply managed independently from standard VDD_HV supply.
Figure 5 shows the constraints of the ADC power supply.
Figure 5. Independent ADC supply (–0.3 V VDD_HV_REG 6.0 V)
VDD_HV_xxx
VDD_HV_IOx
–0.3 V
6.0 V
–0.3 V 6.0 V
VDD_HV_ADCx
6.0 V
VDD_HV_REG
–0.3 V
2.7 V
–0.3 V 6.0 V
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale42
3.4 Recommended operating conditions
Table 8. Recommended operating conditions (5.0 V)
Symbol Parameter Conditions
Value
Unit
Min Max1
1Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full
functionality. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.
VSS SR Device ground — 0 0 V
VDD_HV_IOx2
2The difference between each couple of voltage supplies must be less than 100 mV, |VDD_HV_IOy – VDD_HV_IOx | <
100 mV.
SR 5.0 V input/output supply
voltage
—4.5 5.5V
VSS_HV_IOx SR Input/output ground voltage — 0 0 V
VDD_HV_FL SR 5.0 V code and data flash
supply voltage
—4.5 5.5V
Relative to
VDD_HV_IOx
VDD_HV_IOx – 0.1 VDD_HV_IOx +0.1
VSS_HV_FL SR Code and data flash ground — 0 0 V
VDD_HV_OSC SR 5.0 V crystal oscillator amplifier
supply voltage
—4.5 5.5V
Relative to
VDD_HV_IOx
VDD_HV_IOx – 0.1 VDD_HV_IOx +0.1
VSS_HV_OSC SR 5.0 V crystal oscillator amplifier
reference voltage
—0 0V
VDD_HV_REG SR 5.0 V voltage regulator supply
voltage
—4.5 5.5V
Relative to
VDD_HV_IOx
VDD_HV_IOx – 0.1 VDD_HV_IOx +0.1
VDD_HV_ADC03
3The difference between ADC voltage supplies must be less than 100 mV, |VDD_HV_ADC1 VDD_HV_ADC0| < 100 mV.
SR 5.0 V ADC_0 supply and high
reference voltage
—4.5 5.5V
Relative to
VDD_HV_REG
VDD_HV_REG – 0.1 —
VSS_HV_ADC0 SR ADC_0 ground and low
reference voltage
—0 0V
VDD_HV_ADC13SR 5.0 V ADC_1 supply and high
reference voltage
—4.5 5.5V
Relative to
VDD_HV_REG
VDD_HV_REG – 0.1 —
VSS_HV_ADC1 SR ADC_1 ground and low
reference voltage
—0 0V
VDD_LV_REGCOR4,5 CC Internal supply voltage — — — V
VSS_LV_REGCOR4SR Internal reference voltage — 0 0 V
VDD_LV_CORx4,5 CC Internal supply voltage — — — V
VSS_LV_CORx4SR Internal reference voltage — 0 0 V
TASR Ambient temperature under
bias
— –40 125 °C
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 43
4To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced
by an on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must
be shorted to high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected
to the external ballast emitter.
5The low voltage supplies (VDD_LV_xxx) are not all independent.
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the
low voltage supply to the data flash module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
VDD_LV_REGCOR and VDD_LV_REGCORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Table 9. Recommended operating conditions (3.3 V)
Symbol Parameter Conditions
Value
Unit
Min Max1
VSS SR Device ground — 0 0 V
VDD_HV_IOx2SR 3.3 V input/output supply
voltage
—3.0 3.6V
VSS_HV_IOx SR Input/output ground voltage — 0 0 V
VDD_HV_FL SR 3.3 V code and data flash
supply voltage
—3.0 3.6V
Relative to
VDD_HV_IOx
VDD_HV_IOx – 0.1 VDD_HV_IOx +0.1
VSS_HV_FL SR Code and data flash ground — 0 0 V
VDD_HV_OSC SR 3.3 V crystal oscillator amplifier
supply voltage
—3.0 3.6V
Relative to
VDD_HV_IOx
VDD_HV_IOx – 0.1 VDD_HV_IOx +0.1
VSS_HV_OSC SR 3.3 V crystal oscillator amplifier
reference voltage
—0 0V
VDD_HV_REG SR 3.3 V voltage regulator supply
voltage
—3.0 3.6V
Relative to
VDD_HV_IOx
VDD_HV_IOx – 0.1 VDD_HV_IOx +0.1
VDD_HV_ADC03SR 3.3 V ADC_0 supply and high
reference voltage
—3.0 5.5V
Relative to
VDD_HV_REG
VDD_HV_REG – 0.1 5.5
VSS_HV_ADC0 SR ADC_0 ground and low
reference voltage
—0 0V
VDD_HV_ADC13SR 3.3 V ADC_1 supply and high
reference voltage
—3.0 5.5V
Relative to
VDD_HV_REG
VDD_HV_REG – 0.1 5.5
VSS_HV_ADC1 SR ADC_1 ground and low
reference voltage
—0 0V
VDD_LV_REGCOR4,5 CC Internal supply voltage — — — V
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale44
VSS_LV_REGCOR4SR Internal reference voltage — 0 0 V
VDD_LV_CORx4,5 CC Internal supply voltage — — — V
VSS_LV_CORx4SR Internal reference voltage — 0 0 V
TASR Ambient temperature under
bias
— –40 125 °C
1Parametric figures can be out of specification when voltage drops below 4.5 V, however, guaranteeing the full
functionality. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed.
2The difference between each couple of voltage supplies must be less than 100 mV, |VDD_HV_IOy – VDD_HV_IOx | <
100 mV.
3The difference between each couple of voltage supplies must be less than 100 mV, |VDD_HV_ADC1 – VDD_HV_ADC0|
< 100 mV. As long as that condition is met, ADC_0 and ADC_1 can be operated at 5 V with the rest of the device
operating at 3.3 V.
4To be connected to emitter of external NPN. Low voltage supplies are not under user control—they are produced
by an on-chip voltage regulator—but for the device to function properly the low voltage grounds (VSS_LV_xxx) must
be shorted to high voltage grounds (VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected
to the external ballast emitter.
5The low voltage supplies (VDD_LV_xxx) are not all independent.
VDD_LV_COR1 and VDD_LV_COR2 are shorted internally via double bonding connections with lines that provide the
low voltage supply to the data flash module. Similarly, VSS_LV_COR1 and VSS_LV_COR2 are internally shorted.
VDD_LV_REGCOR and VDD_LV_REGCORx are physically shorted internally, as are VSS_LV_REGCOR and VSS_LV_CORx.
Table 9. Recommended operating conditions (3.3 V) (continued)
Symbol Parameter Conditions
Value
Unit
Min Max1
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 45
Figure 6 shows the constraints of the different power supplies.
Figure 6. Power supplies constraints (3.0 V VDD_HV_IOx 5.5 V)
The MPC5604P supply architecture allows the ADC supply to be managed independently from the standard VDD_HV supply.
Figure 7 shows the constraints of the ADC power supply.
Figure 7. Independent ADC supply (3.0 V VDD_HV_REG 5.5 V)
VDD_HV_xxx
VDD_HV_IOx
3.0 V
5.5 V
3.0 V 5.5 V
3.3 V
3.3 V
Note: IO AC and DC characteristics are guaranteed only in the range of 3.0–3.6 V when
PAD3V5V is low, and in the range of 4.5–5.5 V when PAD3V5V is high.
5.5 V
3.0 V
VDD_HV_REG
3.0 V 5.5 V
VDD_HV_ADCx
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale46
3.5 Thermal characteristics
3.5.1 Package thermal characteristics
Table 10. Thermal characteristics for 144-pin LQFP
Symbol Parameter Conditions Typical value Unit
RJA Thermal resistance junction-to-ambient,
natural convection1
1Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board
meets JEDEC specification for this package.
Single layer board—1s 54.2 °C/W
Four layer board—2s2p 44.4 °C/W
RJB Thermal resistance junction-to-board2
2Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets
JEDEC specification for the specified package.
Four layer board—2s2p 29.9 °C/W
RJCtop Thermal resistance junction-to-case (top)3
3Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold
plate temperature is used for the case temperature. Reported value includes the thermal resistance
of the interface layer.
Single layer board—1s 9.3 °C/W
JB Junction-to-board, natural convection4
4Thermal characterization parameter indicating the temperature difference between the board and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JB.
Operating conditions 30.2 °C/W
JC Junction-to-case, natural convection5
5Thermal characterization parameter indicating the temperature difference between the case and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JC.
Operating conditions 0.8 °C/W
Table 11. Thermal characteristics for 100-pin LQFP
Symbol Parameter Conditions Typical value Unit
RJA Thermal resistance junction-to-ambient,
natural convection1
1Junction-to-ambient thermal resistance determined per JEDEC JESD51-7. Thermal test board
meets JEDEC specification for this package.
Single layer board—1s 47.3 °C/W
Four layer board—2s2p 35.3 °C/W
RJB Thermal resistance junction-to-board2
2Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets
JEDEC specification for the specified package.
Four layer board—2s2p 19.1 °C/W
RJCtop Thermal resistance junction-to-case (top)3
3Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold
plate temperature is used for the case temperature. Reported value includes the thermal resistance
of the interface layer.
Single layer board—1s 9.7 °C/W
JB Junction-to-board, natural convection4
4Thermal characterization parameter indicating the temperature difference between the board and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JB.
Operating conditions 19.1 °C/W
JC Junction-to-case, natural convection5Operating conditions 0.8 °C/W
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 47
3.5.2 General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
TJ = TA + (RJA * PD)Eqn. 1
where:
TA= ambient temperature for the package (°C)
RJA = junction to ambient thermal resistance (°C/W)
PD= power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal
performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value
obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which
value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a
single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a junction to case thermal resistance
and a case to ambient thermal resistance:
RJA = RJC + RCA Eqn. 2
where:
RJA = junction to ambient thermal resistance (°C/W)
RJC = junction to case thermal resistance (°C/W)
RCA = case to ambient thermal resistance (°C/W)
RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to
ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the
interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit
board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal
Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at
the top center of the package case using Equation 3:
TJ = TT + (JT x PD)Eqn. 3
where:
TT= thermocouple temperature on top of the package (°C)
JT = thermal characterization parameter (°C/W)
PD= power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied
to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the
junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects
of the thermocouple wire.
References:
5Thermal characterization parameter indicating the temperature difference between the case and the
junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal
characterization parameter is written as Psi-JC.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale48
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134 U.S.A.
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at
800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
1. C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller
Module, Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.
2. G. Kromann, S. Shidore, and S. Addison, Thermal Modeling of a PBGA for Air-Cooled Applications, Electronic
Packaging and Production, pp. 53–58, March 1998.
3. B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in
Thermal Modeling, Proceedings of SemiTherm, San Diego, 1999, pp. 212–220.
3.6 Electromagnetic interference (EMI) characteristics
3.7 Electrostatic discharge (ESD) characteristics
Table 12. EMI testing specifications
Symbol Parameter Conditions Clocks Frequency Level
(Max) Unit
VEME Radiated emissions Device configuration, test
conditions and EM testing per
standard IEC61967-2
Supply voltage = 5 V DC
Ambient temperature = 25 °C
Worst-case orientation
fOSC 8MHz
fCPU 64 MHz
No PLL frequency
modulation
150 kHz–150 MHz 16 dBµV
150–1000 MHz 15
IEC Level M —
fOSC 8MHz
fCPU 64 MHz
1% PLL frequency
modulation
150 kHz–150 MHz 15 dBµV
150–1000 MHz 14
IEC Level M —
Table 13. ESD ratings1,2
1All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
Circuits.
2A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification requirements. Complete DC parametric and functional testing shall be performed per applicable
device specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Symbol Parameter Conditions Value Unit
VESD(HBM) SR Electrostatic discharge (Human Body Model) — 2000 V
VESD(CDM) SR Electrostatic discharge (Charged Device Model) — 750 (corners) V
500 (other)
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 49
3.8 Power management electrical characteristics
3.8.1 Voltage regulator electrical characteristics
The internal voltage regulator requires an external NPN ballast to be connected as shown in Figure 8. Table 14 contains all
approved NPN ballast components. Capacitances should be placed on the board as near as possible to the associated pins. Care
should also be taken to limit the serial inductance of the VDD_HV_REG
, BCTRL and VDD_LV_CORx pins to less than LReg, see
Table 15.
NOTE
The voltage regulator output cannot be used to drive external circuits. Output pins are used
only for decoupling capacitances.
VDD_LV_COR must be generated using internal regulator and external NPN transistor. It is
not possible to provide VDD_LV_COR through external regulator.
For the MPC5604P microcontroller, capacitors, with total values not below CDEC1, should be placed between
VDD_LV_CORx/VSS_LV_CORx close to external ballast transistor emitter. 4 capacitors, with total values not below CDEC2, should
be placed close to microcontroller pins between each VDD_LV_CORx/VSS_LV_CORx supply pairs and the
VDD_LV_REGCOR/VSS_LV_REGCOR pair . Additionally, capacitors with total values not below CDEC3, should be placed between
the VDD_HV_REG/VSS_HV_REG pins close to ballast collector. Capacitors values have to take into account capacitor accuracy,
aging and variation versus temperature.
All reported information are valid for voltage and temperature ranges described in recommended operating condition, Table 8
and Table 9.
Figure 8. Configuration with resistor on base
BCTRL
VDD_LV_COR
CDEC3
CDEC2 CDEC1
VDD_HV_REG
BJT(1)
MPC5604P
1Refer to Table 14.
RB
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale50
Table 14. Approved NPN ballast components (configuration with resistor on base)
Part Manufacturer Approved derivatives1
1For automotive applications please check with the appropriate transistor vendor for automotive grade
certification
BCP68 ON Semi BCP68
NXP BCP68-25
Infineon BCP68-25
BCX68 Infineon BCX68-10;BCX68-16;BCX68-25
BC868 NXP BC868
BC817 Infineon BC817-16;BC817-25;BC817SU;
NXP BC817-16;BC817-25
BCP56 ST BCP56-16
Infineon BCP56-10;BCP56-16
ON Semi BCP56-10
NXP BCP56-10;BCP56-16
Table 15. Voltage regulator electrical characteristics (configuration with resistor on base)
Symbol C Parameter Conditions
Value
Unit
Min Typ Max
VDD_LV_REGCOR CC P Output voltage under maximum
load run supply current
configuration
Post-trimming 1.15 — 1.32 V
RBSR — External resistance on bipolar
junction transistor (BJT) base
—18—22k
CDEC1 SR — External decoupling/stability
ceramic capacitor
BJT from Table 14. 3
capacitances (i.e. X7R or X8R
capacitors) with nominal value
of 10 µF
19.5 30 — µF
BJT BC817, one capacitance
of 22 µF
14.3 22 µF
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 51
Figure 9. Configuration without resistor on base
RREG SR — Resulting ESR of all three
capacitors of CDEC1
BJT from Table 14. 3x10 µF.
Absolute maximum value
between 100 kHz and 10 MHz
——50m
Resulting ESR of the unique
capacitor CDEC1
BJT BC817, 1x 22 µF.
Absolute maximum value
between 100 kHz and 10 MHz
10 — 40 m
CDEC2 SR — External decoupling/stability
ceramic capacitor
4 capacitances (i.e. X7R or
X8R capacitors) with nominal
value of 440 nF
1200 1760 — nF
CDEC3 SR — External decoupling/stability
ceramic capacitor on
VDD_HV_REG
3 capacitances (i.e. X7R or
X8R capacitors) with nominal
value of 10 µF; CDEC3 has to
be equal or greater than
CDEC1
19.5 30 — µF
LReg SR — Resulting ESL of VDD_HV_REG
,
BCTRL and VDD_LV_CORx pins
———15nH
Table 15. Voltage regulator electrical characteristics (configuration with resistor on base) (continued)
Symbol C Parameter Conditions
Value
Unit
Min Typ Max
BCTRL
VDD_LV_COR
CDEC3
CDEC2 CDEC1
VDD_HV_REG
MPC5604P
BCP56,
BCP68,
BCX68,
BC817
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale52
3.8.2 Voltage monitor electrical characteristics
The device implements a Power-on Reset module to ensure correct power-up initialization, as well as three low voltage
detectors to monitor the VDD and the VDD_LV voltage while device is supplied:
• POR monitors VDD during the power-up phase to ensure device is maintained in a safe reset state
• LVDHV3 monitors VDD to ensure device reset below minimum functional supply
• LVDHV5 monitors VDD when application uses device in the 5.0V ± 10% range
• LVDLVCOR monitors low voltage digital power domain
Table 16. Voltage regulator electrical characteristics (configuration without resistor on base)
Symbol C Parameter Conditions
Value
Unit
Min Typ Max
VDD_LV_REGCOR CC P Output voltage under maximum
load run supply current
configuration
Post-trimming 1.15
—
1.32 V
CDEC1 SR — External decoupling/stability
ceramic capacitor
4 capacitances 40 56 — µF
RREG SR — Resulting ESR of all four CDEC1 Absolute maximum value
between 100 kHz and 10 MHz ——45
m
CDEC2 SR — External decoupling/stability
ceramic capacitor
4 capacitances of 100 nF each 400 — — nF
CDEC3 SR — External decoupling/stability
ceramic capacitor on
VDD_HV_REG
—40——
µF
LReg SR — Resulting ESL of VDD_HV_REG
,
BCTRL and VDD_LV_CORx pins
———15nH
Table 17. Low voltage monitor electrical characteristics
Symbol C Parameter Conditions1Value
Unit
Min Max
VPORH T Power-on reset threshold — 1.5 2.7 V
VPORUP P Supply for functional POR module TA = 25 °C 1.0 — V
VREGLVDMOK_H P Regulator low voltage detector high threshold — — 2.95 V
VREGLVDMOK_L P Regulator low voltage detector low threshold — 2.6 — V
VFLLVDMOK_H P Flash low voltage detector high threshold — — 2.95 V
VFLLVDMOK_L P Flash low voltage detector low threshold — 2.6 — V
VIOLVDMOK_H P I/O low voltage detector high threshold — — 2.95 V
VIOLVDMOK_L P I/O low voltage detector low threshold — 2.6 — V
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 53
3.9 Power up/down sequencing
To prevent an overstress event or a malfunction within and outside the device, the MPC5604P implements the following
sequence to ensure each module is started only when all conditions for switching it ON are available:
• A POWER_ON module working on voltage regulator supply controls the correct start-up of the regulator. This is a
key module ensuring safe configuration for all voltage regulator functionality when supply is below 1.5V. Associated
POWER_ON (or POR) signal is active low.
• Several low voltage detectors, working on voltage regulator supply monitor the voltage of the critical modules (voltage
regulator, I/Os, flash memory and low voltage domain). LVDs are gated low when POWER_ON is active.
• A POWER_OK signal is generated when all critical supplies monitored by the LVD are available. This signal is active
high and released to all modules including I/Os, flash memory and RC16 oscillator needed during power-up phase and
reset phase. When POWER_OK is low the associated module are set into a safe state.
Figure 10. Power-up typical sequence
VIOLVDM5OK_H P I/O 5V low voltage detector high threshold — — 4.4 V
VIOLVDM5OK_L P I/O 5V low voltage detector low threshold — 3.8 — V
VMLVDDOK_H P Digital supply low voltage detector high — — 1.145 V
VMLVDDOK_L P Digital supply low voltage detector low — 1.08 — V
1VDD = 3.3V ± 10% / 5.0V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified
Table 17. Low voltage monitor electrical characteristics (continued)
Symbol C Parameter Conditions1Value
Unit
Min Max
VDD_HV_REG
0V
3.3V
0V
3.3V
VDD_LV_REGCOR
0V
1.2V
0V
3.3V
POWER_ON
LVDM (HV)
0V
LVDD (LV) 3.3V
0V
POWER_OK 3.3V
RC16MHz Oscillator
0V
1.2V
P0 P1 0V
1.2V
Internal Reset Generation Module
FSM
~1us
VPOR_UP
VPORH
VLVDHV3H
VMLVDOK_H
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale54
Figure 11. Power-down typical sequence
Figure 12. Brown-out typical sequence
VDD_HV_REG
0V
3.3V
0V
3.3V
VDD_LV_REGCOR 0V
1.2V
3.3V
POWER_ON
LVDM (HV)
0V
LVDD (LV) 3.3V
0V
POWER_OK
3.3V
RC16MHz Oscillator
0V
1.2V
P0IDLE 0V
1.2V
Internal Reset Generation Module
FSM
VLVDHV3L VPORH
0V
VDD_HV_REG
0V
3.3V
0V
3.3V
VDD_LV_REGCOR 0V
1.2V
3.3V
POWER_ON
LVDM (HV)
0V
LVDD (LV) 3.3V
0V
POWER_OK
3.3V
RC16MHz Oscillator
0V
1.2V
P0IDLE 0V
1.2V
Internal Reset Generation Module
FSM
VLVDHV3L
0V
VLVDHV3H
P1
~1us
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 55
3.10 DC electrical characteristics
3.10.1 NVUSRO register
Portions of the device configuration, such as high voltage supply, and watchdog enable/disable after reset are controlled via bit
values in the non-volatile user options (NVUSRO) register.
For a detailed description of the NVUSRO register, please refer to the device reference manual.
3.10.1.1 NVUSRO[PAD3V5V] field description
The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 18 shows how NVUSRO[PAD3V5V]
controls the device configuration.
3.10.2 DC electrical characteristics (5 V)
Table 19 gives the DC electrical characteristics at 5 V (4.5 V < VDD_HV_IOx < 5.5 V, NVUSRO[PAD3V5V] = 0); see Figure 13.
Table 18. PAD3V5V field description
Value1
1Default manufacturing value before flash initialization is ‘1’ (3.3 V).
Description
0 High voltage supply is 5.0 V
1 High voltage supply is 3.3 V
Table 19. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)
Symbol C Parameter Conditions
Value
Unit
Min Max
VIL D Low level input voltage — –0.11—V
P——0.35V
DD_HV_IOx V
VIH P High level input voltage — 0.65 VDD_HV_IOx —V
D——V
DD_HV_IOx +0.1
1V
VHYS T Schmitt trigger hysteresis — 0.1 VDD_HV_IOx —V
VOL_S P Slow, low level output voltage IOL =3mA — 0.1V
DD_HV_IOx V
VOH_S P Slow, high level output voltage IOH =–3mA 0.8V
DD_HV_IOx —V
VOL_M P Medium, low level output voltage IOL =3mA — 0.1V
DD_HV_IOx V
VOH_M P Medium, high level output voltage IOH =–3mA 0.8V
DD_HV_IOx —V
VOL_F P Fast, low level output voltage IOL =3mA — 0.1V
DD_HV_IOx V
VOH_F P Fast, high level output voltage IOH =–3mA 0.8V
DD_HV_IOx —V
VOL_SYM P Symmetric, low level output voltage IOL =3mA — 0.1V
DD_HV_IOx V
VOH_SYM P Symmetric, high level output voltage IOH =–3mA 0.8V
DD_HV_IOx —V
IPU P Equivalent pull-up current VIN =V
IL –130 — µA
VIN =V
IH — –10
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale56
IPD P Equivalent pull-down current VIN =V
IL 10 — µA
VIN =V
IH — 130
IIL P Input leakage current (all
bidirectional ports)
TA = –40 to 125 °C –1 1 µA
IIL P Input leakage current (all ADC
input-only ports)
TA = –40 to 125 °C –0.5 0.5 µA
CIN D Input capacitance — — 10 pF
IPU D RESET, equivalent pull-up current
VIN =V
IL –130 —
µA
VIN =V
IH — –10
1“SR” parameter values must not exceed the absolute maximum ratings shown in Ta b le 7.
Table 20. Supply current (5.0 V, NVUSRO[PAD3V5V] = 0)
Symbol C Parameter Conditions
Value
Unit
Typ Max
IDD_LV_CORx T
Supply current
RUN—Maximum mode1
1Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled. I/O
supply current excluded.
VDD_LV_CORx
externally forced at 1.3 V
40 MHz 62 77 mA
64 MHz 71 88
RUN—Typical mode2
2Typical mode configurations: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only. I/O supply current excluded.
40 MHz 45 56
64 MHz 52 65
P RUN—Maximum mode3VDD_LV_CORx
externally forced at 1.3 V
64 MHz 60 75
HALT mode4VDD_LV_CORx
externally forced at 1.3 V
—1.510
STOP mode5VDD_LV_CORx
externally forced at 1.3 V
—110
IDD_FLASH T Flash during read VDD_HV_FL at 5.0 V — 10 12
Flash during erase operation on 1
flash module
VDD_HV_FL at 5.0 V — 15 19
IDD_ADC T ADC—Maximum mode1VDD_HV_ADC0 at 5.0 V
VDD_HV_ADC1 at 5.0 V
fADC = 16MHz
ADC_1 3.5 5
ADC_0 3 4
ADC—Typical mode2ADC_1 0.8 1
ADC_0 0.005 0.006
IDD_OSC T Oscillator VDD_OSC at 5.0 V 8 MHz 2.6 3.2
Table 19. DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0) (continued)
Symbol C Parameter Conditions
Value
Unit
Min Max
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 57
3.10.3 DC electrical characteristics (3.3 V)
Table 21 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V, NVUSRO[PAD3V5V] = 1); see
Figure 13.
3Code fetched from RAM, PLL_0: 64 MHz system clock (x4 multiplier with 16 MHz XTAL), PLL_1 is ON at
PHI_div2 = 120 MHz and PHI_div3 = 80 MHz, auxiliary clock sources set that all peripherals receive maximum
frequency, all peripherals enabled.
4Halt mode configurations: code fetched from RAM, code and data flash memories in low power mode,
OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.
5STOP “P” mode Device Under Test (DUT) configuration: code fetched from RAM, code and data flash memories
OFF, OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.
Table 21. DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)1
1These specifications are design targets and subject to change per device characterization.
Symbol C Parameter Conditions
Value
Unit
Min Max
VIL D Low level input voltage — –0.12—V
P——0.35V
DD_HV_IOx V
VIH P High level input voltage — 0.65 VDD_HV_IOx —V
D——V
DD_HV_IOx +0.1
2V
VHYS T Schmitt trigger hysteresis — 0.1 VDD_HV_IOx —V
VOL_S P Slow, low level output voltage IOL = 1.5 mA — 0.5 V
VOH_S P Slow, high level output voltage IOH =–1.5mA V
DD_HV_IOx –0.8 — V
VOL_M P Medium, low level output voltage IOL =2mA — 0.5 V
VOH_M P Medium, high level output voltage IOH =–2mA V
DD_HV_IOx –0.8 — V
VOL_F P Fast, low level output voltage IOL = 1.5 mA — 0.5 V
VOH_F P Fast, high level output voltage IOH =–1.5mA V
DD_HV_IOx –0.8 — V
VOL_SYM P Symmetric, low level output voltage IOL = 1.5 mA — 0.5 V
VOH_SYM P Symmetric, high level output voltage IOH =–1.5mA V
DD_HV_IOx –0.8 — V
IPU P Equivalent pull-up current VIN =V
IL –130 — µA
VIN =V
IH —–10
IPD P Equivalent pull-down current VIN =V
IL 10 — µA
VIN =V
IH —130
IIL P Input leakage current (all
bidirectional ports)
TA = –40 to 125 °C — 1 µA
IIL P Input leakage current (all ADC
input-only ports)
TA = –40 to 125 °C — 0.5 µA
CIN D Input capacitance — — 10 pF
IPU D RESET, equivalent pull-up current
VIN =V
IL –130 —
µA
VIN =V
IH —–10
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale58
3.10.4 Input DC electrical characteristics definition
Figure 13 shows the DC electrical characteristics behavior as function of time.
2“SR” parameter values must not exceed the absolute maximum ratings shown in Ta b le 7.
Table 22. Supply current (3.3 V, NVUSRO[PAD3V5V] = 1)
Symbol C Parameter Conditions
Value
Unit
Typ Max
IDD_LV_CORx T
Supply current
RUN—Maximum mode1
1Maximum mode: FlexPWM, ADCs, CTU, DSPI, LINFlex, FlexCAN, 15 output pins, 1st and 2nd PLL enabled. I/O
supply current excluded.
VDD_LV_CORx
externally forced at 1.3 V
40 MHz 62 77 mA
64 MHz 71 89
RUN—Typical mode2
2Typical mode: DSPI, LINFlex, FlexCAN, 15 output pins, 1st PLL only. I/O supply current excluded.
40 MHz 45 56
64 MHz 53 66
P RUN—Maximum mode3
3Code fetched from RAM, PLL_0: 64 MHz system clock (x4 multiplier with 16 MHz XTAL), PLL_1 is ON at
PHI_div2 = 120 MHz and PHI_div3 = 80 MHz, auxiliary clock sources set that all peripherals receive maximum
frequency, all peripherals enabled.
VDD_LV_CORx
externally forced at 1.3 V
64 MHz 60 75
HALT mode4
4Halt mode configurations: code fetched from RAM, code and data flash memories in low power mode,
OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.
VDD_LV_CORx
externally forced at 1.3 V
—1.510
STOP mode5
5STOP “P” mode Device Under Test (DUT) configuration: code fetched from RAM, code and data flash memories
OFF, OSC/PLL_0/PLL_1 are OFF, core clock frozen, all peripherals are disabled.
VDD_LV_CORx
externally forced at 1.3 V
—110
IDD_FLASH T Flash during read on single mode VDD_HV_FL at 3.3 V — 8 10
Flash during erase operation on
single mode
VDD_HV_FL at 3.3 V — 10 12
IDD_ADC T ADC—Maximum mode1VDD_HV_ADC0 at 3.3 V
VDD_HV_ADC1 at 3.3 V
fADC =16MHz
ADC_1 2.5 4
ADC_0 2 4
ADC—Typical mode2ADC_1 0.8 1
ADC_0 0.005 0.006
IDD_OSC T Oscillator VDD_OSC at 3.3V 8MHz 2.4 3
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 59
Figure 13. Input DC electrical characteristics definition
3.10.5 I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as
described in Table 23.
Table 24 provides the weight of concurrent switching I/Os.
In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain
below 100%.
Table 23. I/O supply segment
Package
Supply segment
12345 6 7
144
LQFP
pin8 – pin20 pin23 – pin38 pin39 – pin55 pin58 – pin68 pin73 – pin89 pin92 – pin125 pin128 – pin5
100
LQFP
pin15 – pin26 pin27 – pin38 pin41 – pin46 pin51 – pin61 pin64 – pin86 pin89 – pin10 —
Table 24. I/O weight
Pad
144 LQFP 100 LQFP
Weight 5V Weight 3.3V Weight 5V Weight 3.3V
NMI1%1%1%1%
PAD[6] 6% 5% 14% 13%
PAD[49] 5% 4% 14% 12%
PAD[84] 14% 10% — —
PAD[85] 9% 7% — —
VIL
VIN
VIH
PDIx = ‘1’
VDD
VHYS
(GPDI register of SIUL)
PDIx = ‘0’
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale60
PAD[86] 9% 6% — —
MODO[0] 12% 8% — —
PAD[7] 4% 4% 11% 10%
PAD[36] 5% 4% 11% 9%
PAD[8] 5% 4% 10% 9%
PAD[37] 5% 4% 10% 9%
PAD[5] 5% 4% 9% 8%
PAD[39] 5% 4% 9% 8%
PAD[35] 5% 4% 8% 7%
PAD[87] 12% 9% — —
PAD[88] 9% 6% — —
PAD[89] 10% 7% — —
PAD[90] 15% 11% — —
PAD[91] 6% 5% — —
PAD[57] 8% 7% 8% 7%
PAD[56] 13% 11% 13% 11%
PAD[53] 14% 12% 14% 12%
PAD[54] 15% 13% 15% 13%
PAD[55] 25% 22% 25% 22%
PAD[96] 27% 24% — —
PAD[65] 1% 1% 1% 1%
PAD[67] 1% 1% — —
PAD[33] 1% 1% 1% 1%
PAD[68] 1% 1% — —
PAD[23] 1% 1% 1% 1%
PAD[69] 1% 1% — —
PAD[34] 1% 1% 1% 1%
PAD[70] 1% 1% — —
PAD[24] 1% 1% 1% 1%
PAD[71] 1% 1% — —
PAD[66] 1% 1% 1% 1%
PAD[25] 1% 1% 1% 1%
PAD[26] 1% 1% 1% 1%
Table 24. I/O weight (continued)
Pad
144 LQFP 100 LQFP
Weight 5V Weight 3.3V Weight 5V Weight 3.3V
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 61
PAD[27] 1% 1% 1% 1%
PAD[28] 1% 1% 1% 1%
PAD[63] 1% 1% 1% 1%
PAD[72] 1% 1% — —
PAD[29] 1% 1% 1% 1%
PAD[73] 1% 1% — —
PAD[31] 1% 1% 1% 1%
PAD[74] 1% 1% — —
PAD[30] 1% 1% 1% 1%
PAD[75] 1% 1% — —
PAD[32] 1% 1% 1% 1%
PAD[76] 1% 1% — —
PAD[64] 1% 1% 1% 1%
PAD[0] 23% 20% 23% 20%
PAD[1] 21% 18% 21% 18%
PAD[107] 20% 17% — —
PAD[58] 19% 16% 19% 16%
PAD[106] 18% 16% — —
PAD[59] 17% 15% 17% 15%
PAD[105] 16% 14% — —
PAD[43] 15% 13% 15% 13%
PAD[104] 14% 13% — —
PAD[44] 13% 12% 13% 12%
PAD[103] 12% 11% — —
PAD[2] 11% 10% 11% 10%
PAD[101] 11% 9% — —
PAD[21] 10% 8% 10% 8%
TMS1%1%1%1%
TCK1%1%1%1%
PAD[20] 16% 11% 16% 11%
PAD[3] 4% 3% 4% 3%
PAD[61] 9% 8% 9% 8%
PAD[102] 11% 10% — —
Table 24. I/O weight (continued)
Pad
144 LQFP 100 LQFP
Weight 5V Weight 3.3V Weight 5V Weight 3.3V
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale62
PAD[60] 11% 10% 11% 10%
PAD[100] 12% 10% — —
PAD[45] 12% 10% 12% 10%
PAD[98] 12% 11% — —
PAD[46] 12% 11% 12% 11%
PAD[99] 13% 11% — —
PAD[62] 13% 11% 13% 11%
PAD[92] 13% 12% — —
VPP_TEST 1% 1% 1% 1%
PAD[4] 14% 12% 14% 12%
PAD[16] 13% 12% 13% 12%
PAD[17] 13% 11% 13% 11%
PAD[42] 13% 11% 13% 11%
PAD[93] 12% 11% — —
PAD[95] 12% 11% — —
PAD[18] 12% 10% 12% 10%
PAD[94] 11% 10% — —
PAD[19] 11% 10% 11% 10%
PAD[77] 10% 9% — —
PAD[10] 10% 9% 10% 9%
PAD[78] 9% 8% — —
PAD[11]9%8%9%8%
PAD[79] 8% 7% — —
PAD[12] 7% 7% 7% 7%
PAD[41] 7% 6% 7% 6%
PAD[47] 5% 4% 5% 4%
PAD[48] 4% 4% 4% 4%
PAD[51] 4% 4% 4% 4%
PAD[52] 5% 4% 5% 4%
PAD[40] 5% 5% 6% 5%
PAD[80] 9% 8% — —
PAD[9] 10% 9% 11% 10%
PAD[81] 10% 9% — —
Table 24. I/O weight (continued)
Pad
144 LQFP 100 LQFP
Weight 5V Weight 3.3V Weight 5V Weight 3.3V
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 63
PAD[13] 10% 9% 12% 11%
PAD[82] 10% 9% — —
PAD[22] 10% 9% 13% 12%
PAD[83] 10% 9% — —
PAD[50] 10% 9% 14% 12%
PAD[97] 10% 9% — —
PAD[38] 10% 9% 14% 13%
PAD[14] 9% 8% 14% 13%
PAD[15] 9% 8% 15% 13%
Table 25. I/O consumption
Symbol C Parameter Conditions1Value
Unit
Min Typ Max
ISWTSLW,2 CC D Dynamic I/O current
for SLOW
configuration
CL = 25 pF VDD = 5.0 V ± 10%,
PAD3V5V = 0
——20mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1
——16
ISWTMED(2) CC D Dynamic I/O current
for MEDIUM
configuration
CL = 25 pF VDD = 5.0 V ± 10%,
PAD3V5V = 0
——29mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1
——17
ISWTFST(2) CC D Dynamic I/O current
for FAST
configuration
CL = 25 pF VDD = 5.0 V ± 10%,
PAD3V5V = 0
——110mA
VDD = 3.3 V ± 10%,
PAD3V5V = 1
——50
IRMSSLW CC D Root medium square
I/O current for SLOW
configuration
CL = 25 pF, 2 MHz VDD = 5.0 V ± 10%,
PAD3V5V = 0
——2.3mA
CL = 25 pF, 4 MHz — — 3.2
CL = 100 pF, 2 MHz — — 6.6
CL = 25 pF, 2 MHz VDD = 3.3 V ± 10%,
PAD3V5V = 1
——1.6
CL = 25 pF, 4 MHz — — 2.3
CL = 100 pF, 2 MHz — — 4.7
Table 24. I/O weight (continued)
Pad
144 LQFP 100 LQFP
Weight 5V Weight 3.3V Weight 5V Weight 3.3V
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale64
3.11 Main oscillator electrical characteristics
The MPC5604P provides an oscillator/resonator driver.
IRMSMED CC D Root medium square
I/O current for
MEDIUM
configuration
CL = 25 pF, 13 MHz VDD = 5.0 V ± 10%,
PAD3V5V = 0
——6.6mA
CL = 25 pF, 40 MHz — — 13.4
CL = 100 pF, 13 MHz — — 18.3
CL = 25 pF, 13 MHz VDD = 3.3 V ± 10%,
PAD3V5V = 1
—— 5
CL = 25 pF, 40 MHz — — 8.5
CL = 100 pF, 13 MHz — — 11
IRMSFST CC D Root medium square
I/O current for FAST
configuration
CL = 25 pF, 40 MHz VDD = 5.0 V ± 10%,
PAD3V5V = 0
——22mA
CL = 25 pF, 64 MHz — — 33
CL = 100 pF, 40 MHz — — 56
CL = 25 pF, 40 MHz VDD = 3.3 V ± 10%,
PAD3V5V = 1
——14
CL = 25 pF, 64 MHz — — 20
CL = 100 pF, 40 MHz — — 35
IAVGSEG SR D Sum of all the static
I/O current within a
supply segment
VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 70 mA
VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 65
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified
2Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.
Table 26. Main oscillator output electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)
Symbol C Parameter
Value
Unit
Min Max
fOSC SR — Oscillator frequency 4 40 MHz
gm— P Transconductance 6.5 25 mA/V
VOSC — T Oscillation amplitude on XTAL pin 1 — V
tOSCSU — T Start-up time1,2
1The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and
excessive capacitive loads can cause long start-up time.
2Value captured when amplitude reaches 90% of XTAL
8—ms
Table 25. I/O consumption (continued)
Symbol C Parameter Conditions1Value
Unit
Min Typ Max
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 65
3.12 FMPLL electrical characteristics
Table 27. Main oscillator output electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)
Symbol C Parameter
Value
Unit
Min Max
fOSC S
R
— Oscillator frequency 4 40 MHz
gm— P Transconductance 4 20 mA/V
VOSC — T Oscillation amplitude on XTAL pin 1 — V
tOSCSU — T Start-up time1,2
1The start-up time is dependent upon crystal characteristics, board leakage, etc., high ESR and
excessive capacitive loads can cause long start-up time.
2Value captured when amplitude reaches 90% of XTAL
8—ms
Table 28. Input clock characteristics
Symbol Parameter
Value
Unit
Min Typ Max
fOSC SR Oscillator frequency 4 — 40 MHz
fCLK SR Frequency in bypass — — 64 MHz
trCLK SR Rise/fall time in bypass — — 1 ns
tDC SR Duty cycle 47.5 50 52.5 %
Table 29. FMPLL electrical characteristics
Symbol C Parameter Conditions1Value
Unit
Min Max
fref_crystal
fref_ext
D PLL reference frequency range2Crystal reference 4 40 MHz
fPLLIN D Phase detector input frequency range (after
pre-divider)
—416MHz
fFMPLLOUT D Clock frequency range in normal mode — 16 120 MHz
fFREE P Free-running frequency Measured using clock
division — typically /16
20 150 MHz
tCYC D System clock period — — 1 / fSYS ns
fLORL
fLORH
D Loss of reference frequency window3Lower limit 1.6 3.7 MHz
Upper limit 24 56
fSCM D Self-clocked mode frequency4,5 — 20 150 MHz
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale66
CJITTER T CLKOUT period
jitter6,7,8,9
Short-term jitter10 fSYS maximum 44%f
CLKOUT
Long-term jitter (avg.
over 2 ms interval)
fPLLIN = 16 MHz
(resonator), fPLLCLK at
64 MHz, 4,000 cycles
—10 ns
tlpll D PLL lock time 11, 12 — — 200 µs
tdc D Duty cycle of reference —4060%
fLCK D Frequency LOCK range — 66% f
SYS
fUL D Frequency un-LOCK range — -18 18 % fSYS
fCS
fDS
D Modulation depth Center spread ±0.25 ±4.013 % fSYS
Down spread 0.5 8.0
fMOD D Modulation frequency14 — — 70 kHz
1VDD_LV_CORx = 1.2 V ±10%; VSS = 0 V; TA = –40 to 125 °C, unless otherwise specified
2Considering operation with PLL not bypassed
3“Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self-clocked
mode.
4Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside
the fLOR window.
5fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in
enhanced mode.
6This value is determined by the crystal manufacturer and board design.
7Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the CJITTER percentage for a given interval.
8Proper PC board layout procedures must be followed to achieve specifications.
9Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and
either fCS or fDS (depending on whether center spread or down spread modulation is enabled).
10 Short term jitter is measured on the clock rising edge at cycle n and cycle n+4.
11 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for
this PLL, load capacitors should not exceed these limits.
12 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
13 This value is true when operating at frequencies above 60 MHz, otherwise fCS is 2% (above 64 MHz).
14 Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.
Table 29. FMPLL electrical characteristics (continued)
Symbol C Parameter Conditions1Value
Unit
Min Max
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 67
3.13 16 MHz RC oscillator electrical characteristics
3.14 Analog-to-digital converter (ADC) electrical characteristics
The device provides a 10-bit successive approximation register (SAR) analog-to-digital converter.
Table 30. 16 MHz RC oscillator electrical characteristics
Symbol C Parameter Conditions
Value
Unit
Min Typ Max
fRC P RC oscillator frequency TA = 25 °C — 16 — MHz
RCMVAR P Fast internal RC oscillator variation over temperature and
supply with respect to fRC at TA = 25 °C in high-frequency
configuration
—–5—5%
RCMTRIM T Post Trim Accuracy: The variation of the PTF1 from the
16 MHz
1PTF = Post Trimming Frequency: The frequency of the output clock after trimming at typical supply voltage and
temperature
TA = 25 °C –1 — 1 %
RCMSTEP T Fast internal RC oscillator trimming step TA = 25 °C — 1.6 — %
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale68
Figure 14. ADC characteristics and error definitions
3.14.1 Input impedance and ADC accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor
with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as
possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it sources charge
during the sampling phase, when the analog signal source is a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC
filtering may be limited according to the source impedance value of the transducer or circuit supplying the analog signal to be
measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal
(bandwidth) and the equivalent input impedance of the ADC itself.
(2)
(1)
(3)
(4)
(5)
Offset Error OSE
Offset Error OSE
Gain Error GE
1 LSB (ideal)
1023
1022
1021
1020
1019
1018
5
4
3
2
1
0
7
6
1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer curve
1 LSB ideal = VDD_ADC / 1024
Vin(A) (LSBideal)
code out
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 69
In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: CS and CP2 being
substantially two switched capacitances, with a frequency equal to the ADC conversion rate, it can be seen as a resistive path
to ground. For instance, assuming a conversion rate of 1 MHz, with CS+CP2 equal to 3 pF, a resistance of 330 k is obtained
(REQ = 1 / (fc × (CS+CP2)), where fc represents the conversion rate at the considered channel). To minimize the error induced
by the voltage partitioning between this resistance (sampled voltage on CS+CP2) and the sum of RS + RF, the external circuit
must be designed to respect the Equation 4:
Eqn. 4
Equation 4 generates a constraint for external network design, in particular on resistive path.
Figure 15. Input equivalent circuit
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are
initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 15): A charge sharing phenomenon
is installed when the sampling phase is started (A/D switch closed).
VA
RSRF
+
REQ
---------------------
1
2
---LSB
RF
CF
RSRLRSW1
CP2 CS
VDD
Sampling
Source Filter Current Limiter
EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME
CP1
RAD
Channel
Selection
VA
RS: Source impedance
RF: Filter resistance
CF: Filter capacitance
RL: Current limiter resistance
RSW1: Channel selection switch impedance
RAD: Sampling switch impedance
CP: Pin capacitance (two contributions, CP1 and CP2)
CS: Sampling capacitance
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale70
Figure 16. Transient behavior during sampling phase
In particular two different transient periods can be distinguished:
• A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series,
and the time constant is
Eqn. 5
Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS
is always much longer than the internal time constant:
Eqn. 6
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance
according to Equation 7:
Eqn. 7
• A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance
RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality
would be faster), the time constant is:
Eqn. 8
VA
VA1
VA2
t
TS
VCS Voltage Transient on CS
V <0.5 LSB
12
1 < (RSW + RAD) CS << TS
2
= R
L
(C
S
+ C
P1
+ C
P2
)
1RSW RAD
+=
CPCS
CPCS
+
---------------------
1RSW RAD
+CSTS
«
VA1 CSCP1 CP2
++VACP1 CP2
+=
2RL
CSCP1 CP2
++
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 71
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time TS, a constraints on RL sizing is obtained:
Eqn. 9
Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source
impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2
(at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge
balance assuming now CS already charged at VA1):
Eqn. 10
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to
provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of
the filter is very high with respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
Figure 17. Spectral representation of input signal
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, fF),
according to the Nyquist theorem the conversion rate fC must be at least 2f0; it means that the constant time of the filter is greater
than or at least equal to twice the conversion period (TC). Again the conversion period TC is longer than the sampling time TS,
which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a
specific channel): in conclusion it is evident that the time constant of the filter RFCF is definitively much higher than the
sampling time TS, so the charge level on CS cannot be modified by the analog signal source during the time in which the
sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage
drop on CS; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled
voltage on CS:
8.5 2
8.5 RLCSCP1 CP2
++=T
S
VA2 CSCP1 CP2 CF
+++VACF
VA1
+C
P1 CP2
+C
S
+=
f0f
Analog Source Bandwidth (VA)
f0f
Sampled Signal Spectrum (fC = conversion Rate)
fC
f
Anti-Aliasing Filter (fF = RC Filter pole)
fF
2 f0 fC (Nyquist)
fF f0 (Anti-aliasing Filtering Condition)
TC 2 RFCF (Conversion Rate vs. Filter Pole)
Noise
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale72
Eqn. 11
From this formula, in the worst case (when VA is maximum, that is for instance 5 V), assuming to accept a maximum error of
half a count, a constraint is evident on CF value:
Eqn. 12
3.14.2 ADC conversion characteristics
Table 31. ADC conversion characteristics
Symbol C Parameter Conditions1Value
Unit
Min Typ Max
VINAN0 SR ADC0 and shared ADC0/1
analog input voltage2, 3
—V
SS_HV_ADV
0
0.3
—V
DD_HV_ADV
0
+ 0.3
V
VINAN1 SR ADC1 analog input voltage2, 4
—V
SS_HV_ADV
1
0.3
—V
DD_HV_ADV
1
+ 0.3
V
fCK SR — ADC clock frequency (depends
on ADC configuration)
(The duty cycle depends on
AD_clk5 frequency)
—3
6—60MHz
fsSR — Sampling frequency — — — 1.53 MHz
tADC_S — D Sample time7fADC = 20 MHz,
INPSAMP = 3
125 — — ns
fADC = 9 MHz,
INPSAMP = 255
— — 28.2 µs
tADC_C — P Conversion time8fADC = 20 MHz9,
INPCMP = 1
0.650 — — µs
tADC_PU SR — ADC power-up delay (time
needed for ADC to settle
exiting from software power
down; PWDN bit = 0)
———1.5µs
CS10 — D ADC input sampling
capacitance
———2.5pF
CP110 — D ADC input pin capacitance 1 — — — 3 pF
CP210 — D ADC input pin capacitance 2 — — — 1 pF
VA
VA2
------------
CP1 CP2
+C
F
+
CP1 CP2
+C
FCS
++
--------------------------------------------------------=
CF2048 CS
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 73
RSW110 — D Internal resistance of analog
source
VDD_HV_ADC =
5 V ± 10%
——0.6k
VDD_HV_ADC =
3.3 V ± 10%
—— 3k
RAD10 — D Internal resistance of analog
source
———2k
IINJ — T Input current injection Current injection on
one ADC input,
different from the
converted one.
Remains within TUE
spec.
–5 — 5 mA
INL CC P Integral non-linearity No overload –1.5 — 1.5 LSB
DNL CC P Differential non-linearity No overload –1.0 — 1.0 LSB
OSE CC T Offset error — — ±1 — LSB
GE CC T Gain error — — ±1 — LSB
TUE CC P Total unadjusted error without
current injection
—–2.5—2.5LSB
TUE CC T Total unadjusted error with
current injection
—–3—3LSB
1VDD = 3.3 V to 3.6 V / 4.5 V to 5.5 V, TA = –40 °C to TA MAX, unless otherwise specified and analog input voltage
from VSS_HV_ADCx to VDD_HV_ADCx.
2VAINx may exceed VSS_HV_AD and VDD_HV_AD limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
3Not allowed to refer this voltage to VDD_HV_ADV1, VSS_HV_ADV1
4Not allowed to refer this voltage to VDD_HV_ADV0, VSS_HV_ADV0
5AD_clk clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
6When configured to allow 60 MHz ADC, the minimum ADC clock speed is 9 MHz, below which precision is lost.
7During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC_S. After the
end of the sample time tADC_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC_S depend on programming.
8This parameter includes the sample time tADC_S.
920 MHz ADC clock. Specific prescaler is programmed on MC_PLL_CLK to provide 20 MHz clock to the ADC.
10 See Figure 15.
Table 31. ADC conversion characteristics (continued)
Symbol C Parameter Conditions1Value
Unit
Min Typ Max
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale74
3.15 Flash memory electrical characteristics
Table 32. Program and erase specifications
Symbol C Parameter
Value
Unit
Min Typical1
1Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to
change pending device characterization.
Initial
max2
2Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
Max3
3The maximum program and erase times occur after the specified number of program/erase cycles. These maximum
values are characterized but not guaranteed.
Tdwprogram P Double Word (64 bits) Program Time4
4Actual hardware programming times. This does not include software overhead.
— 22 50 500 µs
TBKPRG P Bank Program (512 KB)4, 5
5Typical Bank programming time assumes that all cells are programmed in a single pulse. In reality some cells will
require more than one pulse, adding a small overhead to total bank programming time (see Initial Max column).
— 1.45 1.65 33 s
P Bank Program (64 KB)4, 5— 0.18 0.21 4.10 s
T16kpperase P 16 KB Block Pre-program and Erase Time — 300 500 5000 ms
T32kpperase P 32 KB Block Pre-program and Erase Time — 400 600 5000 ms
T128kpperase P 128 KB Block Pre-program and Erase Time — 800 1300 7500 ms
Table 33. Flash memory module life
Symbol C Parameter Conditions
Value
Unit
Min Typ
P/E C Number of program/erase cycles per block
for 16 KB blocks over the operating
temperature range (TJ)
— 100,000 — cycles
P/E C Number of program/erase cycles per block
for 32 KB blocks over the operating
temperature range (TJ)
— 10,000 100,000 cycles
P/E C Number of program/erase cycles per block
for 128 KB blocks over the operating
temperature range (TJ)
— 1,000 100,000 cycles
Retention C Minimum data retention at 85 °C average
ambient temperature1
1Ambient temperature averaged over duration of application, not to exceed recommended product operating
temperature range.
Blocks with 0–1,000 P/E
cycles
20 — years
Blocks with 10,000 P/E
cycles
10 — years
Blocks with 100,000 P/E
cycles
5 — years
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 75
3.16 AC specifications
3.16.1 Pad AC specifications
Table 34. Flash memory read access timing
Symbol C Parameter Conditions1
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified
Max value Unit
fmax C Maximum working frequency at given number of
wait states in worst conditions
2 wait states 66 MHz
0 wait states 18
Table 35. Output pin transition times
Symbol C Parameter Conditions1
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified
Value
Unit
Min Typ Max
ttr CC D Output transition time output pin2
SLOW configuration
2CL includes device and package capacitances (CPKG < 5 pF).
CL = 25 pF VDD = 5.0 V ± 10%,
PAD3V5V = 0
——50ns
TC
L = 50 pF — — 100
DC
L = 100 pF — — 125
DC
L = 25 pF VDD = 3.3 V ± 10%,
PAD3V5V = 1
——40
TC
L = 50 pF — — 50
DC
L = 100 pF — — 75
ttr CC D Output transition time output pin2
MEDIUM configuration
CL = 25 pF VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
——10ns
TC
L = 50 pF — — 20
DC
L = 100 pF — — 40
DC
L = 25 pF VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
——12
TC
L = 50 pF — — 25
DC
L = 100 pF — — 40
ttr CC D Output transition time output pin2
FAST configuration
CL = 25 pF VDD = 5.0 V ± 10%,
PAD3V5V = 0
SIUL.PCRx.SRC = 1
—— 4 ns
CL = 50 pF — — 6
CL = 100 pF — — 12
CL = 25 pF VDD = 3.3 V ± 10%,
PAD3V5V = 1
SIUL.PCRx.SRC = 1
—— 4
CL = 50 pF — — 7
CL = 100 pF — — 12
tSYM3
3Transition timing of both positive and negative slopes will differ maximum 50%
CC T Symmetric transition time, same drive
strength between N and P transistor
VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 4 ns
VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 5
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale76
Figure 18. Pad output delay
3.17 AC timing characteristics
3.17.1 RESET pin characteristics
The MPC5604P implements a dedicated bidirectional RESET pin.
Figure 19. Start-up reset requirements
VDD_HV_IOx/2
VOH
VOL
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
Pad
Data Input
Pad
Output
VIL
VDD
device reset forced by VRESET
VDDMIN
VRESET
VIH
device start-up phase
TPOR
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 77
Figure 20. Noise filtering on reset signal
Table 36. RESET electrical characteristics
Symbol C Parameter Conditions1Value
Unit
Min Typ Max
VIH SR P Input High Level CMOS
(Schmitt Trigger)
— 0.65VDD —V
DD+0.4 V
VIL SR P Input low Level CMOS
(Schmitt Trigger)
— –0.4 — 0.35VDD V
VHYS CC C Input hysteresis CMOS
(Schmitt Trigger)
—0.1V
DD ——V
VOL CC P Output low level Push Pull, IOL = 2mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
— — 0.1VDD V
Push Pull, IOL = 1mA,
VDD = 5.0 V ± 10%, PAD3V5V = 12
— — 0.1VDD
Push Pull, IOL = 1mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
——0.5
VRESET
VIL
VIH
VDD
filtered by
hysteresis
filtered by
lowpass filter
WFRST
WNFRST
hw_rst
‘1’
‘0’
filtered by
lowpass filter
WFRST
unknown reset
state device under hardware reset
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale78
3.17.2 IEEE 1149.1 interface timing
ttr CC D Output transition time
output pin3
MEDIUM configuration
CL = 25pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
— — 10 ns
CL = 50pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
——20
CL = 100pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
——40
CL = 25pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——12
CL = 50pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——25
CL = 100pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——40
WFRST SR P RESET input filtered
pulse
———40ns
WNFRST SR P RESET input not filtered
pulse
—500——ns
tPOR CC D Maximum delay before
internal reset is released
after all VDD_HV reach
nominal supply
Monotonic VDD_HV supply ramp — — 1 ms
|IWPU| CC P Weak pull-up current
absolute value
VDD = 3.3 V ± 10%, PAD3V5V = 1 10 — 150 µA
VDD = 5.0 V ± 10%, PAD3V5V = 0 10 — 150
VDD = 5.0 V ± 10%, PAD3V5V = 1410 — 250
1VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified
2This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
device reference manual).
3CL includes device and package capacitance (CPKG <5pF).
4The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 37. JTAG pin AC electrical characteristics
No. Symbol C Parameter Conditions
Value
Unit
Min Max
1t
JCYC CC D TCK cycle time — 100 — ns
2t
JDC CC D TCK clock pulse width (measured at VDD_HV_IOx/2) — 40 60 ns
3t
TCKRISE CC D TCK rise and fall times (40% – 70%) — — 3 ns
4t
TMSS, tTDIS CC D TMS, TDI data setup time — 5 — ns
Table 36. RESET electrical characteristics (continued)
Symbol C Parameter Conditions1Value
Unit
Min Typ Max
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 79
Figure 21. JTAG test clock input timing
5t
TMSH, tTDIH CC D TMS, TDI data hold time — 25 — ns
6t
TDOV CC D TCK low to TDO data valid — — 40 ns
7t
TDOI CC D TCK low to TDO data invalid — 0 — ns
8t
TDOHZ CC D TCK low to TDO high impedance — 40 — ns
11 tBSDV CC D TCK falling edge to output valid — — 50 ns
12 tBSDVZ CC D TCK falling edge to output valid out of high impedance — — 50 ns
13 tBSDHZ CC D TCK falling edge to output high impedance — — 50 ns
14 tBSDST CC D Boundary scan input valid to TCK rising edge — 50 — ns
15 tBSDHT CC D TCK rising edge to boundary scan input invalid — 50 — ns
Table 37. JTAG pin AC electrical characteristics (continued)
No. Symbol C Parameter Conditions
Value
Unit
Min Max
TCK
1
2
2
3
3
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale80
Figure 22. JTAG test access port timing
TCK
4
5
6
78
TMS, TDI
TDO
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 81
Figure 23. JTAG boundary scan timing
3.17.3 Nexus timing
Table 38. Nexus debug port timing1
No. Symbol C Parameter
Value
Unit
Min Typ Max
1t
MCYC CC D MCKO cycle time 32 — — ns
2t
MDOV CC D MCKO low to MDO data valid2—— 6ns
3t
MSEOV CC D MCKO low to MSEO data valid2—— 6ns
4t
EVTOV CC D MCKO low to EVTO data valid2—— 6ns
5t
TCYC CC D TCK cycle time 643——ns
TCK
Output
Signals
Input
Signals
Output
Signals
11
12
13
14
15
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale82
Figure 24. Nexus output timing
Figure 25. Nexus event trigger and test clock timings
6t
NTDIS CC D TDI data setup time 6 — — ns
tNTMSS CC D TMS data setup time 6 — — ns
7t
NTDIH CC D TDI data hold time 10 — — ns
tNTMSH CC D TMS data hold time 10 — — ns
8t
TDOV CC D TCK low to TDO data valid — — 35 ns
9t
TDOI CC D TCK low to TDO data invalid 6 — — ns
1All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal.
2MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
3Lower frequency is required to be fully compliant to standard.
Table 38. Nexus debug port timing1 (continued)
No. Symbol C Parameter
Value
Unit
Min Typ Max
1
3
4
MCKO
MDO
MSEO
EVTO
Output Data Valid
2
TCK
5
EVTI
EVTO
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 83
Figure 26. Nexus TDI, TMS, TDO timing
3.17.4 External interrupt timing (IRQ pin)
Table 39. External interrupt timing1
1IRQ timing specified at fSYS = 64 MHz and VDD_HV_IOx = 3.0 V to 5.5 V, TA = TL to TH, and CL = 200 pF
with SRC = 0b00.
No. Symbol C Parameter Conditions
Value
Unit
Min Max
1t
IPWL CC D IRQ pulse width low — 4 — tCYC
2t
IPWH CC D IRQ pulse width high — 4 — tCYC
3t
ICYC CC D IRQ edge to edge time2
2Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
—4 + N 3—t
CYC
TDO
6
7
TMS, TDI
8
TCK
9
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale84
Figure 27. External interrupt timing
3.17.5 DSPI timing
3N = ISR time to clear the flag
Table 40. DSPI timing1
No. Symbol C Parameter Conditions
Value
Unit
Min Max
1t
SCK CC D DSPI cycle time Master (MTFE = 0) 60 — ns
Slave (MTFE = 0) 60 —
2t
CSC CC D CS to SCK delay — 16 — ns
3t
ASC CC D After SCK delay — 26 — ns
4t
SDC CC D SCK duty cycle — 0.4 * tSCK 0.6 * tSCK ns
5t
ACC D Slave access time SS active to SOUT valid — 30 ns
6t
DIS CC D Slave SOUT disable time SS inactive to SOUT high
impedance or invalid
—16ns
7t
PCSC CC D PCSx to PCSS time — 13 — ns
8t
PASC CC D PCSS to PCSx time — 13 — ns
9t
SUI CC D Data setup time for inputs Master (MTFE = 0) 35 — ns
Slave 4 —
Master (MTFE = 1, CPHA = 0) 35 —
Master (MTFE = 1, CPHA = 1) 35 —
10 tHI CC D Data hold time for inputs Master (MTFE = 0) –5 — ns
Slave 4 —
Master (MTFE = 1, CPHA = 0) 11 —
Master (MTFE = 1, CPHA = 1) –5 —
IRQ
2
3
1
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 85
Figure 28. DSPI classic SPI timing – Master, CPHA = 0
11 tSUO CC D Data valid (after SCK edge) Master (MTFE = 0) — 12 ns
Slave — 36
Master (MTFE = 1, CPHA = 0) — 12
Master (MTFE = 1, CPHA = 1) — 12
12 tHO CC D Data hold time for outputs Master (MTFE = 0) –2 — ns
Slave 6 —
Master (MTFE = 1, CPHA = 0) 6 —
Master (MTFE = 1, CPHA = 1) –2 —
1All timing is provided with 50 pF capacitance on output, 1 ns transition time on input signal.
Table 40. DSPI timing1 (continued)
No. Symbol C Parameter Conditions
Value
Unit
Min Max
Data Last Data
First Data
First Data Data Last Data
SIN
SOUT
PCSx
SCK Output
4
9
12
1
11
10
4
SCK Output
(CPOL=0)
(CPOL=1)
3
2
Note: Numbers shown reference Ta b l e 4 0.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale86
Figure 29. DSPI classic SPI timing – Master, CPHA = 1
Figure 30. DSPI classic SPI timing – Slave, CPHA = 0
Data Last Data
First Data
SIN
SOUT
12 11
10
Last Data
Data
First Data
SCK Output
SCK Output
PCSx
9
(CPOL=0)
(CPOL=1)
Note: Numbers shown reference Ta ble 40.
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
12
SCK Input
First Data Last Data
SCK Input
2
(CPOL=0)
(CPOL=1)
Note: Numbers shown reference Table 40.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 87
Figure 31. DSPI classic SPI timing – Slave, CPHA = 1
Figure 32. DSPI modified transfer format timing – Master, CPHA = 0
5 6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL=0)
(CPOL=1)
Note: Numbers shown reference Table 40 .
PCSx
3
1
4
10
4
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
2
(CPOL=0)
(CPOL=1)
Note: Numbers shown reference Table 40.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale88
Figure 33. DSPI modified transfer format timing – Master, CPHA = 1
Figure 34. DSPI modified transfer format timing – Slave, CPHA = 0
PCSx
10
9
12 11
SCK Output
SCK Output
SIN
SOUT
First Data Data Last Data
First Data Data Last Data
(CPOL=0)
(CPOL=1)
Note: Numbers shown reference Ta b l e 4 0.
Last Data
First Data
3
4
1
Data
Data
SIN
SOUT
SS
4
5 6
9
11
10
SCK Input
First Data Last Data
SCK Input
2
(CPOL=0)
(CPOL=1)
12
Note: Numbers shown reference Table 40.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 89
Figure 35. DSPI modified transfer format timing – Slave, CPHA = 1
Figure 36. DSPI PCS strobe (PCSS) timing
5 6
9
12
11
10
Last Data
Last Data
SIN
SOUT
SS
First Data
First Data
Data
Data
SCK Input
SCK Input
(CPOL=0)
(CPOL=1)
Note: Numbers shown reference Table 40.
PCSx
78
PCSS
Note: Numbers shown reference Table 40.
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale90
4 Package characteristics
4.1 Package mechanical data
4.1.1 144 LQFP mechanical outline drawing
L
Figure 37. 144 LQFP package mechanical drawing (part 1)
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 91
Figure 38. 144 LQFP package mechanical drawing (part 2)
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale92
4.1.2 100 LQFP mechanical outline drawing
Figure 39. 100 LQFP package mechanical drawing (part 1)
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 93
Figure 40. 100 LQFP package mechanical drawing (part 2)
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale94
Figure 41. 100 LQFP package mechanical drawing (part 3)
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 95
Table 41.
Symbol
Dimensions
mm inches1
1Values in inches are converted from millimeters (mm) and rounded to four decimal digits.
Min Typ Max Min Typ Max
A — — 1.600 — — 0.0630
A1 0.050 — 0.150 0.0020 — 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 — 0.200 0.0035 — 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 — 12.000 — — 0.4724 —
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 — 12.000 — — 0.4724 —
e — 0.500 — — 0.0197 —
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 — 1.000 — — 0.0394 —
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc2
2Tolerance
0.08 0.0031
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale96
5 Ordering information
Figure 42. Commercial product code structure
Qualification Status
Power Architecture Core
Automotive Platform
Core Version
Flash Size (core dependent)
Product
Optional Fields
MPC56 PGF0M
Example code: 04
Temperature spec.
Package Code
Qualification Status
M = MC status
S = Automotive qualified
P = PC status
Automotive Platform
56 = Power Architecture in 90 nm
Core Version
0 = e200z0
Flash Size (z0 core)
3 = 384 KB
4 = 512 KB
Product
P = MPC560xP family
Optional fields
E = Data Flash (blank if none)
F = FlexRay (blank if none)
G = Data Flash + FlexRay
Frequency
LQ
Temperature spec.
V = –40 to 105 °C
M = –40 to 125 °C
Package Code
LL = 100 LQFP
LQ = 144 LQFP
Frequency
4 = 40 MHz
6 = 64 MHz
Fab & Mask Revision
R = Tape & Reel (blank if Tray)
6R
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 97
Appendix A Abbreviations
Table A-1 lists abbreviations used in this document.
Table A-1. Abbreviations
Abbreviation Meaning
CMOS Complementary metal–oxide–semiconductor
CPHA Clock phase
CPOL Clock polarity
CS Peripheral chip select
DUT Device under test
ECC Error code correction
EVTO Event out
GPIO General purpose input/output
MC Modulus counter
MCKO Message clock out
MCU Microcontroller unit
MDO Message data out
MSEO Message start/end out
MTFE Modified timing format enable
NPN Negative-positive-negative
NVUSRO Non-volatile user options register
PTF Post trimming frequency
PWM Pulse width modulation
RBW Resolution bandwidth
SCK Serial communications clock
SOUT Serial data out
TCK Test clock input
TDI Test data input
TDO Test data output
TMS Test mode select
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale98
6 Document revision history
Table 42 summarizes revisions to this document.
Table 42. Revision history
Revision Date Substantive changes
Rev. 1 Aug 2008 Initial release
Rev. 2 Nov 2008 Table 5:
TDO and TDI pins (Port pins B[4:5] are single function pins.
Table 10, Tab le 11 :
Thermal characteristics added.
Table 11, Table 12:
EMI testing specifications split into separate tables for Normal mode and Airbag mode;
data to be added in a later revision.
Table 16, Tab le 1 7 , Table 19, Table 20 :
Supply current specifications split into separate tables for Normal mode and Airbag mode;
data to be added in a later revision.
Table 21:
• Values for IOL and IOH (in Conditions column) changed.
• Max values for VOH_S, VOH_M, VOH_F and VOH_SYM deleted.
•V
ILR max value changed.
•I
PUR min and max values changed.
Table 27:
Sensitivity value changed.
Table 30:
Most values in table changed.
Rev. 3 Feb 2009 • Description of system requirements, controller characteristics and how controller
characteristics are guaranteed updated.
• Electrical parameters updated.
• EMI characteristics are now in one table; values have been updated.
• ESD characteristics are now in one table.
• Electrical parameters are identified as either system requirements or controller
characteristics. Method used to guarantee each controller characteristic is noted
in table.
• AC Timings: 1149.1 (JTAG) Timing, Nexus Timing, External Interrupt Timing,
and DSPI Timing sections deleted
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 99
Rev. 4 24-Jun-2009 Through all document:
– Replaced all “RESET_B” occurrences with “RESET” through all document.
– AC Timings: 1149.1 (JTAG) Timing, Nexus Timing, External Interrupt Timing, and
DSPI Timing sections inserted again.
– Electrical parameters updated.
–
Table 2
– Added row for Data Flash.
Table 3
– Added a footnote regarding the decoupling capacitors.
Table 5
– Removed the “other function“ column.
– Rearranged the contents.
Table 15
– Updated definition of Condition column.
Table 20
– merged in an unique Table the power consumption data related to "Maximum
mode" and "Airbag mode".
Table 22
– merged in an unique Table the power consumption data related to "Maximum
mode" and "Airbag mode".
Table 30
– Updated the parameter definition of RCMVAR.
– Removed the condition definition of RCMVAR.
Table 30
– Added tADC_C and TUE rows.
Table 31
– Added tADC_C and TUE rows.
– Removed Rsw2.
Table 34
– Added.
Table 29
– Updated and added footnotes.
Section 3.17.1, “RESET pin characteristics
– Replaces whole section.
Table 38
– Renamed the “Flash (KB)“ heading column in “Code Flash / Data Flash (EE) (KB)“
– Replaced the value of RAM from 32 to 36KB in the last four rows.
Table 42. Revision history (continued)
Revision Date Substantive changes
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale100
Rev. 5 06-Oct-2009 - Removed B[4] and B[5] rows from “Pin muxing” table and inserted them on “System
pins” table.
- Updated package pinout.
- Rewrote entirely section “Power Up/dpwn Sequencing“ section.
- Renamend “VDD_LV_PLL“ and “VSS_LV_PLL“ supply pins with respectively “VDD_LV_COR3“
and “VSS_LV_COR3”.
- Added explicative figures on “Electrical characteristics” section.
- Updated “Thermal characteristics“ for 100-pin.
- Proposed two different configuration of “voltage regulator. - Inserted Power Up/Down
sequence.
- Added explicative figures on “DC Electrical characteristics”.
- Added “I/O pad current specification” section.
- Renamed the “Airbag mode” with “Typical mode“and updated the values on “supply
current” tables.
Rev. 6 12-Feb-2010 Inserted label of Y-axis in the “Independent ADC supply“ figure.
“Recommended Operating Conditions” tables:
Updated the TA value
Moved the TJ row to “Absolute Maximum Ratings“ table.
Rewrite note 1 and 3
Inverted Min a Typ value of CDEC2 on ”Voltage Regulator Electrical Characteristics” table.
Removed an useless duplicate of “Voltage Regulator Electrical Characteristics“ table.
Inserted the name of CS into “Input Equivalent Circuit“ figure.
Removed leakage Ivpp from datasheet.
Updated “Supply Current” tables.
Added note on “Output pin transition times“ table.
Updated ”Temperature Sensor Electrical Characteristics” table.
Updated “16 MHz RC Oscillator Electrical Characteristics” table.
Removed the note about the condition from “Flash read access timing“ table.
Removed the notes that assert the values need to be confirmed before validation.
Table 42. Revision history (continued)
Revision Date Substantive changes
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 101
Rev. 7 07-Apr-2011 Formatting and editorial changes throughout
Removed all content referencing Junction Temperature Sensor
Section 1, “Introduction: changed title (was: Overview); reorganized contents
MPC5604P device comparison:
• ADC feature: changed “16 channels” to “15-channel”; added footnote to to indicate that
four channels are shared between the two ADCs
• removed MPC5602P column
• indicated that data flash memory is an optional feature
• indicated that FlexRay is an optional feature
• changed “dual channel” to “selectable single or dual channel support” in FlexRay
footnote
• updated “eTimer” feature
• updated footnote relative to “Digital power supply” feature
Updated MPC5604P block diagram
Added MPC5604P series block summary
Added Section 1.5, “Feature details
Section 2.1, “Package pinouts: removed alternate functions from pinout diagrams
Supply pins: updated descriptions of power supply pins (1.2 V)
System pins: updated table
Pin muxing: added rows “B[4]” and “B[5]
Section 3.3, “Absolute maximum ratings: added voltage specifications to titles of Figure 4
and Figure 5; in Table 7, changed row “VSS_HV / Digital Ground” to “VSS / Device
Ground”; updated symbols
Section 3.4, “Recommended operating conditions: added voltage specifications to titles
of Figure 6 and Figure 7
Recommended operating conditions (5.0 V), and Recommended operating conditions
(3.3 V): changed row “VSS_HV / Digital Ground” to “VSS / Device Ground”; updated
symbols
Updated Section 3.5.1, “Package thermal characteristics
Updated Section 3.6, “Electromagnetic interference (EMI) characteristics
Section 3.8.1, “Voltage regulator electrical characteristics: amended titles of Table 15 and
Table 17
Voltage regulator electrical characteristics (configuration without resistor on base) and
Voltage regulator electrical characteristics (configuration with resistor on base):
updated symbol and values for VDD_LV_REGCOR
Low voltage monitor electrical characteristics: Updated VMLVDDOK_H max value—was
1.15 V; is 1.145 V
Section 3.10, “DC electrical characteristics: reorganized contents
Updated Section 3.10.1, “NVUSRO register (includes adding
“NVUSRO[OSCILLATOR_MARGIN] field description” table
Supply current (5.0 V, NVUSRO[PAD3V5V] = 0): updated symbols
Table 42. Revision history (continued)
Revision Date Substantive changes
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale102
Rev. 7
(cont’d)
07-Apr-2011 Corrected parameter descriptions in DC electrical characteristics (3.3 V,
NVUSRO[PAD3V5V] = 1):
•V
OL_F—was “Fast, high level output voltage”; is “Fast, low level output voltage”
•V
OL_SYM—was “Symmetric, high level output voltage”; is “Symmetric, low level output
voltage”
Supply current (3.3 V, NVUSRO[PAD3V5V] = 1): updated symbols
Main oscillator output electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0):
replaced instances of EXTAL with XTAL
Main oscillator output electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1):
replaced instances of EXTAL with XTAL
FMPLL electrical characteristics: replaced “PLLMRFM” with “FMPLL” in table title;
updated conditions; removed fsys row; updated fFMPLLOUT min value
ADC conversion characteristics: updated symbols; added row tADC_PU
Flash memory read access timing: added footnote to “Conditions” column
Section 3.16.1, “Pad AC specifications: added Pad output delay diagram
In the range of figures “DSPI Classic SPI Timing — Master, CPHA = 0” to “DSPI PCS
Strobe (PCSS) Timing”: added note
Removed Orderable Part Number Summary table
Updated “Commercial product code structure” figure
Table A-1: Added abbreviations “DUT”, “NPN”, and “RBW”
Table 42. Revision history (continued)
Revision Date Substantive changes
MPC5604P Microcontroller Data Sheet, Rev. 8
Freescale 103
Rev. 8 23-May-2012 Section 1.5.4, “Flash memory: Changed “Data flash memory: 32-bit ECC” to “Data flash
memory: 64-bit ECC”
Figure 42 (Commercial product code structure), replaced "C = 60 MHz, 5 V" and "D = 60
MHz, 3.3 V" with respectively "C = 40 MHz, 5 V" and "D = 40 MHz, 3.3 V"
Table 7 (Absolute maximum ratings), updated TVDD parameter, the minimum value to
3.0 V/s and the maximum value to 0.5 V/µs
Table 5 (Pin muxing), changed the description in the column "I/O direction" from "I/O" to
"O" for the following port pins:
A[10] with function B[0]
A[11] with function A[0]
A[11] with function A[2]
A[12] with function A[2]
A[12] with function B[2]
A[13] with function B[2]
C[7] with function A[1]
C[10] with function A[3]
C[15] with function A[1]
D[0] with function B[1]
D[10] with function A[0]
D[11] with function B[0]
D[13] with function A[1]
D[14] with function B[1]
Updated Section 3.8.1, “Voltage regulator electrical characteristics
Added Table 25 (I/O consumption)
Section 3.10, DC electrical characteristics:
deleted references to “oscillator margin”
deleted subsection “NVUSRO[OSCILLATOR_MARGIN] field description”
Table 19 (DC electrical characteristics (5.0 V, NVUSRO[PAD3V5V] = 0)), added IPU row
for RESET pin
Table 21 (DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V] = 1)), added IPU row
for RESET pin
Table 31 (ADC conversion characteristics), added VINAN entry
Removed “Order codes” table
Table 42. Revision history (continued)
Revision Date Substantive changes
Document Number: MPC5604P
Rev. 8
07/2012
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