IBM043616CXLBC
IBM041816CXLBC
16Mb (512K x 36 & 1M x 18) SRAM
Page 12 of 24
CXLBCds.fm.00
June 3, 2002
AC Characteristics (TA = 0 to +85°C, VDD = 2.5 V ± 5%)
Symbol Parameter -20 -25 -27 -28 -30 Units Notes
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tKHKH Cycle Time 2.0 2.5 2.7 2.8 3.0 ns
tKHKL Clock High Pulse Width 0.9 1.2 1.2 1.2 1.4 ns
tKLKH Clock Low Pulse Width 0.9 1.2 1.2 1.2 1.4 ns
tAVKH Address Setup Time 0.4 0.4 0.4 0.4 0.4 ns 1, 6, 8
tKHAX Address Hold Time 0.4 0.4 0.4 0.4 0.4 ns 1, 8
tBVKH Function Control (B1, B2, B3) Setup
Time 0.4 0.4 0.4 0.4 0.4 ns 1, 8
tKHBX Function Control (B1, B2, B3) Hold
Time 0.4 0.4 0.4 0.4 0.4 ns 1, 8
tDVKH Data-In Setup Time 0.17 0.21 0.30 0.30 0.30 ns 1, 9, 6, 8
tKHDX Data-In Hold Time 0.17 0.21 0.30 0.30 0.30 ns 1, 9, 6, 8
tINPW Input Pulse Width 0.8 1.0 1.0 1.0 1.2
tCHCL Echo Clock (CQ) High Pulse Width tKHKL
-0.1
tKHKL
+0.1
tKHKL
-0.1
tKHKL
+0.1
tKHKL
-0.1
tKHKL
+0.1
tKHKL
-0.1
tKHKL
+0.1
tKHKL
-0.1
tKHKL
+0.1 ns 1, 3, 6
tCLCH Echo Clock (CQ) Low Pulse Width tKLKH
-0.1
tKLKH
+0.1
tKLKH
-0.1
tKLKH
+0.1
tKLKH
-0.1
tKLKH
+0.1
tKLKH
-0.1
tKLKH
+0.1
tKLKH
-0.1
tKLKH
+0.1 ns 1, 3, 6
tKXCV Clock (CK) crossing to Echo clock
(CQ) Valid 0.8 2.3 0.8 1.8 0.8 1.8 0.8 1.8 0.8 1.7 ns 1, 2, 4, 6,
7
tKXQV Clock (CK) crossing to Output Valid 0.8 2.3 0.8 1.8 0.8 1.8 0.8 1.8 0.8 1.7 ns 1, 2, 6, 7
tKXQZ Clock (CK) crossing to Output High-Z 0.8 2.3 0.8 1.8 0.8 1.8 0.8 1.8 0.8 1.7 ns 1, 2, 7
tKXQLZ Clock (CK) crossing to Output Active 0.8 2.3 0.8 1.8 0.8 1.8 0.8 1.8 0.8 1.7 ns 1, 2, 6, 7
tQVTRK
Echo Clock (CQ) Valid to Output Valid
Tracking (tKXCV - tKXQV)-0.2 0.2 -0.2 0.2 -0.2 0.2 -0.2 0.2 -0.2 0.2 ns 1, 3, 5, 6
tQZTRK
Echo Clock (CQ) Valid to Output
High-Z Tracking (tKXCV - tKXQZ)-0.2 0.2 -0.2 0.2 -0.2 0.2 -0.2 0.2 -0.2 0.2 ns 1, 3, 5, 6
tQLZ-
TRK
Echo Clock (CQ) Valid to Output
Active Tracking (tKXCV - tKXQLZ)-0.2 0.2 -0.2 0.2 -0.2 0.2 -0.2 0.2 -0.2 0.2 ns 1, 3, 5, 6
tGHQZ Output Enable (G) High to High-Z — 1.4 — 1.7 — 1.7 — 1.7 — 2.0 ns 3
tGLQV Output Enable (G) Low to Output
Valid 0.5 1.4 0.5 1.7 0.5 1.7 0.5 1.7 0.5 2.0 ns 2, 3
1. See AC Test Loading on page 11. To guarantee AC timing specifications, AC test conditions must be met.
2. Maximum is tested at 2.38V and 85°C. Minimum is tested at 2.75V and 0°C.
3. These parameters may not be tested at the values shown in this table, and may only be guaranteed by design.
4. Echo clock (CQ) Valid refers to CQ and CQ rising and falling edges.
5. The tracking between echo-clock access times and DQ access times is across all cycle boundaries for any given SRAM address
and function pattern.
6. CK and CK clocks must be used differentially in order to meet specification.
7. Access pushes out as cycle time decreases.
8. To guarantee AC characteristics; VIH, VIL, Trise, and Tfall of inputs and clocks must be within 20% of each other. If these conditions
are not met then:
• Setup time is measured from clock crossing to inputs at their switched VIHAC, VILAC levels.
• Hold time is measured from clock crossing to inputs switching out of their valid VIHAC, VILAC levels.
9. Guaranteed by design and tested without guardband.