S3C9404/P9404/C9414/P9414 1 PRODUCT OVERVIEW PRODUCT OVERVIEW SAM87RI PRODUCT FAMILY Samsung's SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations. S3C9404/C9414 MICROCONTROLLER The S3C9404/C9414 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM87Ri CPU core. The S3C9404/C9414 is a versatile microcontroller, with its A/D converter and a zero-crossing detection capability it can be used in a wide range of general purpose applications. Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The S3C9404/C9414 has 4-Kbytes of program memory on-chip (ROM) and 208-bytes of general purpose register area RAM. Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core: -- Four configurable I/O ports (S3C9404: 22 pins, S3C9414: 16 pins) -- Six interrupt sources with one vector and one interrupt level -- Two 8-bit timer/counter with various operating modes -- Analog to digital converter (S3C9404: 8-bit, 8-channel, S3C9414: 10-bit, 5-channel) -- One zero cross detection module The S3C9404/C9414 microcontroller is ideal for use in a wide range of electronic applications requiring simple timer/counter, PWM, ADC, ZCD and capture functions. S3C9404 is available in a 30-pin SDIP and a 32-pin SOP package. S3C9414 is available in a 24-pin SDIP and a 24-pin SOP package. OTP The S3P9404/P9414 is an OTP (one time programmable) version of the S3C9404/C9414 microcontroller. The S3P9404/P9414 has on-chip 4-Kbyte one-time programmable EEPROM instead of masked ROM. The S3P9404/P9414 is fully compatible with the S3C9404/C9414, in function, in D.C. electrical characteristics and in pin configuration. 1-1 PRODUCT OVERVIEW S3C9404/P9404/C9414/P9414 FEATURES CPU Timer/Counter * * One 8-bit basic timer for watchdog function * One 8-bit timer/counter with three operating modes (10-bit PWM 1ch) * One 8-bit timer/counter for the zero-crossing detection circuit SAM87Ri CPU core Memory * 4-Kbyte internal program memory (ROM) * 208-byte general purpose register area (RAM) Instruction Set Zero-Crossing Detection Circuit * 41 instructions * * IDLE and STOP instructions added for power-down modes. Instruction Execution Time * 600 ns at 10 MHz fOSC (minimum) Zero-crossing detection circuit that generates a digital signal in synchronism with an AC signal input Buzzer Frequency Range * 200 Hz to 20 kHz signal can be generated Operating Temperature Range Interrupts * 6 interrupt sources with one vector and one level interrupt structure * - 40C to + 85C Operating Voltage Range Oscillation Frequency * * 1 MHz to 10 MHz external crystal oscillator OTP Interface Protocol Spec * Maximum 10 MHz CPU clock * * 4 MHz RC oscillator 2.7 V to 5.5 V Serial OTP Package Types General I/O * 30-pin SDIP, 32-pin SOP for S3C9404/P9404 * Four I/O ports (22 pins for S3C9404, 16 pins for S3C9414) * 24-pin SDIP, 24-pin SOP for S3C9414/P9414 * Bit programmable ports A/D Converter * Eight analog input pins * 8-bit conversion resolution (S3C9404) * 10-bit conversion resolution (S3C9414) 1-2 S3C9404/P9404/C9414/P9414 PRODUCT OVERVIEW BLOCK DIAGRAM P0.0-P0.7 BASIC TIMER XIN XOUT PORT 0 P1.0-P1.3 /ZCD,BUZ,T0,CLO PORT 1 OSC I/O PORT I/O and INTERRUPT CONTROL T0(PWM) TIMER 0 P1.1/BUZ TIMER 1 PORT 2 P2.0-P2.3 /INT0-INT1 /ADC6-ADC7 SAM87RI CPU ADC0 -ADC7 ADC P1.0/ ZCD ZCD PORT 3 4-KB ROM P3.0-P3.5 /ADC0-ADC5 208-BYTE REGISTER FILE Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C9404/P9404/C9414/P9414 PIN ASSIGNMENTS VSS XIN XOUT TEST P0.1 P0.0 RESET P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S3C9404 30-SDIP (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P1.3 / CLO P2.0 / INT0 P2.1 / INT1 P2.2 / ADC6 P2.3 / ADC7 Figure 1-2. Pin Assignment Diagram (30-Pin SDIP Package) VSS XIN XOUT TEST P0.1 P0.0 RESET NC P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3C9404 32-SOP (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 NC P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P1.3 / CLO P2.0 / INT0 P2.1 / INT1 P2.2 / ADC6 P2.3 / ADC7 Figure 1-3. Pin Assignment Diagram (32-Pin SOP Package) 1-4 S3C9404/P9404/C9414/P9414 PRODUCT OVERVIEW VSS XIN XOUT TEST P0.1 P0.0 RESET P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 1 2 3 4 5 6 7 8 9 10 11 12 S3C9414 24-SDIP (Top View) 24 23 22 21 20 19 18 17 16 15 14 13 VDD P0.2 P0.3 P0.4 P0.5 P0.6 P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P2.0 / INT0 AVref AVSS Figure 1-4. Pin Assignment Diagram (24-Pin SDIP Package) VSS XIN XOUT TEST P0.1 P0.0 RESET P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 1 2 3 4 5 6 7 8 9 10 11 12 KS86C4104 24-SOP (Top View) 24 23 22 21 20 19 18 17 16 15 14 13 VDD P0.2 P0.3 P0.4 P0.5 P0.6 P1.0 / ZCD P1.1 / BUZ P1.2 / T0(PWM) P2.0 / INT0 AVref AVSS Figure 1-5. Pin Assignment Diagram (24-Pin SOP Package) 1-5 PRODUCT OVERVIEW S3C9404/P9404/C9414/P9414 PIN DESCRIPTIONS Table 1-1. S3C9404/C9414 Pin Descriptions Pin Names Pin Type Pin Description Circuit Type P0.0-P0.7 I/O Bit-programmable I/O port for normal input or push-pull, open-drain output. Pull-up resistors are assignable by software. E-2 P1.0-P1.3 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 1 pins can also be used as alternative functions. F D D D ZCD BUZ T0(PWM) CLO P2.0-P2.3 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull, open drain output. Pull up resistors are assignable by software. Port 2 can also be used as external interrupt, A/D input. E E-1 INT0-INT1 ADC6-ADC7 P3.0-P3.5 I/O Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port 3 pins can also be used as A/D converter input. F ADC0-ADC5 XIN, XOUT - Crystal/ceramic, or RC oscillator signal for system clock. - - INT0-INT1 I External interrupt input. E P2.0-P2.1 RESET I System RESET signal input pin. B - TEST I Test signal input pin (for factory use only: must be connected to VSS) - - VDD, VSS - Voltage input pin and ground - - AVREF, AVSS - A/D converter reference voltage input and ground - - ZCD I Zero crossing detector input F P1.0 BUZ O 200 Hz-20 kHz frequency output for buzzer sound D P1.1 T0 I/O Timer 0 capture input or 10-bit PWM output D P1.2 CLO O System clock output port D P1.3 ADC0-ADC7 I A/D converter input F E-1 P3.0-P3.5 P2.2-P2.3 NOTE: Port 0.7, P1.3, P2.1-P2.3 and P3.5 is not available in S3C9414/P4104 . 1-6 Share Pins S3C9404/P9404/C9414/P9414 PRODUCT OVERVIEW PIN CIRCUITS VDD VDD P-CHANNEL P-CHANNEL DATA OUT IN N-CHANNEL N-CHANNEL OUTPUT DISABLE Figure 1-6. Pin Circuit Type A Figure 1-8. Pin Circuit Type C VDD PULL-UP RESISTOR VDD PULL-UP RESISTOR RESISTOR ENABLE DATA IN OUTPUT DISABLE P-CHANNEL CIRCUIT TYPE C IN/OUT DATA Figure 1-7. Pin Circuit Type B Figure 1-9. Pin Circuit Type D 1-7 PRODUCT OVERVIEW S3C9404/P9404/C9414/P9414 VDD VDD VDD VDD PULL-UP RESISTOR PNE P-CH PULL-UP RESISTOR PNE PULL-UP ENABLE DATA IN/OUT P-CH PULL-UP ENABLE DATA IN/OUT N-CH N-CH OUTPUT DISABLE OUTPUT DISABLE INPUT INPUT Figure 1-10. Pin Circuit Type E Figure 1-10. Pin Circuit Type E-2 VDD VDD VDD PULL-UP RESISTOR PNE P-CH PULL-UP ENABLE PULL-UP RESISTOR PULL-UP ENABLE VDD DATA DATA IN/OUT N-CH OUTPUT DISABLE OUTPUT DISABLE CIRCUIT TYPE C DIGITAL INPUT DIGITAL INPUT ANALOG INPUT ANALOG INPUT Figure 1-11. Pin Circuit Type E-1 1-8 Figure 1-12. Pin Circuit Type F IN/OUT S3C9404/P9404/C9414/P9414 2 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C9404/C9414 microcontroller has two kinds of address space: -- Internal program memory (ROM) -- Internal register file A 12-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file. The S3C9404/C9414 has 4-Kbytes of mask-programmable on-chip program memory: which is configured as the Internal ROM mode, all of the 4-Kbyte internal program memory is used. The S3C9404/C9414 microcontroller has 208 general-purpose registers in its internal register file. Thirty-two bytes in the register file are mapped for system and peripheral control functions. 2-1 ADDRESS SPACES S3C9404/P9404/C9414/P9414 PROGRAM MEMORY (ROM) Normal Operating Mode The S3C9404/C9414 has 4-Kbytes (locations 0H-0FFFH) of internal mask-programmable program memory. The first 2-bytes of the ROM (0000H-0001H) are interrupt vector address. Unused locations (0002H-00FFH) can be used as normal program memory. The program reset address in the ROM is 0100H. (DECIMAL) (HEX) 4,095 0FFFH 4-KBYTE PROGRAM MEMORY AREA 256 Program start 2 1 INTERRUPT VECTOR 0 0100H 0002H 0001H 0000H Figure 2-1. Program Memory Address Space 2-2 S3C9404/P9404/C9414/P9414 ADDRESS SPACES REGISTER ARCHITECTURE The upper 64-bytes of the S3C9404/C9414's internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 192-bytes of internal register file(00H-BFH) is called the general purpose register space. The total addressable register space is thereby 256-bytes. 240 registers in this space can be accessed; 208 are available for general-purpose use. For many SAM87Ri microcontrollers, the addressable area of the internal register file is further expanded by additional register pages at the general purpose register space (00H-BFH). This register file expansion is not implemented in the S3C9404/C9414, however. The specific register types and the area (in bytes) that they occupy in the internal register file are summarized in Table 2-1. Table 2-1. Register Type Summary Register Type Number of Bytes CPU and system control registers 10 Peripheral, I/O, and clock control and data registers 22 General-purpose registers (including the 16-bit common working register area) 208 Total Addressable Bytes 240 2-3 ADDRESS SPACES S3C9404/P9404/C9414/P9414 FFH PERIPHERAL CONTROL REGISTERS 64 BYTES OF COMMON AREA E0H DFH SYSTEM REGISTERS D0H CFH WORKING REGISTERS C0H BFH GENERAL PURPOSE REGISTERS OR STACK AREA (PAGE 0) 192 BYTES 00H Figure 2-2. Internal Register File Organization 2-4 S3C9404/P9404/C9414/P9414 ADDRESS SPACES COMMON WORKING REGISTER AREA (C0H-CFH) The SAM87Ri register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. This16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages. However, because the S3C9404/C9414 uses only page 0, you can use the common area for any internal data operation. The Register (R) addressing mode can be used to access this area Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. MSB LSB Rn Rn + 1 n = EVEN ADDRESS Figure 2-3. 16-Bit Register Pairs + PROGRAMMING TIP -- Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H-CFH, using working register addressing mode only. Examples: 1. LD 0C2H,40H ; Invalid addressing mode! Use working register addressing instead: LD R2,40H ; R2 (C2H) the value in location 40H 2. ADD 0C3H,#45H ; Invalid addressing mode! Use working register addressing instead: ADD R3,#45H ; R3 (C3H) R3 + 45H 2-5 ADDRESS SPACES S3C9404/P9404/C9414/P9414 SYSTEM STACK S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9404/C9414 architecture supports stack operations in the internal register file. Stack Operations Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address is always decremented before a push operation and incremented after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-4. HIGH ADDRESS PCL PCL TOP OF STACK PCH PCH STACK CONTENTS AFTER A CALL INSTRUCTION TOP OF STACK LOW ADDRESS FLAGS STACK CONTENTS AFTER AN INTERRUPT Figure 2-4. Stack Operations Stack Pointer (SP) Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C9404/C9414, the SP must be initialized to an 8bit value in the range 00H-0C0H. NOTE In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This means that a Stack Pointer access invalid stack area. 2-6 S3C9404/P9404/C9414/P9414 ADDRESS SPACES + PROGRAMMING TIP -- Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SP,#0C0H ; SP C0H (Normally, the SP is set to 0C0H by the ; initialization routine) SYM R15 20H R3 ; ; ; ; Stack address 0BFH Stack address 0BEH Stack address 0BDH Stack address 0BCH R3 20H R15 SYM ; ; ; ; R3 Stack address 0BCH 20H Stack address 0BDH R15 Stack address 0BEH SYM Stack address 0BFH * * * PUSH PUSH PUSH PUSH SYM R15 20H R3 * * * POP POP POP POP 2-7 S3C9404/P9404/C9414/P9414 3 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM87Ri instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. The SAM87Ri instruction set supports six explicit addressing modes. Not all of these addressing modes are available for each instruction. The addressing modes and their symbols are as follows: -- Register (R) -- Indirect Register (IR) -- Indexed (X) -- Direct Address (DA) -- Relative Address (RA) -- Immediate (IM) 3-1 ADDRESSING MODES S3C9404/P9404/C9414/P9414 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses an 16-byte working register space in the register file and an 4-bit register within that space (see Figure 3-2). PROGRAM MEMORY REGISTER FILE 8-BIT REGISTER FILE ADDRESS dst OPCODE ONE-OPERAND INSTRUCTION (EXAMPLE) OPERAND POINTS TO ONE REGISTER IN REGISTER FILE VALUE USED IN INSTRUCTION EXECUTION SAMPLE INSTRUCTION: DEC CNTR ; Where CNTR is the label of an 8-bit register address Figure 3-1. Register Addressing REGISTER FILE CFH PROGRAM MEMORY 4-BIT WORKING REGISTER 4 LSBs dst TWOOPERAND INSTRUCTION (EXAMPLE) src OPCODE OPERAND POINTS TO THE WORKING REGISTER (1 OF 16) SAMPLE INSTRUCTION: ADD R1,R2 ; Where R1=C1H and R2=C2H Figure 3-2. Working Register Addressing 3-2 . . . . C0H S3C9404/P9404/C9414/P9414 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. REGISTER FILE PROGRAM MEMORY 8-BIT REGISTER FILE ADDRESS dst POINTS TO ONE REGISTER IN REGISTER FILE OPCODE ONE-OPERAND INSTRUCTION (EXAMPLE) ADDRESS ADDRESS OF OPERAND USED BY INSTRUCTION VALUE USED IN INSTRUCTION EXECUTION OPERAND SAMPLE INSTRUCTION: RL @SHIFT ; Where SHIFT is the label of an 8-bit register address Figure 3-3. Indirect Register Addressing to Register File 3-3 ADDRESSING MODES S3C9404/P9404/C9414/P9414 INDIRECT REGISTER ADDRESSING MODE (Continued) REGISTER FILE PROGRAM MEMORY REGISTER EXAMPLE INSTRUCTION REFERENCES PROGRAM MEMORY dst OPCODE PAIR POINTS TO REGISTER PAIR PROGRAM MEMORY SAMPLE INSTRUCTIONS: CALL JP @RR2 @RR2 VALUE USED IN INSTRUCTION OPERAND Figure 3-4. Indirect Register Addressing to Program Memory 3-4 16-BIT ADDRESS POINTS TO PROGRAM MEMORY S3C9404/P9404/C9414/P9414 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) REGISTER FILE CFH . . . . PROGRAM MEMORY 4-BIT WORKING REGISTER ADDRESS dst src OPCODE 4 LSBs OPERAND POINTS TO THE WORKING REGISTER (1 OF 16) C0H SAMPLE INSTRUCTION: OR R6,@R2 VALUE USED IN INSTRUCTION OPERAND Figure 3-5. Indirect Working Register Addressing to Register File 3-5 ADDRESSING MODES S3C9404/P9404/C9414/P9414 INDIRECT REGISTER ADDRESSING MODE (Concluded) REGISTER FILE CFH PROGRAM MEMORY 4-BIT WORKING REGISTER ADDRESS EXAMPLE INSTRUCTION REFERENCES EITHER PROGRAM MEMORY OR DATA MEMORY dst . . . . src OPCODE NEXT 3 BITS POINT TO WORKING REGISTER PAIR (1 OF 8) REGISTER PAIR LSB SELECTS PROGRAM MEMORY OR DATA MEMORY VALUE USED IN INSTRUCTION C0H OPERAND SAMPLE INSTRUCTIONS: LDC LDE LDE R5,@RR2 R3,@RR14 @RR4,R8 ; Program memory access ; External data memory access ; External data memory access Figure 3-6. Indirect Working Register Addressing to Program or Data Memory 3-6 16-BIT ADDRESS POINTS TO PROGRAM MEMORY OR DATA MEMORY S3C9404/P9404/C9414/P9414 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range - 128 to + 127. This applies to external memory accesses only (see Figure 3-8). For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address (see Figure 3-9). The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented. REGISTER FILE ~ ~ VALUE USED IN INSTRUCTION OPERAND + PROGRAM MEMORY ~ ~ X(OFFSET) TWOOPERAND INSTRUCTION EXAMPLE src dst OPCODE 4 LSBs POINTS TO ONE OF THE WORKING REGISTERS (1 OF 16) INDEX SAMPLE INSTRUCTION: LD R0,#BASE[R1] ; Where BASE is an 8-bit immediate value Figure 3-7. Indexed Addressing to Register File 3-7 ADDRESSING MODES S3C9404/P9404/C9414/P9414 INDEXED ADDRESSING MODE (Continued) REGISTER FILE PROGRAM MEMORY 4-BIT WORKING REGISTER ADDRESS XS(OFFSET) dst NEXT 3 BITS src REGISTER PAIR 16-BIT ADDRESS ADDED TO OFFSET POINT TO WORKING REGISTER PAIR (1 OF 8) OPCODE LSB SELECTS + 8 BITS 16 BITS PROGRAM MEMORY OR DATA MEMORY 16 BITS OPERAND VALUE USED IN INSTRUCTION SAMPLE INSTRUCTIONS: LDC R4,#04H[RR2] ; The values in the program address (RR2 + #04H) are loaded into register R4. LDE R4,#04H[RR2] ; Identical operation to LDC example, except that external program memory is accessed. Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset 3-8 S3C9404/P9404/C9414/P9414 ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) REGISTER FILE PROGRAM MEMORY XLH (OFFSET) 4-BIT WORKING REGISTER ADDRESS XLL(OFFSET) dst NEXT 3 BITS src REGISTER PAIR 16-BIT ADDRESS ADDED TO OFFSET POINT TO WORKING REGISTER PAIR (1 OF 8) OPCODE LSB SELECTS + 16 BITS 16 BITS PROGRAM MEMORY OR DATA MEMORY 16 BITS OPERAND VALUE USED IN INSTRUCTION SAMPLE INSTRUCTIONS: LDC R4,#1000H[RR2] ; The values in the program address (RR2 + #1000H) are loaded into register R4. LDE R4,#1000H[RR2] ; Identical operation to LDC example, except that external program memory is accessed. Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset 3-9 ADDRESSING MODES S3C9404/P9404/C9414/P9414 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented. PROGRAM OR DATA MEMORY PROGRAM MEMORY MEMORY ADDRESS USED UPPER ADDR BYTE LOWER ADDR BYTE dst / src "0" OR "1" OPCODE LSB SELECTS PROGRAM MEMORY OR DATA MEMORY: "0" = PROGRAM MEMORY "1" = DATA MEMORY SAMPLE INSTRUCTIONS: LDC R5,1234H ; The values in the program address (1234H) are loaded into register R5. LDE R5,1234H ; Identical operation to LDC example, except that external program memory is accessed. Figure 3-10. Direct Addressing for Load Instructions 3-10 S3C9404/P9404/C9414/P9414 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) PROGRAM MEMORY NEXT OPCODE PROGRAM MEMORY ADDRESS USED LOWER ADDR BYTE UPPER ADDR BYTE OPCODE SAMPLE INSTRUCTIONS: JP C,JOB1 ; Where JOB1 is a 16-bit immediate address CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address Figure 3-11. Direct Addressing for Call and Jump Instructions 3-11 ADDRESSING MODES S3C9404/P9404/C9414/P9414 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between - 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. The instructions that support RA addressing is JR. PROGRAM MEMORY NEXT OPCODE PROGRAM MEMORY ADDRESS USED CURRENT PC VALUE DISPLACEMENT CURRENT INSTRUCTION OPCODE + SIGNED DISPLACEMENT VALUE SAMPLE INSTRUCTION: JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128 Figure 3-12. Relative Addressing IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. Immediate addressing mode is useful for loading constant values into registers. PROGRAM MEMORY OPERAND OPCODE (THE OPERAND VALUE IS IN THE INSTRUCTION) SAMPLE INSTRUCTION: LD R0,#0AAH Figure 3-13. Immediate Addressing 3-12 S3C9404/P9404/C9414/P9414 4 CONTROL REGISTERS CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3C9404/C9414 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs. System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the standard register description format. Control register descriptions are arranged in alphabetical order according to register mnemonic. More information about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this manual. 4-1 CONTROL REGISTERS S3C9404/P9404/C9414/P9414 Table 4-1. System and Peripheral control Registers Register Name Mnemonic Hex R/W T0CNT D0H R Timer 0 data register T0DATA D1H R/W Timer 0 control register (high) T0CONH D2H R/W Timer 0 control register (low) T0CONL D3H R/W Clock control register CLKCON D4H R/W System flags register FLAGS D5H R/W D9H R/W Timer 0 counter register Locations D6H-D8H are not mapped. Stack pointer register SP Location DAH is not mapped. Location DBH is reserved. Basic timer control register BTCON DCH R/W Basic timer counter BTCNT DDH R DFH R/W Location DEH is reserved. System mode register 4-2 SYM S3C9404/P9404/C9414/P9414 CONTROL REGISTERS Table 4-1. System and Peripheral Control Registers (Continued) Register Name Mnemonic Hex R/W Port 0 data register P0 E0H R/W Port 1 data register P1 E1H R/W Port 2 data register P2 E2H R/W Port 3 data register P3 E3H R/W Locations E4H-E5H are not mapped. Port 0 control register P0CON E6H R/W Port 0 pull-up resistor enable register P0PUR E7H R/W Port 0 N-channel open-drain mode register P0PNE E8H R/W Port 1 control register P1CON E9H R/W Port 2 control register P2CON EAH R/W P2DPUR EBH R/W P2PND ECH R/W Port 2 open-drain, pull-up resistor enable Port 2 interrupt pending register Location EDH is not mapped. Port 3 control register (high byte) P3CONH EEH R/W Port 3 control register (low byte) P3CONL EFH R/W Locations F0H-F1H are not mapped. Timer 1 counter register T1CNT F2H R Timer 1 control register T1CON F3H R/W Timer 1 data register T1DATA F4H R/W Zero-crossing detector control register ZCMOD F5H R/W 8-bit prescaler for buzzer output BUZPS F6H R/W A/D control register ADCON F7H R/W A/D converter data register (high byte) ADDATAH F8H R A/D converter data register (low byte) ADDATAL F9H R PWMEX FAH R/W T0EXCNT FBH R PWM extension data register PWM extension counter register Locations FCH-FFH are not mapped. 4-3 CONTROL REGISTERS S3C9404/P9404/C9414/P9414 Bit number(s) that is/are appended to the register name for bit addressing Register mnemonic Name of individual bit or bit function Register address (hexadecimal) Full register name D5H FLAGS-- System Flags Register Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value Read/Write x R/W x R/W x R/W x R/W x R/W x R/W 0 R/W 0 R/W . 7 Carry Flag (C) 0 Operation does not generate a carry or borrow condition 1 Operation generates carry-out or borrow into high-order bit 7 . 6 Zero Flag (Z) 0 Operation result is a non-zero value 1 Operation result is zero . 5 Sign Flag (S) 0 Operation generates positive number (MSB = "0") 1 Operation generates negative number (MSB = "1") R= W= R/W = '-' = Read-only Write-only Read/write Not used Addressing mode or modes you can use to modify register values Description of the effect of specific bit settings RESET '-' = 'x' = '0' = '1' = Figure 4-1. Register Description Format 4-4 Bit number: MSB = Bit 7 LSB = Bit 0 value notation: Not used Undetermined value Logic zero Logic one S3C9404/P9404/C9414/P9414 CONTROL REGISTERS ADCON -- A/D Converter Control Register F7H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - 0 0 0 0 - - 0 Read/Write - R/W R/W R/W R/W - - R/W .7 Not used for S3C9404/P9404/C9414/P9414 .6-.4 A/D Converter Input Pin Selection Bits .3 0 0 0 ADC0 (P3.0) 0 0 1 ADC1 (P3.1) 0 1 0 ADC2 (P3.2) 0 1 1 ADC3 (P3.3) 1 0 0 ADC4 (P3.4) 1 0 1 ADC5 (P3.5) (Not used for S3C9414/P9414) 1 1 0 ADC6 (P2.2) (Not used for S3C9414/P9414) 1 1 1 ADC7 (P2.3) (Not used for S3C9414/P9414) End-of-Conversion Status Bit 0 A/D conversion is in progress 1 A/D conversion complete .2 and .1 Not used for S3C9404/P9404/C9414/P9414 .0 Conversion Start Bit 0 No meaning 1 A/D conversion start 4-5 CONTROL REGISTERS S3C9404/P9404/C9414/P9414 BTCON -- Basic Timer Control Register DCH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.4 Watchdog Timer Function Enable Bit 1 0 1 0 Others .3 and .2 .1 .0 Disable watchdog timer function Enable watchdog timer function Basic Timer Input Clock Selection Bits 0 0 f OSC/4096 0 1 f OSC/1024 1 0 f OSC/128 1 1 Invalid setting Basic Timer 8-bit Counter Clear Bit (note) 0 No effect 1 Clear basic timer counter value Basic Timer Divider Clear Bit (note) 0 No effect 1 Clear both dividers NOTE: When you write a "1" to BTCON.0 (or BTCON.1), the basic timer divider (or basic timer counter) is cleared. The bit is then cleared automatically to "0". 4-6 S3C9404/P9404/C9414/P9414 CONTROL REGISTERS BUZPS -- 6-Bit Prescaler for Buzzer Output F6H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 .6 .5-.0 Buzzer Output Enable Bit 0 Disable buzzer output (buzzer off) 1 Enable buzzer output (buzzer on) Buzzer Clock Selection Bit 0 Divided by 128 (fx/128) 1 Divided by 32 (fx/32) 6-Bit Prescaler 0 0 0 0 0 0 divided by 2 [fx/(128 or 32)] 0 0 0 0 0 1 divided by 4 [fx/(128 or 32)] 0 0 0 0 1 0 divided by 6 [fx/(128 or 32)] 0 0 0 0 1 1 divided by 8 [fx/(128 or 32)] *** 1 1 1 divided by 2x(n+1) [fx/(128 or 32)] 1 1 1 divided by 128 [fx/(128 or 32)] 4-7 CONTROL REGISTERS S3C9404/P9404/C9414/P9414 CLKCON --System Clock Control Register D4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 - - 0 0 - - - R/W - - R/W R/W - - - Read/Write .7 Oscillator IRQ Wake-up Function Enable Bit 0 Enable IRQ for main system oscillator wake-up function 1 Disable IRQ for main system oscillator wake-up function .6 and .5 Not used for S3C9404/P9404/C9414/P9414 .4 and .3 CPU Clock (System Clock) Selection Bits (1) .2-.0 0 0 Divide by 16 (fOSC/16) 0 1 Divide by 8 (fOSC/8) 1 0 Divide by 2 (fOSC/2) 1 1 Non-divided clock (fOSC) (2) Not used for S3C9404/P9404/C9414/P9414 NOTES: 1. After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the appropriate values to CLKCON.3 and CLKCON.4. 2. fOSC means oscillator frequency 4-8 S3C9404/P9404/C9414/P9414 CONTROL REGISTERS FLAGS -- System Flags Register D5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value x x x x x x 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 .6 .5 .4 .3-.0 Carry Flag (C) 0 Operation does not generate a carry or borrow condition 1 Operation generates a carry-out or borrow into high-order bit 7 Zero Flag (Z) 0 Operation result is a non-zero value 1 Operation result is zero Sign Flag (S) 0 Operation generates a positive number (MSB = "0") 1 Operation generates a negative number (MSB = "1") Overflow Flag (V) 0 Operation result is + 127 or - 128 1 Operation result is > + 127 or < - 128 Not used for S3C9404/P9404/C9414/P9414 4-9 CONTROL REGISTERS S3C9404/P9404/C9414/P9414 P0CON -- Port 0 Control Register E6H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 .6 .5 .4 .3 .2 .1 .0 4-10 Port 0, P0.7 Configuration Bits (Not used for S3C9414/P9414) 0 Normal input 1 Push-pull output Port 0, P0.6 Configuration Bits 0 Normal input 1 Push-pull output Port 0, P0.5 Configuration Bits 0 Normal input 1 Push-pull output Port 0, P0.4 Configuration Bits 0 Normal input 1 Push-pull output Port 0, P0.3 Configuration Bits 0 Normal input 1 Push-pull output Port 0, P0.2 Configuration Bits 0 Normal input 1 Push-pull output Port 0, P0.1 Configuration Bits 0 Normal input 1 Push-pull output Port 0, P0.0 Configuration Bits 0 Normal input 1 Push-pull output S3C9404/P9404/C9414/P9414 CONTROL REGISTERS P0PUR -- Port 0 Pull-up Resistor Enable Register E7H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 .6 .5 .4 .3 .2 .1 .0 Port 0.7 Pull-up Resistor Enable Bit (Not used for S3C9414/P9414) 0 Disable pull-up 1 Enable pull-up Port 0.6 Pull-up Resistor Enable Bit 0 Disable pull-up 1 Enable pull-up Port 0.5 Pull-up Resistor Enable Bit 0 Disable pull-up 1 Enable pull-up Port 0.4 Pull-up Resistor Enable Bit 0 Disable pull-up 1 Enable pull-up Port 0.3 Pull-up Resistor Enable Bit 0 Disable pull-up 1 Enable pull-up Port 0.2 Pull-up Resistor Enable Bit 0 Disable pull-up 1 Enable pull-up Port 0.1 Pull-up Resistor Enable Bit 0 Disable pull-up 1 Enable pull-up Port 0.0 Pull-up Resistor Enable Bit 0 Disable pull-up 1 Enable pull-up 4-11 CONTROL REGISTERS S3C9404/P9404/C9414/P9414 P0PNE -- Port 0 N-Channel Open-drain Mode Register E8H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 .6 .5 .4 .3 .2 .1 .0 4-12 Port 0.7 N-Channel Open-drain Enable Bit (Not used for S3C9414/P9414) 0 Configure P0.7 as a push-pull 1 Configure P0.7 as a n-channel open-drain Port 0.6 N-Channel Open-drain Enable Bit 0 Configure P0.6 as a push-pull 1 Configure P0.6 as a n-channel open-drain Port 0.5 N-Channel Open-drain Enable Bit 0 Configure P0.5 as a push-pull 1 Configure P0.5 as a n-channel open-drain Port 0.4 N-Channel Open-drain Enable Bit 0 Configure P0.4 as a push-pull 1 Configure P0.4 as a n-channel open-drain Port 0.3 N-Channel Open-drain Enable Bit 0 Configure P0.3 as a push-pull 1 Configure P0.3 as a n-channel open-drain Port 0.2 N-Channel Open-drain Enable Bit 0 Configure P0.2 as a push-pull 1 Configure P0.2 as a n-channel open-drain Port 0.1 N-Channel Open-drain Enable Bit 0 Configure P0.1 as a push-pull 1 Configure P0.1 as a n-channel open-drain Port 0.0 N-Channel Open-drain Enable Bit 0 Configure P0.0 as a push-pull 1 Configure P0.0 as a n-channel open-drain S3C9404/P9404/C9414/P9414 CONTROL REGISTERS P1CON -- Port 1 Control Register E9H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 and .6 .5 and .4 .3 and .2 .1 and .0 Port 1, P1.3/CLO Configuration Bits (Not used for S3C9414/P9414) 0 0 Schmitt trigger input 0 1 Schmitt trigger input; pull-up resistor enable 1 0 Push-pull output 1 1 Alternative function (CLO output) Port 1, P1.2/T0 Configuration Bits 0 0 Schmitt trigger input (or T0 Capture input) 0 1 Schmitt trigger input; pull-up resistor enable 1 0 Push-pull output 1 1 Alternative function (T0 output: match or PWM) Port 1, P1.1/BUZ Configuration Bits 0 0 Schmitt trigger 0 1 Schmitt trigger input; pull-up resistor enable 1 0 Push-pull output 1 1 Alternative function (BUZ output) Port 1, P1.0 /ZCD Configuration Bits 0 0 Schmitt trigger 0 1 Schmitt trigger input; pull-up resistor enable 1 0 Push-pull output 1 1 Alternative function (ZCD input); ZCD enable 4-13 CONTROL REGISTERS S3C9404/P9404/C9414/P9414 P2CON -- Port 2 Control Register EAH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 and .6 .5 and .4 .3 and .2 .1 and .0 4-14 Port 2, P2.3/AD7 Configuration Bits (Not used for S3C9414/P9414) 0 0 Schmitt trigger input 0 1 Schmitt trigger input 1 0 Push-pull output 1 1 A/D converter input (AD7); Schmitt trigger input off Port 2, P2.2/AD6 Configuration Bits (Not used for S3C9414/P9414) 0 0 Schmitt trigger input 0 1 Schmitt trigger input 1 0 Push-pull output 1 1 A/D converter input (AD6); Schmitt trigger input off Port 2, P2.1/INT1 Configuration Bits (Not used for S3C9414/P9414) 0 0 Schmitt trigger input; INT1 interrupt disable 0 1 Schmitt trigger input; interrupt on falling edge 1 0 Push-pull output 1 1 Schmitt trigger input; interrupt on rising edge Port 2, P2.0/INT0 Configuration Bits 0 0 Schmitt trigger input; INT0 interrupt disable 0 1 Schmitt trigger input; interrupt on falling edges 1 0 Push-pull output 1 1 Schmitt trigger input; interrupt on rising edges S3C9404/P9404/C9414/P9414 CONTROL REGISTERS P2DPUR -- Port 2 Open-drain Enable & Pull-up Resistor Enable Register EBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 .6 .5 .4 .3 .2 .1 .0 Port 2.3/AD7, Open-drain Enable Bit (Not used for S3C9414/P9414) 0 Configure P2.3 as a push-pull 1 Configure P2.3 as a n-channel open drain Port 2.2/AD6, Open-drain Enable Bit (Not used for S3C9414/P9414) 0 Configure P2.2 as a push-pull 1 Configure P2.2 as a n-channel open drain Port 2.1/INT1, Open-drain Enable Bit (Not used for S3C9414/P9414) 0 Configure P2.1 as a push-pull 1 Configure P2.1 as a n-channel open drain Port 2.0/INT0, Open-drain Enable Bit 0 Configure P2.0 as a push-pull 1 Configure P2.0 as a n-channel open drain Port 2.3/AD7, Pull-up Resistor Enable Bit (Not used for S3C9414/P9414) 0 Disable pull-up 1 Enable pull-up Port 2.2/AD6, Pull-up Resistor Enable Bit (Not used for S3C9414/P9414) 0 Disable pull-up 1 Enable pull-up Port 2.1/INT1, Pull-up Resistor Enable Bit (Not used for S3C9414/P9414) 0 Disable pull-up 1 Enable pull-up Port 2.0/INT0, Pull-up Resistor Enable Bit 0 Disable pull-up 1 Enable pull-up NOTE: In order to use the open-drain output mode the push-pull output bit in the P2CON should be set first. 4-15 CONTROL REGISTERS S3C9404/P9404/C9414/P9414 P2PND -- Port 2 Interrupt Pending Register ECH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - - - - - 0 0 Read/Write (NOTE) - - - - - - R/W R/W .7-.2 Not used for S3C9404/P9404/C9414/P9414 .1 P2.1/INT1, Interrupt Pending Bit (Not used for S3C9414/P9414) .0 0 No interrupt pending (when read) 0 Clear this pending bit (when write) 1 Interrupt is pending (when read)/No effect (when write) P2.0/INT0, Interrupt Pending Bit 0 No interrupt pending (when read) 0 Clear this pending bit (when write) 1 Interrupt is pending (when read)/No effect (when write) NOTES: 1. To clear an interrupt pending condition at a port2 pin, you must write a "0" to the corresponding P2PND bit location. 2. To avoid programming errors, we recommend using load instructions when manipulating P2PND values. 4-16 S3C9404/P9404/C9414/P9414 CONTROL REGISTERS P3CONH -- Port 3 Control Register (High Byte) EEH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - - - 0 0 0 0 Read/Write - - - - R/W R/W R/W R/W .7-.4 Not used for S3C9404/P9404/C9414/P9414 .3 and .2 Port 3, P3.5/ADC5 Configuration Bits (Not used for S3C9414/P9414) .1 and .0 0 0 Schmitt trigger input 0 1 Schmitt trigger input, pull-up resistor enabled 1 0 Push-pull output 1 1 A/D converter input (ADC5); Schmitt trigger input off Port 3, P3.4/ADC4 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input, pull-up resistor enabled 1 0 Push-pull output 1 1 A/D converter input (ADC4); Schmitt trigger input off 4-17 CONTROL REGISTERS S3C9404/P9404/C9414/P9414 P3CONL -- Port 3 Control Register (Low Byte) EFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 and .6 .5 and .4 .3 and .2 .1 and .0 4-18 Port 3, P3.3/ADC3 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input, pull-up resistor enabled 1 0 Push-pull output 1 1 A/D converter input (ADC3); Schmitt trigger input off Port 3, P3.2/ADC2 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input, pull-up resistor enabled 1 0 Push-pull output 1 1 A/D converter input (ADC2); Schmitt trigger input off Port 3, P3.1/ADC1 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input, pull-up resistor enabled 1 0 Push-pull output 1 1 A/D converter input (ADC1); Schmitt trigger input off Port 3, P3.0/ADC0 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input, pull-up resistor enabled 1 0 Push-pull output 1 1 A/D converter input (ADC0); Schmitt trigger input off S3C9404/P9404/C9414/P9414 CONTROL REGISTERS SYM -- System Mode Register DFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - - - - 0 0 0 Read/Write - - - - - R/W R/W R/W .7-.3 Not used for S3C9404/P9404/C9414/P9414 .2 Global Interrupt Enable Bit (note) .1 and .0 0 Disable all interrupt (DI instruction) 1 Enable all interrupt (EI Instruction) Page Selection Bits 0 0 page 0 0 1 page 1 (not used for S3C9404/P9404/C9414/P9414) 1 0 page 2 (not used for S3C9404/P9404/C9414/P9414) 1 1 page 3 (not used for S3C9404/P9404/C9414/P9414) NOTE: Following a reset, you enable global interrupt processing by executing an EI instruction (not by writing a "1" to SYM.2). 4-19 CONTROL REGISTERS S3C9404/P9404/C9414/P9414 T0CONH -- TIMER 0 Control Register (High Byte) D2H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 (8) RESET Value - - - - - - - 0 Read/Write - - - - - - - R/W .7-.1 Not used for S3C9404/P9404/C9414/P9414 .0 (8) Timer 0 Overflow Interrupt Pending Bit (overflow interrupt) 4-20 0 No interrupt pending (when read) 0 Clear Pending bit (when write) 1 Interrupt is pending (when read) S3C9404/P9404/C9414/P9414 CONTROL REGISTERS T0CONL -- TIMER 0 Control Register (Low Byte) D3H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 and .6 .5 and .4 .3 .2 .1 .0 Timer 0 Input Clock Selection Bits 0 0 f OSC/4096 0 1 f OSC/256 1 0 f OSC/8 1 1 f OSC/1 Timer 0 Operating Mode Selection Bits 0 0 Interval mode 0 1 Capture mode (capture on rising edge, counter running, OVF) 1 0 Capture mode (capture on falling edge, counter running, OVF) 0 0 PWM mode (OVF interrupt can occur) Timer 0 Counter Clear Bit 0 No effect 1 clears the timer 0 counter (when write) Timer 0 Overflow Interrupt Enable Bit 0 Disable overflow interrupt 1 Enable overflow interrupt Timer 0 Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt Timer 0 Interrupt Pending Bit (Capture or Match Interrupt) 0 No interrupt pending (when read) 0 Clear pending bit (when write) 1 Interrupt is pending (when read) 4-21 CONTROL REGISTERS S3C9404/P9404/C9414/P9414 T1CON -- Timer 1 Control Register F3H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - 0 0 0 0 0 0 Read/Write - - R/W R/W R/W R/W R/W R/W .7 and .6 Not used for S3C9404/P9404/C9414/P9414 .5 and .4 Timer 1 Input Clock Selection Bits .3 .2 .1 .0 4-22 0 0 f OSC/512 0 1 f OSC/256 1 0 f OSC/128 1 1 f OSC/64 Timer 1 Counter Automatic Clear Enable Bit 0 Disable 1 Enable ZCD clear signal to clear the timer 1 counter Timer 1 Counter Clear Enable Bit 0 No effect 1 Clear the timer 1 counter (when write) Timer 1 Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt Timer 1 Interrupt Pending Bit 0 No interrupt pending (when read) 0 Clear pending bit (when write) 1 Interrupt is pending (when read) S3C9404/P9404/C9414/P9414 CONTROL REGISTERS ZCMOD -- Zero Crossing Detection Control Register F5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value - - - - 0 0 0 0 Read/Write - - - - R/W R/W R/W R/W .7-.4 Not used for S3C9404/P9404/C9414/P9414 .3 and .2 Interrupt Mode Selection Bits .1 .0 0 0 Interrupt on falling edge 0 1 Interrupt on rising edge 1 0 Interrupt on both edge 1 1 Not used ZCD Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt ZCD Interrupt Pending Bit 0 No interrupt pending (when read) 0 Clear pending bit (when write) 1 Interrupt is pending (when read) 4-23 S3C9404/P9404/C9414/P9414 5 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The SAM87Ri interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through an interrupt vector which is assigned in ROM address 0000H. VECTOR SOURCES S1 0000H 0001H S2 S3 Sn NOTES: 1. The SAM87Ri interrupt has only one vector address(0000H-0001H) 2. The number of Sn value is expandable. Figure 5-1. S3C9-Series Interrupt Type INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can be controlled in two ways: either globally, or by specific interrupt level and source. The system-level control points in the interrupt structure are therefore: -- Global interrupt enable and disable (by EI and DI instructions) -- Interrupt source enable and disable settings in the corresponding peripheral control register(s) ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) The system mode register, SYM (DFH), is used to enable and disable interrupt processing. SYM.2 is the enable and disable bit for global interrupt processing respectively, by modifying SYM.2. An Enable Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. Although you can manipulate SYM.2 directly to enable and disable interrupts during normal operation, we recommend that you use the EI and DI instructions for this purpose. 5-1 INTERRUPT STRUCTURE S3C9404/P9404/C9414/P9414 INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM87Ri, the order of service is determined by a sequence of source which is executed in interrupt service routine. "EI" INSTRUCTION EXECUTION S RESET R SOURCE INTERRUPTS SOURCE INTERRUPT ENABLE Q INTERRUPT PENDING REGISTER INTERRUPT PRIORITY IS DETERMINED BY SOFTWARE POLLING METHOD GLOBAL INTERRUPT CONTROL (EI, DI instructions) Figure 5-2. Interrupt Function Diagram 5-2 VECTOR INTERRUPT CYCLE S3C9404/P9404/C9414/P9414 INTERRUPT STRUCTURE INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal. 3. The service routine starts and the source's pending flag is cleared to "0" by software. 4. Interrupt priority must be determined by software polling method. INTERRUPT SERVICE ROUTINES Before an interrupt request can be serviced, the following conditions must be met: -- Interrupt processing must be enabled (EI, SYM.2 = "1") -- Interrupt must be enabled at the interrupt's source (peripheral control register) If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence: 1. Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.2 = "0") to disable all subsequent interrupts. 2. Save the program counter and status flags to stack. 3. Branch to the interrupt vector to fetch the service routine's address. 4. Pass control to the interrupt service routine. When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores the PC and status flags and sets SYM.2 to "1" (EI), allowing the CPU to process the next interrupt request. GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to stack. 2. Push the program counter's high-byte value to stack. 3. Push the FLAGS register values to stack. 4. Fetch the service routine's high-byte address from the vector address 0000H. 5. Fetch the service routine's low-byte address from the vector address 0001H. 6. Branch to the service routine specified by the 16-bit vector address. 5-3 INTERRUPT STRUCTURE S3C9404/P9404/C9414/P9414 S3C9404/C9414 INTERRUPT STRUCTURE The S3C9404/C9414 microcontroller has six peripheral interrupt sources: -- Timer 0 match/capture interrupt -- Timer 0 overflow interrupt -- Timer 1 match interrupt -- Zero-cross detection -- Two external interrupts for port 2, P2.0-P2.1 (P2.1 not used S3C9414/P9414) VECTOR PENDING BITS T0CONL.0 T0CONH.0 T1C0N.0 0000H 0001H ZCMOD.0 SYM.2 ( EI,DI ) P2PND.0 P2PND.1 ENABLE/DISABLE Timer 0 Match or Capture T0CONL.1 Timer 0 Overflow T0CONL.2 T1CON.1 Timer 1 Match Zero-cross Detect ZCMOD.1 P2.0 External Interrupt P2CON.1 - 0 P2.1 External Interrupt P2CON.3 - 2 Figure 5-3. S3C9404/C9414 Interrupt Structure 5-4 SOURCES S3C9404/P9404/C9414/P9414 7 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW An RC oscillation source provides a typical 4 MHz clock for S3C9404/C9414. An internal capacitor supports the RC oscillator circuit. An external crystal or ceramic oscillation source provides a maximum 10 MHz clock. The XIN and XOUT pins connect the oscillation source to the on-chip clock circuit. Simplified RC oscillator and crystal/ceramic oscillator circuits are shown in Figures 7-1 and 7-2. Figure 7-1. Main Oscillator Circuit (RC Oscillator with Internal Capacitor) C1 XIN S3C9404 S3C9414 C2 X OUT Figure 7-2. Main Oscillator Circuit (Crystal/Ceramic Oscillator) MAIN OSCILLATOR LOGIC To increase processing speed and to reduce clock noise, non-divided logic is implemented for the main oscillator circuit. For this reason, very high resolution waveforms (square signal edges) must be generated in order for the CPU to efficiently process logic operations. CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect clock oscillation as follows: -- In Stop mode, the main oscillator "freezes", halting the CPU and peripherals. The contents of the register file and current system register values are retained. Stop mode is released, and the oscillator started, by a reset operation or by an external interrupt with RC-delay noise filter (for S3C9404/C9414, INT0-INT1). -- In Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt control and the timer. The current CPU status is preserved, including stack pointer, program counter, and flags. Data in the register file is retained. Idle mode is released by a reset or by an interrupt (external or internally-generated). 7-1 CLOCK CIRCUIT S3C9404/P9404/C9414/P9414 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in location D4H. It is read/write addressable and has the following functions: -- Oscillator IRQ wake-up function enable/disable (CLKCON.7) -- Oscillator frequency divide-by value: non-divided, 2, 8, or 16 (CLKCON.4 and CLKCON.3) The CLKCON register controls whether or not an external interrupt can be used to trigger a Stop mode release (This is called the "IRQ wake-up" function). The IRQ wake-up enable bit is CLKCON.7. After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the f OSC/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to fOSC, fOSC/2 or fOSC/8. SYSTEM CLOCK CONTROL REGISTER (CLKCON) D4H, R/W MSB .7 .6 Oscillator IRQ wake-up enable bit: 0 = Enable IRQ for main system oscillator wake-up function in power down mode 1 = Disable IRQ for main system oscillater wake-up function in poqwer down mode .5 .4 .3 .2 .1 .0 Not used for S3C9404/P9404/C9414/P9414 Divide-by selection bits for CPU clock frequency: 00 = fOSC/16 01 = fOSC/8 10 = fOSC/2 11 = fOSC (non-divided) Not used for S3C9404/P9404/C9414/P9414 Figure 7-3. System Clock Control Register (CLKCON) 7-2 LSB S3C9404/P9404/C9414/P9414 CLOCK CIRCUIT CLKCON.4-3 STOP Instruction Oscillator Stop 1/2 MAIN OSC Oscillator Wake-up NOISE FILTER 1/8 M U X CPU CLOCK P1.3/CLO 1/16 P1CON.7-6 CLKCON.7 INT Pin NOTE: An external interrupt with an RC-delay noise filter can be used to release Stop mode and "wake up" the main oscillator. In the S3C9404/C9414, the INT0- INT1 external interrupts and ZCD interrupt are of this type. Figure 7-4. System Clock Circuit Diagram 7-3 RESET and POWER-DOWN S3C9404/P9404/C9414/P9414 8 RESET and POWER-DOWN SYSTEM RESET OVERVIEW During a power-on reset, the voltage at VDD is High level and the RESET pin is forced to Low level. The RESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock. This brings the S3C9404/C9414 into a known operating status. The RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize. The minimum required oscillation stabilization time for a reset is approximately 6.55 ms ( 216/f OSC, fOSC= 10 MHz). When a reset occurs during normal operation (with both VDD and RESET at High level), the signal at the RESET pin is forced Low and the reset operation starts. All system and peripheral control registers are then set to their default hardware reset values (see Table 8-1). The following sequence of events occurs during a reset operation: -- All interrupts are disabled. -- The watchdog function (basic timer) is enabled. -- Ports 0-3 are set to input mode and all pull-up resistors are disabled. -- Peripheral control and data registers are disabled and reset to their initial values. -- The program counter is loaded with the ROM reset address, 0100H. -- When the programmed oscillation stabilization time interval has elapsed, the address stored in ROM location 0100H (and 0101H) is fetched and executed. NOTE To program the duration of the oscillation stabilization interval, you must make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing "1010B" to the upper nibble of BTCON. 8-1 RESET and POWER-DOWN S3C9404/P9404/C9414/P9414 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 5 A. All system functions are halted when the clock "freezes", but data stored in the internal register file is retained. Stop mode can be released in one of two ways: by a RESET signal or by an external interrupt. Using RESET to Release Stop Mode Stop mode is released when the RESET signal is released and returns to High level. All system and peripheral control registers are then reset to their default values and the contents of all data registers are retained. A reset operation automatically selects a slow clock (1/16) because CLKCON.3 and CLKCON.4 are cleared to "00B". After the oscillation stabilization interval has elapsed, the CPU executes the system initialization routine by fetching the 16-bit address stored in ROM locations 0100H and 0101H. Using an External Interrupt to Release Stop Mode Only external interrupts with an RC-delay noise filter circuit can be used to release Stop mode (Clock-related external interrupts cannot be used). External interrupts INT0-INT1 in the S3C9404/C9414 interrupt structure meet this criteria. Note that when Stop mode is released by an external interrupt, the current values in system and peripheral control registers are not changed. When you use an interrupt to release Stop mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock value is used. If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering Stop mode. The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated Stop mode is executed. IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while select peripherals remain active. During Idle mode, the internal clock signal is gated off to the CPU, but not to interrupt logic and timer/counters. Port pins retain the mode (input or output) they had at the time Idle mode was entered. There are two ways to release Idle mode: 1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects a slow clock (1/16) because CLKCON.3 and CLKCON.4 are cleared to "00B". If interrupts are masked, a reset is the only way to release Idle mode. 2. Activate any enabled interrupt, causing Idle mode to be released. When you use an interrupt to release Idle mode, the CLKCON.3 and CLKCON.4 register values remain unchanged, and the currently selected clock value is used. The interrupt is then serviced. Following the IRET from the service routine, the instruction immediately following the one that initiated Idle mode is executed. NOTES 1. Only external interrupts that are not clock-related can be used to release stop mode. To release Idle mode, however, any type of interrupt (that is, internal or external) can be used. 2. Before enter the STOP or IDLE mode, the ZCD (P1CON) and ADC (P2CON, P3CONH, P3CONL) must be disabled. Otherwise, the STOP or IDLE current will be increased significantly. 8-2 RESET and POWER-DOWN S3C9404/P9404/C9414/P9414 HARDWARE RESET VALUES Table 8-1 lists the values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation in normal operating mode. -- A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. -- An "x" means that the bit value is undefined following a reset. -- A dash ("-") means that the bit is either not used or not mapped. Table 8-1. Register Values after a Reset Register Name General purpose register (page 0) Mnemonic Bit Values After RESET Address 7 6 5 4 3 2 1 0 - 00H-BFH x x x x x x x x Working registers R0-R15 C0H-CFH x x x x x x x x Timer 0 counter register T0CNT D0H 0 0 0 0 0 0 0 0 Timer 0 data register T0DATA D1H 1 1 1 1 1 1 1 1 Timer 0 control register (high) T0CONH D2H - - - - - - - 0 Timer 0 control register (low) T0CONL D3H 0 0 0 0 0 0 0 0 Clock control register CLKCON D4H 0 - - 0 0 - - - System flags register FLAGS D5H x x x x - - - - x x x x x x x x Locations D6H-D8H are not mapped. Stack pointer register SP D9H Location DAH is not mapped. Location DBH is reserved. Basic timer control register BTCON DCH 0 0 0 0 0 0 0 0 Basic timer counter BTCNT DDH 0 0 0 0 0 0 0 0 - - - - - 0 0 0 Location DEH is reserved. System mode register SYM DFH 8-3 RESET and POWER-DOWN S3C9404/P9404/C9414/P9414 Table 8-1. Register Values After a Reset (continued) Bank 0 Register Name Mnemonic Address Bit Values After a Reset 7 6 5 4 3 2 1 0 Port 0 data register P0 E0H 0 0 0 0 0 0 0 0 Port 1 data register P1 E1H - - - - 0 0 0 0 Port 2 data register P2 E2H - - - - 0 0 0 0 Port 3 data register P3 E3H - - 0 0 0 0 0 0 Locations E4H-E5H are not mapped. Port 0 control register P0CON E6H 0 0 0 0 0 0 0 0 Port 0 pull-up resistor enable register P0PUR E7H 0 0 0 0 0 0 0 0 Port 0 N-channel open-drain mode P0PNE E8H 0 0 0 0 0 0 0 0 Port 1 control register P1CON E9H 0 0 0 0 0 0 0 0 Port 2 control register P2CON EAH 0 0 0 0 0 0 0 0 Port 2 open-drain, pull-up resistor enable P2DPUR EBH 0 0 0 0 0 0 0 0 P2PND ECH - - - - - - 0 0 Port 2 interrupt pending register Location EDH is not mapped. Port 3 control register (high byte) P3CONH EEH - - - - 0 0 0 0 Port 3 control register (low byte) P3CONL EFH 0 0 0 0 0 0 0 0 Locations F0H-F1H are not mapped. Timer 1 counter register T1CNT F2H 0 0 0 0 0 0 0 0 Timer 1 control register T1CON F3H - - 0 0 0 0 0 0 Timer 1 data register T1DATA F4H 1 1 1 1 1 1 1 1 Zero-crossing detector control register ZCMOD F5H - - - - 0 0 0 0 8-bit prescaler for buzzer output BUZPS F6H 0 0 0 0 0 0 0 0 A/D control register ADCON F7H - 0 0 0 0 - - 0 A/D converter data register (high byte) ADDATAH F8H x x x x x x x x A/D converter data register (low byte) ADDATAL F9H 0 0 0 0 0 0 x x PWMEX FAH - - - - - - 0 0 T0EXCNT FBH - - - - - - 0 0 PWM extension data register PWM extension counter register Locations FCH-FFH are not mapped. NOTE: 8-4 "-" means not mapped, "x" means undefined. RESET and POWER-DOWN S3C9404/P9404/C9414/P9414 + PROGRAMMING TIP -- Sample S3C9404 Initialization Routine The following sample program suggests how to program the initial program settings for S3C9404 address space, interrupt, and peripheral function. Program comment guide you through the necessary steps. ;-------<< Interrupt vector address >> .ORG 0000H .VECTOR 00H, COMMON_INT ; IRQ0/Interrupt vector address ;-------<< Initialize system and peripherals >> RESET: .ORG DI LD 0100H LD LD LD LD LD LD LD LD LD CLKCON,#00011000B SP,#0C0H P0CON,#0FFH P0PUR,#00H P0PNE,#00H P1CON,#1010101011B ZCMOD,#00000010B T1DATA,#81H T1CON,#00001100B LD P2CON,#11000110B LD P2DPUR,#00010110B LD LD LD P2PND,#00H P3CONH,#0FH P3CONL,#0AAH BTCON,#00000010B ; Reset start address ; disable interrupt ; enable watchdog function ; clock source: fosc/4096 (104 ms overflow at 10 MHz) ; CPU clock source select (non-divided) ; S3C9404 Stack pointer initial ; push-pull output (LED direct drive Low active) ; disable pull-up resistor ; disable open-drain ; P1.0 ZCD input enable/P1.1-3 push-pull ; enable falling edge interrupt ; ZCD clear enable (fosc/512) ; timer 1 interrupt disable ; P2.3 A/D input mode/P2.2 input mode ; P2.1 falling edge interrupt ; P2.0 open-drain output mode ; P2.2 pull-up enable ; P2.1 pull-up enable ; no interrupt pending ; AD input mode (AD4,AD5) ; P3.0-3 push-pull output mode * * * ;-------<< Initialize data register >> RAMCLR: LD CLR DEC JR R0,#0BFH @R0 R0 NZ,RAMCLR ; (00h-0BFh) #00h ; Initialize data register * * LD LD LD EI T0DATA,#26H T0CONH,#00H T0CONL,#01001010B ; 1 ms interval at 10 MHz system clock ; timer 0 overflow interrupt disable ; timer 0 match interrupt enable ; clock source: fosc/256 ; enable interrupt ;-------<< Main loop >> 8-5 RESET and POWER-DOWN MAIN: S3C9404/P9404/C9414/P9414 * CALL CALL XXX YYY ; subroutine call ; subroutine call LD BTCON,#02H JP T,MAIN ; enable watchdog function ; basic counter (BTCNT) clear ; for main loop * * ;-------<< Subroutines >> XXX: * * RET YYY: * * * RET * * * ;-------<< Interrupt service routine >> COMMON_INT: TM JP TM JP TM JP TM JP TM JP TM JP IRET TIMER0_INT: * AND ZCMOD,#00000001B NZ,ZCD_INT T1CON,#00000001B NZ,TIMER1_INT T0CONL,#00000001B NZ,TIMER0_INT P2PND,#00000001B NZ,EXT20_INT P2PND,#00000010B NZ,EXT21_INT T0CONH,#00000001B T0OVERFLOW_INT T0CONL,#11110110B ; timer0 pending bit clear * * IRET TIMER1_INT: * AND XOR IRET 8-6 ; timer0 interrupt return T1CON,#11111100B P1,#00000100B ; timer1 pending bit clear/timer 1 interrupt disable ; P1.2 toggle RESET and POWER-DOWN S3C9404/P9404/C9414/P9414 ZCD_INT: AND XOR LD ZCMOD,#11111110B P1,#00001000B T1CON,#00001010B ; pending bit clear ; P1.3 toggle ; timer1 interrupt enable (fosc/512) ; enable ZCD clear signal to clear the timer 1 counter IRET EXT20_INT: PUSH R5 LD P2PND,#00000010B ; P2.0 pending bit clear * LD POP IRET EXT21_INT: R5,#X1 R5 PUSH R8 LD P2PND,#00000001B ; P2.1 pending bit clear * AND POP IRET T0OVERFLOW_INT: NOP LD INC IRET R8,#X2 R8 T0CONH,#0 CAPTURE_BUFH ; overflow pending bit clear * * END 8-7 S3C9404/P9404/C9414/P9414 9 I/O PORTS I/O PORTS OVERVIEW The S3C9404/C9414 has four I/O ports (0-3): S3C9404/P9404, with 22 pins total and S3C9414/P9414, with 16 pins total. You access these ports directly by writing or reading port data register addresses. Port 0 can be configured as LED drive. (High current output: typical 15 mA) Table 9-1. S3C9404/C9414 Port Configuration Overview Port Function Description Programmability 0 Bit-programmable I/O port for normal input or push-pull, open-drain output. Pull-up resistors are assignable by software Bit 1 Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port1 pins can also be used as alternative function. (ZCD, PWM, buzzer) Bit 2 Bit-programmable I/O port for Schmitt trigger input or push-pull, open drain output. Pull-up resistors are assignable by software. Port2 can also be used as external interrupt, A/D converter input. Bit 3 Bit-programmable I/O port for Schmitt trigger input or push-pull output. Pull-up resistors are assignable by software. Port3 pins can also be used as A/D converter input. Bit 9-1 I/O PORTS S3C9404/P9404/C9414/P9414 PORT DATA REGISTERS Table 9-2 gives you an overview of the port data register names, locations, and addressing characteristics. Data registers for ports 0-3 have the structure shown in Figure 9-1. Table 9-2. Port Data Register Summary Register Name Mnemonic Hex R/W Port 0 data register P0 E0H R/W Port 1 data register P1 E1H R/W Port 2 data register P2 E2H R/W Port 3 data register P3 E3H R/W NOTE: A reset operation clears the P0-P3 data register to "00H". I/O PORT n DATA REGISTER (n=0-3) MSB .7 Pn.7 .6 Pn.6 .5 Pn.5 .4 Pn.4 .3 Pn.3 .2 Pn.2 .1 Pn.1 .0 Pn.0 NOTES 1. Eight bits of the data register are used in the port 0. 2. Only lower four bits of the data register are used in the port 1 and port 2. 3. Only lower six bits of the data register are used in the port 3. Figure 9-1. Port Data Register Format 9-2 LSB S3C9404/P9404/C9414/P9414 I/O PORTS PORT 0 Port 0 is a bit-programmable, general-purpose, I/O ports. You can select normal input or push-pull, open drain output mode. In addition, you can configure a pull-up resistor to individual pins using control register settings. It is designed for high-current functions such as LED direct drive. You access port 0 directly by writing or reading the corresponding port data register, P0 (E0H). A reset clears the port control register, P0CON, to "00H" configuring port 0 pins as normal inputs. Two addition resisters are used to control Port 0: P0PUR (E7H) and P0PNE (E8H). By setting bits in the Port 0 open-drain enable register P0PNE, you can configure specific pin as a open-drain output. PORT 0 CONTROL REGISTERS E6H, R/W MSB .7 P0.7 .6 P0.6 .5 P0.5 .4 P0.4 .3 .2 .1 .0 P0.2 P0.1 P0.0 P0.3 LSB Port 0 Configration Bits: 0 1 Normal input Push-pull output NOTE: Port 0.7 is not used for S3C9414/P9414. Figure 9-2. Port 0 Control Registers (P0CON) 9-3 I/O PORTS S3C9404/P9404/C9414/P9414 PORT 0 PULL-UP ENABLE CONTROL REGISTERS E7H, R/W MSB .7 P0.7 .6 P0.6 .5 P0.5 .4 P0.4 .3 .2 .1 .0 P0.2 P0.1 P0.0 P0.3 LSB Port 0 Pull-up Enable Bit: 0 1 Disable pull-up resister Enable pull-up resister Figure 9-3. Port 0 Pull-up Enable Control Registers (P0PUR) PORT 0 N-CHANNEL OPEN-DRAIN CONTROL REGISTERS E8H, R/W MSB .7 P0.7 .6 P0.6 .5 P0.5 .4 P0.4 .3 .2 .1 .0 P0.2 P0.1 P0.0 P0.3 Port 0 N-channel Open-drain Control Bit: 0 1 Push-pull N-channel open-drain NOTE: In order to use the open-drain output mode, the push-pull output bit in the P0CON should be set first. Figure 9-4. Port 0 Control Registers (P0PNE) 9-4 LSB S3C9404/P9404/C9414/P9414 I/O PORTS PORT 1 Port 1, is a 4-bit I/O port with individually configurable pins. It can be used for general I/O port (Schmitt trigger input mode or push-pull output mode). You can also use port1 as special input (ZCD) or output (BUZ, T0, CLO). In addition, you can configure a pull-up resistor to individual pin using control register settings. In normal operating mode, a reset clears P1CON to "00H", configuring P1.0-P1.3 as normal Schmitt trigger inputs, but you can also configure P1CON to "0FFH" for alternative functions. You address port 1 bits directly by writing or reading the port 1 data register, P1 (E1H). The port 1 control register, P1CON is located at addresses E9H. PORT 1 CONTROL REGISTERS E9H, R/W MSB .7 P1.3/ CLO .6 .5 .4 .3 P1.2/ T0 .2 P1.1/ BUZ .1 .0 LSB P1.0/ ZCD P1CON Pin Configration Settings: 00 01 10 11 NOTE: Schmitt trigger input (or T0 Capture input of P1.2) Schmitt trigger input; Pull-up register enable Push-pull output Alternative Function (ZCD input of P1.0; Buzzer output of P1.1; T0 match or PWM output of P1.2; CLO output of P1.3) Port 1.3 is not used for S3C9414/P9414 Figure 9-5. Port 1 Control Registers (P1CON) 9-5 I/O PORTS S3C9404/P9404/C9414/P9414 PORT 2 Port 2 is a 4-bit I/O port with individually configurable pins. It can be used for general I/O port (Schmitt trigger input mode or push-pull output mode or N-channel open-drain output mode). You can also use port 2 pins as external interrupt (INT0-INT1) or A/D inputs. In addition, you can configure a pull-up resistor to individual pins using control register settings. In normal operating mode, a reset clears P2CON to "00H", configuring P2.0-P2.3 as normal Schmitt trigger inputs. You address port 2 bits directly by writing or reading the port 2 data register, P2 (E2H). The port 2 control register, P2CON is located at addresses EAH. Two additional registers are used to control Port 2: P2DPUR (EBH) and P2PND (ECH). By setting port 2 open-drain and pull-up resistor enable register, P2DPUR, you can configure specific pins as open-drain or push-pull output. The application program polls the port 2 interrupt pending register, P2PND, to detect interrupt requests. When an interrupt request is acknowledged, the corresponding pending bit must be cleared by the interrupt service routine. PORT 2 CONTROL REGISTERS EAH, R/W, MSB .7 P2.3/ ADC7 .6 .5 P2.2/ ADC6 .4 .3 .2 .1 P2.1/ INT1 .0 LSB P2.0/ INT0 P2CON. 7-4 Pin Configration Settings: 00 01 10 11 Schmitt trigger input Schmitt trigger input Push-pull output A/D converter input(ADC7,ADC6); Schmitt trigger input off P2CON.3-0 Pin Configration Settings: 00 01 10 11 Schmitt trigger input; Interrupt disable Schmitt trigger input; Interrupt on falling edge Push-pull output Schmitt trigger input; interrupt on rising edge NOTE: Port 2.1-3 are not used for S3C9414/P9414. Figure 9-6. Port 2 Control Registers (P2CON) 9-6 S3C9404/P9404/C9414/P9414 I/O PORTS PORT 2 OPEN-DRAIN ENABLE & PULL-UP RESISTOR ENABLE REGISTER EBH, R/W MSB .7 .6 P2.2/ P2.3/ ADC6 ADC7 .5 P2.1/ INT1 .4 P2.0/ INT0 .2 P2.3/ ADC7 P2.2/ ADC6 .1 .0 P2.1/ INT1 P2.0/ INT0 LSB Pull-up resistor Enable Bit Open-drain Enable Bit 0 1 .3 Configure P2.n as a push-pull Configure P2.n as a n-channel open-drain 0 1 Disable pull-up Enable pull-up NOTE: In order to use the open-drain output mode, the push-pull output bit in the P2CON should be set first. Figure 9-7. Port 2 Open-Drain and Pull-Up Resistor Enable Register (P2DPUR) PORT 2 INTERRUPT PENDING REGISTERS ECH, R/W MSB .7 .6 .5 .4 .3 .2 Not used .1 .0 P2.1/ INT1 P2.0/ INT0 LSB P2PND Interrupt Pending Bit 0 0 1 No interrupt pending (when read) Clear this pending bit (when write) Interrupt is pending (when read) Figure 9-8. Port 2 Interrupt Pending Register (P2PND) 9-7 I/O PORTS S3C9404/P9404/C9414/P9414 PORT 3 Port 3 is a 6-bit I/O port with individually configurable pins. It can be used for general I/O port. You can also use port 3 pins as A/D I/O inputs. In addition, you can configure a pull-up register to individual pins using control register settings. In normal operating mode, reset clears P3CONH and P3CONL to "00H", configures P3.0-P3.5 schmitt trigger input mode. Using the P3CONH and P3CONL registers (EEH and EFH respectively), you can alternatively configure the port 3 pins as push-pull outputs, or as A/D converter input pins. PORT 3 CONTROL REGISTERS (High Byte) EFH, R/W .7 MSB .6 .5 .4 Not used .3 .2 P3.5/ADC5 .1 .0 P3.4/ADC4 P3CONH Configration Bits 00 01 10 11 Schmitt trigger input Schmitt trigger input, pull-up resistor enabled Push-pull output A/D converter input (ADC5/ADC4); Schmitt trigger input off NOTE: Port 3.5 is not used for S3C9414/P9414. Figure 9-9. Port 3 High-Byte Control Registers (P3CONH) 9-8 LSB S3C9404/P9404/C9414/P9414 I/O PORTS PORT 3 CONTROL REGISTERS (Low Byte) EFH, R/W MSB .7 .6 P3.3/ADC3 .5 .4 P3.2/ADC2 .3 .2 P3.1/ADC1 .1 .0 LSB P3.0/ADC0 P3CONL Configration Bits 00 01 10 11 Schmitt trigger input Schmitt trigger input, pull-up resistor enabled Push-pull output A/D converter input (ADC3-ADC0); Schmitt trigger input off Figure 9-10. Port 3 Low-Byte Control Registers (P3CONL) 9-9 I/O PORTS S3C9404/P9404/C9414/P9414 + PROGRAMMING TIP - Configuring I/O Port Pins to Specification The following sample program shows how to configure the KS86C4004 I/O ports to specification Program comments show the effect of the settings: * * * LD LD LD LD LD LD LD P0CON,#0FFH P0PUR,#00H P0PNE,#00H P1CON,#1010101011B ZCMOD,#00000010B T1DATA,#81H T1CON,#00001100B LD P2CON,#11000110B LD P2DPUR,#00010110B LD LD LD P2PND,#00H P3CONH,#0FH P3CONL,#0AAH * * * 9-10 ; push-pull output (LED direct drive Low active) ; disable pull-up resistor ; disable open-drain ; P1.0 ZCD input enable/P1.1-3 push-pull ; enable falling edge interrupt ; ZCD clear enable (fosc/512) ; timer 1 interrupt disable ; P2.3 A/D input mode/P2.2 input mode ; P2.1 falling edge interrupt ; P2.0 open-drain output mode ; P2.2 pull-up enable ; P2.1 pull-up enable ; no interrupt pending ; AD input mode (ADC4,ADC5) ; P3.0-3 push-pull output mode S3C9404/P9404/C9414/P9414 10 BASIC TIMER and TIMERS BASIC TIMER and TIMERS MODULE OVERVIEW The S3C9404/C9414 has three default timers: an 8-bit basic timer, one 8-bit general-purpose timer/counter, called timer 0, and one 8-bit timer/counter for the zero-crossing detection circuit called timer 1. Basic Timer (BT) You can use the basic timer (BT) in two different ways: -- As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. -- To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release. The functional components of the basic timer block are: -- Clock frequency divider (fOSC divided by 4096, 1024, or 128) with multiplexer -- 8-bit basic timer counter, BTCNT (DDH, read-only) -- Basic timer control register, BTCON (DCH, read/write) Timer 0 Timer 0 has three operating modes, one of which you select by an appropriate T0CON setting: -- Interval timer mode -- Capture input mode -- 10-bit PWM output mode Timer 0 has the following functional components: -- Clock frequency divider (fOSC divided by 4096, 256, 8, or 1) with multiplexer -- -- -- -- 10(8)-bit counter (T0CNT + T0EXCNT), 8-bit comparator, and 10(8)-bit data register (T0DATA + PWMEX) I/O pin (P1.2, T0 match or PWM) for timer 0 match/PWM output or capture input Timer 0 overflow interrupt (T0OVF) and match interrupt (T0INT) generation Timer 0 control registers, T0CONH and T0CONL (D2H and D3H respectively) Timer 1 Timer 1 has one operating mode, interval timer mode. You can clear the timer 1 counter by appropriate setting of T1CON register. If T1CON.3 is set to "1", T1CNT is cleared by the ZCD edge detection. Timer 1 has the following components: -- Clock frequency divider (fOSC divided by 512, 256, 128, or 64) -- 8-bit counter (T1CNT), 8-bit compare register, and a 8-bit data register (T1DATA) -- Timer 1 control register, T1CON 10-1 BASIC TIMER and TIMERS S3C9404/P9404/C9414/P9414 BASIC TIMER (BT) BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of f OSC/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register control bits BTCON.7-BTCON.4. The 8-bit basic timer counter, BTCNT, can be cleared during normal operation by writing a "1" to BTCON.1. To clear the frequency dividers for both the basic timer input clock and the timer 0 clock, you write a "1" to BTCON.0. BASIC TIMER CONTROL REGISTER (BTCON) DCH, R/W MSB .7 .6 .5 .4 .3 Watchdog timer enable bits: 1010B = Disable watchdog function Other value = Enable watchdog function .2 .1 .0 LSB Divider clear bit for timers: 0 = No effect 1 = Clear both dividers Basic timer counter clear bit: 0 = No effect 1 = Clear basic timer counter Basic timer input clock selection bits: 00 = fosc /4096 01 = fosc /1024 10 = fosc /128 11 = Invalid selection Figure 10-1. Basic Timer Control Register (BTCON) 10-2 S3C9404/P9404/C9414/P9414 BASIC TIMER and TIMERS BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7-BTCON.4 to any value other than "1010B" (The "1010B" value disables the watchdog function). A reset clears BTCON to "00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CCON register setting) divided by 4096 as the BT clock. A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be cleared (by writing a "1" to BTCON.1) at regular intervals. If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically. Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt. In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fOSC/4096 (for reset), or at the rate of the preset clock source (for an external interrupt). When BTCNT.4 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation. In summary, the following events occur when Stop mode is released: 1. During Stop mode, a power-on reset or an external interrupt occurs to trigger the Stop mode release and oscillation starts. 2. If a power-on reset occurred, the basic timer counter will increase at the rate of fOSC/4096. If an external interrupt is used to release Stop mode, the BTCNT value increases at the rate of the preset clock source. 3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set. 4. When a BTCNT.4 is set, normal CPU operation resumes. Figure 10-2 and 10-3 shows the oscillation stabilization time on RESET and STOP mode release 10-3 BASIC TIMER and TIMERS S3C9404/P9404/C9414/P9414 Oscillation stabilization time VDD 0.8 V DD Reset Release Voltage RESETB Internal Reset Release Normal operating mode trst RC 0.8 V DD Oscillator (Xout) Oscillator stabilization time BTCNT clock BTCNT value 10000B 00000B t WAIT=4096x16x1/fosc Basic timer increment and CPU operations are IDLE mode NOTE: Duration of the oscillator stabilization wait time, tWAIT, when it is released by a Power-on-reset is 4096x16/fosc. trst RC (R is external resister and C is on chip capacitor) Figure 10-2. Oscillation Stabilization Time on RESET 10-4 S3C9404/P9404/C9414/P9414 BASIC TIMER and TIMERS Normal operating mode STOP mode Oscillation stabilization time Normal operating mode VDD STOP instruction execution STOP mode release signal External interrupt RESETB STOP release signal Oscillator (Xout) BTCNT clock 10000B BTCNT value 00000B t WAIT Basic timer increment NOTE: Duration of the oscillator stabilization wait time, tWAIT, it is released by an interrupt is determined by the setting in basic timer control register, BTCON. tWAIT tWAIT (When fosc is 10MHz) BTCON.3 BTCON.2 0 0 4096 x 16 / fosc 6.55 ms 0 1 1024 x 16 / fosc 1.64 ms 1 0 128 x 16 / fosc 0.2 ms 1 1 Invalid setting - Figure 10-3. Oscillation Stabilization Time on STOP Mode Release 10-5 BASIC TIMER and TIMERS S3C9404/P9404/C9414/P9414 + Programming Tip -- Configuring the Basic Timer This example shows how to configure the basic timer to sample specification ;----------<< Interrupt vector address>> ORG 0000H VECTOR 00H, COMMON_INT ; IRQ0/Interrupt vector address ;----------<<Initialize system and peripherals>> RESET ORG DI LD 0100H LD LD CLKCON,#00011000B SP,#0C0H BTCON,#10100010B ; ; ; ; ; ; Reset start address disable interrupt disable watchdog function clock source: fOSC/4096 (104 ms overflow at 10 MHz) CPU clock source select (non-divided) S3C9404 Stack pointer initial * * * * EI ; enable interrupt ;----------<< Main loop >> MAIN * * * LD BTCON,#02H ; enable watchdog function ; basic Timer Counter (BTCNT) clear * * * JP T,MAIN * * * 10-6 ; for main loop S3C9404/P9404/C9414/P9414 BASIC TIMER and TIMERS TIMER 0 TIMER 0 CONTROL REGISTERS (T0CONH and T0CONL) The timer 0 control register low byte, T0CONL, is used to select the timer 0 operating mode (interval timer, capture mode, or PWM mode) and input clock frequency, to clear the timer 0 counter, and to enable the T0 overflow interrupt and T0 match/capture interrupt. It also contains a pending bit for T0 match/capture interrupts. Timer 0 control register high byte, T0CONH, contains a pending bit for T0 overflow interrupt. Only one bit in T0CONH register is used, T0CONH.0. A reset clears T0CONL to "00H". This sets timer 0 to normal interval timer mode, selects an input clock frequency of fOSC /4096, and disables the T0 overflow interrupt and match/capture interrupts. The T0 counter can be cleared at any time during normal operation by writing a "1" to T0CONL.3. The T0 overflow interrupt, T0OVF, is IRQ0 with vector 00H. When a T0 overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared manually set by writing "0" to T0CONH.0. To enable the T0 match/capture interrupt (T0INT, IRQ0, vector 00H), you must set T0CONL.1 to "1". The interrupt service routine must clear the pending condition by writing a "0" to the T0 interrupt pending bit, T0CONL.0. TIMER 0 CONTROL REGISTERS (HIGH BYTE) D2H, R/W, MSB .7 .6 .5 .4 .3 .2 .1 .0(8) LSB Not used Timer 0 overflow Interrupt Pending Bit (overflow interrupt) 0 0 1 No interrupt pending (when read) Clear pending bit (when write) Interrupt is pending (when read) Figure 10-4. Timer 0 Control Registers (T0CONH) 10-7 BASIC TIMER and TIMERS S3C9404/P9404/C9414/P9414 TIMER 0 CONTROL REGISTER (LOW BYTE) D3H, R/W MSB .7 .6 .5 .4 Timer 0 input clock selection bits: 00 = f OSC /4096 01 = f OSC /256 10 = f OSC /8 11 = f OSC /1 Timer 0 operating mode selection bits: 00 = Interval mode 01 = Capture mode (capture on rising edge, counter running, OVF can occur) 10 = Capture mode (capture on falling edge, counter running, OVF can occur) 11 = PWM mode (OVF interrupt can occur) .3 .2 .1 .0 Timer 0 interrupt pending bit: 0 = No T0 interrupt pending ( when read) 0 = Clear T0 pending bit ( when write) 1 = T0 interrupt is pending ( when read) Timer 0 interrupt enable bit: 0 = Disable T0 interrupt 1 = Enable T0 interrupt Timer 0 overflow interrupt enable bit: 0 = Disable T0 overflow interrupt 1 = Enable T0 overflow interrupt Timer 0 counter clear bit: 0 = No effect 1 = Clear the Timer 0 counter (when write) Figure 10-5. Timer 0 Control Registers (T0CONL) 10-8 LSB S3C9404/P9404/C9414/P9414 BASIC TIMER and TIMERS TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts (IRQ0, Vectors 00H) The Timer 0 module can generate two interrupts; the timer 0 overflow interrupt (T0OVF), and the timer 0 match/capture interrupt (T0INT). T0OVF is interrupt level IRQ0, vector 00H; T0INT is also level IRQ0, vector 00H. The T0OVF interrupt pending condition is cleared by setting the T0CONH.0 pending bit to "0". The T0INT pending condition must be cleared by software by writing a "0" to the T0CONL.0 pending bit. INTERVAL TIMER MODE In interval timer mode, a match signal is generated when the counter value is identical to the value written to the Timer 0 reference data register, T0DATA. The match signal generates a Timer 0 match interrupt (T0INT, vector 00H) and then clears the counter. If, for example, you write the value "10H" to T0DATA, the counter will increment until it reaches "10H". At this point, the Timer 0 interrupt request is generated, the counter value is reset and counting resumes. With each match, the level of the signal at the Timer 0 output pin is inverted. Interrupt Enable/Disable CLK COUNTER R (Clear) PND IRQ0 (T0OVF) PND IRQ0 (T0INT) Interrupt Enable/Disable COMPARATOR Match CTL P1.2/T0 TOGGLE DATA REGISTER Figure 10-6. Simplified Timer 0 Function Diagram (Interval Timer Mode) 10-9 BASIC TIMER and TIMERS S3C9404/P9404/C9414/P9414 PULSE WIDTH MODULATION MODE Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T0 pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the T0 data register (T0DATA). In PWM mode, however, the match signal does not clear the counter (it runs continuously, overflowing at "FFH", and continues incrementing from "00H"). Although it is possible to use the match signal to generate a T0INT interrupt, an interrupt is typically not used in PWM-type applications. Instead, the pulse at the T0 pin is held to High level as long as the data register (T0DATA) value is greater than the counter (T0CNT) value for 8-bit PWM operation. For 2-bit extension control logic operation (10-bit PWM) the pulse is held to High level when the data value is equal to the counter value. One frame width is equal to tCLK x 1024. (See Figure 10-9.) TIMER 0 COUNTER CLOCK (4MHz) T0DATA = "0" 250 ns T0DATA = "1" 32 s T0DATA = 80H 250 ns T0DATA = FFH PWM CYCLE 64 s NOTES 1. A system clock frequency of 4MHz is assumed. 2. The input clock of timer 0 count (T0CNT) is assumed in non-divided (fOSC/1). Figure 10-7. Simplified Timer 0 Function Diagram (PWM Mode) 10-10 S3C9404/P9404/C9414/P9414 BASIC TIMER and TIMERS From 10-bit up counter (T0EXCNT) (9:8) From 10-bit up counter (T0CNT) (7:0) "1" when T0DATA > Counter "0" when T0DATA <= Counter 8-BIT COMPARATOR "1" when T0DATA = Counter P1.2/T0(PWM) Extension Control Logic 8-BIT DATA REGISTER PWM Extension DATA REGISTER PWMEX (FAH) DATA BUS (7:0) Figure 10-8. PWM Block Function Diagram Table 10-1. PWM Output "Stretch" Values for Extension Register PWMEX PWMEX Cycle Number That is "Stretched" 00H Not Stretched 01H 2 02H 1, 3 03H 1, 2, 3 NOTE: Bits 0 and 1 of the PWM extension register PWMEX are used only. 10-11 BASIC TIMER and TIMERS S3C9404/P9404/C9414/P9414 00H 100H 200H 300H 00H 100H 200H PWM COUNTER CLOCK (4MHz) T0DATA = 00H PWMEX = 00B T0DATA = 01H PWMEX = 00B T0DATA = 01H PWMEX = 01B T0DATA = 01H PWMEX = 10B T0DATA = 01H PWMEX = 11B T0DATA = 80H PWMEX = 01B T0DATA = XXH PWMEX = XXB T0DATA = FFH PWMEX = 00B T0DATA = FFH PWMEX = 01B T0DATA = FFH PWMEX = 10B 250ns at 4MHz T0DATA = FFH PWMEX = 11B PWM CYCLE 0 1 2 3 0 1 1frame = t CLK x 1024 Figure 10-9. 10-Bit PWM Waveforms with Various T0DATA and PWMEX 10-12 S3C9404/P9404/C9414/P9414 BASIC TIMER and TIMERS CAPTURE MODE In capture mode, a signal edge that is detected at the T0 pin opens a gate and loads the current counter value into the T0 data register. Rising edges or falling edges can be selected to trigger this operation. Both kinds of T0 interrupts can be used in capture mode: T0OVF is generated when a counter overflow occurs, and T0INT is generated when the counter value is loaded into the data register. By reading the captured data value in T0DATA, and assuming a specific value for tCLK, you can determine the pulse width (duration) of the signal being input at the T0 pin. (See Figure 10-10.) INTERRUPT ENABLE/DISABLE CLK COUNTER PND IRQ0 (T0OVF) PND IRQ0 (T0INT) P1.2/T0 (CAP) INTERRUPT ENABLE/DISABLE DATA REGISTER T0CONL Figure 10-10. Simplified Timer 0 Function Diagram (Capture Mode) 10-13 BASIC TIMER and TIMERS S3C9404/P9404/C9414/P9414 RESET or STOP Bit 1 Basic Timer Control Register (Write '1010xxxxB' to disable.) Bits 3, 2 Clear Data Bus 1/4096 DIV 1/1024 XIN R MUX 8-Bit Up Counter (BTCNT, Read-Only) RESET OVF 1/128 When BTCNT.4 is set after releasing from RESET or STOP mode, CPU clock starts. Bits 7, 6 Bit 0 Bit 2 Data Bus R 1/256 MUX XIN 1/8 Bit 8 IRQ0 OVF 1/4096 T0CNT (D0H) (Read-Only) T0EXCNT (FBH) DIV Match 1/1 Clear Bit 3 Bit 1 Bit 0 8-Bit Comparator T0 (CAP) T0 (PWM interval) Bits 5, 4 Bits 5, 4 T0DATA (D1H) (Read/Write) PWMEX (FAH) Basic Timer Control Register Data Bus Timer 0 Control Register NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter is set). Figure 10-11. Basic Timer and Timer 0 Block Diagram 10-14 IRQ0 S3C9404/P9404/C9414/P9414 BASIC TIMER and TIMERS + PROGRAMMING TIP1 -- Configuring Timer 0 (Interval Mode) The following sample program sets Timer 0 to interval timer mode. ;----------<< Interrupt vector address >> ORG VECTOR 0000H 00H, COMMON_INT ; IRQ0/Interrupt vector address ;----------<< Initialize system and peripherals >> RESET ORG DI LD 0100H LD LD CLKCON,#00011000B SP,#0C0H BTCON,#00000010B ; ; ; ; ; Reset start address disable interrupt enable watchdog function clock source: fOSC/4096 (104 ms overflow at 10 MHz) CPU clock source select (non-divided) ; S3C9404 Stack pointer initial ; ; ; ; ; ; 1 ms interval at 10 MHz system clock 100 ns x 256 x 39 = 998.4 s timer 0 overflow interrupt disable timer 0 match interrupt enable clock source: fOSC/256 enable interrupt * * * * LD T0DATA,#26H LD LD T0CONH,#00H T0CONL,#01001010B EI ;----------<< Main loop >> MAIN * * * LD BTCON,#02H JP T,MAIN ; enable watchdog function ; basic counter (BTCNT) clear ; for main loop * * ;----------<< Interrupt service routine >> COMMON_INT TM JP T0CONL,#00000001B NZ,TIMER0_INT * * * * IRET 10-15 BASIC TIMER and TIMERS S3C9404/P9404/C9414/P9414 + PROGRAMMING TIP1 -- Configuring Timer 0 (Interval Mode) TIMER0_INT AND T0CONL,#11110110B INC TIMER_MODE CP TIMER_MODE,#5 JR ULT,TMODE_JP CLR TIMER_MODE ; Timer0 pending bit clear TMODE_JP LD RCF RLC CLR LDC LDC CALL R9,TIMER_MODE R9 ; TIMER_MODE x 2 R8 R10,#TBL_TMODE[RR8] R11,#TBL_TMODE+1[RR8] @RR10 ; MULTI CALL * * IRET TBL_TMODE DW DSP_7SEGMENT ; MULTI CALL ADDRESS ; TA_MODE = 0 KEY_SCAN ; TA_MODE = 4 * * DW DSP_7SEGMENT ; display * * RET KEY_SCAN ; key scanning * RET * * * END 10-16 S3C9404/P9404/C9414/P9414 BASIC TIMER and TIMERS + PROGRAMMING TIP2 -- Configuring Timer 0 (PWM Mode) The following sample program sets Timer 0 to 10-bit PWM mode. * * * RESET ORG DI LD LD LD 0100H BTCON,#10100010B CLKCON,#00011000B SP,#0C0H ; ; ; ; ; reset start address disable interrupt disable watchdog function CPU clock source select (non-divided) S3C9404 Stack pointer initial T0CONH,#00H P1CON,#10111010B ; timer0 overflow interrupt disable ; P1.2 PWM output mode LD BTCON,#02H JP T,MAIN ; enable watchdog function ; basic counter (BTCNT) clear ; for main loop T0DATA,#34 PWMEX,#02H T0CONL,#11111000B ; duty = 34/256 (High width) ; total duty = 138/1024 (High width) ; timer0 PWM mode/non-divided T0DATA,#80H PWMEX,#00H ; duty = 128/256 (High width) ; total duty = 512/1024 (High width) * * LD LD * * ;-------<< MAIN LOOP >> MAIN * * * * PWM_OUT * * LD LD LD * * LD LD * * 10-17 BASIC TIMER and TIMERS S3C9404/P9404/C9414/P9414 TIMER 1 TIMER 1 CONTROL REGISTER (T1CON) The timer 1 control register,T1CON, located at F3H operates in interval timer mode. By setting the appropriate bits in T1CON you can select the input clock frequency and enable the Timer 1 interrupt. T1CON also contains a pending bit for Timer 1 interrupt. A reset clears T1CON to "00H". This sets timer 1 to normal interval mode and selects an input clock frequency of f osc/512 and disables the Timer 1 interrupt. You may clear the timer 1 counter by either setting T1CON.2 to "1" or enable ZCD clear signal to clear the timer 1 counter by setting T1CON.3 to "1". To enable Timer 1 match interrupt (IRQ0, vector 00H) you must set T1CON.1 to "1". The interrupt service routine must clear the pending condition by writing a "0" to the Timer 1 interrupt pending bit, T1CON.0. TIMER 1 CONTROL REGISTER (T1CON) F3H, R/W MSB .7 .6 .5 .4 Not used Timer 1 input clock selection bits: 00 = fosc /512 01 = fosc /256 10 = fosc /128 11 = fosc /64 Timer 1 counter automatic clear enable bit: 0 = Disable 1 = Enable ZCD clear signal to cleat the timer 1 counter .3 .2 .1 .0 Timer 1 interrupt pending bit: 0 = No interrupt pending (when read) 0 = Clear pending bit (when write) 1 = Interrupt is pending (when read) Timer 1 interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Timer 1 counter clear enable bit: 0 = No effect 1 = Cleat the timer 1 counter Figure 10-12. Timer 1 Control Register (T1CON) 10-18 LSB S3C9404/P9404/C9414/P9414 BASIC TIMER and TIMERS Bits 5,4 Data Bus Bit 2 1/512 R XIN DIV 1/256 1/128 T1CNT (F2H) (Read-only) MUX R From ZCD 1/64 1/128 Bit 3 Clear Bit 1 1/32 Bit 0 8-Bit Comparator IRQ0 Match MUX T1DATA (F4H) (Read/Write) Data Bus P1.1 .7 .6 6-Bit prescaler M U X TOGGLE P1.1/Buzzer Bit 7 P1CON.3,2 NOTE: When P1.1/Buzzer is used as Buzzer output pin, the initial value is "0" (Low Level). (When the bit7 of BUZPS is set to "0", the output of P1.1 is Low.) Figure 10-13. Timer 1 Block Diagram 10-19 BASIC TIMER and TIMERS S3C9404/P9404/C9414/P9414 BUZZER OUTPUT CONTROL REGISTER (BUZPS) Buzzer output control register is used to select the frequency from 200 Hz to 20 KHz. And these various frequency can be used to generate the melody signal. By selecting the clock source (bit of BUZPS) and the value of prescaler, the desire frequency can be obtained. The BUZPS.7 can be used to control the buzzer output when P1.1 is set to buzzer output mode (configure P1CON). BUZPS CONTROL REGISTER F6H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Buzzer clock selection bit 0 = Divided by 128 (fx/128) 1 = Divided by 32 (fx/32) Prescaler value: Buzzer output enable bit: 0 = Disable buzzer output (Buzzer off) 1 = Enable buzzer output (Buzzer on) 0 0 0 0 0 0 0 0 0 0 0 0 . . . 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 Divided by 2 [fx/(128 or 32)] Divided by 4 [fx/(128 or 32)] Divided by 6 [fx/(128 or 32)] Divided by 8 [fx/(128 or 32)] Divided by 2x(n+1) [fx/(128 or 32)] Divided by 128 [fx/(128 or 32)] Figure 10-14. Buzzer output control register (BUZPS) 10-20 S3C9404/P9404/C9414/P9414 BASIC TIMER and TIMERS + PROGRAMMING TIP - Configuring Timer 1 The following sample program sets Timer 1 to interval timer mode and generates the melody signal by using buzzer. INCLUDE "C:\SMDS2P\INCLUDE\REG\86C4004.REG" ;-----------------<< Interrupt vector address >> ORG VECTOR 0000H 00H, COMMON_INT ; IRQ0/Interrupt vector address ;-----------------<< Initialize system and peripherals >> RESET: ORG DI LD 0100H LD LD LD LD CLKCON,#00011000B SP,#0C0H P1CON,#00001100B T1DATA,#4DH LD T1CON,#00000110B BTCON,#00000010B ; ; ; ; ; ; ; ; ; ; ; reset start address disable interrupt enable watchdog function clock source: fosc/4096 (262ms overflow at 4 MHz) CPU clock source select (non-divided) S3C9404 Stack pointer initial P1.1 buzzer output mode 10 ms interval at 4 MHz system clock 250 ns x 512 x 78 = 9.984 ms timer1 match interrupt enable clock source: fosc/512 * * EI ; enable interrupt ;-----------------<< Main loop >> MAIN: * * * LD BTCON,#02H JP T,MAIN MELODY_CHK: OR OR LD CLR RET TIMER_CHK,#00000100B MELODY_FLAG,#00000001B MUSIC_INTERVAL,#1 BEEP_POINTER ; enable watchdog function ; basic counter (BTCNT) clear ; for main loop ; melody signal enable 10-21 BASIC TIMER and TIMERS S3C9404/P9404/C9414/P9414 + PROGRAMMING TIP - Configuring Timer 1 (Continued) ;-----------------<< Interrupt service routine >> COMMON_INT: TM JP T1CON,#00000001B NZ,TIMER1_INT ; timer 1 interrupt pending check TIMER1_INT: AND TM JP IRET T1CON,#11111010B MELODY_FLAG,#00000001B NZ,MELODY_ENABLE ; timer 1 pending bit clear ; MELODY_FLAG.bit0 == 0 melody disable ; == 1 melody enable MELODY_ENABLE: DEC CP JP IRET MUSIC_INTERVAL MUSIC_INTERVAL,#0 EQ,MELODY_LOAD ; note duration check ; next DB data load? MELODY_LOAD: LD RL CLR LDC LDC LD LD INC CP JP IRET R15,BEEP_POINTER R15 R14 R8,#MELODY_DB[RR14] R9,#MELODY_DB+1[RR14] MUSIC_INTERVAL,R8 BUZPS,R9 BEEP_POINTER MUSIC_INTERVAL,#0FFH EQ,MELODY_OFF MELODY_OFF: AND LD IRET MELODY_FLAG,#11111110B BUZPS,#0 * * * IRET 10-22 ; melody interval reload ; BEEP_POINTER x 2 ; R8 Note duration ; R9 tone ; P1.1 buzzer signal on, clock selection ; Special code check ; melody signal disable ; Buzzer off S3C9404/P9404/C9414/P9414 BASIC TIMER and TIMERS + PROGRAMMING TIP - Configuring Timer 1 (Concluded) MELODY_DB: DW DW DW DW DW DW DW DW DW ; ; ; 32BCH,32B6H,32AFH,32ADH ; 32A8H,32A3H,32A0H,329EH ; 3200H 649EH,649BH,6498H,6496H ; 6494H,6492H,64FFH,64FBH ; 3200H 32FBH,32F5H,32F0H,32ECH ; 32E8H,32E4H,32E0H,32DFH ; 0FF00H ; DW wxyzH (wx: Note duration yz:Frequency,Tone) 4 MHz OSC Clock 500 ms interval C4-C5 1000 ms interval C5-C6 500 ms interval C6-C7 special code (melody end) * * * 10-23 S3C9404/P9404/C9414/P9414 11 A/D CONVERTER A/D CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10-bit digital values. The analog input level must lie between the AVREF and AVSS values. The A/D converter has the following components: -- Analog comparator with successive approximation logic -- D/A converter logic (resistor string type) -- ADC control register (ADCON) -- Eight multiplexed analog data input pins (ADC0-ADC7) -- 10-bit A/D conversion data output register (ADDATAH/L): S3C9414 -- 8-bit A/D conversion data output register (ADDATAH): S3C9404 -- AVREF and AVSS pins To initiate an analog-to-digital conversion procedure, you write the channel selection data in the A/D converter control register ADCON to select one of the eight analog input pins (ADCn, n = 0-7) and set the conversion start or enable bit, ADCON.0. The read-write ADCON register is located at address F7H. During a normal conversion, A/D C logic initially sets the successive approximation register to 200H (the approximate half-way point of an 10-bit register). This register is then updated automatically during each conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time. You can dynamically select different channels by manipulating the channel selection bit value (ADCON.6- 4) in the ADCON register. To start the A/D conversion, you should set a the enable bit, ADCON.0. When a conversion is completed, ACON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the ADDATA register where it can be read. The A/D converter ten enters an idle state. Remember to read the contents of ADDATA before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result. NOTE Because the ADC does not use sample-and-hold circuitry, it is important that any fluctuations in the analog level at the ADC0-ADC7 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input level, perhaps due to circuit noise, will invalidate the result. 11-1 A/D CONVERTER S3C9404/P9404/C9414/P9414 USING A/D PINS FOR STANDARD DIGITAL INPUT The ADC module's input pins are alternatively used as digital input in port 3 and port 2. The ADC0-ADC5 share pin names are P3.0-P3.5 and ADC6-ADC7 share pin names are P2.2-P2.3, respectively A/D CONVERTER CONTROL REGISTER (ADCON) The A/D converter control register, ADCON, is located at address F7H. Only bits 6-3 and 0 are used in the S3C9404/4104 implementation. ADCON has three functions: -- Bits 6-4 select an analog input pin (ADC0-ADC7). -- Bit 3 indicates the status of the A/D conversion. -- Bit 0 starts the A/D conversion. Only one analog input channel can be selected at a time. You can dynamically select any one of the eight analog input pins (ADC0-ADC7) by manipulating the 3-bit value for ADCON.6-ADCON.4 A/D CONVERTER CONTROL REGISTER (ADCON) F7H, R/W MSB .7 .6 .5 .4 Not used .3 .2 .1 LSB Not used .0 Conversion S tart Bit: 0 1 No effect A/D conversion start .3 End-of-conversion Status Bit: 0 1 A/D conversion is in progress A/D conversion complete (when read) Analog Input Pin Selection Bits: .6 .5 .4 Selected Input Pin 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 ADC0 (P3.0) ADC1 (P3.1) ADC2 (P3.2) ADC3 (P3.3) ADC4 (P3.4) ADC5 (P3.5) (Not used for S3C9414/P9414) ADC6 (P2.2) (Not used for S3C9414/P9414) ADC7 (P2.3) (Not used for S3C9414/P9414) Figure 11-1. A/D Converter Control Register (ADCON) 11-2 .0 S3C9404/P9404/C9414/P9414 A/D CONVERTER INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range AVSS to AVREF (usually, AVREF = VDD). Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. The reference voltage level for the first bit conversion is always 1/2 AVREF. A/D CONVERTER CONTROL REGISTER ADCON (F7H) ADCON.0 (ADEN) ADCON .6-.4 CONTROL CIRCUIT ADCON .3 (EOC Flag) ADC0/P3.0 M U L T I P L E X E R ADC1/P3.1 ADC2/P3.2 ADC3/P3.3 ADC4/P3.4 ADC5/P3.5 ADC6/P2.2 + - SUCCESSIVE APPROXIMATION CIRCUIT ANALOG COMPARATOR CONVERSION RESULT AVref D/A CONVERTER ADC7/P2.3 AVss ADDATAH (F8H) ADDATAL (F9H) TO DATA BUS Figure 11-2. A/D Converter Circuit Diagram ADDATAH MSB .9 .8 .7 .6 .5 .4 .3 .2 LSB ADDATAL MSB - - - - - - .1 .0 LSB Figure 11-3. A/D Converter Data Register (ADDATAH/L) 11-3 A/D CONVERTER S3C9404/P9404/C9414/P9414 tCON = 50 CPU clock Conversion Start EOC ADDATAH Previous Value Value remains undetermined Valid Data Figure 11-4. S3C9404 A/D Converter Timing Diagram CONVERSION TIMING (S3C9404) The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 18 clocks to step-up A/D conversion. Therefore, total of 50 clocks are required to complete an 8-bit conversion: With an 10 MHz CPU clock frequency, one clock cycle is 100 ns. If each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 8-bits + step-up time (18 clock) = 50 clocks 50 clock x 100 ns = 5 s at 10 MHz, 1 clock time = CPU clock INTERNAL A/D CONVERSION PROCEDURE 1. Analog input must remain between the voltage range of AVSS and AVREF. 2. Configure the analog input pins to input mode by making the appropriate settings in P3CONH, P3CONL and P2CON registers. 3. Before the conversion operation starts, you must first select one of the eight input pins (ADC0-ADC7) by writing the appropriate value to the ADCON register. 4. When conversion has been completed, (50 CPU clocks have elapsed), the EOC flag is set to "1", so that a check can be made to verify that the conversion was successful. 5. The converted digital value is loaded to the output register, ADDATAH, than the ADC module enters an idle state. 6. The digital conversion result can now be read from the ADDATAH register. 11-4 S3C9404/P9404/C9414/P9414 A/D CONVERTER tCON = 50 x 4/fosc Conversion Start EOC ADDATAH ADDATAL Previous Value Value remains undetermined Valid Data Figure 11-5. S3C9414 A/D Converter Timing Diagram CONVERSION TIMING (S3C9414) The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: With an 10 MHz CPU clock frequency, one clock cycle is 400 ns (4/fosc). If each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10-bits + step-up time (10 clock) = 50 clocks 50 clock x 400 ns = 20 s at 10 MHz, 1 clock time = 4/fOSC INTERNAL A/D CONVERSION PROCEDURE 1. Analog input must remain between the voltage range of AVSS and AVREF. 2. Configure the analog input pins to input mode by making the appropriate settings in P3CONH and P3CONL registers. 3. Before the conversion operation starts, you must first select one of the five input pins (ADC0-ADC4) by writing the appropriate value to the ADCON register. 4. When conversion has been completed, (50 clocks have elapsed), the EOC flag is set to "1", so that a check can be made to verify that the conversion was successful. 5. The converted digital value is loaded to the output register, ADDATAH (8-bit) and ADDATAL (2-bit), than the ADC module enters an idle state. 6. The digital conversion result can now be read from the ADDATAH and ADDATAL register. 11-5 A/D CONVERTER S3C9404/P9404/C9414/P9414 VDD REFERENCE VOLTAGE INPUT R AV REF VDD 104 ANALOG INPUT PIN ADC0-ADC7 S3C9404 S3C9414 101 AV SS VSS NOTE: The symbol "R" signifies an offset resistor with a value of from 50 to 100 . Figure 11-6. Recommended A/D Converter Circuit for Highest Absolute Accuracy + PROGRAMMING TIP PROGRAMMING TIP - Configuring A/D Converter * * * LD LD LD P3CONL,#00001111B P2CON,#11110000B P2DPUR,#00000000B ; P3.1-0 A/D Input MODE ; P2.3-2 A/D Input MODE ; P2 PULL-UP Disable ADCON,#00000001B ADCON,#00001000B Z,AD0_CHK AD0BUFH,ADDATAH AD0BUFL, ADDATAL ; channel ADC0: P3.0/conversion start ; A/D conversion end ? EOC check ; no ; Conversion data ADCON,#01100001B ADCON,#00001000B Z,AD6_CHK AD6BUH,ADDATAH AD6BUFL,ADDATAL ; channel ADC6: P2.2/Conversion start ; A/D conversion end ? EOC check ; no ; Conversion data * * * AD0_CHK: LD TM JR LD LD * * AD6_CHK: LD TM JR LD LD * * 11-6 S3C9404/P9404/C9414/P9414 12 ZERO-CROSSING DETECTION CIRCUIT ZERO-CROSSING DETECTION CIRCUIT OVERVIEW Zero-crossing detection circuit in Samsung's S3C9404/C9414, generates a digital signal in synchronism with an AC signal input. It provides the timing signal for operations which are synchronized with the AC line. The zero crossing detection circuit digitizes the AC signal it receives from the power supply. By setting bits 1 and 0 in port 1 control register (P1CON), you can enable zero-crossing detection. Zero-crossing detector is shown in Figure 12-1. ZCMOD. 3-2 Bit 1 P1CON. 1-0 AC Input P1.0 N/F Edge Detection Bit 0 IRQ0 (ZCINT) 0.1F TIMER 1 COUNTER CLEAR ZCD Enable P1CON. 1-0 Normal Input NOTE: N/F is the abbreviation of noise filter. Figure 12-1. Zero-Crossing Detector Diagram 12-1 ZERO-CROSSING DETECTION CIRCUIT S3C9404/P9404/C9414/P9414 ZERO-CROSSING DETECTOR CONTROL REGISTER The zero crossing detector control register, ZCMOD, is used to select interrupt mode (interrupt on falling edge, rising edge or both). Reset clears ZCMOD to `00H', and configures interrupt selection mode to falling edge and disables ZCD interrupt. The interrupt pending bit must be cleared by writing "0" to ZCMOD.0 ZERO CROSSING DETECTOR CONTROL REGISTERS F5H, R/W, MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used Interrupt Mode Selection Bits: 00 01 10 11 Interrupt on falling edge Interrupt on rising edge Interrupt on both edge Not used ZCD Interrupt Enable Bit: 0 = Disable Interrupt 1 = Enable Interrupt ZCD Interrupt Pending Bit: 0 = No Interrupt Pending (when read) 0 = Clear Pending Bit (when write) 1 = Interrupt is Pending (when read) Figure 12-2. Zero-Crossing Detector Control Register (ZCMOD) 12-2 S3C9404/P9404/C9414/P9414 ZERO-CROSSING DETECTION CIRCUIT ZERO CROSS DETECTOR ZCD circuit detects the zero-cross point of the AC waveform. Three types of detection can be selected, the point from positive to negative, the point from negative to positive, and both. The zero cross detection circuit has the noise filter circuit in it. The detected zero cross point can be used to clear the timer 1 counter (T1CON.3 = 1). 1/fZC AC Input VAZC VAZ(P-P) ZCINT Figure 12-3. Zero-Crossing Waveform Diagram 12-3 ZERO-CROSSING DETECTION CIRCUIT + S3C9404/P9404/C9414/P9414 PROGRAMMING TIP - Configuring ZCD and Timer1 Programming procedure 1. Configure port 1 input pin to alternative function mode by making the appropriate bit setting to P1CON. 2. Select the correct clock source for timer 1 and set bit 3 (T1CON.3 = 1) to enable the ZCD signal to clear the timer 1. Load the proper data to timer 1 data register. 3. Enable the timer 1 interrupt in ZCD interrupt. 4. Set the relay on signal in timer 1 interrupt and disable the timer 1 interrupt. RESET: .ORG .VECTOR 0000H 00H, COMMON_INT .ORG DI LD 0100H LD LD LD LD LD LD CLKCON, #00011000B SP, #0C0H P1CON, #1010101011B ZCMOD, #00001010B T1DATA, #81H T1CON, #00001100B BTCON, #00000010B ; IRQ0/Interrupt vector address ; Reset start address ; Disable interrupt ; Enable watchdog function ; clock source:fosc/4096 ; (104 ms overflow at 10 MHz) ; CPU clock source select (non-divided) ; S3C9404 Stack pointer initial ; P1.0 ZCD input enable/P1.1-3 push-pull ; Enable both edge interrupt ; ZCD clear enable (fosc/512) ; Timer1 interrupt disable * * EI MAIN: ; Enable interrupt * * LD BTCON,#02H ; Enable watchdog function ; Basic counter (BTCNT) clear T,MAIN ; For main loop * * JP * * * COMMON_INT: TM JP TM JP * * * 12-4 ZCMOD, #00000001B NZ, ZCD_INT T1CON, #00000001B NZ, TIMER1_INT S3C9404/P9404/C9414/P9414 + ZERO-CROSSING DETECTION CIRCUIT PROGRAMMING TIP - Configuring ZCD and Timer1 (Continued) TIMER1_INT: AND XOR IRET ZCD_INT: AND XOR LD T1CON, #11111100B P1, #00000100B ; timer1 pending bit clear/t1 int disable ; P1.2 toggle ZCMOD, #11111110B P1, #00001000B T1CON, #00001010B ; pending bit clear ; P1.3 toggle ; Timer1 interrupt enable (fosc/512) ; Enable ZCD clear signal to clear the ; timer 1 counter IRET * * 12-5 S3C9404/P9404/C9414/P9414 13 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this section, the following S3C9404/C9414 electrical characteristics are presented in tables and graphs: -- Absolute maximum ratings -- D.C. electrical characteristics -- A.C. electrical characteristics -- Oscillator characteristics -- Oscillation stabilization time -- Operating Voltage Range -- Schmitt trigger input characteristics -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by a RESET -- A/D converter electrical characteristics -- Zero-crossing detector -- Zero Crossing Waveform Diagram 13-1 ELECTRICAL DATA S3C9404/P9404/C9414/P9414 Table 13-1. Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol Conditions VDD - Rating Unit - 0.3 to + 6.5 V Input voltage VI All input ports - 0.3 to VDD + 0.3 V Output voltage VO All output ports - 0.3 to VDD + 0.3 V Output current I OH One I/O pin active - 18 All I/O pins active - 60 One I/O pin active + 30 Total pin current for ports 1, 2, 3 + 100 Total pin current for ports 0 + 200 high Output current I OL low mA mA Operating temperature TA - - 40 to + 85 C Storage temperature TSTG - - 65 to + 150 C Table 13-2. DC Electrical Characteristics (TA = - 40C to + 85C, VDD = 2.7 V to 5.5 V) Parameter Symbol Conditions Typ Max Unit 0.8 VDD - VDD V - 0.2 VDD V VIH1 Ports 1,2,3, and VIH2 Port 0 0.7 VDD VIH3 XIN and XOUT VDD -0.1 VIL1 Ports 1,2,3, and VIL2 Port 0 VIL3 XIN and XOUT Output high voltage VOH IOH = - 1 mA ports 0, 1, 2, 3 VDD= 4.5 to 5.5 V VDD - 1.0 - - V Output low voltage VOL1 IOL = 15 mA port 0 VDD= 4.5 to 5.5 V - 0.4 2.0 V VOL2 IOL = 4 mA port 1,2,3 VDD= 4.5 to 5.5 V 0.4 2.0 Input high voltage Input low voltage 13-2 RESET RESET VDD= 2.7 to 5.5 V Min VDD= 2.7 to 5.5 V - 0.3 VDD 0.1 S3C9404/P9404/C9414/P9414 ELECTRICAL DATA Table 13-2. DC Electrical Characteristics (Continued) (TA = - 40C to + 85C, VDD = 2.7 V to 5.5 V) Parameter Symbol Input high leakage current ILIH1 All inputs except ILIH2 VIN = VDD ILIH2 XIN, XOUT VIN = VDD ILIL1 All inputs except ILIL2 and RESET VIN = 0 V ILIL2 XIN, XOUT VIN = 0 V Output high leakage current ILOH All outputs VOUT = VDD - - 2 A Output low leakage current ILOL All outputs VOUT = 0 V - - -2 A Pull-up resistors RP VIN = 0 V VDD = 5 V 30 47 70 k RESET VDD = 3 V 30 280 350 Run mode 10 MHz CPU clock VDD = 5 V 10% - 7.5 15 8 MHz CPU clock VDD = 3 V 10% 3 6 Idle mode 10 MHz CPU clock VDD = 5 V 10% 2 5 8 MHz CPU clock VDD = 3 V 10% 0.7 2.5 Stop mode VDD = 5 V 10% 0.1 5 Input low leakage current Supply current IDD1 IDD2 IDD3 Conditions Ports 0-3 and Min Typ Max Unit - - 1 A 20 - - -1 A - 20 mA A VDD = 3 V 10% NOTE: D.C. electrical values for Supply current (IDD1 to IDD3) do not include current drawn through internal pull-up resisters, output port drive current, ZCD and ADC. 13-3 ELECTRICAL DATA S3C9404/P9404/C9414/P9414 Table 13-3. AC Electrical Characteristics (TA = -20C to + 85C, VDD = 2.7 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Interrupt input high, low width tINTH, tINTL Port 2 VDD = 5V 10% - 200 - ns RESET input low width ZCD noise filter tRSL Input VDD = 5V 10% - 1 - s - 1 tCPU tNF1L t NF1H tRSL tNF2 0.8 VDD 0.2 VDD NOTE: The unit tCPU means one CPU clock period. Figure 13-1. Input Timing Measurement Points 13-4 S3C9404/P9404/C9414/P9414 ELECTRICAL DATA Table 13-4. Oscillator Characteristics (TA = - 40C to + 85C) Oscillator Clock Circuit Main crystal or ceramic XIN C1 Test Condition Min Typ Max Unit VDD = 4.5 to 5.5 V VDD = 2.7 to 4.5 V 1 1 - - 10 8 MHz VDD = 4.5 to 5.5 V VDD = 2.7 to 4.5 V 1 1 - - 10 8 VDD = 4.75 to 5.25 V - XOUT C2 External clock XIN XOUT RC oscillator XIN R R = 8.2K 4 (P1.3/ CLO) - XOUT Table 13-5. Oscillation Stabilization Time (TA = - 40C to + 85C, VDD = 2.7 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit ms Main crystal f OSC > 1.0 MHz - - 20 Main ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. - - 10 External clock (main system) XIN input high and low width (tXH, tXL) 25 - 500 ns Oscillator stabilization tWAIT when released by a reset (1) - 216/fOSC - ms wait time tWAIT when released by an interrupt (2) - - - NOTES: 1. fOSC is the oscillator frequency. 2. The duration of the oscillator stabilization wait time, tWAIT, when it is released by an interrupt is determined by the settings in the basic timer control register, BTCON. 13-5 ELECTRICAL DATA S3C9404/P9404/C9414/P9414 CPU CLOCK 10 MHz 8 MHz 4 MHz 3 MHz 2 MHz 1 MHz 1 2 2.7 3 4 5 5.5 6 SUPPLY VOLTAGE (V) Figure 13-2. Operating Voltage Range Vout VDD A = 0.2 V DD B = 0.4 VDD C = 0.6 VDD D = 0.8 VDD VSS A B 0.3 V DD C D Vin 0.7 V DD Figure 13-3. Schmitt Trigger Input Characteristics Diagram 13-6 7 S3C9404/P9404/C9414/P9414 ELECTRICAL DATA Table 13-6. Data Retention Supply Voltage in Stop Mode (TA = - 40C to + 85C, VDD = 2.7 V to 5.5V) Parameter Symbol Conditions Data retention supply voltage VDDDR Stop mode Data retention supply current IDDDR Stop mode; VDDDR = 2.0 V Min Typ Max Unit 2.0 - 5.5 V - 0.1 5 A NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. VDD STOP MODE INTERNAL RESET DATA RETENTION MODE IDLE MODE (BASIC TIMER ACTIVE) NORMAL OPERATING MODE VDDDR RESET EXECUTION OF STOP 0.8 V DD 0.2 V DD t WAIT NOTE: tWAIT is the same as 4096 x 16 x 1/f OSC Figure 13-4. Stop Mode Release Timing When Initiated by a RESET 13-7 ELECTRICAL DATA S3C9404/P9404/C9414/P9414 Table 13-7. A/D Converter Electrical Characteristics (S3C9404) (TA = - 40C to + 85C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Symbol Test Conditions VDD = 5.12 V Total accuracy S3C9404: 8-bit ADC Min Typ Max Unit - - 2 LSB Integral linearity error ILE CPU clock = 10 MHz AVREF = 5.12 V - 1.5 Differential linearity error DLE AVSS = 0 V - 1 Offset error of top EOT -1 2 Offset error of bottom EOB -1 2 Conversion time(1) tCON 5 - - s Analog input voltage VIAN - AVSS - AVREF V Analog input impedance RAN - 2 - - M ADC reference voltage AVREF - 2.5 - VDD V ADC reference ground AVSS - VSS - VSS + 0.3 V Analog input current IADIN AVREF = VDD = 5 V conversion time = 5 s - - 10 A ADC block current (2) IADC AVREF = VDD = 5 V conversion time = 5 s - 1 3 mA 0.5 1.5 100 500 fcpu = 10 MHz AVREF = VDD = 3 V conversion time = 5 s AVREF = VDD = 5 V Power down mode - NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion. 13-8 nA S3C9404/P9404/C9414/P9414 ELECTRICAL DATA Table 13-8. A/D Converter Electrical Characteristics (S3C9414) (TA = - 40C to + 85C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Symbol Test Conditions Resolution VDD = 5.12 V Total accuracy S3C9414: 10-bit ADC Min Typ Max Unit - 10 - bit - - 3 LSB Integral linearity error ILE CPU clock = 10 MHz AVREF = 5.12 V - 2 Differential linearity error DLE AVSS = 0 V - 1 Offset error of top EOT 1 3 Offset error of bottom EOB 0.5 2 Conversion time tCON 10-bit conversion 50 x 4/ fOSC (3) 20 - - s Analog input voltage VIAN - AVSS - AVREF V Analog input impedance RAN - 2 - - M Analog reference voltage AVREF - 2.5 - VDD V Analog ground AVSS - VSS - VSS + 0.3 V Analog input current IADIN AVREF = VDD = 5 V conversion time = 20 s - - 10 A Analog block current (2) IADC AVREF = VDD = 5 V conversion time = 20 s 1 3 mA AVREF = VDD = 3 V conversion time = 20 s 0.5 1.5 mA AVREF = VDD = 5 V when power down mode 100 500 nA (1) NOTES: 1. "Conversion time" is the time required from the moment a conversion operation starts until it ends. 2. IADC is operating current during A/D conversion. 3. fOSC is the main oscillator clock. 13-9 ELECTRICAL DATA S3C9404/P9404/C9414/P9414 Table 13-9. Zero Crossing Detector (TA = - 40C to + 85C, VDD = 4.5 V to 5.5 V, VSS = 0 V) Parameter Zero-crossing detection input voltage Zero-crossing detection accuracy Zero-crossing detection input frequency Symbol VZC VAZC Test Conditions AC connection c = 0.1 F f ZC = 60 Hz Min 1.0 Typ - Max 3.0 Unit Vp-p - - 150 mV 40 - 200 Hz (sine wave) VDD = 5 V f OSC = 10 MHz - f ZC 1/fZC AC Input VAZC ZCINT Figure 13-5. Zero Crossing Waveform Diagram 13-10 VAZ(P-P) S3C9404/P9404/C9414/P9414 ELECTRICAL DATA 70 VDD = 5.5 V 60 VDD = 5.0 V 50 VDD = 4.5 V 40 I OL (mA) 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VOL (V) Figure 13-6. IOL vs. VOL (P0, TA = 25 C) 13-11 ELECTRICAL DATA S3C9404/P9404/C9414/P9414 50 VDD = 5.5 V 40 VDD = 5.0 V I OL (mA) VDD = 4.5 V 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VOL (V) Figure 13-7. IOL vs. VOL (P1-P3, TA = 25 C) 13-12 4.5 5.0 5.5 S3C9404/P9404/C9414/P9414 ELECTRICAL DATA - 36 - 32 - 28 - 24 20 I OH - (mA) - 16 VDD = 5.5 V - 12 VDD = 5.0 V -8 VDD = 4.5 V -4 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VOH (V) Figure 13-8. IOH vs. VOH (P0, TA = 25 C) 13-13 ELECTRICAL DATA S3C9404/P9404/C9414/P9414 - 24 20 I OH - (mA) - 16 - 12 VDD = 5.5 V -8 VDD = 5.0 V -4 VDD = 4.5 V 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VOH (V) Figure 13-9. IOH vs. VOH (P1-P3, TA = 25 C) 13-14 5.0 5.5 S3C9404/P9404/C9414/P9414 14 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C9404/C9414 is available in a 30-pin SDIP package (Samsung: 30-SDIP-400) and a 32-pin SOP package (32-SOP-450A), a 24-pin SDIP package (24-SDIP-300) and a 24-pin SOP package (24-SOP-375). Package dimensions are shown in Figures 14-1, 14-2, 14-3, and 14-4. #16 - 0.05 0.25 +0.1 30-SDIP-400 0.56 0.1 (1.30) 1.12 0.1 1.778 5.08MAX 27.48 0.2 3.30 0.3 27.88 MAX 3.81 0.2 #15 0.51MIN #1 0-15 10.16 8.94 0.2 #30 NOTE: Dimensions are in millimeters. Figure 14-1. 30-Pin SDIP Package Dimensions 14-1 MECHANICAL DATA S3C9404/P9404/C9414/P9414 0~8 #16 (0.43) 0.2 0.40 0.1 1.27 0.0MIN 19.90 0.20 2.00 0.2 #1 +0.10 - 0.05 0.10 MAX NOTE: Dimensions are in millimeters. Figure 14-2. 32-SOP-450A Package Dimensions 14-2 0.2 0.78 32-SOP-450A 11.43 8.34 0.2 #17 2.40MAX 12.00 0.3 #32 S3C9404/P9404/C9414/P9414 MECHANICAL DATA #13 0.89 0.1 1.778 - 0.05 5.08MAX 0.46 0.1 3.30 0.3 22.95 0.2 3.25 0.2 #12 23.35 MAX (1.69) 0.25 +0.1 7.62 24-SDIP-300 #1 0-15 0.51MIN 6.40 0.2 #24 NOTE: Dimensions are in millimeters. Figure 14-3. 24-SDIP-300 Package Dimensions 14-3 MECHANICAL DATA S3C9404/P9404/C9414/P9414 0-8 #12 15.34 0.2 0.38 0.1 1.27 0.05MIN 15.74 MAX (0.69) +0.10 0.15 - 0.05 2.30 0.2 #1 0.10 MAX NOTE: Dimensions are in millimeters. Figure 14-4. 24-SOP-375 Package Dimensions 14-4 0.85 0.20 24-SOP-375 9.53 7.50 0.2 #13 2.70MAX 10.30 0.3 #24 S3C9404/P9404/C9414/P9414 15 S3P9404/P9414 OTP S3P9404/P9414 OTP OVERVIEW The S3P9404/P9414 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9404/C9414 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P9404/P9414 is fully compatible with the S3C9404/C9414 , both in function and in pin configuration. Because of its simple programming requirements, the S3P9404/P9414 is ideal for use as an evaluation chip for the S3C9404/C9414 . VSS/VSS XIN XOUT VPP/TEST P0.1 P0.0 RESET/RESET P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S3P9404 30-SDIP (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD/ VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P0.7 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P1.3/CLO P2.0/INT0 P2.1/INT1 P2.2/ADC6 P2.3/ADC7 NOTE: The bolds indicate an OTP pin name. Figure 15-1. Pin Assignment Diagram (30-Pin SDIP Package) 15-1 S3P9404/P9414 OTP S3C9404/P9404/C9414/P9414 VSS/VSS XIN XOUT VPP/TEST P0.1 P0.0 RESET/RESET NC P3.5/ADC5 P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 AVSS AVref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3P9404 32-SOP (Top View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD/ VDD P0.2/SCLK P0.3/SDAT P0.4 P0.5 P0.6 P0.7 NC P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P1.3/CLO P2.0/INT0 P2.1/INT1 P2.2/ADC6 P2.3/ADC7 NOTE: The bolds indicate an OTP pin name. Figure 15-2. Pin Assignment Diagram (32-Pin SOP Package) 15-2 S3C9404/P9404/C9414/P9414 S3P9404/P9414 OTP VSS/V SS XIN XOUT VPP/TEST P0.1 P0.0 RESET/RESET P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 1 2 3 4 5 6 7 8 9 10 11 12 S3P9414 24-SDIP (Top View) 24 23 22 21 20 19 18 17 16 15 14 13 VDD/ VDD P0.2/ SCLK P0.3/ SDAT P0.4 P0.5 P0.6 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P2.0/INT0 AVref AVSS NOTE: The bolds indicate an OTP pin name. Figure 15-3. Pin Assignment Diagram (24-Pin SDIP Package) 15-3 S3P9404/P9414 OTP S3C9404/P9404/C9414/P9414 VSS/V SS XIN XOUT VPP/TEST P0.1 P0.0 RESET/RESET P3.4/ADC4 P3.3/ADC3 P3.2/ADC2 P3.1/ADC1 P3.0/ADC0 1 2 3 4 5 6 7 8 9 10 11 12 S3P9414 24-SOP (Top View) 24 23 22 21 20 19 18 17 16 15 14 13 VDD/ VDD P0.2/ SCLK P0.3/ SDAT P0.4 P0.5 P0.6 P1.0/ZCD P1.1/BUZ P1.2/T0(PWM) P2.0/INT0 AVref AVSS NOTE: The bolds indicate an OTP pin name. Figure 15-4. Pin Assignment Diagram (24-Pin SOP Package) 15-4 S3C9404/P9404/C9414/P9414 S3P9404/P9414 OTP Table 15-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P0.3 SDAT S3P9404: 28 (30) S3P9414: 22 (22) I/O Serial data pin (output when reading, Input when writing) Input and push-pull output port can be assigned P0.2 SCLK S3P9404: 29 (31) S3P9414: 23 (23) I/O Serial clock pin (input only pin) TEST VPP (TEST) 4 I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) RESET RESET 7 I Chip Initialization VDD/VSS VDD/VSS I Logic power supply pin. S3P9404: 30 (32) / 1 S3P9414: 24 (24) / 1 NOTE: ( ) means the SOP OTP pin number. Table 15-2. Comparison of S3P9404/P9414and S3C9404/C9414 Features Characteristic S3P9404/P9414 S3C9404/C9414 4-Kbyte EPROM 4-Kbyte mask ROM Operating Voltage (VDD) 2.7 V to 5.5 V 2.7 V to 5.5 V OTP Programming Mode VDD = 5 V, VPP (TEST) = 12.5 V Program Memory Pin Configuration 30 SDIP/32 SOP/24 SDIP/24 SOP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3P9404/P9414, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-3. Operating Mode Selection Criteria VDD VPP REG/MEM MEM (TEST) 5V ADDRESS R/W MODE (A15-A0) 5V 0 0000H 1 EPROM read 12.5 V 0 0000H 0 EPROM program 12.5 V 0 0000H 1 EPROM verify 12.5 V 1 0E3FH 0 EPROM read protection NOTE: "0" means Low level; "1" means High level. 15-5 S3C9404/P9404/C9414/P9414 16 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for S3C7, S3C8, S3C9 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options. SHINE Samsung Host Interface for in-circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. SASM86 The SASM86 is an relocatable assembler for Samsung's S3C9-series microcontrollers. The SASM86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM86 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by HEX2ROM, the value "FF" is filled into the unused ROM area upto the maximum ROM size of the target device automatically. TARGET BOARDS Target boards are available for all S3C9-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. OTPs One times programmable microcontrollers (OTPs) are under development for S3C9404/C9414 microcontroller. 16-1 DEVELOPMENT TOOLS S3C9404/P9404/C9414/P9414 IBM-PC AT or Compatible RS-232C SMDS2+ TARGET APPLICATION SYSTEM PROM/OTP WRITER UNIT RAM BREAK/ DISPLAY UNIT BUS PROBE ADAPTER TRACE/TIMER UNIT POD SAM8 BASE UNIT TB9404/9414 TARGET BOARD POWER SUPPLY UNIT Figure 16-1. SMDS Product Configuration (SMDS2+) 16-2 EVA CHIP S3C9404/P9404/C9414/P9414 DEVELOPMENT TOOLS TB9404/9414 TARGET BOARD The TB9404/9414 target board is used for the S3C9404/C9414 microcontrollers. It is supported by the SMDS2+ development systems. The TB9404/9414 target board can also be used for S3C9404/C9414. TB9404/9414 To User_Vcc On Vcc Off Stop + + U1 Idle GND RESET 25 J101 100 QFP S3E9400 EVA CHIP CN1 15 1 1 30 30-Pin DIP Socket 100-PIN Connector 1 16 30 External Triggers CH1 CH2 SMDS2 SMDS2+ SM1312A Figure 16-2. TB9404/9414 Target Board Configuration 16-3 DEVELOPMENT TOOLS S3C9404/P9404/C9414/P9414 Table 16-1. Power Selection Settings for TB9404/9414 "To User_Vcc" Settings Operating Mode Comments To User_Vcc OFF a TB9404 /9414 ON TARGET SYSTEM VCC VSS The SMDS2+ main board supplies VCC to the target board (evaluation chip) and the target system. VCC SMDS2+ To User_Vcc OFF a TB9404 /9414 ON TARGET SYSTEM External VCC VSS VCC The SMDS2+ main board supplies VCC only to the target board (evaluation chip). The target system must have its own power supply. SMDS2+ NOTE: The following symbol in the "To User_Vcc" Setting column indicates the electrical short (off) configuration: a SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 16-2. The SMDS2+ Tool Selection Setting "SW1" Setting SMDS2 SMDS2+ Operating Mode R/W* SMDS2+ 16-4 R/W* TARGET BOARD S3C9404/P9404/C9414/P9414 DEVELOPMENT TOOLS Table 16-3. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part EXTERNAL TRIGGERS CH1 Comments Connector from external trigger sources of the application system CH2 a You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace functions. 16-5 DEVELOPMENT TOOLS S3C9404/P9404/C9414/P9414 J101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30-PIN CONNECTOR VSS NC NC VSS P0.1 P0.0 RESET P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 AVSS AVref 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VCC P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 Figure 16-3. 30-Pin Connector for TB9404/9414 TARGET BOARD TARGET SYSTEM J101 30-PIN CONNECTOR 1 1 30 30 1 30 Part Name: AP30SD-D Order Code: SM6523 15 30 SDIP Conversion PCB 16 15 15 16 16 Figure 16-4. S3C9C4004 Probe Adapter for 30-SDIP Package 16-6 S3C9404/P9404/C9414/P9414 DEVELOPMENT TOOLS TARGET BOARD TARGET SYSTEM J101 30-PIN CONNECTOR 1 1 30 24 1 30 24 SDIP Conversion PCB Part Name: AP24SD-A Order Code: SM6531 15 16 12 15 16 13 Figure 16-5. S3C9C4104 Probe Adapter for 24-SDIP Package 16-7