Product Brief April 2003 MARS1G2 T-LT (TSOT021G2) SONET/SDH 155/622 Mbits/s Overhead and Path Processor Features One of the next generation system on a chip devices of Agere Systems' multiapplication & rate solutions MARSTM family of framers. Transmission convergence and SONET/SDH terminal/ADM functionality for linear and ring networks. Versatile IC supports 155/622 Mbits/s SONET/ SDH overhead and path processor solutions. Low-power 1.6/3.3 V operation. SONET/SDH Interface -- T1.105: SONET-Basic Description including Multiplex Structure, Rates, and Formats. -- T1.105.02 SONET-Payload Mappings. -- T1.105.03 SONET-Jitter at Network Interfaces. -- T1.105.06 SONET Physical Layer Specifications. -- T1.105.07 SONET-Sub-STS-1 Interface Rates and Formats Specification. -- ITU-T I.432: B-ISDN User-Network InterfacePhysical Layer Specification. -- IETF RFC 2615: PPP over SONET/SDH. -- IETF RFC 1661: The Point-to-Point Protocol (PPP). -- IETF RFC 1662: PPP in HDLC-like Framing. Interfaces Termination of quad STS-3/STM-1 or dual STS-12/ STM-4. Built-in redundant STS/STM backplane interface using 622 MHz LVDS technology. Supports overhead processing for transport and path overhead bytes. Optional insertion and extraction of overhead bytes via serial overhead interface. Mate-to-mate backplane interface using 622 MHz LVDS technology for 1 + 1, 1:1, BLSR, and UPSR network support. STS pointer processing to align the receive frame to the system frame. Optional 78 MHz bus (32-bit) for STS/STM interface. IEEE(R) 1149.1 port with BIST, scan, and boundry scan. STS-1 granularity cross connect between receive, mate, STM, and data payloads. Support for 1 + 1 and 1:1 linear networks; UPSR and BLSR ring networks. Microprocessor Interface Full path termination and SPE extraction/insertion. Up to 66 MHz synchronous. SONET/SDH compliant condition and alarm reporting. 16-bit address and 16-bit data interface. Synchronous or asynchronous modes available. Handles all concatenation levels of STS-3c to STS-24c (in multiples of 3: e.g., 3c, 6c, 9c, etc.). Configurable to operate with most commercial microprocessors. Built-in diagnostic loopback modes. Compliant with the following Telcordia Technologies(R), ANSI(R), and ITU standards: -- GR-253 CORE: SONET Transport Systems: Common Generic Criteria. -- ITU-T G.707: Network Node Interface for the Synchronous Digital Hierarchy. -- ITU-T G.803: Architecture of Transport Networks Based on the Synchronous Digital Hierarchy. MARS1G2 T-LT (TSOT021G2) SONET/SDH 155/622 Mbits/s Overhead and Path Processor Product Brief April 2003 Description The MARS1G2 T-LT SONET/SDH overhead and path processor provides a versatile solution for quad OC-3 and dual OC-12, linear and ring datacom/telecom applications. Constructed using COM2 CMOS modular process, this device incorporates integrated SONET/SDH section/line/path termination, pointer processing, and cross connect blocks. Communication with the MARS1G2 T-LT device is accomplished through a generic microprocessor interface. The device supports separate address and data buses. With this device, support for different types of applications for OC-3/OC-12 data equipment is possible, enabling dramatic system cost reduction and the ease of development of extremely competitive solutions. The interface rates supported are dual STS-12/STM-4 and quad STS-3/STM-1. The concatenation levels supported by this device are STS-1, STS-3c, STS-6c, STS-9c, STS-12c, STS-15c, . . . , STS-21c, and STS-24c. MATE INTERFACE LINE INTERFACE SWITCHING TSI 3 STM INTERFACE* 3 PATH SWITCH DUAL STM-4/STS-12 OR QUAD STM-1/STS-3 STMLSI 78 MHz LINE SWITCH TRANSPORT OVERHEAD TERMINATION OVERHEAD PROCESSOR MONITOR POINTER PROCESSOR DUAL STM-4/STS-12 OR QUAD STM-1/STS-3 OVERHEAD PROCESSOR INSERT INTERFACE BLOCK TXCLK DUAL STM BACKPLANE INTERFACE PT CONNECTION MEMORY CONTROL MPU INTERFACE TXTOAC RXTOAC (PTR INTER) MISCELLANEOUS GPIO/STMDCC TOAC INTERFACE Note: PT = path terminator. * An STM low-speed interface (STMLSI) is available. Figure 1. MARS1G2 T-LT Block Diagram 2 Agere Systems Inc. Product Brief April 2003 MARS1G2 T-LT (TSOT021G2) SONET/SDH 155/622 Mbits/s Overhead and Path Processor Target Applications Supported MARS1G2 T-LT (792-Pin PBGA) This multirate/multiprotocol/multimode SONET/SDH add/drop multiplexer device targets the following applications. See Figure 2 for device interface speed/rate information: PON. Access/core router. MATE INTERFACE (2 x 622 Mbits/s OR 4 x 155 Mbits/s LVDS) LINE INTERFACE SWITCHING TSI 3 STM INTERFACE* 3 DUAL (1 x 622 Mbits/s LVPECL) or QUAD (1 x 155 Mbits/s LVPECL) STMLSI 78 MHz LINE SWITCH TRANSPORT OVERHEAD TERMINATION OVERHEAD PROCESSOR MONITOR POINTER PROCESSOR TXCLK OVERHEAD PROCESSOR INSERT INTERFACE BLOCK DUAL (1 x 622 Mbits/s LVPECL) or QUAD (1 x 155 Mbits/s LVPECL) PATH SWITCH DUAL STM BACKPLANE INTERFACE (DUAL 2 x 622 Mbits/s OR 4 x 155 Mbits/s LVDS) PT CONNECTION MEMORY CONTROL TXTOAC RXTOAC MPU INTERFACE (PTR INTER) MISCELLANEOUS GPIO/STMDCC * An STM low-speed interface (STMLSI) is available. Figure 2. MARS1G2 T-LT Device Interface Speed/Rate Diagram Agere Systems Inc. 3 Telcordia Technologies is a trademark of Telcordia Technologies, Inc. ANSI is a registered trademark of American National Standards Institute, Inc. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc. MARS is a trademark of Agere Systems Inc. Copyright (c) 2003 Agere Systems Inc. All Rights Reserved April 2003 PB03-088SONT