DS1338U-33 - Maxim Integrated - Datasheet.Directory

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GENERAL DESCRIPTION

The DS1338 serial real-time clock (RTC) is a low-

power, full binary-coded decimal (BCD)

clock/calendar plus 56 bytes of NV SRAM. Address

and data are transferred serially through an I2C

interface. The clock/calendar provides seconds,

minutes, hours, day, date, month, and year

information. The end of the month date is

automatically adjusted for months with fewer than 31

days, including corrections for leap year. The clock

operates in either the 24-hour or 12-hour format with

AM/PM indicator. The DS1338 has a built-in power-

sense circuit that detects power failures and

automatically switches to the backup supply,

maintaining time and date operation

APPLICATIONS

Handhelds (GPS, POS Terminal)

Consumer Electronics (Set-Top Box, Digital

Recording, Network Appliance)

Office Equipment (Fax/Printer, Copier)

Medical (Glucometer, Medicine Dispenser)

Telecommunications (Router, Switcher, Server)

Other (Utility Meter, Vending Machine, Thermostat,

Modem)

UL is a registered trademark of Underwriters Laborat ori es I nc.

TYPICAL OPERATING CIRCUIT

BENEFITS AND FEATURES

• Completely Manages All Timekeeping

Functions

o RTC Counts Seco nd s, Minutes, Hours,

Date of the Month, Month, Day of the

Week, and Year with Leap-Year

Compensation Valid Up to 2100

o 56-Byte, Batt er y-Backed, Gen eral-

Purpose RAM with Unlimited Writes

o Programmable Square-Wave Output

Signal

• Surface-Mount Package with an Integrated

Crystal (DS1338C) Saves Additional Space

and Simplifies Design

• Interfa ces with Most Microc ontrol le rs

o I2C Serial Interface

• Low-Power Operation Extends Battery

Backup Ru n Time

o Automatic Power-Fail Detec t and Switch

Circuitry

• -40

C to +85

C Industrial Temperature Range

Supports Operation in a Wide Range of

Applications

• Underwriters Laboratories (UL®) Recognized

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE TOP MARK†

DS1338Z-18+

-40°C to +85°C

8 SO (0.150

″

)

DS1338-18

DS1338Z-3+

-40°C to +85°C

8 SO (0.150″)

DS1338-3

DS1338Z-33+

-40°C to +85°C

8 SO (0.150″)

DS133833

DS1338U-18+ -40°C to +85°C 8 µSOP

1338

rr-18

DS1338U-3+ -40°C to +85°C 8 µSOP

1338

rr-3

DS1338U-33+ -40°C to +85°C 8 µSOP

1338

rr-33

DS1338C-18#

-40°C to +85°C

16 SO (0.300

″

)

DS1338C-18

DS1338C-3#

-40°C to +85°C

16 SO (0.300″)

DS1338C-3

DS1338C-33#

-40°C to +85°C

16 SO (0.300″)

DS1338C-33

rr = second line, revision level

+ Denotes a lead(Pb)-free/RoHS-compliant dev ic e.

# Denotes a RoHS-compliant device that may include lead that is

exempt under the RoHS requirements. The lead finish is JESD97

category e3, and is compatible with both lead-bas ed and lead-free

soldering processes.

† A “+” anywhere on the top mark denotes a lead-free device. A “#”

denotes a RoHS-compliant device.

Pin Configurations appear at end of data sheet.

DS1338

CPU

SDA

SCL

GND

CRYSTAL

SQW/OUT

BAT

= t

DS1338

I2C RTC with 56-Byte NV RAM

19-6019; Rev 4/15

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ABSOLUTE MAXIMUM RATINGS

Voltage Range on Any Pin Relative to Ground………………………………………………………..……..-0.3V to +6.0V

Operating Temperature Range…………………………………………………………………………..……-40°C to +85°C

Storage Temperature Range………………………………………………………………………………...-55°C to +125°C

Lead Temperature (soldering, 10s) ……….………………………………………………………………………. +260°C

Soldering Temperature (reflo w) …………………… ………………………………………………………………. +260°C

Stresses beyond those listed under “Absolute Maximum Ratings” may c ause permanent damage to the devic e. These are stress ratings only,

and functional operat ion of the device at these or any other conditions bey ond those indicated in the operational s ecti ons of the specifications is

not implied. Exposure to the absolute maximum rating condit i ons for extended periods may aff ect device reliabi l i ty.

RECOMMENDED DC OPERATING CONDITIONS

(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, unless

otherwise noted.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Suppl y Voltage VCC

DS1338-18

1.71

1.8

5.5

DS1338-3

2.7

3.0

5.5

DS1338-33

3.0

3.3

5.5

Logic 1 VIH (Note 2)

0.7 x

VCC

0.3

Logic 0 VIL (Note 2) -0.3

+0.3 x

VCC

Power-Fail Voltage VPF

DS1338-18

1.51

1.62

1.71

DS1338-3

2.45

2.59

2.70

DS1338-33

2.70

2.82

2.97

VBAT Input Voltage VBAT (Note 2) 1.3 3.0 3.7 V

DC ELECTRICAL CHARACTERISTICS

(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = TYP,

TA = +25°C, unless otherwise noted.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input Leakage ILI (Note 3) 1 µA

I/O Leakage ILO (Note 4) 1 µA

SDA Logic 0 Output IOLSDA

VCC > 2V; VOL = 0.4V

3.0

< 2V; V

= 0.2 x V

3.0

SQW/OUT Logic 0 Output IOLSQW

> 2V; V

= 0.4V

3.0

1.71V < V

< 2V;

VOL = 0.2 x VCC

3.0

1.3V < V

< 1.71V;

VOL = 0.2 x VCC

250 µA

Active Supply Current

(Note 5) ICCA

DS1338-18: VCC = 1.89V

150

µA

DS1338-3: VCC = 3.30V

110

200

DS1338-33

VCC = 3.63V

120

200

VCC = 5.5V

325

Standby Current (Note 6) ICCS

DS1338-18: VCC = 1.89V

100

µA

DS1338-3: VCC = 3.30V

125

DS1338-33

VCC = 3.63V

125

VCC = 5.5V

200

VBAT Leakage Current

(VCC Active) IBATLKG 25 100 nA

DS1338

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DC ELECTRICAL CHARACTERISTICS

(VCC = 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VBAT = 3.0V, TA = +25°C, unl e s s

otherwise noted.) (Note 1)

PARAMETER SYMBOL MIN TYP MAX UNITS

VBAT Current (OSC ON); VBAT = 3.7V, SQW/OUT OFF (Note 7) IBATOSC1 800 1200 nA

VBAT Current (OSC ON); VBAT = 3.7V, SQW/OUT ON (32kHz)

(Note 7) IBATOSC2 1025 1400 nA

VBAT Data-Retention Current (Osc Off); VBAT = 3.7V (Note 7) IBATDAT 10 100 nA

AC ELECTRICAL CHARACTERISTICS

(VCC = VCC(MIN) to VCC(MAX), TA = -40°C to +85°C) (Note 1)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS

SCL Clock Frequency fSCL

Fast mode

100

400

kHz

Standard mode 0 100

Bus Free Time Between STOP

and START Condition tBUF Fast mode 1.3 µs

Standard mode 4.7

Hold Time (Repeated) START

Condition (Note 8) tHD:STA Fast mode 0.6 µs

Standard mode 4.0

LOW Period of SCL Clock tLOW Fast mode 1.3 µs

Standard mode 4.7

HIGH Period of SCL Clock tHIGH Fast mode 0.6 µs

Standard mode 4.0

Setup Time for Repeated

START Condi ti on tSU:STA Fast mode 0.6 µs

Standard mode 4.7

Data Hold Time (Notes 9, 10) tHD:DAT Fast mode 0 0.9 µs

Standard mode 0

Data Setup Time (Note 11) tSU:DAT Fast mode 100 ns

Standard mode 250

Rise Time of Both SDA and

SCL Signals (Note 12) tR Fast mode 20 + 0.1CB 300 ns

Standard mode 20 + 0.1CB 1000

Fall Time of Both SDA and

SCL Signals (Note 12) tF Fast mode 20 + 0.1CB 300 ns

Standard mode 20 + 0.1CB 300

Setup Time for STOP

Condition tSU:STO Fast mode 0.6 µs

Standard mode 4.0

Capacitive Load for Each Bus

Line CB (Note 12) 400 pF

I/O Capacitance (SDA, SCL) CI/O (Note 13) 10 pF

Oscillator Stop Flag (OSF)

Delay tOSF (Note 14) 100 ms

DS1338

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POWER-UP/POWER-DOWN CHARACTERISTICS

(TA = -40°C to +85°C) (Note 1, Figure 1)

PARAMETER SYMBOL MIN TYP MAX UNITS

Recovery at Power-Up (Note 15) tREC 2 ms

VCC Fall Time; VPF(MAX) to VPF(MIN) tVCCF 300 µs

VCC Rise Time; VPF(MIN) to V PF(MAX) tVCCR 0 µs

Warning: Negative undershoots below -0.3V while the part is in battery-backed mode may cause

loss of data.

Note 1:

Limi ts at -40°C are guaranteed by design and not production tested.

Note 2:

All voltages are referenc ed to ground.

Note 3:

SCL only.

Note 4:

SDA and SQW/OUT.

Note 5:

ICCA—SCL clocking at max frequency = 400kHz.

Note 6:

Specified with the I

C bus inactive.

Note 7:

Measured with a 32.768kHz crystal attached to X1 and X2.

Note 8:

After this period, t he first clock puls e is generat ed.

Note 9: A device must internall y provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to

bridge the undefined region of the falli ng e dge of SCL.

Note 10:

The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

Note 11: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is

automatical l y the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW

period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line

is released.

Note 12:

CB—total capacitance of one bus line in pF.

Note 13:

Guaranteed by design. Not production t ested.

Note 14: The parameter tOSF is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of

0.0V ≤ VCC ≤ VCC(MAX) and 1.3V ≤ VBAT ≤ 3.7V.

Note 15: This delay applies only if the oscillator is enabled and runni ng. If the oscill at or is disabled or stopped, no power-up delay occ urs.

Figure 1. Power-Up/Power-Down Timing

OUTPUTS

PF(MAX)

PF(MIN)

INPUTS

HIGH-Z

DON'T CARE

VALID

RECOGNIZED

VALID

VCCF

VCCR

REC

DS1338

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Figure 2. Timing Diagram

Figure 3. Block Diagram

RAM

(56 X 8)

SERIAL BUS

INTERFACE

AND ADDRESS

CONTROL

LOGIC

1Hz

1Hz/4.096kHz/8.192kHz/32.768kHz MUX/

BUFFER

USER BU FFER

(7 BYTES)

CLOCK,

CALENDAR,

AND CONTROL

REGISTERS

"C" VERSION ONLY

POWER

CONTROL

DS1338

SDA

SCL

SQW/OUT

GND

BAT

Oscillator

and divider

DS1338

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TYPICAL OPERATING CHARACTERISTICS

BAT

vs. V

BAT

550

600

650

700

750

800

850

900

950

1000

1050

1100

1150

1200

1250

1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

BAT

(V)

SUPPLY CURRENT (nA

VCC=0V

RS1=RS0=1

IBATOSC2

(SQWE = 1)

IBATOSC1

(SQWE = 0)

BAT

vs. Temper at ur e

BAT

= 3.0V

600

650

700

750

800

850

900

950

1000

-40 -20 020 40 60 80

TEMPERATURE (°C)

SUPPLY CURRENT (nA

VCC=0V

SQWE=1

SQWE=0

vs. V

100

125

150

175

200

225

250

1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3

(V)

SUPPLY CURRENT (uA

SCL=400kHz

SCL=SDA=0Hz

Oscillator Frequency vs. Suppl y Volt age

32768.0

32768.1

32768.2

32768.3

32768.4

32768.5

1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8

Oscillator Supply Voltage (V)

FREQUENCY (Hz)

DS1338

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PIN DESCRIPTION

NAME FUNCTION

1 — X1 32.768kHz Crystal Connections. The internal oscillator circuitry is designed for

operation with a crystal having a specified load capacitance (CL) of 12.5pF. An

external 32.768kHz oscillator can also drive the DS1338. In this configuration,

the X1 pin is connected to the external oscillator signal and the X2 pin is left

unconnected.

Note: For more information about crystal selection and crystal layout considerations,

refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.

2 — X2

3 14 VBAT

Backup Supply Input for Lithium Cell or Other Energy Source. Battery voltage

must be held between the minimum and maximum limits for proper operation.

Diodes placed in series between the backup source and the VBAT pin may

prevent proper operation. If a backup supply is not required, VBAT must be

grounded. UL recognized to ensure against reverse charging when used with a

lithium cell. For more information, visit www.maxim-ic.com/qa/info/ul.

4 15 GND

Ground. DC power is provided to the device on these pins. VCC is the primary

power input. When voltage is applied within normal limits, the device is fully

accessible and data can be written and read. When a backup supply is

connected to the device and VCC is below VPF, reads and writes are inhibited.

However, the timekeeping function continues unaffected by the lower input

voltage.

5 16 SDA

Serial Data. Input/output pin for the I2C serial interface. It is an open drain

output and requires an external pullup resistor. The pull up voltage may be up

to 5.5V regardless of the voltage on VCC.

6 1 SCL

Serial Clock. Input pin for the I2C serial interface. Used to synchronize data

movement on the serial interface. The pull up voltage may be up to 5.5V

regardless of the voltage on VCC.

7 2 SQW/OUT

Square-Wave/Output Driver. When enabled and the SQWE bit set to 1, the

SQW/OUT pin outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz,

32kHz). It is an open drain output and requires an external pullup resistor.

Operates with ei ther VCC or VBAT applied. The pull up voltage may be up to

5.5V regardless of the voltage on VCC. If not used, this pin may be left

unconnected.

8 3 VCC

Primary Power Supply. When voltage is applied within normal limits, the device

is fully accessible and data can be w ritten and read. When a backup supply is

connected to the device and VCC is below VPF, reads and writes are inhibited.

The backup supply maintains the timekeeping function while VCC is absent.

— 4–13 N.C. No Connection. These pins are not connected internally, but must be grounded

for proper operation.

DETAILED DESCRIPTION

The DS1338 s erial RTC is a low-power, f ull BCD c lock/cal endar plus 56 b ytes of NV SR AM. Address and d ata are

transferred serially through an I2C interface. The clock/calendar provides seconds, minutes, hours, day, date,

month, and year information. The end of the month date is automatically adjusted for months with fewer than 31

days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM

indicator. The DS1338 has a built-in power-sense circuit that detects power failures and automatically switches to

the VBAT supply.

DS1338

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OPERATION

The DS1338 o perates as a slave dev ice on the serial bus. Acc ess is obtai ned by impl ementing a START condition

and providing a device identification code, followed by data. Subsequent registers can be accessed sequentially

until a STOP condition is executed. The device is fully accessible and data can be written and read when VCC is

greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If

VPF is less than VBAT, the device power is switched from VCC to VBAT when VCC drops below VPF. If VPF is greater

than VBAT, the device power is switched from VCC to VBAT when VCC drops below VBAT. The oscillator and

timekeeping functions are maintained from the VBAT source until VCC is returned to nominal levels. The block

diagram (Figure 3) shows the main elements of the DS1338.

An enable bit in the seconds register controls the oscillator. Oscillator startup times are highly dependent upon

crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major

contribut ors to l ong s tart -up ti m es . A ci r cui t us i ng a c r ys tal with th e r ecom mended c har ac teri s ti cs and pr o per l a yout

usually starts within 1 second.

POWER CONTROL

The power-control function is provided by a precise, temperature-compensated voltage reference and a

compar ator c i rc uit that m oni tor s the VCC l evel . T he devic e i s full y accessi bl e and data c an be writt en and rea d when

VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any

access. If VPF is les s than VBAT, t he devic e power i s switche d from V CC to VBAT when VCC drops belo w VPF. If VPF is

greater than VBAT, the device power is switched from VCC to VBAT when VCC drops below VBAT. The registers are

maintai ned fr om the VBAT s ource unti l VCC is returned t o nomi nal l evels (Table 1). After VCC r eturns ab ove VPF, read

and write access is allowed after tREC (Figure 1). On the first application of power to the device the time and date

registers are reset to 01/01/00 01 00:00:00 (DD/MM/YY DOW HH:MM:SS). The CH bit in the seconds register will be set

to a 0.

Table 1. Power Control

SUPPLY

CONDITION READ/WRITE

ACCESS POWERED

VCC < VPF, VCC < VBAT

VBAT

VCC < VPF, VCC > VBAT

VCC

VCC > VPF, VCC < VBAT

Yes

VCC

> V

, V

> V

BAT

Yes

OSCILLATOR CIRCUIT

The DS1338 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or

capacitors to operate. Table 2 specifies several crystal parameters for the external crystal. Figure 3 shows a

functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal

with the specified characteristics.

Table 2. Crystal Specifications*

PARAMETER SYMBOL MIN TYP MAX UNITS

Nominal Frequency fO 32.768 kHz

Series Resistance ESR 50 kΩ

Load Capacitance CL 12.5 pF

*The crystal, t races, and crystal input pins should be isolated from RF generating signals. Refer to

Applic ation Note 58: Crystal Considerati ons for Dallas Real-Time Cloc ks for additional specifications.

DS1338

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CLOCK ACCURACY

The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between

the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal

frequency drift caused by temperature shifts creates additional error. External circuit noise coupled into the

oscillator circuit can result in the clock running fast. Figure 4 shows a typical PC board layout for isolating the

crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks

for detailed information.

DS1338C ONLY

The DS1338 C integrates a s tandard 32,768H z c rystal in the package. T ypical accuracy at nominal VCC and +25°C

is approximately 10ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature.

Figure 4. Typical PC Board Layout for Crystal

RTC AND R AM AD DRESS MAP

Table 3 shows the address map for the RTC and RAM registers. The RTC registers and control register are located

in address l oc ati ons 0 0h to 07h. T he R A M r egi st ers are located i n ad dres s l ocat ions 08h to 3F h. D ur i ng a m u l ti b yte

access, when the register pointer reaches 3Fh (the end of RAM space) it wraps around to location 00h (the

beginning of the clock space). On an I2C START, STOP, or register pointer incrementing to location 00h, the

current time and date is transferred to a second set of registers. The time and date in the secondary registers are

read in a multib yte data tra nsfer, while the cl ock conti nues to run. T his el iminates the n eed to re-r ead the r egister s

in case of an update of the main registers during a read.

CLOCK AND CALENDAR

The tim e and calendar inform ation is obtained b y re ading the appropr iate register b yt es. See Figure 6 f or the RTC

register s. The time and cal endar are s et or initiali zed by writing t he appropri ate register bytes . The contents of the

time and c alendar regi sters are in the BCD f ormat. Bi t 7 of Register 0 is the clock halt (CH) bit. W hen this bit is set

to 1, the oscillator is disabled. W hen cleared to 0, the oscillator is enabled. The clock can be halted whenever the

timekeeping functions are not required, which minimizes VBAT current (IBATDAT) when VCC is not applied.

The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but

must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries

result in undefined operation.

W hen reading or wr iting the t ime and date regis ters, secondar y (user) buffers are us ed to prevent error s when the

internal registers update. When reading the time and date registers, the user buffers are synchronized to the

internal regi s ters on any start or s to p a nd whe n t he re gi s ter point er r ol ls ov er to zer o. Th e c ou ntdown chai n is res et

whenever the seconds register is written. Write transfers occur on the acknowledge from the DS1338. Once the

LOCAL GROUND PLANE (LAYER 2)

CRYSTAL

GND

NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED

AREA (UPPER LEFT-HAND QUADRANT) OF THE PACKAGE

UNL ESS THERE IS A GR OUND PLAN E BETWEEN TH E SIGNAL

LINE AND THE PA CK AGE.

DS1338

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countdown chain is reset, to avoid rollover issues the remaining time and date registers must be written within

1 second. The 1Hz square-wave output, if enabled, transitions high 500ms after the seconds data transfer,

provided the oscillator is already running.

The DS1338 runs in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12-hour or 24-hour

mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit, with logic

high being PM. In the 24-hour mode, bit 5 is the 20-hour bit (20–23 hours). If the 12/24-hour mode select is

changed, the hours register must be re-initialized to the new format.

On an I2C START, the current time is transferred to a second set of registers. The time information is read from

these secondary registers, while the clock continues to run. This eliminates the need to re-read the registers in

case of an update of the main registers during a read.

Table 3. RTC and RAM Address Map

ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE

00H

10 Seconds

Seconds

00–59

01H

10 Minutes

Minutes

00–59

02H 0 12/24 AM

/PM

Hour Hour Hours

1–12

+AM/PM

00–23

20 Hour

03H

Day

1–7

04H

10 Date

Date

01–31

05H 0 0 0

Month

Month Month 01–12

06H

10 Year

Year

00–99

07H OUT 0 OSF SQWE 0 0 RS1 RS0 Control

08H–3FH RAM 56 x 8 00H–FFH

Note: Bits listed as “0” always read as a 0.

DS1338

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CONTROL REGISTER (07H)

The control register controls the operation of the SQW/OUT pin and provides oscillator status.

Bit #

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Name

OUT

OSF

SQWE

RS1

RS0

POR

Bit 7: Output Contr o l (OUT). Controls the output level of the SQW/OUT pin when the square-wave output is

disabled. If SQWE = 0, the logic level on the SQW/OUT pin is 1 if OUT = 1; it is 0 if OUT = 0.

Bit 5: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for

some time period and can be used to judge the validity of the clock and calendar data. This bit is edge triggered,

and is set to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a

STOP condition. The following are examples of conditions that may cause the OSF bit to be set:

1) The first time power is applied.

2) The voltage present on VCC and VBAT are insufficient to support oscillation.

3) The CH bit is set to 1, disabling the oscillator.

4) External influences on the crystal (i.e., noise, leakage, etc.).

This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF to

logic 1 leaves the value unchanged.

Bit 4: Square-Wave Enable (SQWE). When set to logic 1, this bit enables the oscillator output to operate with

either VCC or VBAT applied. The frequency of the square-wave output depends upon the value of the RS0 and RS1

bits.

Bits 1 and 0: Rate Select (RS1 and RS0). These bits control the frequency of the square-wave output wh e n the

square-wave output has been enabled. The table below lists the square-wave frequencies that can be selected

with the RS bits.

Square-Wave Output

OUT

RS1

RS0

SQW OUTPUT

SQWE

1Hz

4.096kHz

8.192kHz

32.768kHz

DS1338

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I2C SERIAL DATA BUS

The DS1338 supports the I2C protocol. A device that sends data onto the bus is defined as a transmitter and a

device receiving data is a receiver. The device that controls the message is called a master. The devices that are

controll ed b y the m as ter are r ef er red to as s l av es. T he bus m ust be contr ol l ed b y a master dev ic e, whic h gen er ates

the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1338

operates as a slave on the I2C bus. Within the bus specifications, a standard mode (100kHz maximum clock rate)

and a fast m ode (400k Hz maximum clock r ate) are defined. The D S1338 work s in both modes. C onnection s to the

bus are made through the open-drain I/O lines SDA and SCL.

The following bus protocol has been defined (Figure 5).

 Data transfer can be initiated only when the bus is not busy.

 During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data

line while the clock line is HIGH are interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data li ne, from HIGH to LOW, while the c lock i s HIGH, defines a

START condition.

Stop data transfer: A change in the s tate of the d ata l i ne, fr om LOW to HIGH, whil e the cl ock line i s HIGH, def i nes

the STOP condition.

Data valid: The stat e of the data line represents valid data when, after a START condition, the data line is stable

for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data

bytes trans fer red bet ween START an d STOP con diti ons is not l imited and i s deter mined b y the master device. The

information is transferred byte-wise and each receiver acknow ledges with a ninth bit.

Acknowledge: Each recei v ing devi ce, when addr essed, i s obl iged t o gen erate a n ack no wledge af ter the re cepti on

of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that

the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and

hold times must be taken into account. A master must signal an end of data to the slave by not generating an

ack nowledge bi t on the l ast b yte that has bee n cl ock ed out of the slav e. In thi s cas e, the s lave m ust l eave the d ata

line HIGH to enable the master to generate the STOP condition.

Figure 5. Data Transfer on I2C Serial Bus

DS1338

13 of 16

Depending upon the state of the R/W bit, two types of data transfer are possible:

1) Data transfer from a master transmitter to a slave receiver. The master transmits the first byte (the slave

address) . Next foll ows a number of data bytes. The sl ave returns an ac knowledge bit after eac h received b yte.

Data is transferred with the most significant bit (MSB) first.

2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave

address). The slave then returns an acknowledge bit, which is followed by the slave transmitting a number of

data bytes . The master ret urns an ack nowledge bit after all received bytes ot her than the las t byte. At the end

of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock

pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated

START con di ti on. Sinc e a repeated START co ndi ti on i s als o the begi nni n g of the next serial tr ansfer, the bus i s

not released. Data is transferred with the most significant bit (MSB) first.

The DS1338 can operate in the following two modes:

1) Slave receiver mode (write mode): Serial data and clock are received through SDA and SCL. An

ack nowledge bi t is tr ansm itted af ter e ach b yte is recei ved. ST ART and ST OP condi tions ar e reco gni zed as t he

beginning and end of a serial transfer. Hardware performs address recognition after reception of the slave

address and direction bit (Figure 6). The slave address byte is the first byte received after the master

generates the START condition. The slave address byte contains the 7-bit DS1338 address—1101000—

foll owed by the direc tion bi t (R/W) , which, f or a write, is 0. Af ter rec eiving and dec odi ng the sl ave addres s b yte,

the slave outputs an acknowledge on the SDA line. After the DS1338 acknowledges the slave address and

write bit, th e master transmi ts a register addr ess to the DS1338. This sets the regist er pointer on the DS1338 ,

with DS1338 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the

DS1338 acknowledgi ng e a c h b yte receiv ed. T h e regi s ter point er i nc rem ents af ter eac h dat a byte is transferred.

The master generates a STOP condition to terminate the data write.

2) Slave transmitter mode (read mode): The first byte is received and handled as in the slave receiver mode.

However, i n this mode, the direction bi t indicates that the transfer di rection is rever sed. The DS1338 tra nsmits

serial data on SDA whil e the serial c lock is input on S CL. START and STOP conditi ons are recogni zed as the

beginning and end of a serial transfer (Figure 7). The slave address byte is the first byte received after the

master generates the START condition. The slave address byte contains the 7-bit DS1338 address—

1101000—followed by the direction bit (R/W), which, for a read, is 1. After receiving and decoding the slave

address byte, the slave outputs an acknowledge on the SDA line. The DS1338 then starts transmitting data

using the regi ster address poi nted t o by the regi ster poi nter. If the regis ter pointer is not set bef ore the i nitiation

of a read m ode, the first addr es s t hat i s r ead i s the l as t one stored i n th e r egi s ter poi nter . The r egi st er poi nt er i s

incremented after each byte is transferred. The DS1338 must receive a “not acknowledge” to end a read.

DS1338

14 of 16

Figure 6. Data Wr ite—Slave Receiver Mode

Figure 7. Data Rea d (From Current P oi nter Location)—Slave Transmitter Mode

Figure 8. Data Read (Write Pointer, Then Read—Slave Receive and Transmit

...

XXXXXXXX

1101000

XXXXXXXX

S - START

A - ACKNOWLEDGE (ACK)

P - STOP

- NOT ACKNOWLEDGE (NACK)

<R/W>

DATA TRAN SF ER RED

(X+1 BYTES + ACKNOWLEDG E)

NOTE: LAST DATA BYTE IS FOLLOW ED BY A NACK

MASTER TO SLAVE

SLAVE TO MASTER

...

XXXXXXXX

S - START

SR - REPEATED START

A - ACKNOWLEDGE (ACK)

P - STOP

A - NOT ACKNOWLEDGE (NACK)

DATA TRANSFERRED

(X+1 BYTES + ACKNOWLEDGE)

NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK

XXXXXXXX

1101000

<R/W>

1101000

<R/W>

MASTER TO SLAVE

SLAVE TO MASTER

...

XXXXXXXX

S - START

A - ACKNOWLEDGE (ACK)

P - STOP

<R/W>

DATA TRANSFERRED

(X+1 BYTES + ACKNOWLEDGE)

1101000

MASTER TO SLAVE

SLAVE TO MASTER

DS1338

15 of 16

HANDLING, PCB LAYOUT, AND AS SEM BLY

The DS1338C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but

precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning should be avoided to

prevent damage to the crystal. Exposure to reflow is limited to 2 times maximum.

Avoid running signal traces under the package, unless a ground plane is placed between the package and the

signal line. All N.C. (no connect) pins must be connected to ground.

The RoHS a nd lea d-fr ee/RoHS pac k ages ma y be refl owed us ing a ref lo w profi le that compl ies with JEDEC J -STD-

020.

Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package

label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-

sensitive device (MSD) classifications.

PIN CONFIGURATIONS

CHIP INFORMATION

TRANSISTOR COUNT: 12,231

PROCESS: CMOS

THERMAL INFORMATION

PART THETA-JA

(°C/W) THETA-JC

(°C/W)

8 SO

132

8 μSOP

206.3

16 SO

PACKAGE INFORMATION

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.

Note that a “+” , “#”, or “-“ i n the package c ode indic ates RoHS status onl y. Pack age drawings ma y show a di fferent

suffix character, but the drawing pertains to the package regardless of RoHS status.

PACKAGE TYPE

PACKAGE CODE

OUTLINE NO.

LAND PATTER N NO.

8 SO

S8+4

21-0041

90-0096

8 µMAX

U8+1

21-0036

90-0092

16 SO

W16#H2

21-0042

90-0107

SO, μSOP

SQW/OUT

BAT

GND

SCL

SDA

TOP VIEW

SCL

SDA

GND

BAT

SQW/OUT

Vcc

N.C.

DS1338C

SO (300 mils)

TOP VIEW

DS1338

16 of 16

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim

reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 160 Rio Robles, San Jose, CA 95134 408-601-1000

REVISION HISTORY

REVISION

DATE

DESCRIPTION

PAGES

CHANGED

100108

Modified the Features bullet to indicate that battery-backed RAM has unlimited

writes.

Removed leaded part numbers from the Ordering Information table. 1

Removed the pullup resistor voltage spec from the Recommended DC

Operating Conditions table and added it to the pin descriptions.

2, 7

Updated the block diagram (Figure 3) to show that SQW is open drain.

Added the initial POR state for time and date registers in the Power Control

section.

Added text to explain the use of the oscillator bit to control battery current in the

Clock and Calendar section.

9/11

Updated the Absolut e Max i mum Rat ings , Recommended DC Operating

Conditions, DC Electrical Characteristics, Power Control, Oscillator Circuit,

Table 3, Handling, PBB Layout, and Assembly, Thermal Information, and

Package Infor mation.

2, 8, 10, 15

3/12 Corrected the CH bit POR condition from 1 to 0 in the Power Control section 8

4/15 Revised Benefits and Features section 1