S1C60N08 - Epson Company - Datasheet.Directory

MF1282-02

Technical Manual

CMOS 4-BIT SINGLE CHIP MICROCOMPUTER

S1C60N08 Technical Hardware/S1C60R08 Technical Hardware

S1C60N08/60R08

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko

Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any

liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or

circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such

as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there

is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright

infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic

products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from

the Ministry of International Trade and Industry or other approval from another government agency.

S1C60N08/S1C60R08 Technical Manual

This publication consists of two manuals that explain the hardware specifica-

tions of the S1C60N08 and S1C60R08 (ROM emulator model for S1C60N08)

CMOS 4-bit single chip microcomputers.

I. S1C60N08 Technical Hardware

This manual describes the functions, circuit configuration and control method of

the S1C60N08.

II. S1C60R08 Technical Hardware

This manual describes the hardware specifications of the S1C60R08 except

where the functions are the same as the S1C60N08.

The information of the product number change

Configuration of product number

Devices

Comparison table between new and previous number

S1C60 Family processors

Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,

2001 please use the new product number. For further information, please contact Epson sales

representative.

S1 C60N01 F0A01 Packing specification

Specification

Package (D: die form; F: QFP)

Model number

Model name (C: microcomputer, digital products)

Product classification (S1: semiconductor)

Development tools

S5U1 C60R08 D1 1Packing specification

Version (1: Version 1 ∗2)

Tool type (D1: Development Tool ∗1)

Corresponding model number (60R08: for S1C60R08)

Tool classification (C: microcomputer use)

Product classification

(S5U1: development tool for semiconductor products)

∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)

∗2: Actual versions are not written in the manuals.

Previous No.

E0C6001

E0C6002

E0C6003

E0C6004

E0C6005

E0C6006

E0C6007

E0C6008

E0C6009

E0C6011

E0C6013

E0C6014

E0C60R08

New No.

S1C60N01

S1C60N02

S1C60N03

S1C60N04

S1C60N05

S1C60N06

S1C60N07

S1C60N08

S1C60N09

S1C60N11

S1C60N13

S1C60140

S1C60R08

S1C62 Family processors

Previous No.

E0C621A

E0C6215

E0C621C

E0C6S27

E0C6S37

E0C623A

E0C623E

E0C6S32

E0C6233

E0C6235

E0C623B

E0C6244

E0C624A

E0C6S46

New No.

S1C621A0

S1C62150

S1C621C0

S1C6S2N7

S1C6S3N7

S1C6N3A0

S1C6N3E0

S1C6S3N2

S1C62N33

S1C62N35

S1C6N3B0

S1C62440

S1C624A0

S1C6S460

Previous No.

E0C6247

E0C6248

E0C6S48

E0C624C

E0C6251

E0C6256

E0C6292

E0C6262

E0C6266

E0C6274

E0C6281

E0C6282

E0C62M2

E0C62T3

New No.

S1C62470

S1C62480

S1C6S480

S1C624C0

S1C62N51

S1C62560

S1C62920

S1C62N62

S1C62660

S1C62740

S1C62N81

S1C62N82

S1C62M20

S1C62T30

Comparison table between new and previous number of development tools

Development tools for the S1C60/62 Family

Previous No.

ASM62

DEV6001

DEV6002

DEV6003

DEV6004

DEV6005

DEV6006

DEV6007

DEV6008

DEV6009

DEV6011

DEV60R08

DEV621A

DEV621C

DEV623B

DEV6244

DEV624A

DEV624C

DEV6248

DEV6247

New No.

S5U1C62000A

S5U1C60N01D

S5U1C60N02D

S5U1C60N03D

S5U1C60N04D

S5U1C60N05D

S5U1C60N06D

S5U1C60N07D

S5U1C60N08D

S5U1C60N09D

S5U1C60N11D

S5U1C60R08D

S5U1C621A0D

S5U1C621C0D

S5U1C623B0D

S5U1C62440D

S5U1C624A0D

S5U1C624C0D

S5U1C62480D

S5U1C62470D

Previous No.

DEV6262

DEV6266

DEV6274

DEV6292

DEV62M2

DEV6233

DEV6235

DEV6251

DEV6256

DEV6281

DEV6282

DEV6S27

DEV6S32

DEV6S37

EVA6008

EVA6011

EVA621AR

EVA621C

EVA6237

EVA623A

New No.

S5U1C62620D

S5U1C62660D

S5U1C62740D

S5U1C62920D

S5U1C62M20D

S5U1C62N33D

S5U1C62N35D

S5U1C62N51D

S5U1C62560D

S5U1C62N81D

S5U1C62N82D

S5U1C6S2N7D

S5U1C6S3N2D

S5U1C6S3N7D

S5U1C60N08E

S5U1C60N11E

S5U1C621A0E2

S5U1C621C0E

S5U1C62N37E

S5U1C623A0E

Previous No.

EVA623B

EVA623E

EVA6247

EVA6248

EVA6251R

EVA6256

EVA6262

EVA6266

EVA6274

EVA6281

EVA6282

EVA62M1

EVA62T3

EVA6S27

EVA6S32R

ICE62R

KIT6003

KIT6004

KIT6007

New No.

S5U1C623B0E

S5U1C623E0E

S5U1C62470E

S5U1C62480E

S5U1C62N51E1

S5U1C62N56E

S5U1C62620E

S5U1C62660E

S5U1C62740E

S5U1C62N81E

S5U1C62N82E

S5U1C62M10E

S5U1C62T30E

S5U1C6S2N7E

S5U1C6S3N2E2

S5U1C62000H

S5U1C60N03K

S5U1C60N04K

S5U1C60N07K

I. S1C60N08 Technical Har d ware

S1C60N08 TECHNICAL HARDWARE EPSON I-i

CONTENTS

CHAPTER 1OVERVIEW _______________________________________________I-1

1.1 Configuration .............................................................................................. I-1

1.2 Features....................................................................................................... I-1

1.3 Blo ck Diagram ............................................................................................ I-2

1.4 Pin Layout Diagram ................................................................................... I-3

1.5 Pin Description ........................................................................................... I-4

1.6 S1C60N08 Option List................................................................................ I-4

CHAPTER 2POWER SUPPLY AND INITIAL RESET ____________________________I-7

2.1 Power Supply .............................................................................................. I-7

2.2 Initial Reset ................................................................................................. I-9

2.2.1 Power-on re set circuit ...............................................................................I-9

2.2.2 RESET terminal.........................................................................................I-9

2.2.3 Simultaneous high input to input ports (K00–K03) .................................I-9

2.2.4 Watc hdog timer .........................................................................................I-10

2.2.5 Internal register at initial reset ................................................................I-10

2.3 Test Terminal (TEST) ................................................................................. I-10

CHAPTER 3 CPU, ROM, RAM_______________________________________ I-11

3.1 CPU............................................................................................................ I-11

3.2 ROM ........................................................................................................... I-11

3.3 RAM ........................................................................................................... I-11

CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION_________________________ I-12

4.1 Memory Map .............................................................................................. I-12

4.2 Resetting Watchdog T imer ......................................................................... I-16

4.2.1 Configuration of watchdog timer.............................................................I-16

4.2.2 Mask option ..............................................................................................I-16

4.2.3 Control of watchdog timer .......................................................................I-16

4.2.4 Programming note....................................................................................I-16

4.3 Oscillation Circ uit and Prescaler.............................................................. I-17

4.3.1 Configuration of oscillation circuit and prescaler ..................................I-17

4.3.2 OSC1 oscillation circuit ........................................................................... I-17

4.3.3 OSC3 oscillation circuit ........................................................................... I-18

4.3.4 Control of oscillation circuit and prescaler ............................................ I-19

4.3.5 Programming notes .................................................................................. I-20

4.4 Input Ports (K00–K03, K10, K20–K23) .................................................... I-21

4.4.1 Configuration of input ports ....................................................................I-21

4.4.2 Input comparison registers and interrupt function .................................I-21

4.4.3 Mask option ..............................................................................................I-24

4.4.4 Control of input ports............................................................................... I-24

4.4.5 Programming notes .................................................................................. I-26

4.5 Output Ports (R00–R03, R10–R13) ........................................................... I-27

4.5.1 Configuration of output ports .................................................................. I-27

4.5.2 Mask option ..............................................................................................I-27

4.5.3 Control of output ports.............................................................................I-29

4.5.4 Programming note....................................................................................I-30

I-ii EPSON S1C60N08 TECHNICAL HARDWARE

CONTENTS

4.6 I/O Ports (P00–P03, P10–P13) ................................................................. I-31

4.6.1 Configuration of I/O ports ....................................................................... I-31

4.6.2 I/O contro l register and I/O mode ...........................................................I-31

4.6.3 Mask option ..............................................................................................I-31

4.6.4 Control of I/O ports..................................................................................I-32

4.6.5 Programming notes .................................................................................. I-33

4.7 Serial Interface (SIN, SOUT, SCLK) ......................................................... I-34

4.7.1 Configuration of serial interface ............................................................. I-34

4.7.2 Master mode and slave mode of serial interface.....................................I-34

4.7.3 Data input/output and interrupt function ................................................I-35

4.7.4 Mask option ..............................................................................................I-37

4.7.5 Control of serial interface........................................................................I-38

4.7.6 Programming notes .................................................................................. I-40

4.8 LCD Driver (COM0–COM3, SEG0–SEG47) ........................................... I-41

4.8.1 Configuration of LCD driver ................................................................... I-41

4.8.2 Cadence adjustment of oscillation frequency..........................................I-46

4.8.3 Mask option (segment allocation)............................................................ I-47

4.8.4 Control of LCD driver..............................................................................I-48

4.8.5 Programming notes .................................................................................. I-49

4.9 Clock Timer ................................................................................................ I-50

4.9.1 Configuration of clock timer ....................................................................I-50

4.9.2 Interrupt function ..................................................................................... I-50

4.9.3 Control of clock timer ..............................................................................I-51

4.9.4 Programming notes .................................................................................. I-52

4.10 Stopwatch Timer......................................................................................... I-53

4.10.1 Configuration of stopwatch timer .......................................................... I-53

4.10.2 Count-up pattern ....................................................................................I-53

4.10.3 Interrupt function ................................................................................... I-54

4.10 . 4 C o n t rol of st o p w a t ch t i m e r .................................................................... I - 5 5

4.10.5 Programming notes ................................................................................ I-56

4.11 Sound Generator........................................................................................ I-57

4.11.1 Configuration of sound generator .........................................................I-57

4.11.2 Frequency setting ................................................................................... I-58

4.11 . 3 D i g i t a l e nvelo p e ..................................................................................... I-58

4.11.4 Mask option ............................................................................................ I-59

4.11.5 Control of sound generator.................................................................... I-60

4.11.6 Programming note..................................................................................I-61

4.12 Event Counter ............................................................................................ I-62

4.12.1 Configuration of event counter ..............................................................I-62

4.12.2 Switching count mode ............................................................................ I-62

4.12.3 Mask option ............................................................................................ I-63

4.12.4 Control of event counter.........................................................................I-64

4.12.5 Programming notes ................................................................................ I-65

4.13 Analog Comparator ................................................................................... I-66

4.13.1 Configuration of analog comparator.....................................................I-66

4.13.2 Operation of analog comparator ...........................................................I-66

4.13.3 Control of analog comparator ............................................................... I-67

4.13.4 Programming notes ................................................................................ I-67

4.14 Battery Life Detection (BLD) Circuit ........................................................ I-68

4.14.1 Configuration of BLD circuit .................................................................I-68

4.14.2 Programmable selection of evaluation voltage ..................................... I-68

4.14.3 Detection timing of BLD circuit.............................................................I-69

4.14.4 Control of BLD circuit ...........................................................................I-70

4.14.5 Programming notes ................................................................................ I-71

S1C60N08 TECHNICAL HARDWARE EPSON I-iii

CONTENTS

4.15 Heavy Load Protection Function and Sub-BLD Circuit ........................... I-72

4.15.1 Heavy load protection function.............................................................. I-72

4.15.2 Operation of sub-BLD circuit ................................................................ I-73

4.15.3 Control of heavy load protection function and sub-BLD circuit .......... I-74

4.15.4 Programming notes ................................................................................ I-76

4.16 Interrupt and HALT ................................................................................... I-77

4.16 . 1 I n t e r r u p t f a c t o rs .....................................................................................I-79

4.16.2 Specific masks and factor flags for interrupt ........................................ I-79

4.16.3 Interrupt vectors ..................................................................................... I-80

4.16.4 Control of interrupt and HALT ..............................................................I-81

4.16.5 Programming notes ................................................................................ I-82

CHAPTER 5SUMMARY OF NOTES ______________________________________ I-83

5.1 Notes for Low Current Consumption......................................................... I-83

5.2 Summary of Notes by Function.................................................................. I-84

5.3 Precautions on Mounting .......................................................................... I-89

CHAPTER 6BASIC EXTERNAL WIRING DIAGRAM ___________________________ I-91

CHAPTER 7ELECTRICAL CHARACTERISTICS _______________________________ I-93

7.1 Absolute Maximum Rating......................................................................... I-93

7.2 Recommended Operating Conditions........................................................ I-93

7.3 DC Characteristics .................................................................................... I-94

7.4 Analog Circuit Characteristics and Current Consumption ...................... I-95

7.5 Oscillation Characteristics........................................................................ I-98

CHAPTER 8PACKAGE _______________________________________________ I-99

8.1 Plastic Package .......................................................................................... I-99

8.2 Ceramic Package for Test Samples........................................................... I-100

CHAPTER 9PAD LAYOUT ____________________________________________I-101

9.1 Diagram of Pad Layout............................................................................. I-101

9.2 Pad Coordinates........................................................................................ I-102

S1C60N08 TECHNICAL HARDWARE EPSON I-1

CHAPTER 1: OVERVIEW

CHAPTER 1OVERVIEW

The S1C60N08 Series is a single-chip microcomputer made up of the 4-bit core CPU S1C6200C, ROM

(4,096 words × 12 bits), RAM (832 words × 4 bits), LCD driver, serial interface, event counter with dial

input function, watchdog timer, and two types of time base counter. Because of its low-voltage operation

and low power consumption, this series is ideal for a wide range of applications, and is especially

suitable for battery-driven systems.

1.1 Configuration

The S1C60N08 Series is configured as follows, depending on supply voltage and oscillation circuits.

Table 1.1.1 Model configuration

Model

Supply voltage

Oscillation

circuit

Evaluation tool

S1C60N08

3.0 V

OSC1 only

(Single clock)

S1C60R08

S1C60A08

3.0 V

OSC1 and OSC3

(Twin clock)

S1C60L08

1.5 V

OSC1 only

(Single clock)

–

1.2 Features

Table 1.2.1 Features

Model

OSC1 oscillation circuit

OSC3 oscillation circuit

Instruction set

Instruction execution time

(differs depending on instruction)

(CLK: CPU operation frequency)

ROM capacity

RAM capacity

Input ports

Output ports

I/O ports

Serial interface

LCD driver

Time base counter

Watchdog timer

Event counter

Sound generator

Analog comparator

Battery low detection circuit

(BLD)

External interrupt

Internal interrupt

Supply voltage

Current

consumption

(Typ. value)

Form when shipped

S1C60N08/S1C60R08 S1C60L08 S1C60A08/S1C60R08

Crystal oscillation circuit 32.768 kHz (Typ.)/38.400 kHz (Typ.)

–CR or ceramic oscillation

circuit (selected by mask

option) 500 kHz (Typ.)

108 types

153 µsec, 214 µsec, 366 µsec (CLK = 32.768 kHz)

130 µsec, 182 µsec, 313 µsec (CLK = 38.400 kHz)

–10 µsec, 14 µsec, 24 µsec

(CLK = 500 kHz)

4,096 words × 12 bits

832 words × 4 bits

9 bits (pull-down resistor can be added by mask option)

8 bits (BZ, BZ, FOUT and SIOF outputs are available by mask option)

8 bits (pull-down resistor is added during input data read-out)

1 port (8-bit clock synchronous system)

48 segments × 4, 3, or 2 commons (selected by mask option)

V-3 V 1/4, 1/3 or 1/2 duty (voltage regulator and booster circuits built-in)

Two types (timer and stopwatch)

Built-in (can be disabled by mask option)

Two 8-bit inputs (dial input evaluation or independent)

Programmable in 8 sounds (8 frequencies)

Digital envelope built-in (can be disabled by mask option)

Inverted input × 1, non-inverted input × 1

Dual system (programmable in 8 values and a fixed value)

2.4 V, 2.2–2.55 V 1.2 V, 1.05–1.4 V 2.4 V, 2.2–2.55 V

Input interrupt: 3 systems

Time base counter interrupt: 2 systems

Serial interface interrupt: 1 system

3.0 V (1.8–3.5 V) 1.5 V (0.9–1.7 V) 3.0 V (2.2–3.5 V)

1.0 µA 1.0 µA 1.1 µA

2.2 µA 2.2 µA 3.0 µA

––50 µA

QFP5-100pin, QFP15-100pin or chip

CLK= 32.768 kHz

(when halted)

CLK= 32.768 kHz

(when executed)

CLK= 500 kHz

(when executed)

I-2 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 1: OVERVIEW

1.3 Block Diagram

OSC1

OSC2

OSC3

OSC4

AMPP

AMPM

COM0–3

SEG0–47

VDD

VL1

VL2

VL3

VS1

VSS

K00–K03, K10

K20–K23

TEST

RESET

P00–P03

P10–P13

R00–R03

R10–R13

SIN

SOUT

SCLK

Core CPU S1C6200C

ROM

4,096 words × 12 bits System Reset

Control

Interrupt

Generator

RAM

832 words × 4 bits

LCD Driver

48 SEG × 4 COM

Power

Controller

OSC

SVD

Event

Counter

Comparator

Sound

Generator

Serial I/F

Timer

Stopwatch

Input Port

I/O Port

Output Port

Fig. 1.3.1 Block diagram

S1C60N08 TECHNICAL HARDWARE EPSON I-3

CHAPTER 1: OVERVIEW

1.4 Pin Layout Diagram

QFP5-100pin

QFP15-100pin

Fig. 1.4.1 Pin layout

No.

Pin name

COM1

COM0

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

SEG41

SEG40

SEG39

SEG38

SEG37

SEG36

SEG35

SEG34

SEG33

SEG32

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

No.

Pin name

SEG24

TEST

SEG23

SEG22

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

No.

Pin name

SEG0

AMPP

AMPM

K23

K22

K21

K20

K10

K03

K02

K01

K00

SIN

SOUT

N.C.

SCLK

P03

P02

P01

P00

N.C.

P13

P12

P11

No.

100

Pin name

P10

R03

R02

R01

R00

R12

R11

R10

R13

VSS

RESET

OSC4

OSC3

VS1

OSC2

OSC1

VDD

VL3

VL2

VL1

N.C.

COM3

COM2

N.C. = No connection

No.

Pin name

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

SEG41

SEG40

SEG39

SEG38

SEG37

SEG36

SEG35

SEG34

SEG33

SEG32

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26

SEG25

SEG24

TEST

No.

Pin name

SEG23

SEG22

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

N.C.

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

No.

Pin name

AMPP

AMPM

K23

K22

K21

K20

K10

K03

K02

K01

K00

SIN

SOUT

N.C.

SCLK

N.C.

P03

P02

P01

P00

P13

P12

P11

P10

R03

No.

100

Pin name

R02

R01

R00

R12

R11

R10

R13

VSS

RESET

OSC4

OSC3

VS1

OSC2

OSC1

VDD

VL3

VL2

VL1

N.C.

COM3

COM2

COM1

COM0

N.C. = No connection

5180

INDEX

301

100

5175

INDEX

251

100

I-4 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 1: OVERVIEW

1.5 Pin Description

Table 1.5.1 Pin description

Pin name

VDD

VSS

VS1

VL1

VL2

VL3

CA, CB

OSC1

OSC2

OSC3

OSC4

K00–K03

K10

K20–K23

P00–P03

P10–P13

R00–R03

R10

R13

R11

R12

SIN

SOUT

SCLK

AMPP

AMPM

SEG0–47

COM0–3

RESET

TEST

Pin No. Function

Power supply pin (+)

Power supply pin (-)

Oscillation and internal logic system voltage output pin

LCD drive voltage output pin (approx. -1.05 V or 1/2·VL2)

LCD drive voltage output pin (2·VL1 or approx. -2.10 V)

LCD drive voltage output pin (3·VL1 or 3/2·VL2)

Boost capacitor connecting pin

Crystal oscillation input pin

Crystal oscillation output pin

CR or ceramic oscillation input pin * (N.C. for S1C60N08 and S1C60L08)

CR or ceramic oscillation output pin * (N.C. for S1C60N08 and S1C60L08)

Input port pin

I/O port pin

Output port pin

Output port pin or BZ output pin *

Output port pin or SIOF output pin *

Output port pin or FOUT output pin *

Serial interface data input pin

Serial interface data output pin

Serial interface clock input/output pin

Analog comparator non-inverted input pin

Analog comparator inverted input pin

LCD segment output pin

or DC output pin *

LCD common output pin (1/2, 1/3 or 1/4 duty are selectable *)

Initial reset input pin

Input pin for test

QFP5-100

96, 97

62–59

57–54

70–67

76–73

80–77

51–28, 26–3

2, 1, 100, 99

QFP15-100

94, 95

61–58

56–53

70–67

74–71

78–75

50–39,

37–26, 24–1

100–97

I/O

(I)

–

I/O

∗ Can be selected by mask option

1.6 S1C60N08 Option List

Multiple specifications are available in each option item as indicated in the Option List. Select the specifi-

cations that meet the target system. Be sure to record the specifications for unused ports too, according to

the instructions provided.

1. DEVICE TYPE

• DEVICE TYPE ........................................... ■■ 1. S1C60N08 (Normal Type)

■■ 2. S1C60L08 (Low Power Type)

■■ 3. S1C60A08 (Twin Clock Type)

• CLOCK TYPE (for Evaluation board)... ■■ 1. 32 kHz ■■ 2. 38 kHz

. OSC3 SYSTEM CLOCK (only for S1C60A08)

■■ 1. CR ■■ 2. Ceramic

S1C60N08 TECHNICAL HARDWARE EPSON I-5

CHAPTER 1: OVERVIEW

3. MULTIPLE KEY ENTRY RESET

• COMBINATION .................................. ■■ 1. Not Use

■■ 2. Use K00, K01

■■ 3. Use K00, K01, K02

■■ 4. Use K00, K01, K02, K03

• TIME AUTHORIZE............................. ■■ 1. Use ■■ 2. Not Use

. WA TCHDOG TIMER ■■ 1. Use ■■ 2. Not Use

5. INPUT INTERRUPT NOISE REJECTOR

• K00–K03 ................................................ ■■ 1. Use ■■ 2. Not Use

• K10 ......................................................... ■■ 1. Use ■■ 2. Not Use

• K20–K23 ................................................ ■■ 1. Use ■■ 2. Not Use

6. INPUT PORT PULL DOWN RESISTOR

• K00 ......................................................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K01 ......................................................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K02 ......................................................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K03 ......................................................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K10 ......................................................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K20 ......................................................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K21 ......................................................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K22 ......................................................... ■■ 1. With Resistor ■■ 2. Gate Direct

• K23 ......................................................... ■■ 1. With Resistor ■■ 2. Gate Direct

. OUTPUT PORT SPECIFICATION (R00–R03)

• R00.......................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• R01.......................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• R02.......................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• R03.......................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

8. R10 SPECIFICATION

• OUTPUT SPECIFICATION ............... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• OUTPUT TYPE .................................... ■■ 1. DC Output ■■ 2. Buzzer Output

9. R11 SPECIFICATION

• OUTPUT SPECIFICATION ............... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• OUTPUT TYPE .................................... ■■ 1. DC Output ■■ 2. SIO Flag

10.R12 SPECIFICATION

• OUTPUT SPECIFICATION ............... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• OUTPUT TYPE .................................... ■■ 1. DC Output

■■ 2. FOUT 32768 or 38400 [Hz]

■■ 3. FOUT 16384 or 19200 [Hz]

■■ 4. FOUT 8192 or 9600 [Hz]

■■ 5. FOUT 4096 or 4800 [Hz]

■■ 6. FOUT 2048 or 2400 [Hz]

■■ 7. FOUT 1024 or 1200 [Hz]

■■ 8. FOUT 512 or 600 [Hz]

■■ 9. FOUT 256 or 300 [Hz]

I-6 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 1: OVERVIEW

11.R13 SPECIFICATION

• OUTPUT SPECIFICATION ............... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• OUTPUT TYPE .................................... ■■ 1. DC Output

■■ 2. Buzzer Inverted Output (R13 Control)

■■ 3. Buzzer Inverted Output (R10 Control)

.I/O PORT SPECIFICATION

• P00 .......................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• P01 .......................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• P02 .......................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• P03 .......................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• P10 .......................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• P11 .......................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• P12 .......................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• P13 .......................................................... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

.SIN PULL DOWN RESISTOR ■■ 1. With Resistor ■■ 2. Gate Direct

.SOUT SPECIFICATION ■■ 1. Complementary ■■ 2. Pch-OpenDrain

.SCLK SPECIFICATION

• PULL DOWN RESISTOR ................... ■■ 1. With Resistor ■■ 2. Gate Direct

• OUTPUT SPECIFICATION ............... ■■ 1. Complementary ■■ 2. Pch-OpenDrain

• LOGIC ................................................... ■■ 1. Positive ■■ 2. Negative

.SIO DATA PERMUTATION ■■ 1. MSB First ■■ 2. LSB First

.EVENT COUNTER NOISE REJECTOR

■■ 1. 2048 or 2400 [Hz] ■■ 2. 256 or 300 [Hz]

.LCD SPECIFICATION

• BIAS SELECTION

S1C60N08.............................................. ■■ 1. 1/3 Bias, Regulator Used, LCD 3 V

■■ 2. 1/3 Bias, Regulator Not Used, LCD 3 V

■■ 3. 1/2 Bias, Regulator Not Used, LCD 3 V

■■ 4. 1/3 Bias, Regulator Not Used, LCD 4.5 V

S1C60L08 .............................................. ■■ 1. 1/3 Bias, Regulator Used, LCD 3 V

■■ 2. 1/2 Bias, Regulator Not Used, LCD 3 V

■■ 3. 1/3 Bias, Regulator Not Used, LCD 4.5 V

S1C60A08 .............................................. ■■ 1. 1/3 Bias, Regulator Used, LCD 3 V

■■ 2. 1/3 Bias, Regulator Not Used, LCD 3 V

■■ 3. 1/2 Bias, Regulator Not Used, LCD 3 V

■■ 4. 1/3 Bias, Regulator Not Used, LCD 4.5 V

• DUTY SELECTION ............................. ■■ 1. 1/4 Duty

■■ 2. 1/3 Duty

■■ 3. 1/2 Duty

.SEGMENT MEMORY ADDRESS ■■ 1. 0 Page (040–06F)

■■ 2. 2 Page (240–26F)

S1C60N08 TECHNICAL HARDWARE EPSON I-7

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

CHAPTER 2POWER SUPPLY AND INITIAL RESET

2.1 Power Supply

With a single external power supply (∗1) supplied to VDD through VSS, the S1C60N08 Series generates the

necessary internal voltage with the regulated voltage circuit (<VS1> for oscillators, <VL1 or VL2> for LCD)

and the voltage booster/reducer circuit (<VL2 and VL3, or VL1 and VL3> for LCD).

∗1 Supply voltage: S1C60N08/60A08 .. 3 V, S1C60L08 .. 1.5 V

Figure 2.1.1 shows the power supply configuration of the S1C60N08.

Figure 2.1.2 shows the power supply configuration of the S1C60A08 and S1C60L08.

The voltage <VS1> for the internal circuit that is generated by the internal system voltage regulator is

-1.2 V (VDD ground).

The S1C60N08 generates <VL2> with the LCD system voltage regulator and <VL1, VL3> with the voltage

booster/reducer. The S1C60A08 and the S1C60L08 generate <VL1> with the voltage regulator and <VL2,

VL3> with the voltage booster/reducer.

Notes: •External loads cannot be driven by the output voltage of the voltage regulator and voltage

booster/reducer.

•See Chapter 7, "Electrical Characteristics", for voltage values.

Internal system

voltage regurator

LCD system

voltage regurator

LCD system

voltage booster/reducer

Oscillation

circuit

Internal

circuit

LCD

driver

External

power

supply

OSC1, 2

COM0–3

SEG0–47

Fig. 2.1.1 Power supply configuration of S1C60N08

Internal system

voltage regurator

LCD system

voltage regurator

LCD system

voltage booster/reducer

Oscillation

circuit

Internal

circuit

LCD

driver

External

power

supply

OSC1, 2

OSC3, 4 (S1C60A08)

COM0–3

SEG0–47

Fig. 2.1.2 Power supply configuration of S1C60A08 and S1C60L08

I-8 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

The LCD system voltage regulator can be disabled by mask option. In this case, external elements can be

minimized because the external capacitors for the LCD system voltage regulator are not necessary.

However when the LCD system voltage regulator is not used, the display quality of the LCD panel, when

the supply voltage fluctuates (drops), is inferior to when the LCD system voltage regulator is used.

Figure 2.1.3 shows the external element configuration when the LCD system voltage regulator is not

used.

3.0 V

4.5 V LCD panel

1/4, 1/3 or 1/2 duty, 1/3 bias

Note: V

is shorded to V

inside the IC

3.0 V

3 V LCD panel

1/4, 1/3 or 1/2 duty, 1/3 bias

Note: V

is shorded to V

inside the IC

1.5 V

4.5 V LCD panel

1/4, 1/3 or 1/2 duty, 1/3 bias

3.0 V

3 V LCD panel

1/4, 1/3 or 1/2 duty, 1/2 bias

1.5 V

3 V LCD panel

1/4, 1/3 or 1/2 duty, 1/2 bias

Note: V

is shorded to V

inside the IC

Fig. 2.1.3 External elements when LCD system voltage regulator is not used

Note: If there is any segment pad that is set to be DC type, the internal LCD voltage regulator cannot be

chosen in all models. Or, if the inter nal LCD voltage regulator is chosen in any model, the segment

pad cannot be set to be DC type.

Table 2.1.1 LCD voltage regulator and DC output from SEG terminals

LCD system voltage regulator

Use

Not use

DC output from SEG terminals

Not available

Available

S1C60N08 TECHNICAL HARDWARE EPSON I-9

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

2.2 Initial Reset

To initialize the S1C60N08 Series circuits, initial reset must be executed. There are four ways of doing this.

(1) Initial reset by the power on reset circuit

(2) External initial reset by the RESET terminal

(3) External initial reset by simultaneous high input to terminals K00–K03

(4) Initial reset by the watchdog timer

Figure 2.2.1 shows the configuration of the initial reset circuit.

OSC1

oscillation circuit

Power-on

reset circuit

Time authorize

circuit

OSC1

VSS

Mask option

OSC2

K00

K01

K02

K03

VSS

Initial

reset

RESET

Watchdog

timer

Noise

rejector

Fig. 2.2.1 Configuration of initial reset circuit

2.2.1 Power-on reset circuit

The power-on reset circuit outputs the initial reset signal at power-on until the oscillation circuit starts

oscillating.

Note: The power-on reset circuit may not work proper ly due to unstable or lower voltage input. The

following two initial reset method are recommended to generate the initial reset signal.

2.2.2 RESET terminal

Initial reset can be executed externally by setting the reset terminal to the high level. This high level must

be maintained for at least 5 msec (when oscillating frequency is fOSC1 = 32 kHz), because the initial reset

circuit contains a noise rejector. When the reset terminal goes low the CPU begins to operate.

2.2.3 Simultaneous high input to input ports (K00–K03)

Another way of executing initial reset externally is to input a high signal simultaneously to the input

ports (K00–K03) selected with the mask option. The specified input port terminals must be kept high for

at least 5 msec (when oscillating frequency is fOSC1 = 32 kHz), because the initial reset circuit contains a

noise rejector. Table 2.2.3.1 shows the combinations of input ports (K00–K03) that can be selected with the

mask option.

Table 2.2.3.1 Input port combination

Selection

Combination

Not used

K00∗K01

K00∗K01∗K02

K00∗K01∗K02∗K03

When, for instance, mask option D (K00*K01*K02*K03) is selected, initial reset is executed when the

signals input to the four ports K00–K03 are all high at the same time.

I-10 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 2: POWER SUPPLY AND INITIAL RESET

Further, the time authorize circuit can be selected with the mask option. The time authorize circuit

performs initial reset, when the input time of the simultaneous high input is authorized and found to be

the same or more than the defined time (1 to 2 sec).

If you use this function, make sure that the specified ports do not go high at the same time during

ordinary operation.

2.2.4 W atchdog timer

If the CPU runs away for some reason, the watchdog timer will detect this situation and output an initial

reset signal. See Section 4.2, "Resetting Watchdog Timer", for details.

2.2.5 Internal register at initial reset

Initial reset initializes the CPU as shown in the table below.

Table 2.2.5.1 Initial values

∗ See Section 4.1, "Memory Map".

Name

Program counter step

Program counter page

New page pointer

Stack pointer

Index register X

Index register Y

General-purpose register A

General-purpose register B

Interrupt flag

Decimal flag

Zero flag

Carry flag

CPU Core

Symbol

PCS

PCP

NPP

Bit size

Initial value

00H

Undefined

Name

RAM

Display memory

Other peripheral circuits

Peripheral Circuits

Bit size

Initial value

Undefined

∗

2.3 Test Terminal (TEST)

This terminal is used when the IC load is being detected. During ordinary operation be certain to connect

this terminal to VSS.

S1C60N08 TECHNICAL HARDWARE EPSON I-11

CHAPTER 3: CPU, ROM, RAM

CHAPTER 3 CPU, ROM, RAM

3.1 CPU

The S1C60N08 Series employs the core CPU S1C6200C for the CPU, so that register configuration,

instructions and so forth are virtually identical to those in other family processors using the S1C6200/

6200A/6200B/6200C.

Refer to the "S1C6200/6200A Core CPU Manual" for details about the core CPU.

Note the following points with regard to the S1C60N08 Series:

(1) The SLEEP operation is not assumed, so the SLP instruction cannot be used.

(2) Because the ROM capacity is 4,096 words, bank bits are unnecessary and PCB and NBP are not used.

(3) RAM is set up to four pages, so only the two low-order bits are valid for the page portion (XP, YP) of

the index register that specifies addresses. (The two high-order bits are ignored.)

3.2 ROM

The built-in ROM, a mask ROM for loading the program, has a capacity of 4,096 steps, 12 bits each. The

program area is 16 pages (0–15), each of 256 steps (00H–FFH). After initial reset, the program start

address is page 1, step 00H. The interrupt vector is allocated to page 1, steps 01H–0FH.

Step 00H

Step 01H

Step 0FH

Step 10H

Step FFH

12 bits

Program start address

Interrupt vector area

Bank 0

Program area

Page 0

Page 1

Page 2

Page 3

Page 15

Fig. 3.2.1 ROM configuration

3.3 RAM

The RAM, a data memory for storing a variety of data, has a capacity of 832 words, 4-bit words. When

programming, keep the following points in mind:

(1) Part of the data memory is used as stack area when saving subroutine return addresses and registers,

so be careful not to overlap the data area and stack area.

(2) Subroutine calls and interrupts take up three words on the stack.

(3) Data memory 000H–00FH is the memory area pointed by the register pointer (RP).

I-12 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION

Peripheral circuits (timer, I/O, and so on) of the S1C60N08 Series are memory mapped. Thus, all the

peripheral circuits can be controlled by using memory operations to access the I/O memory. The follow-

ing sections describe how the peripheral circuits operate.

4.1 Memory Map

The data memory of the S1C60N08 Series has an address space of 865 words (913 words when display

memory is laid out in Page 2), of which 48 words are allocated to display memory and 33 words, to I/O

memory. Figure 4.1.1 shows the overall memory map for the S1C60N08 Series, and Tables 4.1.1(a)–(c), the

memory maps for the peripheral circuits (I/O space).

Address

Page Low

High 0 1 2 3 4 5 6 7 8 9 A B C D E F

M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF

RAM (256 words × 4 bits)

R/W

RAM (256 words × 4 bits)

R/W

Address

Page Low

High 0 1 2 3 4 5 6 7 8 9 A B C D E F

RAM (64 words × 4 bits)

R/W

I/O mamory (see Table 4.1.1)

Unused area

RAM (256 words × 4 bits)

R/W

Fig. 4.1.1 Memory map

Address

Page Low

High 0 1 2 3 4 5 6 7 8 9 A B C D E F

0 or 2 4

Display memory (48 words × 4 bits)

Page 0: R/W, Page 2: W only

Fig. 4.1.2 Display memory map

Notes: • The display memory area can be selected from between Page 0 (040H–06FH) and Page 2

(240H–26FH) by mask option.

When Page 0 (040H–06FH) is selected, the display memory is assigned in the RAM area. So

read/write operation is allowed.

When Page 2 (240H–26FH) is selected, the display memory is assigned as a wr ite-only memory.

• Memory is not mounted in unused area within the memory map and in memory area not indi-

cated in this chapter. For this reason, normal operation cannot be assured for programs that

have been prepared with access to these areas.

S1C60N08 TECHNICAL HARDWARE EPSON I-13

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(a) I/O memory map (2D0H, 2E0H–2ECH)

Address Comment

D3 D2

D1 D0 Name Init ∗110

2E3H

K03 K02 K01 K00

K03

K02

K01

K00

–

∗

–

∗

–

∗

–

∗

High

Low

Input port data (K00–K03)

2E1H

SWL3 SWL2 SWL1 SWL0

SWL3

SWL2

SWL1

SWL0

MSB

Stopwatch timer 1/100 sec data (BCD)

LSB

2E2H

SWH3 SWH2 SWH1 SWH0

SWH3

SWH2

SWH1

SWH0

MSB

Stopwatch timer 1/10 sec data (BCD)

LSB

2E0H

TM3 TM2 TM1 TM0

TM3

TM2

TM1

TM0

Clock timer data (2 Hz)

Clock timer data (4 Hz)

Clock timer data (8 Hz)

Clock timer data (16 Hz)

2E5H

EIK03 EIK02 EIK01 EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Enable

Mask

Interrupt mask register (K00–K03)

2E4H

KCP03 KCP02 KCP01 KCP00

R/W

KCP03

KCP02

KCP01

KCP00

Input comparison register (K00–K03)

2E6H

HLMOD BLD0 EISWIT1 EISWIT0

R/W R R/W

HLMOD

BLD0

EISWIT1

EISWIT0

Heavy load

Low

Enable

Normal

Mask

Heavy load protection mode register

Sub-BLD evaluation data

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

2E8H

CSDC ETI2 ETI8 ETI32

R/W

CSDC

ETI2

ETI8

ETI32

Static

Enable

Dynamic

Mask

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

2E7H

SCTRG EIK10 KCP10 K10

WRR/W

SCTRG

∗

EIK10

KCP10

K10

–

∗

Trigger

Enable

High

–

Mask

Low

Serial I/F clock trigger

Interrupt mask register (K10)

Input comparison register (K10)

Input port data (K10)

2D0H

000LOF

R R/W

∗

LOF

–

∗

–

∗

–

∗

–

Normal

–

All off

Unused

LCD all off control

2E9H

0 TI2 TI8 TI32

∗

TI2

∗

TI8

∗

TI32

∗

–

∗

–

Yes

–

Unused

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

2EAH

IK1 IK0 SWIT1 SWIT0

IK1

∗

IK0

∗

SWIT1

∗

SWIT0

∗

Yes

Interrupt factor flag (K10)

Interrupt factor flag (K00–K03)

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

2EBH

R03 R02 R01 R00

R/W

R03

R02

R01

R00

High

Low

Output port (R03)

Output port (R02)

Output port (R01)

Output port (R00)

2ECH

R13 R12 R11

SIOF R10

R/W

RR/WR/W

R13

R12

R11

SIOF

R10

High/On

High

Run

High/On

Low/Off

Low

Stop

Low/Off

Output port (R13)/BZ output control

Output port (R12)/FOUT output control

Output port (R11, LAMP)

Output port (SIOF)

Output port (R10)/BZ output control

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read ∗5 Undefined

I-14 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(b) I/O memory map (2EDH–2FAH)

Address Comment

D3 D2

D1 D0 Name Init ∗110

2EFH

WDRST WD2 WD1 WD0

WDRST

∗

WD2

WD1

WD0

Reset

Reset –

Watchdog timer reset

Timer data (watchdog timer) 1/4 Hz

Timer data (watchdog timer) 1/2 Hz

Timer data (watchdog timer) 1 Hz

2EEH

TMRST SWRUN SWRST IOC0

W R/W W R/W

TMRST

∗

SWRUN

SWRST

∗

IOC0

Reset

Run

Reset

Output

–

Stop

–

Input

Clock timer reset

Stopwatch timer Run/Stop

Stopwatch timer reset

I/O control register 0 (P00–P03)

2EDH

P03 P02 P01 P00

R/W

P03

P02

P01

P00

–

∗

–

∗

–

∗

–

∗

High

Low

I/O port data (P00–P03)

Output latch is reset at initial reset

2F0H

SD3 SD2 SD1 SD0

R/W

SD3

SD2

SD1

SD0

∗5 Undefined

∗

Serial I/F data register (low-order 4 bits)

2F1H

SD7 SD6 SD5 SD4

R/W

SD7

SD6

SD5

SD4

∗

Serial I/F data register (high-order 4 bits)

2F2H

SCS1 SCS0 SE2 EISIO

R/W

SCS1

SCS0

SE2

EISIO

0 Enable Mask

Serial I/F clock

mode selection

Serial I/F clock edge selection

Interrupt mask register (serial I/F)

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

CLK 1

CLK/2 2

CLK/4 3

Slave

[SCS1, 0]

Clock

2F3H

0 0 IK2 ISIO

∗

IK2

∗

ISIO

∗

–

∗

–

∗

–

Yes

–

Unused

Interrupt factor flag (K20–K23)

Interrupt factor flag (serial I/F)

2F4H

K23 K22 K21 K20

K23

K22

K21

K20

–

∗

–

∗

–

∗

–

∗

High

Low

Input port data (K20–K23)

2F8H

EV03 EV02 EV01 EV00

EV03

EV02

EV01

EV00

Event counter 0 (low-order 4 bits)

2F9H

EV07 EV06 EV05 EV04

EV07

EV06

EV05

EV04

Event counter 0 (high-order 4 bits)

2FAH

EV13 EV12 EV11 EV10

EV13

EV12

EV11

EV10

Event counter 1 (low-order 4 bits)

2F5H

EIK23 EIK22 EIK21 EIK20

R/W

EIK23

EIK22

EIK21

EIK20

Enable

Mask

Interrupt mask register (K20–K23)

2F6H

BZFQ2 BZFQ1 BZFQ0 ENVRST

R/W W

BZFQ2

BZFQ1

BZFQ0

ENVRST

∗

Reset Reset –

Buzzer

frequency

selection

Envelope reset

2F7H

ENVON ENVRT AMPDT AMPON

RR/WR/W

ENVON

ENVRT

AMPDT

AMPON

1.0 sec

+ > -

Off

0.5 sec

+ < -

Off

Envelope On/Off

Envelope cycle selection register

Analog comparator data

Analog comparator On/Off

OSC1

/8 1

OSC1

/10 2

OSC1

/12 3

OSC1

/14

[BZFQ2–0]

Frequency

OSC1

/16 5

OSC1

/20 6

OSC1

/24 7

OSC1

/28

[BZFQ2–0]

Frequency

S1C60N08 TECHNICAL HARDWARE EPSON I-15

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)

Table 4.1.1(c) I/O memory map (2FBH–2FFH)

Address Comment

D3 D2

D1 D0 Name Init ∗110

2FCH

EVSEL ENRUN EV1RST EV0RST

R/W W

EVSEL

EVRUN

EV1RST

∗

EV0RST

∗

Reset

Separate

Run

Reset

Phase

Stop

–

Event counter mode selection

Event counter Run/Stop

Event counter 1 reset

Event counter 0 reset

2FEH

PRSM CLKCHG OSCC IOC1

R/W

PRSM

CLKCHG

OSCC

IOC1

38 kHz

OSC3

Output

32 kHz

OSC1

Off

Input

OSC1 prescaler selection

CPU clock switch

OSC3 oscillation On/Off

I/O control register (P10–P13)

2FDH

P13 P12 P11 P10

R/W

P13

P12

P11

P10

–

∗

–

∗

–

∗

–

∗

High

Low

I/O port data (P10–P13)

Output latch is reset at initial reset

∗5 Undefined

2FFH

BLS

BLD1 BLC2 BLC1 BLC0

RR/W

BLS

BLD1

BLC2

BLC1

BLC0

∗

Low Off

Normal

BLD On/Off

BLD evaluation data

Evaluation voltage setting register

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

2FBH

EV17 EV16 EV15 EV14

EV17

EV16

EV15

EV14

Event counter 1 (high-order 4 bits)

2.20

1.05

2.25

1.10

2.30

1.15

2.35

1.20

2.40

1.25

2.45

1.30

2.50

1.35

2.55

1.40 (V)

(V)

[BLC2–0]

S1C60N08/60A08

S1C60L08

I-16 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer)

4.2 Resetting W atchdog Timer

4.2.1 Configuration of watchdog timer

The S1C60N08 Series incorporates a watchdog timer as the source oscillator for OSC1 (clock timer 2 Hz

signal). The watchdog timer must be reset cyclically by the software. If reset is not executed in at least 3

or 4 seconds, the initial reset signal is output automatically for the CPU.

Figure 4.2.1.1 is the block diagram of the watchdog timer.

Clock timer

TM0–TM3

2 Hz Watchdog timer

WD0–WD2 Initial reset signal

OSC1 demultiplier

(256 Hz)

Watchdog timer

reset signal

Fig. 4.2.1.1 Watchdog timer block diagram

The watchdog timer, configured of a three-bit binary counter (WD0–WD2), generates the initial reset

signal internally by overflow of the MSB.

Watchdog timer reset processing in the program's main routine enables detection of program overrun,

such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is

incorporated where periodic processing takes place, just as for the timer interrupt routine.

The watchdog timer operates in the halt mode. If the halt status continues for 3 or 4 seconds, the initial

reset signal restarts operation.

4.2.2 Mask option

You can select whether or not to use the watchdog timer with the mask option. When "Not use" is chosen,

there is no need to reset the watchdog timer.

4.2.3 Control of watchdog timer

Table 4.2.3.1 lists the watchdog timer's control bits and their addresses.

Table 4.2.3.1 Control bits of watchdog timer

Address Comment

D3 D2

D1 D0 Name Init ∗110

2EFH

WDRST WD2 WD1 WD0

WDRST

∗

WD2

WD1

WD0

Reset

Reset –

Watchdog timer reset

Timer data (watchdog timer) 1/4 Hz

Timer data (watchdog timer) 1/2 Hz

Timer data (watchdog timer) 1 Hz ∗5 Undefined∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

WDRST: Watchdog timer reset (2EFH•D3)

This is the bit for resetting the watchdog timer.

When "1" is written : Watchdog timer is reset

When "0" is written : No operation

Read-out : Always "0"

When "1" is written to WDRST, the watchdog timer is reset, and the operation restarts immediately after

this. When "0" is written to WDRST, no operation results.

This bit is dedicated for writing, and is always "0" for read-out.

4.2.4 Programming note

When the watchdog timer is being used, the software must reset it within 3-second cycles, and timer data

(WD0–WD2) cannot be used for timer applications.

S1C60N08 TECHNICAL HARDWARE EPSON I-17

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit and Prescaler)

4.3 Oscillation Circuit and Prescaler

4.3.1 Configuration of oscillation circuit and prescaler

The S1C60N08 and S1C60L08 have one oscillation circuit (OSC1), and the S1C60A08 has two oscillation

circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that supplies the operating clock the CPU

and peripheral circuits. OSC3 is either a CR or ceramic oscillation circuit. When processing with the

S1C60A08 requires high-speed operation, the CPU operating clock can be switched from OSC1 to OSC3.

Figure 4.3.1.1 is the block diagram of this oscillation system.

Oscillation circuit control signal

CPU clock selection signal

Prescaler selection signal

To CPU (and serial interface)

To peripheral circuits

Clock

switch

To peripheral circuits (256 Hz)

OSC3

oscillation

circuit

OSC1

oscillation

circuit Selector

Prescaler 2

Prescaler 1

Fig. 4.3.1.1 Oscillation system

As Figure 4.3.1.1 indicates, two prescalers (demultiplier stage) are connected to the oscillation circuit.

Prescaler 1 is for 32.768 kHz and prescaler 2 is for 38.4 kHz. These can be selected through the software to

suit the crystal oscillator. This selection invokes the basic signal (256 Hz) for running the clock timer,

stopwatch timer, and so forth.

Also for S1C60A08, selection of either OSC1 or OSC3 for the CPU's operating clock can be made through

the software.

4.3.2 OSC1 oscillation circuit

The S1C60N08 Series has a built-in crystal oscillation circuit (OSC1 oscillation circuit). As an external

element, the OSC1 oscillation circuit generates the operating clock for the CPU and peripheral circuits by

connecting the crystal oscillator (Typ. 32.768 kHz) and trimmer capacitor (5–25 pF).

Figure 4.3.2.1 is the block diagram of the OSC1 oscillation circuit.

VDD

OSC2

OSC1

X'tal

CGX To CPU and

peripheral circuits

S1C60N08 Series

RFX

CDX

RDX

Fig. 4.3.2.1 OSC1 oscillation circuit

As Figure 4.3.2.1 indicates, the crystal oscillation circuit can be configured simply by connecting the

crystal oscillator (X'tal) between terminals OSC1 and OSC2 to the trimmer capacitor (CGX) between

terminals OSC1 and VDD.

Also, the crystal oscillator can be connected to the 38.4 kHz oscillator in addition to the 32.768 kHz

oscillator.

I-18 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit and Prescaler)

4.3.3 OSC3 oscillation circuit

In the S1C60N08 Series, the S1C60A08 has twin clock specification. The mask option enables selection of

either the CR or ceramic oscillation circuit (OSC3 oscillation circuit) as the CPU's subclock source.

Because the oscillation circuit itself is built-in, it provides the resistance as an external element when CR

oscillation is selected, but when ceramic oscillation is selected both the ceramic oscillator and two

capacitors (gate and drain capacitance) are required.

Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit.

OSC4

OSC3

Oscillation circuit control signal

Ceramic

To CPU

(and serial interface)

OSC4

OSC3

Oscillation circuit control signal

To CPU

(and serial interface)

S1C60A08

CR oscillation circuit

Ceramic oscillation circuit

Fig. 4.3.3.1 OSC3 oscillation circuit

As indicated in Figure 4.3.3.1, the CR oscillation circuit can be configured simply by connecting the

resistor (RCR) between terminals OSC3 and OSC4 when CR oscillation is selected. When 82 kΩ is used for

RCR, the oscillation frequency is about 410 kHz. When ceramic oscillation is selected, the ceramic oscilla-

tion circuit can be configured by connecting the ceramic oscillator (Typ. 500 kHz) between terminals

OSC3 and OSC4 to the two capacitors (CGC and CDC) located between terminals OSC3 and OSC4 and

VDD. For both CGC and CDC, connect capacitors that are about 100 pF. To lower current consumption of

the OSC3 oscillation circuit, oscillation can be stopped through the software.

For the S1C60N08 and S1C60L08 (single clock specification), do not connect anything to terminals OSC3

and OSC4.

S1C60N08 TECHNICAL HARDWARE EPSON I-19

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit and Prescaler)

4.3.4 Control of oscillation circuit and prescaler

Table 4.3.4.1 lists the control bits and their addresses for the oscillation circuit.

Table 4.3.4.1 Control bits of oscillation circuit and prescaler

Address Comment

D3 D2

D1 D0 Name Init ∗110

2FEH

PRSM CLKCHG OSCC IOC1

R/W

PRSM

CLKCHG

OSCC

IOC1

38 kHz

OSC3

Output

32 kHz

OSC1

Off

Input

OSC1 prescaler selection

CPU clock switch

OSC3 oscillation On/Off

I/O control register (P10–P13) ∗5 Undefined∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

OSCC: OSC3 oscillation control (2FEH•D1)

Controls oscillation ON/OFF for the OSC3 oscillation circuit. (S1C60A08 only.)

When "1" is written : The OSC3 oscillation ON

When "0" is written : The OSC3 oscillation OFF

Read-out : Valid

When it is necessary to operate the CPU of the S1C60A08 at high speed, set OSCC to "1". At other times,

set it to "0" to reduce current consumption.

For S1C60N08 and S1C60L08, keep OSCC set to "0".

At initial reset, OSCC is set to "0".

CLKCHG: CPU clock switch (2FEH•D2)

The CPU's operation clock is selected with this register. (S1C60A08 only.)

When "1" is written : OSC3 clock is selected

When "0" is written : OSC1 clock is selected

Read-out : Valid

When the S1C60A08's CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0". This

value.

At initial reset, CLKCHG is set to "0".

PRSM: OSC1 prescaler selection (2FEH•D3)

Selects the prescaler for the crystal oscillator of the OSC1 oscillation circuit.

When "1" is written : 38.4 kHz

When "0" is written : 32.768 kHz

Read-out : Valid

Operation of the clock timer and stopwatch timer can be mode accurate by selecting this register. When

the set value for this register does not suit the crystal oscillator used, the operation cycles of the previ-

ously mentioned peripheral circuitry is multiplied as shown below.

fOSC1 = 32.768 kHz and PRSM = "1": T' ≅ 1.172T

fOSC1 = 38.4 kHz and PRSM = "0": T' ≅ 0.853T

At initial reset, PRSM is set to "0".

I-20 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit and Prescaler)

4.3.5 Programming notes

(1) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabi-

lizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a

minimum of 5 msec have elapsed since the OSC3 oscillation went ON.

Further, the oscillation stabilization time varies depending on the external oscillator characteristics

and conditions of use, so allow ample margin when setting the wait time.

(2) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3

oscillation OFF. An error in the CPU operation can result if this processing is performed at the same

time by the one instruction.

(3) To operate the clock timer and stopwatch timer accurately, select the prescaler of the OSC1 to match

the crystal oscillator used.

S1C60N08 TECHNICAL HARDWARE EPSON I-21

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

4.4 Input Ports (K00–K03, K10, K20–K23)

4.4.1 Configuration of input ports

The S1C60N08 Series has nine bits (4 bits × 2 + 1 bit) of general-purpose input ports. Each of the input

port terminals (K00–K03, K10, K20–K23) provides internal pull-down resistor. Pull-down resistor can be

selected for each bit with the mask option.

Figure 4.4.1.1 shows the configuration of input port.

Interrupt

request

VDD

VSS

Data bus

Address

Mask

option

Fig. 4.4.1.1 Configuration of input port

Selection of "With pull-down resistor" with the mask option suits input from the push switch, key matrix,

and so forth. When "Gate direct" is selected, the port can be used for slide switch input and interfacing

with other LSIs.

Further, The input port terminal K02 and K03 are used as the input terminals for the event counter. (See

Section 4.12, "Event Counter", for details.)

4.4.2 Input comparison registers and interrupt function

All nine bits of the input ports (K00–K03, K10, K20–K23) provide the interrupt function for the five bits,

K00–K03 and K10. The conditions for issuing an interrupt can be set by the software for the five bits, K00–

K03 and K10. Further, whether to mask the interrupt function can be selected individually for all nine bits

by the software.

Figure 4.4.2.1 shows the configuration of K00–K03 and K10.

Figure 4.4.2.3 shows the configuration of K20–K23.

Data bus

Address

Input comparison

Address

Interrupt factor

flag (IK)

Noise

rejector

Address

Interrupt mask

Interrupt request

Mask option

(K00–K03, K10)

One for each terminal series

Fig. 4.4.2.1 Input interrupt circuit configuration (K00–K03, K10)

I-22 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

The input interrupt timing for K00–K03 and K10 depends on the value set for the input comparison

registers (KCP00–KCP03 and KCP10). Interrupt can be selected to occur at the rising or falling edge of the

input.

The interrupt mask registers (EIK00–EIK03, EIK10) enables the interrupt mask to be selected individually

for K00–K03 and K10. However, whereas the interrupt function is enabled inside K00–K03, the interrupt

occurs when the contents change from matching those of the input comparison register to non-matching

contents. Interrupt for K10 can be generated by setting the same conditions individually.

When the interrupt is generated, the interrupt factor flag (IK0 and IK1) is set to "1".

Figure 4.4.2.2 shows an example of an interrupt for K00–K03.

Interrupt mask register

EIK03

1EIK02

1EIK01

1EIK00

Input port

(1) (Initial value)

Interrupt generation

K03

1K02

0K01

1K00

Input comparison register

KCP03

1KCP02

0KCP01

1KCP00

With the above setting, the interrupt of K00–K03 is generated under the following condition:

(2)

K03

1K02

0K01

1K00

(3)

K03

0K02

0K01

1K00

(4)

K03

0K02

1K01

1K00

Because K00 interrupt is masked, interrupt will be

generated when no matching occurs between the

contents of the 3 bits K01–K03 and the 3 bits input

comparison register KCP01–KCP03.

Fig. 4.4.2.2 Example of interrupt of K00–K03

K00 is masked by the interrupt mask register (EIK00), so that an interrupt does not occur at (2). At (3),

K03 changes to "0"; the data of the terminal that is interrupt enabled no longer matches the data of the

input comparison register, so that interrupt occurs. As already explained, the condition for the interrupt

to occur is the change in the port data and contents of the input comparison register from matching to

nonmatching. Hence, in (4), when the nonmatching status changes to another nonmatching status, an

interrupt does not occur. Further, terminals that have been masked for interrupt do not affect the condi-

tions for interrupt generation.

S1C60N08 TECHNICAL HARDWARE EPSON I-23

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

Data bus

Address

Interrupt factor

flag (IK2)

Noise

rejector

Address

Interrupt mask

Interrupt request

Mask option

(K20–K23)

Fig. 4.4.2.3 Input interrupt circuit configuration (K20–K23)

There is no input comparison register for K20–K23, and interrupt is fixed to occur at th rising edge of

input. The interrupt mask can be selected for each of the four terminals with the interrupt mask register

(EIK20–EIK23). When all the enabled terminals are "0", interrupt occurs when one or more of the ports

changed to "1".

When an interrupt occurs, the interrupt factor flag (IK2) is set to "1".

Figure 4.4.2.4 shows an example of an interrupt being generated for K20–K23.

Interrupt mask register

EIK23

0EIK22

1EIK21

1EIK20

Input port

(1) (Initial value)

Interrupt generation

K23

0K22

0K21

0K20

With the above setting, the interrupt of K20–K23 is generated under the following condition:

(2)

K23

1K22

0K21

0K20

(3)

K23

1K22

0K21

1K20

(4)

K23

1K22

0K21

1K20

Because K23 interrupt is masked, interrupt will be

generated when one or more terminals among the 3 bits

K20–K22 become "1" from a state where all terminals

were "0".

Fig. 4.4.2.4 Example of interrupt of K20–K23

The mask register (EIK23) masks the interrupt of K23, so an interrupt does not occur at (2). At (3), K21

becomes "1", so that an interrupt occurs if the interrupt enabled terminals were all "0" and at least one

terminal then changes to "1".

At (4), the conditions for interrupt are not established, so an interrupt does not occur.

Futher, terminals that have been masked for interrupt do not affect the conditions for interrupt genera-

tion.

I-24 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

4.4.3 Mask option

The contents that can be selected with the input port mask option are as follows:

(1) Internal pull-down resistor can be selected for each of the nine bits of the input ports (K00–K03, K10,

K20–K23).

When you have selected "Gate direct", take care that the floating status does not occur for the input.

Select "With pull-down resistor" for input ports that are not being used.

(2) The input interrupt circuit contains a noise rejector for preventing interrupt occurring through noise.

The mask option enables selection of whether to use the noise rejector for each separate terminal

series.

When "Use" is selected, a maximum delay of 1 msec occurs from the time interrupt condition is

established until the interrupt factor flag (IK) is set to "1".

4.4.4 Control of input ports

Table 4.4.4.1 lists the input ports control bits and their addresses.

Table 4.4.4.1 Input port control bits

Address Comment

D3 D2

D1 D0 Name Init ∗110

2E3H

K03 K02 K01 K00

K03

K02

K01

K00

–

∗

–

∗

–

∗

–

∗

High

Low

Input port data (K00–K03)

2E5H

EIK03 EIK02 EIK01 EIK00

R/W

EIK03

EIK02

EIK01

EIK00

Enable

Mask

Interrupt mask register (K00–K03)

2E4H

KCP03 KCP02 KCP01 KCP00

R/W

KCP03

KCP02

KCP01

KCP00

Input comparison register (K00–K03)

2E7H

SCTRG EIK10 KCP10 K10

WRR/W

SCTRG

∗

EIK10

KCP10

K10

–

∗

Trigger

Enable

High

–

Mask

Low

Serial I/F clock trigger

Interrupt mask register (K10)

Input comparison register (K10)

Input port data (K10)

2EAH

IK1 IK0 SWIT1 SWIT0

IK1

∗

IK0

∗

SWIT1

∗

SWIT0

∗

Yes

Interrupt factor flag (K10)

Interrupt factor flag (K00–K03)

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read ∗5 Undefined

2F3H

0 0 IK2 ISIO

∗

IK2

∗

ISIO

∗

–

∗

–

∗

–

Yes

–

Unused

Interrupt factor flag (K20–K23)

Interrupt factor flag (serial I/F)

2F4H

K23 K22 K21 K20

K23

K22

K21

K20

–

∗

–

∗

–

∗

–

∗

High

Low

Input port data (K20–K23)

2F5H

EIK23 EIK22 EIK21 EIK20

R/W

EIK23

EIK22

EIK21

EIK20

Enable

Mask

Interrupt mask register (K20–K23)

S1C60N08 TECHNICAL HARDWARE EPSON I-25

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

K00–K03, K10, K20–K23: Input port data (2E3H, 2E7H•D0, 2F4H)

Input data of the input port terminals can be read out with these registers.

When "1" is read out : High level

When "0" is read out : Low level

Writing : Invalid

The read-out is "1" when the terminal voltage of the nine bits of the input ports (K00–K03, K10, K20–K23)

goes high (VDD), and "0" when the voltage goes low (VSS).

These bits are dedicated for read-out, so writing cannot be done.

KCP00–KCP03, KCP10: Input comparison registers (2E4H, 2E7H•D1)

Interrupt conditions for terminals K00–K03 and K10 can be set with these registers.

When "1" is written : Falling edge

When "0" is written : Rising edge

Read-out : Valid

Of the nine bits of the input ports, the interrupt conditions can be set for the rising or falling edge of

input for each of the five bits (K00–K03 and K10), through the input comparison registers (KCP00–KCP03

and KCP10).

At initial reset, these registers are set to "0".

EIK00–EIK03, EIK10, EIK20–EIK23: Interrupt mask registers (2E5H, 2E7H•D2, 2F5H)

Masking the interrupt of the input port terminals can be selected with these registers.

When "1" is written : Enable

When "0" is written : Mask

Read-out : Valid

With these registers, masking of the input port bits can be selected for each of the nine bits.

Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0").

At initial reset, these registers are all set to "0".

IK0, IK1, IK2: Interrupt factor flags (2EAH•D2 and D3, 2F3H•D1)

These flags indicate the occurrence of input interrupt.

When "1" is read out : Interrupt has occurred

When "0" is read out : Interrupt has not occurred

Writing : Invalid

The interrupt factor flags IK0, IK1 and IK2 are associated with K00–K03, K10 and K20–K23, respectively.

From the status of these flags, the software can decide whether an input interrupt has occurred.

These flags are reset when the software reads them. Read-out can be done only in the DI status (interrupt

flag = "0").

At initial reset, these flags are set to "0".

I-26 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

4.4.5 Programming notes

(1) When input ports are changed from high to low by pull-down resistance, the fall of the waveform is

delayed on account of the time constant of the pull-down resistance and input gate capacitance.

Hence, when fetching input ports, set an appropriate wait time.

Particular care needs to be taken of the key scan during key matrix configuration. Aim for a wait time

of about 1 msec.

(2) When "Use" is selected with the noise rejector mask option, a maximum delay of 1 msec occurs from

time the interrupt conditions are established until the interrupt factor flag (IK) is set to "1" (until the

interrupt is actually generated). Hence, pay attention to the timing when reading out (resetting) the

interrupt factor flag. For example, when performing a key scan with the key matrix, the key scan

changes the input status to set the interrupt factor flag, so it has to be read out to reset it. However, if

the interrupt factor flag is read out immediately after key scanning, the delay will cause the flag to be

set after read-out, so that it will not be reset.

(3) Input interrupt programing related precautions

Port K input

Factor flag set Not set

➁

Factor flag set

Input comparison

Mask register

Active status Active status

Rising edge interrupt

➀

Falling edge interrupt

When the content of the mask register is rewritten while the port K input is in the active status, the

input interrupt factor flags are set at ➀ and ➁, ➀ being the interrupt due to the falling edge and ➁

the interrupt due to the rising edge.

Fig. 4.4.5.1 Input interrupt timing

When using an input interrupt, if you rewrite the content of the mask register, when the value of the

input terminal which becomes the interrupt input is in the active status, the factor flag for input

interrupt may be set.

Therefore, when using the input interrupt, the active status of the input terminal implies

input terminal = low status, when the falling edge interrupt is effected and

input terminal = high status, when the rising edge interrupt is effected.

When an interrupt is triggered at the falling edge of an input terminal, a factor flag is set with the

timing of ➀ shown in Figure 4.4.5.1. However, when clearing the content of the mask register with the

input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again

set at the timing that has been set.

Consequently, when the input terminal is in the active status (low status), do not rewrite the mask

in this case. When clearing, then setting the mask register, set the mask register, when the input

terminal is not in the active status (high status).

When an interrupt is triggered at the rising edge of the input terminal, a factor flag will be set at the

timing of ➁ shown in Figure 4.4.5.1. In this case, when the mask registers cleared, then set, you should

set the mask register, when the input terminal is in the low status.

In addition, when the mask register = "1" and the content of the input comparison register is rewritten

in the input terminal active status, an input interrupt factor flag may be set. Thus, you should rewrite

the content of the input comparison register in the mask register = "0" status.

(4) Read out the interrupt factor flag (IK) only in the DI status (interrupt flag = "0"). Read-out during EI

status (interrupt flag = "1") will cause malfunction.

(5) Write the interrupt mask register (EIK) only in the DI status (interrupt flag = "0"). Writing during EI

status (interrupt flag = "1") will cause malfunction.

S1C60N08 TECHNICAL HARDWARE EPSON I-27

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

4.5 Output Ports (R00–R03, R10–R13)

4.5.1 Configuration of output ports

The S1C60N08 Series has eight bits (4 bits × 2) of general output ports.

Output specifications of the output ports can be selected individually with the mask option. Two kinds of

output specifications are available: complementary output and Pch open drain output.

Further, the mask option enables the output ports R10–R13 to be used as special output ports.

Figure 4.5.1.1 shows the configuration of the output ports.

Data bus

Address

VDD

VSS

Rxx

Complementary

Pch open drain

Mask option

Fig. 4.5.1.1 Configuration of output ports

4.5.2 Mask option

The mask option enables the following output port selection.

(1) Output specifications of output ports

Output specifications for the output ports (R00–R03, R10–R13) enable selection of either complemen-

tary output or Pch open drain output for each of the eight bits.

However, even when Pch open drain output is selected, voltage exceeding source voltage must not be

applied to the output port.

(2) Special output

In addition to the regular DC output, special output can be selected for the output ports R10–R13 as

shown in Table 4.5.2.1. Figure 4.5.2.1 shows the structure of the output ports R10–R13.

Table 4.5.2.1 Special output

Output port

R10

R13

R11

R12

Special output

BZ output

BZ output (selectable only when R10 is used as BZ output)

SIOF output

FOUT output

I-28 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

Data bus

Address 2ECH Mask option

R13

R10

FOUT

SIOF

R11

R12

Fig. 4.5.2.1 Structure of output port R10–R13

BZ, BZ (R10, R13)

BZ and BZ are the buzzer signal output for driving the piezoelectric buzzer. The buzzer signal is

generated by demultiplicaion of fOSC1. Also, a digital envelope can be added to the buzzer signal. See

Section 4.11, "Sound Generator", for details.

Notes: • When the BZ and BZ output signals are tur ned ON or OFF, a hazard can result.

• When DC output is set for the output port R10, the output port R13 cannot be set for BZ output.

Figure 4.5.2.2 shows the output waveform for BZ and BZ.

R00(R03) register

BZ output (R10 terminal)

BZ output (R13 terminal)

"0" "1" "0"

Fig. 4.5.2.2 Output waveform of BZ and BZ

SIOF (R11)

When the output port R11 is set for SIOF output, it outputs the signal indicating the running status

(RUN/STOP) of the serial interface. See Section 4.7, "Serial Interface", for details.

FOUT (R12)

When the output port R12 is set for FOUT output, it outputs the clock of fOSC1 or the demultiplied

fOSC1. The clock frequency is selectable with the mask options, from the frequencies listed in Table

4.5.2.2. Table 4.5.2.2 FOUT clock frequency

Setting value

fOSC1 / 1

fOSC1 / 2

fOSC1 / 4

fOSC1 / 8

fOSC1 / 16

fOSC1 / 32

fOSC1 / 64

fOSC1 / 128

fOSC1 = 32.768 kHz

32,768

16,384

8,192

4,096

2,048

1,024

512

256

Clock frequency (Hz)

fOSC1 = 38.400 kHz

38,400

19,200

9,600

4,800

2,400

1,200

600

300

Note

A hazard may occur when the FOUT signal is turned ON or OFF.

S1C60N08 TECHNICAL HARDWARE EPSON I-29

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

4.5.3 Control of output ports

Table 4.5.3.1 lists the output ports' control bits and their addresses.

Table 4.5.3.1 Control bits of output ports

Address Comment

D3 D2

D1 D0 Name Init ∗110

2EBH

R03 R02 R01 R00

R/W

R03

R02

R01

R00

High

Low

Output port (R03)

Output port (R02)

Output port (R01)

Output port (R00)

2ECH

R13 R12 R11

SIOF R10

R/W

RR/WR/W

R13

R12

R11

SIOF

R10

High/On

High

Run

High/On

Low/Off

Low

Stop

Low/Off

Output port (R13)/BZ output control

Output port (R12)/FOUT output control

Output port (R11, LAMP)

Output port (SIOF)

Output port (R10)/BZ output control

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read ∗5 Undefined

R00–R03, R10–R13 (when DC output): Output port data (2EBH, 2ECH)

Sets the output data for the output ports.

When "1" is written : High output

When "0" is written : Low output

Read-out : Valid

The output port terminals output the data written in the corresponding registers (R00–R03, R10–R13)

without changing it. When "1" is written in the register, the output port terminal goes high (VDD), and

when "0" is written, the output port terminal goes low (VSS).

At initial reset, all registers are set to "0".

R10, R13 (when BZ and BZ output is selected): Buzzer output control (2ECH•D0 and D3)

These bits control the output of the buzzer signals (BZ, BZ).

When "1" is written : Buzzer signal is output

When "0" is written : Low level (DC) is output

Read-out : Valid

BZ is output from terminal R13. With the mask option, selection can be made perform this output control

by R13, or to perform output control simultaneously with BZ by R10.

• When R13 controls BZ output

BZ output and BZ output can be controlled independently. BZ output is controlled by writing data to

R10, and BZ output is controlled by writing data to R13.

• When R10 controls BZ output

BZ output and BZ output can be controlled simultaneously by writing data to R10 only. For this case,

R13 can be used as a one-bit general register having both read and write functions, and data of this

At initial reset, registers R10 and R13 are set to "0".

R11 (when SIOF output is selected): Serial interface status (2ECH•D1)

Indicates the running status of the serial interface.

When "1" is read out : RUN

When "0" is read out : STOP

Writing : Valid

See Section 4.7, "Serial Interface", for details of SIOF.

This bit is exclusively for reading out, so data cannot be written to it.

I-30 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)

R12 (when FOUT is selected): FOUT output control (2ECH•D2)

Controls the FOUT (clock) output.

When "1" is written : Clock output

When "0" is written : Low level (DC) output

Read-out : Valid

FOUT output can be controlled by writing data to R12.

At initial reset, this register is set to "0".

4.5.4 Programming note

When BZ, BZ and FOUT are selected with the mask option, a hazard may be observed in the output

waveform when the data of the output register changes.

S1C60N08 TECHNICAL HARDWARE EPSON I-31

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

4.6 I/O Ports (P00–P03, P10–P13)

4.6.1 Configuration of I/O ports

The S1C60N08 Series has eight bits (4 bits × 2) of general-purpose I/O ports. Figure 4.6.1.1 shows the

configuration of the I/O ports.

The four bits of each of the I/O ports P00–P03 and P10–P13 can be set to either input mode or output

mode. Modes can be set by writing data to the I/O control register.

I/O control

Address

Data bus

Address

VSS

Input

control

Fig. 4.6.1.1 Configuration of I/O port

4.6.2 I/O control register and I/O mode

Input or output mode can be set for the four bits of I/O port P00–P03 and I/O port P10–P13 by writing

data into the corresponding I/O control register IOC0 and IOC1.

To set the input mode, "0" is written to the I/O control register. When an I/O port is set to input mode, it

becomes high impedance status and works as an input port.

However, the input line is pulled down when input data is read.

The output mode is set when "1" is written to the I/O control register. When an I/O port set to output

mode works as an output port, it outputs a high signal (VDD) when the port output data is "1", and a low

signal (VSS) when the port output data is "0".

At initial reset, the I/O control registers are set to "0", and the I/O port enters the input mode.

4.6.3 Mask option

The output specification during output mode (IOC = "1") of these I/O ports can be set with the mask

option for either complementary output or Pch open drain output. This setting can be performed for each

bit of each port.

However, when Pch open drain output has been selected, voltage in excess of the power voltage must not

be applied to the port.

I-32 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

4.6.4 Control of I/O ports

Table 4.6.4.1 lists the I/O ports' control bits and their addresses.

Table 4.6.4.1 I/O port control bits

Address Comment

D3 D2

D1 D0 Name Init ∗110

2EEH

TMRST SWRUN SWRST IOC0

WR/WWR/W

TMRST

∗

SWRUN

SWRST

∗

IOC0

Reset

Run

Reset

Output

–

Stop

–

Input

Clock timer reset

Stopwatch timer Run/Stop

Stopwatch timer reset

I/O control register 0 (P00–P03)

2EDH

P03 P02 P01 P00

R/W

P03

P02

P01

P00

–

∗

–

∗

–

∗

–

∗

High

Low

I/O port data (P00–P03)

Output latch is reset at initial reset

∗5 Undefined∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

2FEH

PRSM CLKCHG OSCC IOC1

R/W

PRSM

CLKCHG

OSCC

IOC1

38 kHz

OSC3

Output

32 kHz

OSC1

Off

Input

OSC1 prescaler selection

CPU clock switch

OSC3 oscillation On/Off

I/O control register (P10–P13)

2FDH

P13 P12 P11 P10

R/W

P13

P12

P11

P10

–

∗

–

∗

–

∗

–

∗

High

Low

I/O port data (P10–P13)

Output latch is reset at initial reset

P00–P03, P10–P13: I/O port data (2EDH, 2FDH)

I/O port data can be read and output data can be set through these ports.

When writing data

When "1" is written : High level

When "0" is written : Low level

When an I/O port is set to the output mode, the written data is output unchanged from the I/O port

terminal. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written,

the level goes low (VSS).

Port data can be written also in the input mode.

When reading data out

When "1" is read out : High level

When "0" is read out : Low level

The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage

level being input to the port terminal can be read out; in the output mode the output voltage level can be

read. When the terminal voltage is high (VDD) the port data that can be read is "1", and when the terminal

voltage is low (VSS) the data is "0".

Further, the built-in pull-down resistance goes ON during read-out, so that the I/O port terminal is

pulled down.

Notes: •When the I/O port is set to the output mode and a low-impedance load is connected to the port

terminal, the data written to the register may differ from the data read out.

•When the I/O port is set to the input mode and a low-level voltage (VSS) is input, erroneous input

results if the time constant of the capacitive load of the input line and the built-in pull-down

resistance load is greater than the read-out time. When the input data is being read out, the time

that the input line is pulled down is equivalent to 1.5 cycles of the CPU system clock. However,

the electric potential of the terminals must be settled within 0.5 cycles. If this condition cannot be

fulfilled, some measure must be devised such as arranging pull-down resistance externally, or

performing multiple read-outs.

S1C60N08 TECHNICAL HARDWARE EPSON I-33

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

IOC0, IOC1: I/O control registers (2EEH•D0, 2FEH•D0)

The input and output modes of the I/O ports can be set with these registers.

When "1" is written : Output mode

When "0" is written : Input mode

Read-out : Valid

The input and output modes of the I/O ports are set in units of four bits. IOC0 sets the mode for P00–P03,

and IOC1 sets the mode for P10–P13.

Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and

writing "0" induces the input mode.

At initial reset, these two registers are set to "0", so the I/O ports are in the input mode.

4.6.5 Programming notes

(1) When input data are changed from high to low by built-in pull-down resistance, the fall of the

waveform is delayed on account of the time constant of the pull-down resistance and input gate

capacitance. Consequently, if data is read out while the CPU is running in the OSC3 oscillation circuit,

data must be read out continuously for about 500 µsec.

(2) When the I/O port is set to the output mode and the data register has been read, the terminal data

instead of the register data can be read out. Because of this, if a low-impedance load is connected and

read-out performed, the value of the register and the read-out result may differ.

I-34 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

4.7 Serial Interface (SIN, SOUT, SCLK)

4.7.1 Configuration of serial interface

The S1C60N08 Series has a synchronous clock type 8 bits serial interface built-in.

The configuration of the serial interface is shown in Figure 4.7.1.1.

The CPU, via the 8 bits shift register, can read the serial input data from the SIN terminal. Moreover, via

the same 8 bits shift register, it can convert parallel data to serial data and output it to the SOUT terminal.

The synchronous clock for serial data input/output may be set by selecting by software any one of 3

types of master mode (internal clock mode: when the S1C60N08 Series is to be the master for serial

input/output) and a type of slave mode (external clock mode: when the S1C60N08 Series is to be the

slave for serial input/output).

Also, when the serial interface is used at slave mode, SIOF signal which indicates whether or not the

serial interface is available to transmit or receive can be output to output port R11 by mask option.

SD0–SD7

SCS0 SCS1

SE2

Output

latch

EISIO

Serial I/F

interrupt control

circuit ISIO

SIOF

SCTRG

Serial I/F

activating

circuit

System clock

Serial clock

counter

Serial clock

selector

Shift register (8 bits)

Serial clock

generator

SOUT

SIN

SCLK

Fig. 4.7.1.1 Configuration of serial interface

4.7.2 Master mode and slave mode of serial interface

The serial interface of the S1C60N08 Series has two types of operation mode: master mode and slave mode.

In the master mode, it uses an internal clock as synchronous clock of the built-in shift register, generates

this internal clock at the SCLK terminal and controls the external (slave side) serial device.

In the slave mode, the synchronous clock output from the external (master side) serial device is input

from the SCLK terminal and uses it as the synchronous clock to the built-in shift register.

The master mode and slave mode are selected by writing data to registers SCS1 and SCS0 (address

2F2H•D2, D3).

When the master mode is selected, a synchronous clock may be selected from among 3 types as shown in

Table 4.7.2.1. Table 4.7.2.1 Synchronous clock selection

SCS1

SCS0

Mode

Master mode

Slave mode

Synchronous clock

CLK

CLK/2

CLK/4

External clock

CLK: CPU system clock

At initial reset, the slave mode (external clock mode) is selected.

Moreover, the synchronous clock, along with the input/output of the 8 bits serial data, is controlled as

follows:

• At master mode, after output of 8 clocks from the SCLK terminal, clock output is automatically sus-

pended and SCLK terminal is fixed at low level.

• At slave mode, after input of 8 clocks to the SCLK terminal, subsequent clock inputs are masked.

S1C60N08 TECHNICAL HARDWARE EPSON I-35

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

Note: When using the serial interface in the master mode, CPU system clock is used as the synchronous

clock. Accordingly, when the serial interface is operating, system clock switching (fOSC1

↔

fOSC3)

should not be performed.

A sample basic serial input/output portion connection is shown in Figure 4.7.2.1.

S1C60N08

Master mode Slave mode

SCLK

SOUT

SIN

Input terminal

External

serial device

CLK

SOUT

SIN

READY

S1C60N08

SCLK

SOUT

SIN

R11(SIOF)

External

serial device

CLK

SOUT

SIN

Input terminal

Fig. 4.7.2.1 Sample basic connection

4.7.3 Data input/output and interrupt function

The serial interface can input/output data via the internal 8 bits shift register. The shift register operates

by synchronizing with either the synchronous clock output from SCLK terminal (master mode), or the

synchronous clock input to SCLK (slave mode).

The serial interface generates interrupt on completion of the 8 bits serial data input/output. Detection of

serial data input/output is done by the counting of the synchronous clock (SCLK); the clock completes

input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates

interrupt.

The serial data input/output procedure data is explained below:

(1)Serial data output procedure and interrupt

The serial interface is capable of outputting parallel data as serial data, in units of 8 bits.

By setting the parallel data to 4 bits registers SD0–SD3 (address 2F0H) and SD4–SD7 (address 2F1H)

individually and writing "1" to SCTRG bit (address 2E7H·D3), it synchronizes with the synchronous

clock and serial data is output at the SOUT terminal. The synchronous clock used here is as follows: in

the master mode, internal clock which is output to the SCLK terminal while in the slave mode,

external clock which is input from the SCLK terminal. The serial output of the SOUT termina changes

with the rising edge of the clock that is input or output from the SCLK terminal.

The serial data to the built-in shift register is shifted with the rising edge of the SCLK signal when SE2

bit (address 2F2H•D1) is "1" and is shifted with the falling edge of the SCLK signal when SE2 bit

(address 2F2H•D1) is "0".

When the output of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO

(address 2F3H•D0) is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by

the interrupt mask register EISIO (address 2F2H•D0).

(2)Serial data input procedure and interrupt

The serial interface is capable of inputting serial data as parallel data, in units of 8 bits.

The serial data is input from the SIN terminal, synchronizes with the synchronous clock, and is

sequentially read in the 8 bits shift register. As in the above item (1), the synchronous clock used here

is as follows: in the master mode, internal clock which is output to the SCLK terminal while in the

slave mode, external clock which is input from the SCLK terminal.

The serial data to the built-in shift register is read with the rising edge of the SCLK signal when SE2

bit is "1" and is read with the falling edge of the SCLK signal when SE2 bit is "0". Moreover, the shift

When the input of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO is set to

"1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register

EISIO. Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor

flag is set to "1" after input of the 8 bits data.

The data input in the shift register can be read from data registers SD0–SD7 by software.

I-36 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

(3)Serial data input/output permutation

The S1C60N08 Series allows the input/output permutation of serial data to be selected by mask

option as to either LSB first or MSB first. The block diagram showing input/output permutation in

case of LSB first and MSB first is provided in Figure 4.7.3.1.

SD7 SD6 SD5 SD4

Address [2F1H]

In case of LSB first

SIN SOUT

SD3 SD2 SD1 SD0

Address [2F0H] Output

latch

SD0 SD1 SD2 SD3

Address [2F0H]

In case of MSB first

SIN SOUT

SD4 SD5 SD6 SD7

Address [2F1H] Output

latch

Fig. 4.7.3.1 Serial data input/output permutation

(4)SIOF signal

When the serial interface is used in the slave mode (external clock mode), SIOF is used to indicate

whether the internal serial interface is available to transmit or receive data for the master side (exter-

nal) serial device. SIOF signal is generated from output port R11 by mask option.

SIOF signal becomes "1" (high) when the S1C60N08 serial interface becomes available to transmit or

receive data; normally, it is at "0" (low).

SIOF signal changes from "0" to "1" immediately after "1" is written to SCTRG and returns from "1" to

"0" when eight synchronous clock has been counted.

(5)Timing chart

The serial interface timing chart is shown in Figure 4.7.3.2.

SCTRG

SCLK

SIN

8-bit shift register

SOUT

ISIO

SIOF

SCTRG

SCLK

SIN

8-bit shift register

SOUT

ISIO

SIOF

(a) SE2 = "1"

(b) SE2 = "0"

Fig. 4.7.3.2 Serial interface timing chart

S1C60N08 TECHNICAL HARDWARE EPSON I-37

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

4.7.4 Mask option

The serial interface may be selected for the following by mask option.

(1) Whether or not the SIN terminal will use built-in pull down resistor may be selected.

If the use of no pull down resistor is selected, take care that floating state does not occur at the SIN

terminal. When the SIN terminal is not used, the use of pull down resistor should be selected.

(2) Either complementary output or P channel (Pch) open drain as output specification for the SOUT

terminal may be selected.

However, even if Pch open drain has been selected, application of voltage exceeding power source

voltage to the SOUT terminal will be prohibited.

(3) Whether or not the SCLK terminal will use pull down resistor which is turned ON during input mode

(external clock) may be selected.

If the use of no pull down resistor is selected, take care that floating state does not occur at the SCLK

terminal during input mode.

Normally, the use of pull down resistor should be selected.

(4) As output specification during output mode, either complementary output or P channel (Pch) open

drain output may be selected for the SCLK terminal.

(5) Positive or negative logic can be selected for the signal logic of the SCLK pin (SCLK or SCLK).

However, keep in mind that only pull-down resistance can be set for the input mode (pull-up resis-

tance is not built-in).

(6) LSB first or MSB first as input/output permutation of serial data may be selected.

(7) Output port R11 may be assigned as SIOF output terminal which will indicate whether the serial

interface is available to transmit or receive signals.

I-38 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

4.7.5 Control of serial interface

The control registers for the serial interface are explained below.

Table 4.7.5.1 Control bits of serial interface

Address Comment

D3 D2

D1 D0 Name Init

∗1

∗5 Undefined∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

2F3H

0 0 IK2 ISIO

∗

IK2

∗

ISIO

∗

–

∗

–

∗

–

Yes

–

Unused

Interrupt factor flag (K20–K23)

Interrupt factor flag (serial I/F)

2E7H

SCTRG IK10 KCP10 K10

WRR/W

SCTRG

∗

EIK0

KCP10

K10

–

∗

Trigger

Enable

High

–

Mask

Low

Serial I/F clock trigger

Interrupt mask register (K10)

Input comparison register (K10)

Input port data (K10)

2ECH

R13 R12 R11

SIOF R10

R/W

RR/WR/W

R13

R12

R11

SIOF

R10

High/On

High

Run

High/On

Low/Off

Low

Stop

Low/On

Output port (R13)/BZ output control

Output port (R12)/FOUT output control

Output port (R11, LAMP)

Output port (SIOF)

Output port (R10)/BZ output control

2F0H

SD3 SD2 SD1 SD0

R/W

SD3

SD2

SD1

SD0

∗

Serial I/F data register (low-order 4 bits)

2F1H

SD7 SD6 SD5 SD4

R/W

SD7

SD6

SD5

SD4

∗

Serial I/F data register (high-order 4 bits)

2F2H

SCS1 SCS0 SE2 EISIO

R/W

SCS1

SCS0

SE2

EISIO

0 Enable Mask

Serial I/F clock

mode selection

Serial I/F clock edge selection

Interrupt mask register (serial I/F)

CLK 1

CLK/2 2

CLK/4 3

Slave

[SCS1, 0]

Clock

SD0–SD3, SD4–SD7: Serial interface data registers (2F0H, 2F1H)

These registers are used for writing and reading serial data.

During writing operation

When "1" is written : High level

When "0" is written : Low level

Writes serial data will be output to SOUT terminal. From the SOUT terminal, the data converted to serial

data as high (VDD) level bit for bits set at "1" and as low (VSS) level bit for bits set at "0".

During reading operation

When "1" is read out : High level

When "0" is read out : Low level

The serial data input from the SIN terminal can be read by this register.

The data converted to parallel data, as high (VDD) level bit "1" and as low (VSS) level bit "0" input from

SIN terminal. Perform data reading only while the serial interface is halted (i.e., the synchronous clock is

neither being input or output).

At initial reset, these registers will be undefined.

S1C60N08 TECHNICAL HARDWARE EPSON I-39

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

SCS1, SCS0: Clock mode selection register (2F2H•D3, D2)

Selects the synchronous clock for the serial interface (SCLK).

Table 4.7.5.2 Synchronous clock selection

SCS1

SCS0

Mode

Master mode

Slave mode

Synchronous clock

CLK

CLK/2

CLK/4

External clock

CLK: CPU system clock

Synchronous clock (SCLK) is selected from among the above 4 types: 3 types of internal clock and

external clock.

At initial reset, external clock is selected.

SE2: Clock edge selection register (2F2H•D1)

Selects the timing for reading in the serial data input.

When "1" is written : Rising edge of SCLK

When "0" is written : Falling edge of SCLK

Read-out : Valid

Selects whether the fetching for the serial input data to registers (SD0–SD7) at the rising edge (at "1"

writing) or falling edge (at "0" writing) of the SCLK signal.

Pay attention if the synchtonous clock goes into reverse phase (SCLK → SCLK) through the mask option.

SCLK rising = SCLK falling, SCLK falling = SCLK rising

When the internal clock is selected as the synchronous clock (SCLK), a hazard occurs in the synchronous

clock (SCLK) when data is written to register SE2.

The input data fetching timing may be selected but output timing for output data is fixed at SCLK rising

edge.

At initial reset, falling edge of SCLK (SE2 = "0") is selected.

EISIO: Interrupt mask register (2F2H•D0)

This is the interrupt mask register of the serial interface.

When "1" is written : Enabled

When "0" is written : Masked

Read-out : Valid

At initial reset, this register is set to "0" (mask).

ISIO: Interrupt factor flag (2F3H•D0)

This is the interrupt factor flag of the serial interface.

When "1" is read out : Interrupt has occurred

When "0" is read out : Interrupt has not occurred

Writing : Invalid

From the status of this flag, the software can decide whether the serial interface interrupt.

The interrupt factor flag is reset when it has been read out.

Note, however, that even if the interrupt is masked, this flag will be set to "1" after the 8 bits data input/

output.

Be sure that the interrupt factor flag reading is done with the interrupt in the DI status (interrupt flag =

"0").

At initial reset, this flag is set to "0".

I-40 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

SCTRG: Clock trigger (2E7H•D3)

This is a trigger to start input/output of synchronous clock.

When "1" is written : Trigger

When "0" is written : No operation

Read-out : Always "0"

When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK)

input/output is started.

As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be performed

prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writ-

ing/reading on data registers SD0–SD7.)

Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from

perfoming trigger input multiple times, as leads to malfunctioning.

Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the

trigger.

SIOF (R11): Serial interface status (2ECH•D1)

Indicates the running status of the serial interface.

When "1" is read out : RUN status

When "0" is read out : STOP status

Writing : Invalid

The RUN status is indicated from immediatery after "1" is written to SCTRG bit through to the end of

serial data input/output.

4.7.6 Programming notes

(1) If the bit data of SE2 changes while SCLK is in the master mode, a hazard will be output to the SCLK

pin. If this poses a problem for the system, be sure to set the SCLK to the external clock if the bit data

of SE2 is to be changed.

(2) Be sure that read-out of the interrupt factor flag (ISIO) is done only when the serial port is in the STOP

status (SIOF = "0") and the DI status (interrupt flag = "0"). If read-out is performed while the serial

data is in the RUN status (during input or output), the data input or output will be suspended and the

initial status resumed. Read-out during the EI status (interrupt flag = "1") causes malfunctioning.

(3) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock.

Accordingly, do not change the system clock (fOSC1 ↔ fOSC3) while the serial interface is operating.

(4) Perform data writing/reading to data registers SD0–SD7 only while the serial interface is halted (i.e.,

the synchronous clock is neither being input or output).

(5) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be per-

formed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through

data writing/reading on data registers SD0–SD7.) Supply trigger only once every time the serial

interface is placed in the RUN state. Moreover, when the synchronous clock SCLK is external clock,

start to input the external clock after the trigger.

(6) Be sure that writing to the interrupt mask register is done only in the DI status (interrupt flag = "0").

Writing to the interrupt mask register while in the EI status (interrupt flag = "1") may cause malfunc-

tion.

S1C60N08 TECHNICAL HARDWARE EPSON I-41

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

4.8 LCD Driver (COM0–COM3, SEG0–SEG47)

4.8.1 Configuration of LCD driver

The S1C60N08 Series has four common terminals and 48 (SEG0–SEG47) segment terminals, so that an

LCD with a maximum of 192 (48 × 4) segments can be driven. The power for driving the LCD is gener-

ated by the internal circuit, so there is no need to supply power externally.

The driving method is 1/4 duty (or 1/3, 1/2 duty is selectable by mask option) dynamic drive, adopting

the four types of potential (1/3 bias), VDD, VL1, VL2 and VL3. Moreover, the 1/2 bias dynamic drive that

uses three types of potential, VDD, VL1 = VL2 and VL3, can be selected by setting the mask option (drive

duty can also be selected from 1/4, 1/3 or 1/2).

1/2 bias drive is effective when the LCD system voltage regulator is not used. The VL1 terminal and the

VL2 terminal should be connected outside the IC.

The frame frequency is 32 Hz for 1/4 duty and 1/2 duty, and 42.7 Hz for 1/3 duty (in the case of fOSC1 =

32.768 kHz).

Figures 4.8.1.1 to 4.8.1.6 show the drive waveform for each duty and bias.

Notes:• "fOSC1" indicates the oscillation frequency of the oscillation circuit.

• If there is any segment pad that is set to be DC type, the internal LCD voltage regulator cannot

be chosen in all models. Or, if the inter nal LCD voltage regulator is chosen in any model, the

segment pad cannot be set to be DC type.

Table 4.8.1.1 LCD voltage regulator and DC output from SEG terminals

LCD system voltage regulator

Use

Not use

DC output from SEG terminals

Not available

Available

I-42 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

COM0

COM1

COM2

COM3

SEG0

–SEG47

Frame frequency

Off

LCD lighting status

COM0

COM1

COM2

COM3

SEG0–47

Fig. 4.8.1.1 Drive waveform for 1/4 duty (1/3 bias)

S1C60N08 TECHNICAL HARDWARE EPSON I-43

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

COM0

COM1

COM2

COM3

Off

SEG0

–SEG47

Frame frequency

LCD lighting status

COM0

COM1

COM2

SEG0–47

Fig. 4.8.1.2 Drive waveform for 1/3 duty (1/3 bias)

COM0

COM1

COM2

COM3

Off

SEG0

–SEG47

Frame frequency

LCD lighting status

SEG0–47

COM0

COM1

Fig. 4.8.1.3 Drive waveform for 1/2 duty (1/3 bias)

I-44 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD lighting status

SEG

0–47

SEG0–47

COM0

COM1

COM2

COM3

COM0

COM1

COM2

COM3

-VDD

-VL1, L2

-VL3

-VDD

-VL1, L2

-VL3

Frame frequency

Off

Fig. 4.8.1.4 Drive waveform for 1/4 duty (1/2 bias)

S1C60N08 TECHNICAL HARDWARE EPSON I-45

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

LCD lighting status

SEG

0–47

SEG0–47

COM0

COM1

COM2

COM0

COM1

COM2

COM3

-VDD

-VL1, L2

-VL3

-VDD

-VL1, L2

-VL3

Frame frequency

Off

Fig. 4.8.1.5 Drive waveform for 1/3 duty (1/2 bias)

COM0

COM1

COM0

COM1

COM2

COM3

-V

L1, L2

-V

L1, L2

-V

LCD lighting status

SEG

0–47

SEG0–47

Frame frequency

Off

Fig. 4.8.1.6 Drive waveform for 1/2 duty (1/2 bias)

I-46 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

4.8.2 Cadence adjustment of oscillation frequency

In the S1C60N08 Series, the LCD drive duty can be set to 1/1 duty by software. This function enables

easy adjustment (cadence adjustment) of the oscillation frequency of the oscillation circuit.

The procedure to set to 1/1 duty drive is as follows:

➀Write "1" to the CSDC register at address 2E8H•D3.

➁Write the same value to all registers corresponding to COMs 0 through 3 of the display memory.

The frame frequency is 32 Hz (fOSC1/1,024, when fOSC1 = 32.768 kHz).

Notes:•Even when l/3 or 1/2 duty is selected by the mask option, the display data corresponding to all

COM are valid during 1/1 duty driving. Hence, for 1/1 duty drive, set the same value for all

display memory corresponding to COMs 0 through 3.

•For cadence adjustment, set the display data corresponding to COMs 0 through 3, so that all the

LCD segments go on.

Figures 4.8.2.1 and 4.8.2.2 show the 1/1 duty drive waveform in 1/3 bias and 1/2 bias driving.

SEG

0–47

COM

0–3

Frame frequency

LCD lighting status

COM0

COM1

COM2

COM3

SEG0–47

-VDD

-VL1

-VL2

-VL3

-VDD

-VL1

-VL2

-VL3

-VDD

-VL1

-VL2

-VL3

Off On

Fig. 4.8.2.1 Drive waveform for 1/1 duty (1/3 bias)

SEG

0–47

COM

0–3

Frame frequency

LCD lighting status

COM0

COM1

COM2

COM3

SEG0–47

-V

L1,

-V

Off On

-V

L1,

-V

L1,

-V

Fig. 4.8.2.2 Drive waveform for 1/1 duty (1/2 bias)

S1C60N08 TECHNICAL HARDWARE EPSON I-47

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

4.8.3 Mask option (segment allocation)

(1)Segment allocation

As shown in Figure 4.1.2, segment data of the S1C60N08 Series is decided depending on display data

written to the display memory at address 040H–06FH (Page 0) or 240H–26FH (Page 2).

• The mask option enables the display memory to be allocated entirely to either Page 0 or Page 2.

• The address and bits of the display memory can be made to correspond to the segment terminals

(SEG0–SEG47) in any form through the mask option. This makes design easy by increasing the

degree of freedom with which the liquid crystal panel can be designed.

Figure 4.8.3.1 shows an example of the relationship between the LCD segments (on the panel) and the

display memory (when page 0 is selected) for the case of 1/3 duty.

aa'

ff'

ee'

dd' p'

SEG10 SEG11 SEG12

Common 0 Common 1 Common 2

09AH

09BH

09CH

09DH

Address

Data

Display data memory allocation

SEG10

SEG11

SEG12

9A, D0

(a)

9A, D1

(b)

9D, D1

(f')

9B, D1

(f)

9B, D2

(g)

9A, D2

(c)

9B, D0

(e)

9A, D3

(d)

9B, D3

(p)

Pin address allocation

Common 0 Common 1 Common 2

Fig. 4.8.3.1 Segment allocation

(2)Drive duty

According to the mask option, either 1/4, 1/3 or 1/2 duty can be selected as the LCD drive duty.

Table 4.8.3.1 shows the differences in the number of segments according to the selected duty.

Table 4.8.3.1 Differences according to selected duty

Duty

1/4

1/3

1/2

COM used

COM0–COM3

COM0–COM2

COM0–COM1

Max. number of segments

192 (48 × 4)

144 (48 × 3)

96 (48 × 2)

Frame frequency *

OSC1

/1,024 (32 Hz)

OSC1

/768 (42.7 Hz)

OSC1

/1,024 (32 Hz)

∗ When f

OSC1

= 32 kHz

I-48 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

(3)Output specification

• The segment terminals (SEG0–SEG47) are selected by mask option in pairs for either segment signal

output or DC output (VDD and VSS binary output). When DC output is selected, the data corre-

sponding to COM0 of each segment terminal is output.

• When DC output is selected, either complementary output or Pch open drain output can be selected

for each terminal by mask option.

Note: The terminal pairs are the combination of SEG (2

∗

n) and SEG (2

∗

n + 1) (where n is an integer from 0 to 23).

(4)Drive bias

For the drive bias of the S1C60N08 or the S1C60L08, either 1/3 bias or 1/2 bias can be selected by the

mask option. When using the LCD system voltage regulator, it is fixed at 1/3 bias.

4.8.4 Control of LCD driver

Table 4.8.4.1 shows the LCD driver's control bits and their addresses. Figure 4.8.4.1 shows the display

memory map.

Table 4.8.4.1 Control bits of LCD driver

Address Comment

D3 D2

D1 D0 Name Init

∗1

2E8H

CSDC ETI2 ETI8 ETI32

R/W

CSDC

ETI2

ETI8

ETI32

Static

Enable

Dynamic

Mask

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

2D0H

000LOF

RR/W

∗

LOF

–

∗

–

∗

–

∗

–

Normal

–

All off

Unused

LCD all off control

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read ∗5 Undefined

Address

Page Low

High 0 1 2 3 4 5 6 7 8 9 A B C D E F

0 or 2 4

Display memory (48 words × 4 bits)

Page 0: R/W, Page 2: W only

Fig. 4.8.4.1 Display memory map

LOF: LCD all Off control (2D0H•D0)

Controls the LCD display.

When "1" is written : LCD displayed

When "0" is written : LCD is all off

Read-out : Valid

By writing "0" to the LOF register, all the LCD dots goes off, and when "1" is written, it returns to normal

display.

Writing "0" outputs an off waveform to the SEG terminals, and does not affect the content of the display

memory.

After an initial reset, LOF is set to "1".

CSDC: LCD drive switch (2E8H•D3)

The LCD drive format can be selected with this switch.

When "1" is written : Static drive

When "0" is written : Dynamic drive

Read-out : Valid

At initial reset, dynamic drive (CSDC = "0") is selected.

S1C60N08 TECHNICAL HARDWARE EPSON I-49

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)

Display memory (040H–06FH or 240H–26FH)

The LCD segments are lit or turned off depending on this data.

When "1" is written : Lit

When "0" is written : Not lit

Read-out : Valid for Page 0

Undefined Page 2

By writing data into the display memory allocated to the LCD segment (on the panel), the segment can be

lit or put out.

At initial reset, the contents of the display memory are undefined.

4.8.5 Programming notes

(1) When Page 0 is selected for the display memory, the memory data and the display will not match

until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the

display memory by executing initial processing.

(2) When Page 2 is selected for the display memory, that area becomes write-only. Consequently, data

cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB).

I-50 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

4.9 Clock Timer

4.9.1 Configuration of clock timer

The S1C60N08 Series has a built-in clock timer as the source oscillator for prescaler. The clock timer is

configured of a seven-bit binary counter that serves as the input clock, a 256 Hz signal output by the

prescaler. Data of the four high-order bits (16 Hz–2 Hz) can be read out by the software.

Figure 4.9.1.1 is the block diagram for the clock timer.

32 Hz, 8 Hz, 2 Hz

256 Hz

Clock timer reset signal Interrupt request

OSC1

oscillation

circuit

Watchdog

timer

Selector

Data bus

128 Hz–32 Hz

Prescaler 1

Prescaler 2 16 Hz–2 Hz

Prescaler selection signal Interrupt

control

Clock Timer

Fig. 4.9.1.1 Clock timer block diagram

Ordinarily, this clock timer is used for all types of timing functions such as clocks.

The input clock of the clock timer is output through the prescaler, so the prescaler mode must be set

correctly to suit the crystal oscillator to be used (32.768 kHz or 38.4 kHz). For how to set the prescaler, see

Section 4.3, "Oscillation Circuit and Prescaler".

4.9.2 Interrupt function

The clock timer can cause interrupts at the falling edge of 32 Hz, 8 Hz and 2 Hz signals. Software can set

whether to mask any of these frequencies.

Figure 4.9.2.1 is the timing chart of the clock timer.

Clock timer timing chartFrequencyRegisterAddress

2E0H

D0 16 Hz

8 Hz

4 Hz

2 Hz

32 Hz interrupt request

8 Hz interrupt request

2 Hz interrupt request

Fig. 4.9.2.1 Clock timer timing chart

As shown in Figure 4.9.2.1, interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz , 2

Hz). At this time, the corresponding interrupt factor flag (TI32, TI8, TI2) is set to "1". Selection of whether

to mask the separate interrupts can be made with the interrupt mask registers (ETI32, ETI8, ETI2).

However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the

falling edge of the corresponding signal.

S1C60N08 TECHNICAL HARDWARE EPSON I-51

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

4.9.3 Control of clock timer

Table 4.9.3.1 shows the clock timer control bits and their addresses.

Table 4.9.3.1 Control bits of clock timer

Address Comment

D3 D2

D1 D0 Name Init ∗110

2E0H

TM3 TM2 TM1 TM0

TM3

TM2

TM1

TM0

Clock timer data (2 Hz)

Clock timer data (4 Hz)

Clock timer data (8 Hz)

Clock timer data (16 Hz)

2E8H

CSDC ETI2 ETI8 ETI32

R/W

CSDC

ETI2

ETI8

ETI32

Static

Enable

Dynamic

Mask

LCD drive switch

Interrupt mask register (clock timer 2 Hz)

Interrupt mask register (clock timer 8 Hz)

Interrupt mask register (clock timer 32 Hz)

2E9H

0 TI2 TI8 TI32

∗

TI2

∗

TI8

∗

TI32

∗

–

∗

–

Yes

–

Unused

Interrupt factor flag (clock timer 2 Hz)

Interrupt factor flag (clock timer 8 Hz)

Interrupt factor flag (clock timer 32 Hz)

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read ∗5 Undefined

2EEH

TMRST SWRUN SWRST IOC0

WR/WWR/W

TMRST

∗

SWRUN

SWRST

∗

IOC0

Reset

Run

Reset

Output

–

Stop

–

Input

Clock timer reset

Stopwatch timer Run/Stop

Stopwatch timer reset

I/O control register 0 (P00–P03)

TM0–TM3: Timer data (2E0H)

The 16 Hz–2 Hz timer data of the clock timer can be read out with this register. These four bits are read-

out only, and writing operations are invalid.

At initial reset, the timer data is initialized to "0H".

ETI32, ETI8, ETI2: Interrupt mask registers (2E8H•D0–D2)

These registers are used to select whether to mask the clock timer interrupt.

When "1" is written : Enabled

When "0" is written : Masked

Read-out : Valid

The interrupt mask registers (ETI32, ETI8, ETI2) are used to select whether to mask the interrupt to the

separate frequencies (32 Hz, 8 Hz, 2 Hz).

Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0").

At initial reset, these registers are all set to "0".

TI32, TI8, TI2: Interrupt factor flags (2E9H•D0–D2)

These flags indicate the status of the clock timer interrupt.

When "1" is read out : Interrupt has occurred

When "0" is read out : Interrupt has not occurred

Writing : Invalid

The interrupt factor flags (TI32, TI8, TI2) correspond to the clock timer interrupts of the respective

frequencies (32 Hz, 8 Hz, 2 Hz). The software can judge from these flags whether there is a clock timer

interrupt. However, even if the interrupt is masked, the flags are set to "1" at the falling edge of the signal.

These flags can be reset through being read out by the software. Also, the flags can be read out only in the

DI status (interrupt flag = "0").

At initial reset, these flags are set to "0".

I-52 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)

TMRST: Clock timer reset (2EEH•D3)

This bit resets the clock timer.

When "1" is written : Clock timer reset

When "0" is written : No operation

Read-out : Always "0"

The clock timer is reset by writing "1" to TMRST. The clock timer starts immediately after this. No

operation results when "0" is written to TMRST.

This bit is write-only, and so is always "0" at read-out.

4.9.4 Programming notes

(1) The prescaler mode must be set correctly to suit the crystal oscillator to be used.

(2) When the clock timer has been reset, the interrupt factor flag (TI) may sometimes be set to "1". Conse-

quently, perform flag read-out (reset the flag) as necessary at reset.

(3) The input clock of the watchdog timer is the 2 Hz signal of the clock timer, so that the watchdog timer

may be counted up at timer reset.

(4) Read-out the interrupt factor flag (TI) only during the DI status (interrupt flag = "0"). Read-out during

EI status (interrupt flag = "1") will cause malfunction.

S1C60N08 TECHNICAL HARDWARE EPSON I-53

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

4.10 Stopwatch Timer

4.10.1 Configuration of stopwatch timer

The S1C60N08 Series incorporates a 1/100 sec and 1/10 sec stopwatch timer. The stopwatch timer is

configured of a two-stage, four-bit BCD counter serving as the input clock of an approximately 100 Hz

signal (signal obtained by approximately demultiplying the 256 Hz signal output by the prescaler). Data

can be read out four bits at a time by the software.

Figure 4.10.1.1 is the block diagram of the stopwatch timer.

10 Hz, 1 Hz

256 Hz 10 Hz

Stopwatch timer reset signal Interrupt request

OSC1

oscillation

circuit Selector

Data bus

SWL counter

Prescaler 1

Prescaler 2 SWH counter

Stopwatch timer RUN/STOP signal

Prescaler selection signal Interrupt

control

Stopwatch Timer

Fig. 4.10.1.1 Stopwatch timer block diagram

The stopwatch timer can be used as a separate timer from the clock timer. In particular, digital watch

stopwatch functions can be realized easily with software.

The input clock of the stopwatch timer is output through the prescaler, so the prescaler mode must be set

correctly to suit the crystal oscillator to be used (32.768 kHz or 38.4 kHz). For how to set the prescaler, see

Section 4.3, "Oscillation Circuit and Prescaler".

4.10.2 Count-up pattern

The stopwatch timer is configured of four-bit BCD counters SWL and SWH.

The counter SWL, at the stage preceding the stopwatch timer, has an approximated 100 Hz signal for the

input clock. It counts up every 1/100 sec, and generates an approximated 10 Hz signal. The counter SWH

has an approximated 10 Hz signal generated by the counter SWL for the input clock. It count-up every 1/

10 sec, and generated 1 Hz signal.

Figure 4.10.2.1 shows the count-up pattern of the stopwatch timer.

256 26

256

256 25

256

256 2

256 3

256 2

256

256 3

256

256 2

256

256 2

256

256 3

256

256 2

256

256 25

256

x 6 + x 4 = 1 (sec)

0 1 2 3 4 5 6 7 8 9 0

1 Hz

signal

generation

Approximate

10 Hz

signal

generation

SWH count value

Count time (sec)

(sec)

SWL count value

Count time (sec)

SWL count value

Count time (sec)

SWH count-up pattern

SWL count-up pattern 1

SWL count-up pattern 2

Approximate

10 Hz

signal

generation

Fig. 4.10.2.1 Count-up pattern of stopwatch timer

I-54 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

SWL generates an approximated 10 Hz signal from the basic 256 Hz signal. The count-up intervals are 2/

256 sec and 3/256 sec, so that finally two patterns are generated: 25/256 sec and 26/256 sec intervals.

Consequently, these patterns do not amount to an accurate 1/100 sec.

SWH counts the approximated 10 Hz signals generated by the 25/256 sec and 26/256 sec intervals in the

ratio of 4:6, to generate a 1 Hz signal. The count-up intervals are 25/256 sec and 26/256 sec, which do not

amount to an accurate 1/10 sec.

4.10.3 Interrupt function

The 10 Hz (approximate 10 Hz) and 1 Hz interrupts can be generated through the overflow of stopwatch

timers SWL and SWH respectively. Also, software can set whether to separately mask the frequencies

described earlier.

Figure 4.10.3.1 is the timing chart for the stopwatch timer.

Address

Stopwatch timer (SWL) timing chart

Stopwatch timer (SWH) timing chart

10 Hz interrupt request

1 Hz interrupt request

2E2H

1/10 sec

(BCD)

2E1H

1/100 sec

(BCD)

Fig. 4.10.3.1 Stopwatch timer timing chart

As shown in Figure 4.10.3.1, the interrupts are generated by the overflow of their respective counters ("9"

changing to "0"). Also, at this time the corresponding interrupt factor flags (SWIT0, SWIT1) are set to "1".

The respective interrupts can be masked separately through the interrupt mask registers (EISWIT0,

EISWIT1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are

set to "1" by the overflow of their corresponding counters.

S1C60N08 TECHNICAL HARDWARE EPSON I-55

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

4.10.4 Control of stopwatch timer

Table 4.10.4.1 list the stopwatch timer control bits and their addresses.

Table 4.10.4.1 Control bits of stopwatch timer

Address Comment

D3 D2

D1 D0 Name Init

∗1

2E1H

SWL3 SWL2 SWL1 SWL0

SWL3

SWL2

SWL1

SWL0

MSB

Stopwatch timer 1/100 sec data (BCD)

LSB

2E2H

SWH3 SWH2 SWH1 SWH0

SWH3

SWH2

SWH1

SWH0

MSB

Stopwatch timer 1/10 sec data (BCD)

LSB

2E6H

HLMOD BLD0 EISWIT1 EISWIT0

R/W R R/W

HLMOD

BLD0

EISWIT1

EISWIT0

Heavy load

Low

Enable

Normal

Mask

Heavy load protection mode register

Sub-BLD evaluation data

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

2EAH

IK1 IK0 SWIT1 SWIT0

IK1

∗

IK0

∗

SWIT1

∗

SWIT0

∗

Yes

Interrupt factor flag (K10)

Interrupt factor flag (K00–K03)

Interrupt factor flag (stopwatch 1 Hz)

Interrupt factor flag (stopwatch 10 Hz)

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read ∗5 Undefined

2EEH

TMRST SWRUN SWRST IOC0

WR/WWR/W

TMRST

∗

SWRUN

SWRST

∗

IOC0

Reset

Run

Reset

Output

–

Stop

–

Input

Clock timer reset

Stopwatch timer Run/Stop

Stopwatch timer reset

I/O control register 0 (P00–P03)

SWL0–SWL3: Stopwatch timer 1/100 sec (2E1H)

Data (BCD) of the 1/100 sec column of the stopwatch timer can be read out. These four bits are read-only,

and cannot be used for writing operations.

At initial reset, the timer data is set to "0H".

SWH0–SWH3: Stopwatch timer 1/10 sec (2E2H)

Data (BCD) of the 1/10 sec column of the stopwatch timer can be read out. These four bits are read-only,

and cannot be used for writing operations.

At initial reset, the timer data is set to "0H".

EISWIT0, EISWIT1: Interrupt mask registers (2E6H•D0 and D1)

These registers are used to select whether to mask the stopwatch timer interrupt.

When "1" is written : Enabled

When "0" is written : Masked

Read-out : Valid

The interrupt mask registers (EISWIT0, EISWIT1) are used to separately select whether to mask the 10 Hz

and 1 Hz interrupts.

At initial reset, these registers are both set to "0".

I-56 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

SWIT0, SWIT1: Interrupt factor flags (2EAH•D0 and D1)

These flags indicate the status of the stopwatch timer interrupt.

When "1" is read out : Interrupt has occurred

When "0" is read out : Interrupt has not occurred

Writing : Invalid

The interrupt factor flags (SWIT0, SWIT1) correspond to the 10 Hz and 1 Hz interrupts respectively. With

these flags, the software can judge whether a stopwatch timer interrupt has occurred. However, regard-

less of the interrupt mask register setting, these flags are set to "1" by the counter overflow.

These flags are reset when read out by the software. Also, read-out is only possible in the DI status

(interrupt flag = "0").

At initial reset, these flags are set to "0".

SWRST: Stopwatch timer reset (2EEH•D1)

This bit resets the stopwatch timer.

When "1" is written : Stopwatch timer reset

When "0" is written : No operation

Read-out : Always "0"

The stopwatch timer is reset when "1" is written to SWRST. When the stopwatch timer is reset in the RUN

status, operation restarts immediately. Also, in the STOP status the reset data is maintained.

This bit is write-only, and is always "0" at read-out.

SWRUN: Stopwatch timer RUN/STOP (2EEH•D2)

This bit controls RUN/STOP of the stopwatch timer.

When "1" is written : RUN

When "0" is written : STOP

Read-out : Valid

The stopwatch timer enters the RUN status when "1" is written to SWRUN, and the STOP status when "0"

is written.

In the STOP status, the timer data is maintained until the next RUN status or resets timer. Also, when the

STOP status changes to the RUN status, the data that was maintained can be used for resuming the count.

When the timer data is read out in the RUN status, correct read-out may be impossible because of the

carry from the low-order bit (SWL) to the high-order bit (SWH). This occurs when read-out has extended

over the SWL and SWH bits when the carry occurs. To prevent this, perform read out after entering the

STOP status, and then return to the RUN status. Also, the duration of the STOP status must be within 976

µsec (256 Hz 1/4 cycle).

At initial reset, this register is set to "0".

4.10.5 Programming notes

(1) The prescaler mode must be set correctly so that the stopwatch timer suits the crystal oscillator to be

used.

(2) If timer data is read out in the RUN status, the timer must be made into the STOP status, and after

data is read out the RUN status can be restored. If data is read out when a carry occurs, the data

cannot be read correctly.

Also, the processing above must be performed within the STOP interval of 976 µsec (256 Hz 1/4

cycle).

(3) Read-out of the interrupt factor flag (SWIT) must be done only in the DI status (interrupt flag = "0").

Read-out during EI status (interrupt flag = "1") will cause malfunction.

S1C60N08 TECHNICAL HARDWARE EPSON I-57

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator)

4.11 Sound Generator

4.11.1 Configuration of sound generator

The S1C60N08 Series outputs buzzer signals (BZ, BZ) to drive the piezoelectric buzzer.

The frequency of the buzzer signal is software-selectable from eight kinds of demultiplied fOSC1. Further,

a digital envelope can be added to the buzzer signal through duty ratio control.

Figure 4.11.1.1 shows the sound generator configuration. Figure 4.11.1.2 shows the sound generator

timing chart.

256 Hz

fOSC1

[ENVRST] [ENVRT]

[BZFQ0–BZFQ2]

[ENVON]

R10 (BZ)

R13 (BZ)

[R10]

[R13]

Output port

Envelope

addition circuit

Programmable

dividing circuit

Envelope generation

circuit

[ ] : Register

Fig. 4.11.1.1 Configuration of sound generator

BZFQ0–2

ENVON

ENVRT

R10(register)

R13(register)

BZ(R10 terminal)

BZ(R13 terminal

Fig. 4.11.1.2 Timing chart of sound generator

I-58 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator)

4.11.2 Frequency setting

The frequencies of the buzzer signals (BZ, BZ) are set by writing data to registers BZFQ0–BZFQ2.

Table 4.11.2.1 lists the register setting values and the frequencies that can be set.

Table 4.11.2.1 Setting of frequencies of buzzer signals

BZFQ Buzzer frequency (Hz)

Demultiplier ratio

fOSC1/8

fOSC1/10

fOSC1/12

fOSC1/14

fOSC1/16

fOSC1/20

fOSC1/24

fOSC1/28

When fOSC1 = 32 kHz

4,096.0

3,276.8

2,730.7

2,340.6

2,048.0

1,638.4

1,365.3

1,170.3

When fOSC1 = 38.4 kHz

4,800.0

3,840.0

3,200.0

2,742.9

2,400.0

1,920.0

1,600.0

1,371.4

Note: A hazard may be observed in the output waveform of the BZ and BZ signals when data of the

buzzer frequency selection registers (BZFQ0–BZFQ2) changes.

4.11.3 Digital envelope

A duty ratio control data envelope (with duty ratio change in eight stages) can be added to the buzzer

signal (BZ, BZ).

The duty ratio is the ratio of the pulse width compared with the pulse cycle. The BZ output is TH/

(TH+TL) when the high level output is TH and the low level output is TL. The BZ output (BZ inverted

output) is TL/ (TH+TL). Also, care must be taken because the duty ratio differs depending on the buzzer

frequency.

The envelope is added by writing "1" to register ENVON. If "0" is written the duty ratio is fixed to the

maximum. Also, if the envelope is added, the duty ratio is reverted to the maximum by writing "1" in

The decay time of the envelope (time for the duty ratio to change) can be selected with the register

ENVRT. This time is 62.5 msec (16 Hz) when "0" is written, and 125 msec (8 Hz) when "1" is written.

However, a maximum difference of 4 msec is taken from envelope-ON until the first change.

Table 4.11.3.1 lists the duty rates and buzzer frequencies. Figure 4.11.3.1 shows the digital envelope

timing chart.

Table 4.11.3.1 Duty rates and buzzer frequencies

Level 1 (max.)

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

Level 8 (min.)

8/16

7/16

6/16

5/16

4/16

3/16

2/16

1/16

BZFQ

(register)

Duty rate

08/20

7/20

6/20

5/20

4/20

3/20

2/20

1/20

112/24

11/24

10/24

9/24

8/24

7/24

6/24

5/24

012/28

11/28

10/28

9/28

8/28

7/28

6/28

5/28

S1C60N08 TECHNICAL HARDWARE EPSON I-59

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator)

BZFQ0–2

ENON

ENVRST

ENVRT

R10 (register)

Level 1 (MAX)

8 (MIN)

BZ signal

duty ratio

No change of duty level

02–07

= 62.5 msec

–4

12–17

= 125 msec

–4

Fig. 4.11.3.1 Digital envelope timing chart

4.11.4 Mask option

(1) Selection can be made whether to output the BZ signal from the R10 terminal.

(2) Selection can be made whether to output the BZ signal from the R13 terminal. However, if the BZ

signal is not output the BZ signal cannot be output.

(3) Selection can be made to perform the BZ signal output control through the R10 register or the R13

See Section 4.5, "Output Ports" for details of the above mask option.

I-60 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator)

4.11.5 Control of sound generator

Table 4.11.5.1 lists the sound generator's control bits and their addresses.

Table 4.11.5.1 Control bits of sound generator

Address Comment

D3 D2

D1 D0 Name Init

∗1

∗5 Undefined∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

2F6H

BZFQ2 BZFQ1 BZFQ0 ENVRST

R/W W

BZFQ2

BZFQ1

BZFQ0

ENVRST

∗

Reset Reset –

Buzzer

frequency

selection

Envelope reset

2F7H

ENVON ENVRT AMPDT AMPON

RR/WR/W

ENVON

ENVRT

AMPDT

AMPON

1.0 sec

+ > -

Off

0.5 sec

+ < -

Off

Envelope On/Off

Envelope cycle selection register

Analog comparator data

Analog comparator On/Off

OSC1

/8 1

OSC1

/10 2

OSC1

/12 3

OSC1

/14

[BZFQ2–0]

Frequency

OSC1

/16 5

OSC1

/20 6

OSC1

/24 7

OSC1

/28

[BZFQ2–0]

Frequency

2ECH

R13 R12 R11

SIOF R10

R/W

RR/WR/W

R13

R12

R11

SIOF

R10

High/On

High

Run

High/On

Low/Off

Low

Stop

Low/On

Output port (R13)/BZ output control

Output port (R12)/FOUT output control

Output port (R11, LAMP)

Output port (SIOF)

Output port (R10)/BZ output control

BZFQ0–BZFQ2: Buzzer frequency selection register (2F6H•D1–D3)

This is used to select the frequency of the buzzer signal.

Table 4.11.5.2 Buzzer frequency

BZFQ2

Buzzer frequency (Hz)

OSC1

/10

OSC1

/12

OSC1

/14

OSC1

/16

OSC1

/20

OSC1

/24

OSC1

/28

BZFQ1

BZFQ0

Buzzer frequency is selected from the above eight types that have been divided by fOSC1 (oscillation

frequency of the OSC1 oscillation circuit).

At initial reset, fOSC1/8 (Hz) is selected.

ENVRST: Envelope reset (2F6H•D0)

This is the reset input to make the duty ratio of the buzzer signal the maximum.

When "1" is written : Reset input

When "0" is written : No operation

Read-out : Always "0"

When the envelope is added to the buzzer signal, the duty ratio is made maximum through this reset

input. When the envelope is not added or when the buzzer signal is not output, the reset input is invalid.

ENVON: Envelope ON/OFF (2F7H•D3)

This controls adding the envelope to the buzzer signal.

When "1" is written : Envelope added (ON)

When "0" is written : No envelope (OFF)

Read-out : Valid

The envelope is the digital envelope based on duty ratio control. When there is no envelope, the duty

ratio is fixed to the maximum.

At initial reset, no envelope (OFF) is selected.

S1C60N08 TECHNICAL HARDWARE EPSON I-61

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator)

ENVRT: Envelope decay time (2F7H•D2)

This input selects the decay time of the envelope added to the buzzer signal.

When "1" is written : 1.0 sec (125 msec × 7 = 875 msec)

When "0" is written : 0.5 sec (62.5 msec × 7 = 437.5 msec)

Read-out : Valid

The decay time of the digital envelope is decided by the time taken for the duty ratio to change. When "1"

is written to ENVRT the time is 125 msec (8 Hz) units, and when "0" is written it is 62.5 msec (16 Hz)

units.

At initial reset, 0.5 sec (437.5 msec) is selected.

R10, R13 (at BZ, BZ output selection): Special output port data (2ECH•D0, D3)

These control output of the buzzer signals (BZ, BZ).

When "1" is written : Buzzer signal output

When "0" is written : Low level (DC) output

Read-out : Valid

• BZ output under R13 control

BZ output and BZ output can be controlled independently. BZ output is controlled by writing data to

• BZ output under R10 control

By writing data to register R10 only, BZ output and BZ output can be controlled simultaneously. In

this case, register R13 can be used as a read/write one-bit general register. This register does not affect

BZ output (output to pin R13).

At initial reset, R10 and R13 are set to "0".

4.11.6 Programming note

A hazard may be observed in the output waveform of the BZ and BZ signals when data of the output

registers (R10, R13) and the buzzer frequency selection registers (BZFQ0–BZFQ2) changes.

I-62 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)

4.12 Event Counter

4.12.1 Configuration of event counter

The S1C60N08 Series has an event counter that counts the clock signals input from outside.

The event counter is configured of a pair of eight-bit binary counters (UP counters). The clock pulses are

input through terminals K02 and K03 of the input port.

The clock signals input from the terminals are input to the event counter via the noise rejector.

The event counter detects the phases of the two clock signals. Software selection provides for two modes,

the phase detection mode in which one of the counters can be chosen to input the clock signal, and the

separate mode in which each clock signal is input to different counters.

Figure 4.12.1.1 shows the configuration of the event counter.

Phase

detection

circuit

Input port

Noise rejector

[EVSEL]

[EVRUN]

K02

K03 Interrupt request

[EV0RST]

[EV1RST]

Event counter 0

[EV00–EV07]

Event counter 1

[EV10–EV17]

[ ] : Register

Noise rejector

Fig. 4.12.1.1 Configuration of event counter

4.12.2 Switching count mode

The event counter detects the phases of the two clock signals. Software selection provides for two modes,

the phase detection mode in which one of the counters can be chosen to input the clock signal, and the

separate mode in which each clock signal is input to different counters.

Selection can be made by writing data to the EVSEL register. When "0" is written the phase detection

mode is enabled, and when "1" is written the separate mode is enabled.

In the phase detection mode, the clock signals having different phases must be input simultaneously to

terminals K02 and K03. When the input from terminal K02 is fast the clock signal is input to event

counter 1, and when the input from terminal K03 is fast the clock signal is input to event counter 0.

In the separate mode, input from terminal K02 is made to event counter 0, and input from terminal K03 is

made to event counter 1.

Figure 4.12.2.1 is the timing chart for the event counter.

S1C60N08 TECHNICAL HARDWARE EPSON I-63

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)

OFF

RUN

STOP

Terminal

K02 input

Terminal

K03 input

EVRUN

When EVSEL="0" (phase detection mode)

Input to event

counter 0

Input to event

counter 1

When EVSEL="1" (separate mode)

Input to event

counter 0

Input to event

counter 1

Defined time

≥ 1.5 Tch

OFF

≥ 1.5 Tch

< 0.5 Tch

Tch = 1/fch: fch, the clock frequency

for thenoise rejector, can be selected

as f

OSC1

/16 or f

OSC1

/128 with the

mask option

Noise

≥ 1.5 Tch

Fig. 4.12.2.1 Event counter timing chart

4.12.3 Mask option

The clock frequency of the noise rejector can be selected as fOSC1/16 or fOSC1/128.

Table 4.12.3.1 lists the defined time depending on the frequency selected.

Table 4.12.3.1 Defined time depending on frequency selected

Selection

OFF

OSC1

= 32.768 kHz

OSC1

/16

0.24

0.74

OSC1

/128

1.95

5.86

OSC1

= 38.400 kHz

OSC1

/16

0.20

0.63

OSC1

/128

1.66

5.00

(Unit: msec)

: Max value

Others : Min value

I-64 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)

4.12.4 Control of event counter

Table 4.12.4.1 shows the event counter control bits and their addresses.

Table 4.12.4.1 Control bits of event counter

Address Comment

D3 D2

D1 D0 Name Init

∗1

∗5 Undefined∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

2F8H

EV03 EV02 EV01 EV00

EV03

EV02

EV01

EV00

Event counter 0 (low-order 4 bits)

2F9H

EV07 EV06 EV05 EV04

EV07

EV06

EV05

EV04

Event counter 0 (high-order 4 bits)

2FAH

EV13 EV12 EV11 EV10

EV13

EV12

EV11

EV10

Event counter 1 (low-order 4 bits)

2FCH

EVSEL ENRUN EV1RST EV0RST

R/W W

EVSEL

EVRUN

EV1RST

∗

EV0RST

∗

Reset

Separate

Run

Reset

Phase

Stop

–

Event counter mode selection

Event counter Run/Stop

Event counter 1 reset

Event counter 0 reset

2FBH

EV17 EV16 EV15 EV14

EV17

EV16

EV15

EV14

Event counter 1 (high-order 4 bits)

EV00–EV03: Event counter 0 low-order data (2F8H)

The four low-order data bits of event counter 0 are read out.

These four bits are read-only, and cannot be used for writing.

At initial reset, event counter 0 is set to "00H".

EV04–EV07: Event counter 0 high-order data (2F9H)

The four high-order data bits of event counter 0 are read out.

These four bits are read-only, and cannot be used for writing.

At initial reset, event counter 0 is set to "00H".

EV10–EV13: Event counter 1 low-order data (2FAH)

The four low-order data bits of event counter 1 are read out.

These four bits are read-only, and cannot be used for writing.

At initial reset, event counter 1 is set to "00H".

EV14–EV17: Event counter 1 high-order data (2FBH)

The four high-order data bits of event counter 1 are read out.

These four bits are read-only, and cannot be used for writing.

At initial reset, event counter 1 is set to "00H".

EV0RST: Event counter 0 reset (2FCH•D0)

This is the register for resetting event counter 0.

When "1" is written : Event counter 0 reset

When "0" is written : No operation

Read-out : Always "0"

When "1" is written, event counter 0 is reset and the data becomes "00H". When "0" is written, no opera-

tion is executed.

This is a write-only bit, and is always "0" at read-out.

S1C60N08 TECHNICAL HARDWARE EPSON I-65

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter)

EV1RST: Event counter 1 reset (2FCH•D1)

This is the register for resetting event counter 1.

When "1" is written : Event counter 1 reset

When "0" is written : No operation

Read-out : Always "0"

When "1" is written, event counter 1 is reset and the data becomes "00H". When "0" is written, no opera-

tion is executed.

This is a write-only bit, and is always "0" at read-out.

EVRUN: Event counter RUN/STOP (2FCH•D2)

This register controls the event counter RUN/STOP status.

When "1" is written : RUN

When "0" is written : STOP

Read-out : Valid

When "1" is written, the event counter enters the RUN status and starts receiving the clock signal input.

When "0" is written, the event counter enters the STOP status and the clock signal input is ignored.

(However, input to the input port is valid.)

At initial reset, this register is set to "0".

EVSEL: Event counter mode (2FCH•D3)

This register control the count mode of the event counter.

When "1" is written : Separate

When "0" is written : Phase detection

Read-out : Valid

When "0" is written, the phases of the two clock signals are detected, and the phase detection mode is

selected, in which one of the counters is chosen to input the clock signal. When "1" is written, the separate

mode is selected, in which each clock signal is input to different counters.

At initial reset, this register is set to "0".

4.12.5 Programming notes

(1) After the event counter has written data to the EVRUN register, it operates or stops in synchroniza-

tion with the falling edge of the noise rejector clock or stops. Hence, attention must be paid to the

above timing when input signals (input to K02 and K03) are being received.

(2) To prevent erroneous reading of the event counter data, read out the counter data several times,

compare it, and use the matching data as the result.

I-66 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator)

4.13 Analog Comparator

4.13.1 Configuration of analog comparator

The S1C60N08 Series incorporates an MOS input analog comparator. This analog comparator, which has

two differential input terminals (inverted input terminal AMPM, non-inverted input terminal AMPP),

can be used for general purposes.

Figure 4.13.1.1 shows the configuration of the analog comparator.

Address

AMPON Power source

control

Input control

Data bus

AMPP

AMPM

–

VDD

AMPDT

VSS

Fig. 4.13.1.1 Configuration of analog comparator

4.13.2 Operation of analog comparator

The analog comparator is ON when the AMPON register is "1", and compares the input levels of the

AMPP and AMPM terminals. The result of the comparison is read from the AMPDT register. It is "1"

when AMPP (+) > AMPM (-) and "0" when AMPP (+) < AMPM (-).

After the analog comparator goes ON it takes a maximum of 3 msec until the output stabilizes.

S1C60N08 TECHNICAL HARDWARE EPSON I-67

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator)

4.13.3 Control of analog comparator

Table 4.13.3.1 lists the analog comparator control bits and their addresses.

Table 4.13.3.1 Control bits of analog comparator

Address Comment

D3 D2

D1 D0 Name Init ∗110

∗5 Undefined∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read

2F7H

ENVON ENVRT AMPDT AMPON

RR/WR/W

ENVON

ENVRT

AMPDT

AMPON

1.0 sec

+ > -

Off

0.5 sec

+ < -

Off

Envelope On/Off

Envelope cycle selection register

Analog comparator data

Analog comparator On/Off

AMPON: Analog comparator ON/OFF (2F7H•D0)

Switches the analog comparator ON and OFF.

When "1" is written : The analog comparator goes ON

When "0" is written : The analog comparator goes OFF

Read-out : Valid

The analog comparator goes ON when "1" is written to AMPON, and OFF when "0" is written.

At initial reset, AMPON is set to "0".

AMPDT: Analog comparator data (2F7H•D1)

Reads out the output from the analog comparator.

When "1" is read out : AMPP (+) > AMPM (-)

When "0" is read out : AMPP (+) < AMPM (-)

Writing : Invalid

AMPDT is "0" when the input level of the inverted input terminal (AMPM) is greater than the input level

of the noninverted input terminal (AMPP); and "1" when smaller.

At initial reset, AMPDT is set to "1".

4.13.4 Programming notes

(1) To reduce current consumption, set the analog comparator to OFF when it is not necessary.

(2) After setting AMPON to "1", wait at least 3 msec for the operation of the analog comparator to

stabilize before reading the output data of the analog comparator from AMPDT.

I-68 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit)

4.14 Battery Life Detection (BLD) Circuit

4.14.1 Configuration of BLD circuit

The S1C60N08 Series has a built-in battery life detection (BLD) circuit, so that the software can find when

the source voltage lowers. The configuration of the BLD circuit is shown in Figure 4.14.1.1.

Also provides a heavy load protection function and an associated sub-BLD circuit. See Section 4.15,

"Heavy Load Protection Function and Sub-BLD Circuit".

Turning the BLD operation ON/OFF is controlled through the software (HLMOD, BLS). Moreover, when

a drop in source voltage (BLD0 = "1") is detected by the sub-BLD circuit, BLD operation is periodically

performed by the hardware until the source voltage is recovered (BLD0 = "0").

Because the power current consumption of the IC increases when the BLD operation is turned ON, set the

BLD operation to OFF unless otherwise necessary.

BLC2

BLC1

BLC0

BLD circuit

Evaluation

voltage

setting circuit

Detection output

Address 2E6H

Address 2FFH

BLS BLD1

HLMOD

Data bus

BLD

sampling

control

VDD

Fig. 4.14.1.1 Configuration of BLD circuit

4.14.2 Programmable selection of evaluation voltage

In the S1C60N08 Series, the evaluation voltage for judging the battery life can be switched by program-

ming. Consequently, the optimum evaluation voltage can be set for the battery used.

One of eight evaluation voltages can be selected with the software. Table 4.14.2.1 lists the evaluation

voltages for the models in the S1C60N08 Series.

Table 4.14.2.1 Evaluation voltages for BLD circuit

S1C60N08

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

BLC2

S1C60L08

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

BLC1

BLC0

S1C60A08

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

See the electrical characteristics for the evaluation voltage accuracy.

S1C60N08 TECHNICAL HARDWARE EPSON I-69

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit)

4.14.3 Detection timing of BLD circuit

This section explains the timing for when the BLD circuit writes the result of the source voltage detection

to the BLD latch.

Turning the BLD operation ON/OFF is controlled through the software (HLMOD, BLS). Moreover, when

a drop in source voltage (BLD0 = "1") is detected by the sub-BLD circuit, BLD operation is periodically

performed by the hardware until the source voltage is recovered (BLD0 = "0").

The result of the source voltage detection is written to the BLD latch by the BLD circuit, and this data can

be read out by the software to find the status of the source voltage.

There are three status, explained below, for the detection timing of the BLD circuit.

(1)Sampling with HLMOD set to "1"

When HLMOD is set to "1" and BLD sampling executed, the detection results can be written to the

BLD latch in the following two timings.

➀Immediately after the time for one instruction cycle has ended immediately after HLMOD = "1"

➁Immediately after sampling in the 2 Hz cycle output by the clock timer while HLMOD = "1"

Consequently, the BLD latch data is loaded immediately after HLMOD has been set to "1", and at the

same time the new detection result is written in 2 Hz cycles.

To obtain a stable BLD detection result, the BLD circuit must be set to ON with at least 100 µsec.

When the CPU system clock is fOSC3 in the S1C60A08, the detection result at the timing in ➀ above

may be invalid or incorrect. (When performing BLD detection using the timing in ➀, be sure that the

CPU system clock is fOSC1.)

(2)Sampling with BLS set to "1"

When BLS is set to "1", BLD detection is executed. As soon as BLS is reset to "0" the detection result is

loaded to the BLD latch. To obtain a stable BLD detection result, the BLD circuit must be set to ON

with at least 100 µsec. Hence, to obtain the BLD detection result, follow the programming sequence

below.

0. Set HLMOD to "1" (only when the CPU system clock is fOSC3 in the S1C60A08)

1. Set BLS to "1"

2. Maintain at 100 µsec minimum

3. Set BLS to "0"

4. Read out BLD

5. Set HLMOD to "0" (only when the CPU system clock is fOSC3 in the S1C60A08)

However, when a crystal oscillation clock (fOSC1) is selected for the CPU system clock in the

S1C60N08, S1C60L08, and S1C60A08, the instruction cycles are long enough, so that there is no need

for concern about maintaining 100 µsec for the BLS = "1" with the software.

(3)Sampling by hardware when sub-BLD latch is set to "1"

When BLD0 (sub-BLD latch) is set to "1", the detection results can be written to the BLD0 (sub-BLD

latch) and BLD1 (BLD latch) in the following two timings (same as that sampling with HLMOD set to

"1").

➀Immediately after the time for one instruction cycle has ended immediately after BLD0 = "1"

➁Immediately after sampling in the 2 Hz cycle output by the clock timer while BLD0 = "1"

Consequently, the BLD0 (sub-BLD latch) and BLD1 (BLD latch) data are loaded immediately after

BLD0 (sub-BLD latch) has been set to "1", and at the same time the new detection result is written in 2

Hz cycles.

To obtain a stable BLD detection result, the BLD circuit must be set to ON with at least 100 µsec.

When the CPU system clock is fOSC3 in the S1C60A08, the detection result at the timing in ➀ above

may be invalid or incorrect.

I-70 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit)

4.14.4 Control of BLD circuit

Table 4.14.4.1 shows the BLD circuit's control bits and their addresses.

Table 4.14.4.1 Control bits of BLD circuit

Address Comment

D3 D2

D1 D0 Name Init ∗110

2E6H

HLMOD BLD0 EISWIT1 EISWIT0

R/W R R/W

HLMOD

BLD0

EISWIT1

EISWIT0

Heavy load

Low

Enable

Normal

Mask

Heavy load protection mode register

Sub-BLD evaluation data

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read ∗5 Undefined

2FFH

BLS

BLD1 BLC2 BLC1 BLC0

RR/W

BLS

BLD1

BLC2

BLC1

BLC0

∗

Low Off

Normal

BLD On/Off

BLD evaluation data

Evaluation voltage setting register

2.20

1.05

2.25

1.10

2.30

1.15

2.35

1.20

2.40

1.25

2.45

1.30

2.50

1.35

2.55

1.40 (V)

(V)

[BLC2–0]

S1C60N08/60A08

S1C60L08

HLMOD: Heavy load protection mode (2E6H•D3)

Sets the IC in heavy load protection mode.

When "1" is written : Heavy load protection mode is set

When "0" is written : Heavy load protection mode is released

Read-out : Valid

When HLMOD is set to "1", the IC operating status enters the heavy load protection mode and at the

same time the battery life detection of the BLD circuit is controlled (ON/OFF).

For details about the heavy load protection mode, see Section 4.15, "Heavy Load Protection Function and

Sub-BLD Circuit".

When HLMOD is set to "1", sampling control is executed for the BLD circuit ON time. There are two

types of sampling time, as follows:

(1) The time of one instruction cycle immediately after HLMOD = "1"

(2) Sampling at cycles of 2 Hz output by the clock timer while HLMOD = "1"

The BLD circuit must be made ON with at least 100 µsec for the BLD circuit to respond. Hence, when the

CPU system clock is fOSC3 in the S1C60A08, the detection result at the timing in (1) above may be invalid

or incorrect. When performing BLD detection using the timing in (1), be sure that the CPU system clock is

fOSC1.

When BLD sampling is done with HLMOD set to "1", the results are written to the BLD latch in the

timing as follows:

(1) As soon as the time has elapsed for one instruction cycle immediately following HLMOD = "1"

(2)

Immediately on completion of sampling at cycles of 2 Hz output by the clock timer while HLMOD = "1"

Consequently, the BLD latch data is written immediately after HLMOD is set to "1", and at the same time

the new detection result is written in 2 Hz cycles.

S1C60N08 TECHNICAL HARDWARE EPSON I-71

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit)

BLS/BLD1: BLD detection/BLD data (2FFH•D3)

Controls the BLD operation.

When "0" is written : BLD detection OFF

When "1" is written : BLD detection ON

When "0" is read out : Source voltage (VDD–VSS) is higher than BLD set value

When "1" is read out : Source voltage (VDD–VSS) is lower than BLD set value

Note that the function of this bit when written is different to when read out.

When this bit is written to, ON/OFF of the BLD detection operation is controlled; when this bit is read

out, the result of the BLD detection (contents of BLD latch) is obtained. Appreciable current is consumed

during operation of BLD detection, so keep BLD detection OFF except when necessary.

When BLS is set to "1", BLD detection is executed. As soon as BLS is reset to "0" the detection result is

loaded to the BLD latch. To obtain a stable BLD detection result, the BLD circuit must be set to ON with at

least 100 µsec. Hence, to obtain the BLD detection result, follow the programming sequence below.

0. Set HLMOD to "1" (only when the CPU system clock is fOSC3 in the S1C60A08)

1. Set BLS to "1"

2. Maintain at 100 µsec minimum

3. Set BLS to "0"

4. Read out BLD

5. Set HLMOD to "0" (only when the CPU system clock is fOSC3 in the S1C60A08)

However, when a crystal oscillation clock (fOSC1) is selected for the CPU system clock in the S1C60N08,

S1C60L08, and S1C60A08, the instruction cycles are long enough, so that there is no need for concern

about maintaining 100 µsec for the BLS = "1" with the software.

4.14.5 Programming notes

(1) It takes 100 µsec from the time the BLD circuit goes ON until a stable result is obtained. For this

reason, keep the following software notes in mind:

When the CPU system clock is fOSC1

1. When detection is done at HLMOD

After writing "1" on HLMOD, read the BLD after 1 instruction has passed.

2. When detection is done at BLS

After writing "1" on BLS, write "0" after at least 100 µsec has lapsed (possible with the next instruc-

tion) and then read the BLD.

When the CPU system clock is fOSC3 (in case of S1C60A08 only)

1. When detection is done at HLMOD

After writing "1" on HLMOD, read the BLD after 0.6 second has passed. (HLMOD holds "1" for at

least 0.6 second)

2. When detection is done at BLS

Before writing "1" on BLS, write "1" on HLMOD first; after at least 100 µsec has lapsed after

writing "1" on BLS, write "0" on BLS and then read the BLD.

(2) BLS resides in the same bit at the same address as BLD1, and one or the other is selected by write or

read operation. This means that arithmetic operations (AND, OR, ADD, SUB and so forth) cannot be

used for BLS control.

I-72 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function and Sub-BLD Circuit)

4.15 Heavy Load Protection Function and Sub-BLD Circuit

This section explains the heavy load protection and sub-BLD circuit.

4.15.1 Heavy load protection function

Note that the heavy load protection function on the S1C60L08 is different from the S1C60N08/60A08.

(1)In case of S1C60L08

The S1C60L08 has the heavy load protection function for when the battery load becomes heavy and

the source voltage drops, such as when an external buzzer sounds or an external lamp lights. The

state where the heavy load protection function is in effect is called the heavy load protection mode. In

this mode, operation with a lower voltage than normal is possible.

The normal mode changes to the heavy load protection mode in the following two cases:

➀When the software changes the mode to the heavy load protection mode (HLMOD = "1")

➁When source voltage drop (BLD0 = "1") in the sub-BLD circuit is detected, the mode will automati-

cally shift to the heavy load protection mode until the source voltage is recovered (BLD0 = "0")

The sub-BLD circuit, a BLD circuit dedicated to 2.4 V/1.2 V detection, operates in synchronize with

the BLD circuit. It is the S1C60L08's battery life detection circuit controlling the heavy load protection

function so that operation is assured even when the source voltage drops.

Based on the workings of the sub-BLD circuit and the heavy load protection function, the S1C60L08

realizes operation at 0.9 V source voltage. See the electrical characteristics for the precisions of voltage

detection by this sub-BLD circuit.

Figure 4.15.1.1 shows the configuration of the heavy load protection function and the sub-BLD circuit.

Vss

HLMOD

BLD0

Vss

BLS BLD1

Sub-BLD circuit Voltage regulator

Data bus

Address 2E6H

Sub-BLD

sampling control

Fig. 4.15.1.1 Configuration of sub-BLD circuit

In the heavy load protection mode, the internally regulated voltage is generated by the liquid crystal

driver source output VL2 so as to operate the internal circuit. Consequently, more current is consumed

in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to

set the heavy load protection mode with the software.

S1C60N08 TECHNICAL HARDWARE EPSON I-73

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function and Sub-BLD Circuit)

(2)In case of S1C60N08/60A08

The S1C60N08/60A08 has the heavy load protection function for when the battery load becomes

heavy and the source voltage changes, such as when an external buzzer sounds or an external lamp

lights. The state where the heavy load protection function is in effect is called the heavy load protec-

tion mode. Compared with the normal operation mode, this mode can reduce the output voltage

variation of the constant voltage/booster voltage circuit of the LCD system.

The normal mode changes to the heavy load protection mode in the following case:

• When the software changes the mode to the heavy load protection mode (HLMOD = "1")

The heavy load protection mode switches the constant voltage circuit of the LCD system to the high-

stability mode from the low current consumption mode. Consequently, more current is consumed in

the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set

the heavy load protection mode with the software.

4.15.2 Operation of sub-BLD circuit

Software control of the sub-BLD circuit is virtually the same as for the BLD circuit, except that the

evaluation voltage cannot be set by programming.

Just as for the BLD circuit, HLMOD or BLS control the detection timing of the sub-BLD circuit and the

timing for writing the detection data to the sub-BLD latch. However, for the S1C60L08, even if the sub-

BLD circuit detects a drop in source voltage (1.2 V or below) and invokes the heavy load protection mode,

this will be the same as when the software invokes the heavy load protection mode, in that the BLD

circuit and sub-BLD circuit will be sampled in timing synchronized to the 2 Hz output from the prescaler.

If the sub-BLD circuit detects a voltage drop and enters the heavy load protection mode, it will return to

the normal mode once the source voltage recovers and the BLD circuit judges that the source voltage is

1.2 V or more.

For the S1C60N08/60A08, when the sub-BLD circuit detects a drop in source voltage (2.4 V or below) and

the detection data is written to the sub-BLD latch, the BLD circuit and sub-BLD circuit will be sampled in

timing synchronized to the 2 Hz output from the prescaler. Once the source voltage recovers and the BLD

circuit judges that the source voltage is 2.4 V or more, the BLD circuit and sub-BLD circuit won't be

sampled in timing synchronized to the 2 Hz output from the prescaler.

I-74 EPSON S1C60N08 TECHNICAL HARDWARE

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function and Sub-BLD Circuit)

4.15.3 Control of heavy load protection function and sub-BLD circuit

Table 4.15.3.1 shows the control bits and their addresses for the heavy load protection function and sub-

BLD circuit.

Table 4.15.3.1 Control bits of heavy load protection function and sub-BLD circuit

Address Comment

D3 D2

D1 D0 Name Init ∗110

2E6H

HLMOD BLD0 EISWIT1 EISWIT0

R/W R R/W

HLMOD

BLD0

EISWIT1

EISWIT0

Heavy load

Low

Enable

Normal

Mask

Heavy load protection mode register

Sub-BLD evaluation data

Interrupt mask register (stopwatch 1 Hz)

Interrupt mask register (stopwatch 10 Hz)

∗1

∗2Initial value at initial reset

Not set in the circuit ∗3

∗4Always "0" being read

Reset (0) immediately after being read ∗5 Undefined

2FFH

BLS

BLD1 BLC2 BLC1 BLC0

RR/W

BLS

BLD1

BLC2

BLC1

BLC0

∗

Low Off

Normal

BLD On/Off

BLD evaluation data

Evaluation voltage setting register

2.20

1.05

2.25

1.10

2.30

1.15

2.35

1.20

2.40

1.25

2.45

1.30

2.50

1.35

2.55

1.40 (V)

(V)

[BLC2–0]

S1C60N08/60A08

S1C60L08

HLMOD: Heavy load protection mode (2E6H•D3)

Sets the IC in heavy load protection mode.

When "1" is written : Heavy load protection mode is set

When "0" is written : Heavy load protection mode is released

Read-out : Valid

When HLMOD is set to "1", the IC operating status enters the heavy load protection mode and at the

same time the battery life detection of the BLD circuit is controlled (ON/OFF).

When HLMOD is set to "1", sampling control is executed for the BLD circuit ON time. There are two

types of sampling time, as follows:

(1) The time of one instruction cycle immediately after HLMOD = "1"

(2) Sampling at cycles of 2 Hz output by the clock timer while HLMOD = "1"

The BLD circuit must be made ON with at least 100 µsec for the BLD circuit to respond. Hence, when the

CPU system clock is fOSC3 in the S1C60A08, the detection result at the timing in (1) above may be invalid

or incorrect. When performing BLD detection using the timing in (1), be sure that the CPU system clock is

fOSC1.

When BLD sampling is done with HLMOD set to "1", the results are written to the BLD latch in the

timing as follows:

(1) As soon as the time has elapsed for one instruction cycle immediately following HLMOD = "1"

(2)

Immediately on completion of sampling at cycles of 2 Hz output by the clock timer while HLMOD = "1"

Consequently, the BLD latch data is written immediately after HLMOD is set to "1", and at the same time

the new detection result is written in 2 Hz cycles.

BLD0: Sub-BLD data (2E6H·D2)

The voltage detection data in the heavy load protection mode is read out.

When "0" is read out : High source voltage upward from about

2.4 V (S1C60N08/60A08)/1.2 V (S1C60L08)

When "1" is read out : Low source voltage from about

2.4 V (S1C60N08/60A08)/1.2 V (S1C60L08) or under

Writing : Invalid

When BLD0 is "1" the CPU enters the heavy load protection mode. In the heavy load protection mode, the

detection operation of the BLD circuit and sub-BLD circuit is sampled in 2 Hz cycles, and the respective

detection results are written to the BLD latch and sub-BLD latch.

S1C60N08 TECHNICAL HARDWARE EPSON I-75