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EP5358xUI 600mA PowerSoC
Step-Down DC-DC Switching Converter with Integrated Inductor
DESCRIPTION
The EP5358xUI (x = L or H) is rated for up to 600mA
of continuous output current. The EP5358xUI
integrates MOSFET switches, control, compensation,
and the magnetics in an advanced 2.5mm x 2.25mm
micro-QFN Package.
Integrated magnetics enables a tiny solution
footprint, low output ripple, low part-count, and high
reliability, while maintaining high efficiency. The
complete solution can be implemented in as little as
14mm2.
The EP5358xUI uses a 3-pin VID to easily select the
output voltage setting. Output voltage settings are
available in 2 optimized ranges providing coverage
for typical VOUT settings.
The VID pins can be changed on the fly for fast
dynamic voltage scaling. EP5358LUI further has the
option to use an external voltage divider.
The EP5358xUI is a perfect solution for noise
sensitive and space constrained applications that
require high efficiency.
FEATURES
• Integrated Inductor Technology
• -40°C to +85°C Ambient Temperature Range
• 2.5mm x 2.25mm x 1.1mm uQFN Package
• Total Solution Footprint 14mm2
• Low VOUT Ripple for RF Compatibility
• High Efficiency, Up to 93%
• Up to 600mA Continuous Output Current
• 5 MHz Switching Frequency
• 3 pin VID for Glitch Free Voltage Scaling
• VOUT Range 0.6V to VIN – 0.25V
• Short Circuit and Over Current Protection
• UVLO and Thermal Protection
• IC Level Reliability in a PowerSOC Solution
APPLICATIONS
• Wireless and RF Applications
• Wireless Broad Band Data Cards
• Small Form Factor Optical Modules
• Low Noise FPGA IO and Transceivers
• Advanced Low Power Processors, DSP, IO,
Memory, Video, Multimedia Engines
Figure 1: Simplified Applications Circuit
Figure 2: Highest Efficiency in Smallest Solution Size
VOUT
VIN
10µF
0805
X7R
4.7µF
0603
X7R
VOUTPVIN
AVIN
PGND AGND
VSENSE
EP5358xUI
VFB
VS0
VS1
VS2
ENABLE
Do not float
35
40
45
50
55
60
65
70
75
80
85
90
95
0100 200 300 400 500 600
EFFICIENCY (%)
OUTPUT CURRENT (mA)
Efficiency vs. IOUT (VIN = 5.0V)
VOUT = 3.3V
CONDITIONS
VIN = 5V
14mm2
DataSheeT – enpirion® power solutions
03541 October 13, 2018 Rev K
Datasheet | Intel® Enpirion® Power Solutions: EP5358LUI/HUI
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ORDERING INFORMATION
Package Markings
TJ Rating
Package Description
AKXX
-40 to +125
16-pin (2.5mm x 2.25mm x 1.1mm) uQFN
ANXX
-40 to +125
16-pin (2.5mm x 2.25mm x 1.1mm) uQFN
QFN Evaluation Board
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
PIN FUNCTIONS
Figure 3: EP5358LUI Pin Out Diagram (Top View)
Figure 4. EP5358HUI Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. However,
they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: White ‘dot’ on top left is pin 1 indicator on top of the device package.
NC(SW)
PGND
VFB
VSENSE
AGND
1
2
3
4
5
6
PVIN
AVIN
ENABLE
VS0
VS2
14
13
12
11
10
9
NC(SW)
NC(SW)
16 15
PGND
VOUT
VOUT
VS1
78
NC(SW)
PGND
NC
VSENSE
AGND
1
2
3
4
5
6
PVIN
AVIN
ENABLE
VS0
VS2
14
13
12
11
10
9
NC(SW)
NC(SW)
16 15
PGND
VOUT
VOUT
VS1
78
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Datasheet | Intel® Enpirion® Power Solutions: EP5358LUI/HUI
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PIN DESCRIPTIONS
PIN
NAME
TYPE
FUNCTION
1, 15,
16
NC(SW)
Analog
NO CONNECT – These pins are internally connected to the common
switching node of the internal MOSFETs. NC (SW) pins are not to be
electrically connected to any external signal, ground, or voltage. However,
they must be soldered to the PCB. Failure to follow this guideline may
result in part malfunction or damage to the device.
2,3
PGND
Ground
Power ground. Connect these pins together and to the ground electrode
of the Input and output filter capacitors.
4
VFB/NC
Analog
EP5358LUI: Feedback pin for external divider option.
EP5358HUI: No Connect
5
VSENSE
Ground
Sense pin for preset output voltages. Refer to application section for
proper configuration.
6
AGND
Analog
Analog ground. This is the quiet ground for the internal control circuitry,
and the ground return for external feedback voltage divider.
7, 8
VOUT
Power
Regulated Output Voltage. Refer to application section for proper layout
and decoupling.
9, 10,
11
VS2, VS1,
VS0
Analog
Output voltage select. VS2 = pin 9, VS1 = pin 10, VS0 = pin 11.
EP5358LUI: Selects one of seven preset output voltages or an external
resistor divider.
EP5358HUI: Selects one of eight preset output voltages.
(Refer to section on output voltage select for more details.) Do not float.
12
ENABLE
Analog
Output Enable. Enable = logic high; Disable = logic low
13
AVIN
Power
Input power supply for the controller circuitry.
14
PVIN
Power
Input Voltage for the MOSFET switches.
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ABSOLUTE MAXIMUM RATINGS
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
Absolute Maximum Pin Ratings
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Supply Voltage
VIN
-0.3
6.0
V
Voltages on: ENABLE, VSENSE, VSO – VS2
-0.3
VIN+ 0.3
V
Voltages on: VFB (EP5358LUI)
-0.3
2.7
V
Absolute Maximum Thermal Ratings
PARAMETER
CONDITION
MIN
MAX
UNITS
Maximum Operating Junction
Temperature
TJ-ABS
+150
°C
Storage Temperature Range
TSTG
-65
+150
°C
Reflow Peak Body Temperature
(10 Sec) MSL3 JEDEC J-STD-020A
+260
°C
Absolute Maximum ESD Ratings
PARAMETER
CONDITION
MIN
MAX
UNITS
HBM (Human Body Model)
±2000
V
CDM (Charged Device Model)
±500
V
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Voltage Range
VIN
2.4
5.5
V
Operating Ambient Temperature
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
THERMAL CHARACTERISTICS
PARAMETER
SYMBOL
TYPICAL
UNITS
Thermal Shutdown
TSD
155
°C
Thermal Shutdown Hysteresis
TSDHYS
25
°C
Thermal Resistance: Junction to Ambient (0 LFM) (1)
JA
85
°C/W
(1) Based on a four layer copper board and proper thermal design per JEDEC EIJ/JESD51 standards.
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ELECTRICAL CHARACTERISTICS
NOTE: VIN=3.6V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Input Voltage
Range
VIN
2.4
5.5
V
Under Voltage Lock-out
– VIN Rising
VUVLO_R
1.915
2.0
2.195
V
Under Voltage Lock-out
– VIN Falling
VUVLO_F
1.815
1.9
2.095
V
Drop Out Resistance
RDO
Input to Output Resistance in
100% duty cycle operation.
350
500
mΩ
Output Voltage Range
VOUT
EP5358LUI (VDO = ILOAD X
RDO)
EP5358HUI
0.6
1.8
VIN-VDO
3.3
V
Dynamic Voltage Slew
Rate (VID Change)
VSLEW
EP5358LUI
EP5358HUI
4
8
V/ms
VID Preset VOUT Initial
Accuracy
VOUT
TA = 25C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V
-2
+2
%
Line Regulation
VOUT_LINE
2.4V ≤ VIN ≤ 5.5V; ILOAD = 0A
0.03
%/V
Load Regulation
VOUT_LOAD
0A ≤ ILOAD ≤ 600mA;
VIN = 3.6V
0.48
%/A
Temperature Variation
VOUT_TEMP
L
-40C ≤ TA ≤ +85C
24
ppm/
C
Output Current Range
IOUT
0
600
mA
Shut-down Current
ISD
Enable = Low
0.75
µA
OCP Threshold
ILIM
2.4V ≤ VIN ≤ 5.5V
0.6V ≤ VOUT ≤ 3.3V
1.25
1.4
A
Feedback Pin Voltage
Initial Accuracy
VFB
TA = 25C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V
0.588
0.6
0.612
V
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PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Feedback Pin Input
Current (2)
IFB
<100
nA
VS0-VS2, Pin Logic Low
VVSLO
0.0
0.3
V
VS0-VS2, Pin Logic High
VVSHI
1.4
VIN
V
VS0-VS2, Pin Input
Current (2)
IVSX
<100
nA
Enable Pin Logic Low
VENLO
0.3
V
Enable Pin Logic High
VENHI
1.4
V
Enable Pin Current (2)
IENABLE
<100
nA
Operating Frequency
FOSC
5
MHz
Soft Start Slew Rate
VSS
EP5358LUI (VID MODE)
EP5358HUI (VID MODE)
2.6
5.2
4
8
5.4
10.8
V/ms
VOUT Rise Time
TRISE
EP5358LUI VFB MODE
146
225
304
µs
(2) Parameter guaranteed by design and characterization.
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TYPICAL PERFORMANCE CURVES
35
40
45
50
55
60
65
70
75
80
85
90
95
0100 200 300 400 500 600
EFFICIENCY (%)
OUTPUT CURRENT (mA)
Efficiency vs. IOUT (VIN = 5.0V)
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
VIN = 5V
35
40
45
50
55
60
65
70
75
80
85
90
95
100
0100 200 300 400 500 600
EFFICIENCY (%)
OUTPUT CURRENT (mA)
Efficiency vs. IOUT (VIN = 3.3V)
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.5V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
VIN = 3.3V
CONDITIONS
VIN = 5V
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
0100 200 300 400 500 600
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
VOUT = 1.0V
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
0100 200 300 400 500 600
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
VOUT = 1.2V
1.480
1.485
1.490
1.495
1.500
1.505
1.510
1.515
1.520
0100 200 300 400 500 600
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
VOUT = 1.5V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
0100 200 300 400 500 600
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
VOUT = 1.8V
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TYPICAL PERFORMANCE CURVES (CONTINUED)
2.480
2.485
2.490
2.495
2.500
2.505
2.510
2.515
2.520
0100 200 300 400 500 600
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Output Voltage vs. Output Current
VIN = 5.0V
VIN = 3.3V
CONDITIONS
VOUT = 2.5V
3.280
3.285
3.290
3.295
3.300
3.305
3.310
3.315
3.320
0100 200 300 400 500 600
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
Output Voltage vs. Output Current
VIN = 5.0V
CONDITIONS
VOUT = 3.3V
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
2.5 3 3.5 4 4.5 5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
LOAD = 600mA
LOAD = 0A
CONDITIONS
VOUT_NOM = 1.0V
1.180
1.185
1.190
1.195
1.200
1.205
1.210
1.215
1.220
2.5 3 3.5 4 4.5 5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
LOAD = 600mA
LOAD = 0A
CONDITIONS
VOUT_NOM = 1.2V
1.480
1.485
1.490
1.495
1.500
1.505
1.510
1.515
1.520
2.5 3 3.5 4 4.5 5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
LOAD = 600mA
LOAD = 0A
CONDITIONS
VOUT_NOM = 1.5V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.5 3 3.5 4 4.5 5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
LOAD = 600mA
LOAD = 0A
CONDITIONS
VOUT_NOM = 1.8V
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TYPICAL PERFORMANCE CURVES (CONTINUED)
2.480
2.485
2.490
2.495
2.500
2.505
2.510
2.515
2.520
3 3.5 4 4.5 5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
LOAD = 600mA
LOAD = 0A
CONDITIONS
VOUT_NOM = 2.5V
3.200
3.220
3.240
3.260
3.280
3.300
3.320
3.340
3.360
3.380
3.400
5 5.1 5.2 5.3 5.4 5.5
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Output Voltage vs. Input Voltage
LOAD = 600mA
LOAD = 0A
CONDITIONS
VOUT_NOM = 3.3V
0.980
0.990
1.000
1.010
1.020
1.030
-40 -15 10 35 60 85
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
Output Voltage vs. Temperature
LOAD = 600mA
LOAD = 0A
CONDITIONS
VIN = 3.3V
VOUT_NOM = 1.0V
0.980
0.990
1.000
1.010
1.020
1.030
-40 -15 10 35 60 85
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
Output Voltage vs. Temperature
LOAD = 600mA
LOAD = 0A
CONDITIONS
VIN = 5.0V
VOUT_NOM = 1.0V
1.780
1.790
1.800
1.810
1.820
1.830
1.840
-40 -15 10 35 60 85
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
Output Voltage vs. Temperature
LOAD = 600mA
LOAD = 0A
CONDITIONS
VIN = 3.3V
VOUT_NOM = 1.8V
1.780
1.790
1.800
1.810
1.820
1.830
1.840
-40 -15 10 35 60 85
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
Output Voltage vs. Temperature
LOAD = 600mA
LOAD = 0A
CONDITIONS
VIN = 5.0V
VOUT_NOM = 1.8V
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TYPICAL PERFORMANCE CURVES (CONTINUED)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
55 60 65 70 75 80 85
MAXIMUM OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
No De-rating (VIN = 3.3V)
VOUT = 1.8V
VOUT = 2.5V
CONDITIONS
VIN = 3.3V
TJMAX = 125°C
θJA = 85°C/W
No Air Flow
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
55 60 65 70 75 80 85
MAXIMUM OUTPUT CURRENT (A)
AMBIENT TEMPERATURE (°C)
No De-rating (VIN = 5V)
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
VIN = 5.0V
TJMAX = 125°C
θJA = 85°C/W
No Air Flow
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TYPICAL PERFORMANCE CHARACTERISTICS
VOUT
(AC Coupled)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 5V
VOUT = 1.2V
IOUT = 500mA
VOUT
(AC Coupled)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 5V
VOUT = 3.3V
IOUT = 500mA
VOUT
(AC Coupled)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 3.3V
VOUT = 1.8V
IOUT = 500mA
VOUT
(AC Coupled)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 3.3V
VOUT = 1.2V
IOUT = 500mA
ENABLE
Enable Power Up
CONDITIONS
VIN = 5V
VOUT = 3.3V (VID Mode)
IOUT = 10mA
VOUT
ENABLE
Enable Power Up
CONDITIONS
VIN = 5V
VOUT = 3.3V (VID Mode)
IOUT = 10mA
VOUT
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TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
ENABLE
Enable Power Up
CONDITIONS
VIN = 5V
VOUT = 3.3V (VID Mode)
IOUT = 500mA
VOUT
ENABLE
Enable Power Down
CONDITIONS
VIN = 5V
VOUT = 3.3V (VID Mode)
IOUT = 500mA
VOUT
VOUT
(AC Coupled)
Load Transient from 0 to 500mA
CONDITIONS
VIN = 5V
VOUT = 1.2V
LOAD
VOUT
(AC Coupled)
Load Transient from 0 to 500mA
CONDITIONS
VIN = 3.3V
VOUT = 1.8V
LOAD
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FUNCTIONAL BLOCK DIAGRAM
DAC
Switch
VREF
(+)
(-)
Error
Amp
VSENSE
VFB
VOUT
Package Boundry
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Sawtooth
Generator
(+)
(-)PWM
Comp
PVIN
ENABLE
PGND
Logic
Compensation
Network
NC(SW)
Voltage
Select
VS0 VS1
AVIN VS2AGND
Figure 5: Functional Block Diagram
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FUNCTIONAL DESCRIPTION
Functional Overview
The EP5358xUI requires only 2 small MLCC capacitors for a complete DC-DC converter solution. The device
integrates MOSFET switches, PWM controller, Gate-drive, compensation, and inductor into a tiny 2.5mm x
2.25mm x 1.1mm micro-QFN package. Advanced package design, along with the high level of integration,
provides very low output ripple and noise. The EP5358xUI uses voltage mode control for high noise immunity
and load matching to advanced ≤90nm loads. A 3-pin VID allows the user to choose from one of 8 output
voltage settings. The EP5358xUI comes with two VID output voltage ranges. The EP5358HUI provides VOUT
settings from 1.8V to 3.3V, the EP5358LUI provides VID settings from 0.8V to 1.5V, and also has an external
resistor divider option to program output setting over the 0.6V to VIN-0.25V range. The EP5358xUI provides
the industry’s highest power density of any 600mA DC-DC converter solution.
The key enabler of this revolutionary integration is Altera’s proprietary power MOSFET technology. The
advanced MOSFET switches are implemented in deep-submicron CMOS to supply very low switching loss at
high switching frequencies and to allow a high level of integration. The semiconductor process allows seem-
less integration of all switching, control, and compensation circuitry.
The proprietary magnetics design provides high-density/high-value magnetics in a very small footprint. Altera
Enpirion magnetics are carefully matched to the control and compensation circuitry yielding an optimal
solution with assured performance over the entire operating range.
Protection features include under-voltage lock-out (UVLO), over-current protection (OCP), short circuit
protection, and thermal overload protection
Integrated Inductor: Low-Noise Low-EMI
The EP5358xUI utilizes a proprietary low loss integrated inductor. The integration of the inductor greatly
simplifies the power supply design process. The inherent shielding and compact construction of the integrated
inductor reduces the conducted and radiated noise that can couple into the traces of the printed circuit board.
Further, the package layout is optimized to reduce the electrical path length for the high di/dT input AC ripple
currents that are a major source of radiated emissions from DC-DC converters. The integrated inductor
provides the optimal solution to the complexity, output ripple, and noise that plague low power DC-DC
converter design.
Control Matched to sub 90nm Loads
The EP5358xUI utilizes an integrated type III compensation network. Voltage mode control is inherently
impedance matched to the sub 90nm process technology that is used in today’s advanced ICs. Voltage mode
control also provides a high degree of noise immunity at light load currents so that low ripple and high
accuracy are maintained over the entire load range. The very high switching frequency allows for a very wide
control loop bandwidth and hence excellent transient performance.
Soft Start
nternal soft start circuits limit in-rush current when the device starts up from a power down condition or when
the “ENABLE” pin is asserted “high”. Digital control circuitry limits the VOUT ramp rate to levels that are safe for
the Power MOSFETS and the integrated inductor.
The EP5358HUI has a soft-start slew rate that is twice that of the EP5358LUI.
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Page 15
When the EP5358LUI is configured in external resistor divider mode, the device has a fixed VOUT ramp time.
Therefore, the ramp rate will vary with the output voltage setting. Output voltage ramp time is given in the
Electrical Characteristics Table.
Excess bulk capacitance on the output of the device can cause an over-current condition at startup. Maximum
allowable output capacitance depends on the device’s minimum current limit, the output current at startup,
the minimum soft-start time and the output voltage (all are listed in the Electrical Characteristics Table). The
total maximum capacitance on the output rail is estimated by the equation below:
COUT_MAX = (ILIMIT - IOUT) * tSS / VOUT
COUT_MAX = maximum allowable output capacitance
ILIMIT = DC current limit with margin = 0.8A
IOUT = output current at startup
VOUT = output voltage
tSS(VFB) = min soft-start time
= 0.146ms External feedback setting
tSS(VID_HUI) = VOUT [V] / 10.8 [V/ms] “H” VID setting
tSS(VID_LUI) = VOUT [V] / 5.4 [V/ms] “L” VID setting
The soft-start time in VID setting is different than External Feedback (VFB) setting, so be sure to use the correct
value when calculating the maximum allowable output capacitance.
NOTE: Do not use excessive output capacitance since it may affect device stability. The EP5358xUI has high
loop bandwidth and 60µF is all that is needed for transient response optimization.
Over Current/Short Circuit Protection
The current limit function is achieved by sensing the current flowing through a sense P-MOSFET which is
compared to a reference current. When this level is exceeded the P-FET is turned off and the N-FET is turned
on, pulling VOUT low. This condition is maintained for approximately 0.5mS and then a normal soft start is
initiated. If the over current condition still persists, this cycle will repeat.
Thermal Protection
The thermal shutdown circuit disables the device operation (switching stops) when the junction temperature
exceeds 160°C. When the junction temperature drops by approximately 25°C, the converter will re-start with
a normal soft-start. By preventing operation at excessive temperatures, the thermal shutdown circuit will
protect the device from overstress.
Under Voltage Lockout
During initial power up an under voltage lockout circuit will hold-off the switching circuitry until the input
voltage reaches a sufficient level to insure proper operation. If the voltage drops below the UVLO threshold
the lockout circuitry will again disable the switching. Hysteresis is included to prevent chattering between
states.
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Enable
The ENABLE pin provides a means to shut down the converter or enable normal operation. A logic low will
disable the converter and cause it to shut down. A logic high will enable the converter into normal operation.
NOTE: The ENABLE pin must not be left floating.
Thermal Shutdown
When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature
exceeds the thermal shutdown temperature the thermal shutdown circuit turns off the converter output
voltage thus allowing the device to cool. When the junction temperature decreases by 15°C, the device will go
through the normal startup process.
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Page 17
APPLICATION INFORMATION
Figure 6. EP5358HUI Application Circuit
Figure 7. EP5358LUI Application Circuit
Output Voltage Programming
The EP5358xUI utilizes a 3-pin VID to program the output voltage value. The VID is available in two sets of
output VID programming ranges. The VID pins should be connected either to AVIN or to AGND to avoid noise
coupling into the device.
The “Low” range is optimized for low voltage applications. It comes with preset VID settings ranging from
0.80V and 1.5V. This VID set also has an external divider option.
To specify this VID range, order part number EP5358LUI.
The “High” VID set provides output voltage settings ranging from 1.8V to 3.3V. This version does not have an
external divider option. To specify this VID range, order part number EP5358HUI.
Internally, the output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is
connected to the non-inverting input of the error amplifier. This allows the use of a single feedback divider
with constant loop gain and optimum compensation, independent of the output voltage selected.
NOTE: The VID pins must not be left floating.
EP5358L Low VID Range Programming
The EP5358LUI is designed to provide a high degree of flexibility in powering applications that require low
VOUT settings and dynamic voltage scaling (DVS). The device employs a 3-pin VID architecture that allows
the user to choose one of seven (7) preset output voltage settings, or the user can select an external voltage
divider option. The VID pin settings can be changed on the fly to implement glitch-free voltage scaling.
VOUT
VIN
10µF
0805
X7R
4.7µF
0603
X7R
VOUTPVIN
AVIN
PGND AGND
VSENSE
EP5358HUI
VS0
VS1
VS2
ENABLE
Do not float
VOUT
VIN
10µF
0805
X7R
4.7µF
0603
X7R
VOUTPVIN
AVIN
PGNDAGND
VSENSE
EP5358LUI
VFB
VS0
VS1
VS2
ENABLE
Do not float
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Page 18
Table 1: EP5358LUI VID Voltage Select Settings
VS2
VS1
VS0
VOUT
0
0
0
1.50V
0
0
1
1.45V
0
1
0
1.20V
0
1
1
1.15V
1
0
0
1.10V
1
0
1
1.05
1
1
0
0.80V
1
1
1
EXT
Table 1 shows the VS2-VS0 pin logic states for the EP5358LUI and the associated output voltage levels. A
logic “1” indicates a connection to AVIN or to a “high” logic voltage level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These pins can be either hardwired to AVIN or AGND or alternatively
can be driven by standard logic levels. Logic levels are defined in the electrical characteristics table. Any level
between the logic high and logic low is indeterminate.
EP5358LUI External Voltage Divider
The external divider option is chosen by connecting VID pins VS2-VS0 to VIN or a logic “1” or “high”. The
EP5358LUI uses a separate feedback pin, VFB, when using the external divider. VSENSE must be connected
to VOUT as indicated in Figure 8.
The output voltage is selected by the following formula:
Rb
Ra
OUT VV 16.0
Ra must be chosen as 237KΩ to maintain loop gain. Then Rb is given as:
6.0
102.142 3
OUT
bVx
R
VOUT can be programmed over the range of 0.6V to (VIN – 0.25V).
NOTE: Dynamic Voltage Scaling is not allowed between internal preset voltages and external divider.
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Page 19
Figure 8. EP5358LUI Using External Divider
EP5358HUI High VID Range Programming
The EP5358HUI VOUT settings are optimized for higher nominal voltages such as those required to power IO,
RF, or IC memory. The preset voltages range from 1.8V to 3.3V. There are eight (8) preset output voltage
settings. The EP5358HUI does not have an external divider option. As with the EP5358LUI, the VID pin settings
can be changed while the device is enabled.
Table 2 shows the VS0-VS2 pin logic states for the EP5358HUI and the associated output voltage levels. A
logic “1” indicates a connection to AVIN or to a “high” logic voltage level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These pins can be either hardwired to AVIN or AGND or alternatively
can be driven by standard logic levels. Logic levels are defined in the electrical characteristics table. Any level
between the logic high and logic low is indeterminate. These pins must not be left floating.
Table 2: EP5358HUI VID Voltage Select Settings
VS2
VS1
VS0
VOUT
0
0
0
3.30V
0
0
1
3.00V
0
1
0
2.90V
0
1
1
2.60V
1
0
0
2.50V
1
0
1
2.20V
1
1
0
2.10V
1
1
1
1.80V
VOUT
VIN
10µF
0805
X7R
4.7µF
0603
X7R
VOUTPVIN
AVIN
PGND AGND
VSENSE
EP5358LUI
VFB
VS0
VS1
VS2
ENABLE
RA
RB
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Page 20
Custom VID Setting Adjustment
Figure 9: EP5358xUI with RC inserted in VSENSE path to modify VID output voltages.
It is possible to adjust VOUT for a given VID setting by inserting a parallel RC combination in the VSENSE path
as shown in figure 9. The capacitor value is 5.0pF to ensure stability. Note that the value of VOUT can only be
increased from its nominal setting (VOUTNEW>VOUTOLD):
For EP5358LUI:
kOhms
VOUT
VOUT
Rs
OLD
NEW
L
1*711
For EP5358HUI:
kOhms
VOUT
VOUT
Rs
OLD
NEW
H
1*356
VOUTNEW is the desired “new” VOUT.
VOUTOLD is the VID table output voltage.
For a given Rs Value, the VOUTNEW for VID settings is determined by the following equations:
EP5358LUI:
Volts
Rs
VOUTVOUT L
OLDNEW
1
711
EP5358HUI:
Volts
Rs
VOUTVOUT H
OLDNEW
1
356
NOTE: The amount of adjustment is limited to approximately 15% of the nominal VID setting.
NOTE: Adjusting VOUT using this method will increase the tolerance of the output voltage. The larger the
adjustment, the greater the increase in tolerance.
VOUT
VIN
10µF
0805
X7R
4.7µF
0603
X7R
VOUTPVIN
AVIN
PGND AGND
VSENSE
EP5358xUI
VFB
VS0
VS1
VS2
ENABLE
5pF RS
Do not float
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Input Filter Capacitor
The input capacitor requirement is a minimum of 4.7µF 0603 X7R MLCC. Y5V or equivalent dielectric
formulations lose capacitance with frequency, bias, and with temperature, and are not suitable for switch-
mode DC-DC converter input filter applications.
Output Filter Capacitor
The output filter capacitor requirement is a minimum of 10µF 0805 MLCC. Ripple performance can be
improved by using 2x10µF 0603 MLCC capacitors (for any allowed VIN).
The maximum output filter capacitance next to the output pins of the device is 60µF low ESR MLCC
capacitance. VOUT has to be sensed at the last output filter capacitor next to the EP5358xUI.
Additional bulk capacitance for decoupling and bypass can be placed at the load as long as there is sufficient
separation between the VOUT Sense point and the bulk capacitance.
Excess total capacitance on the output (Output Filter + Bulk) can cause an over-current condition at startup.
Refer to the section on Soft-Start for the maximum total capacitance on the output.
The output capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric
formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch-mode DC-
DC converter output filter applications.
Power-Up/Down Sequencing
During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before
AVIN. The PVIN should never be powered when AVIN is off. Durig power down, the AVIN should not be
powered down before the PVIN. Tying PVIN and AVIN or all three pins (AVIN, PVIN, ENABLE) together during
power up or power down meets these requirements.
Pre-Bias Start-up
The EP5358xUI supports startup into a pre-biased output of up to 1.5V. The output of the EP5358xUI can
be pre-biased with a voltage up to 1.5V when it is first enabled.
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THERMAL CONSIDERATIONS
Thermal considerations are important power supply design facts that cannot be avoided in the real world.
Whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be
accounted for. The Enpirion PowerSoC helps alleviate some of those concerns. The Enpirion EP5358xUI DC-
DC converter is packaged in a 2.5x2.25x1.1mm 16-pin QFN package. The recommended maximum junction
temperature for continuous operation is 125°C. Continuous operation above 125°C may reduce long-term
reliability. The device has a thermal overload protection circuit designed to turn off the device at an
approximate junction temperature value of 155°C.
The following example and calculations illustrate the thermal performance of the EP5358xUI.
Example:
VIN = 5V
VOUT = 3.3V
IOUT = 600mA
First calculate the output power.
POUT = 3.3V x 600mA = 1.98W
Next, determine the input power based on the efficiency (η) shown in Figure 10.
Figure 10: Efficiency vs. Output Current
For VIN = 5V, VOUT = 3.3V at 600mA, η ≈ 91%
η = POUT / PIN = 91% = 0.91
PIN = POUT / η
PIN ≈ 1.98W / 0.91 ≈ 2.18W
35
40
45
50
55
60
65
70
75
80
85
90
95
0100 200 300 400 500 600
EFFICIENCY (%)
OUTPUT CURRENT (mA)
Efficiency vs. IOUT (VIN = 5.0V)
VOUT = 3.3V
CONDITIONS
VIN = 5V
91%
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The power dissipation (PD) is the power loss in the system and can be calculated by subtracting the output
power from the input power.
PD = PIN – POUT
≈ 2.18W – 1.98W ≈ 0.2W
With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA
value (θJA). The θJA parameter estimates how much the temperature will rise in the device for every watt of
power dissipation. The EP5358xUI has a θJA value of 85°C/W without airflow.
Determine the change in temperature (ΔT) based on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 0.2W x 85°C/W ≈ 17°C
The junction temperature (TJ) of the device is approximately the ambient temperature (TA) plus the change in
temperature. We assume the initial ambient temperature to be 25°C.
TJ = TA + ΔT
TJ ≈ 25°C + 17°C ≈ 42°C
The maximum operating junction temperature (TJMAX) of the device is 125°C, so the device can operate at a
higher ambient temperature. The maximum ambient temperature (TAMAX) allowed can be calculated.
TAMAX = TJMAX – PD x θJA
≈ 125°C – 17°C ≈ 108°C
The maximum ambient temperature (before de-rating) the device can reach is 84°C given the input and output
conditions. Note that the efficiency will be slightly lower at higher temperatures and this calculation is an
estimate.
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Page 24
LAYOUT RECOMMENDATIONS
Figure 11 shows critical components and layer 1 traces of a recommended minimum footprint
EP5358LUI/EP5358HUI layout with ENABLE tied to VIN. Alternate ENABLE configurations, and other small
signal pins need to be connected and routed according to specific customer application. Please see the Gerber
files on the Altera website www.altera.com/powersoc for exact dimensions and other layers. Please refer to
Figure 11 while reading the layout recommendations in this section.
Figure 11. Top PCB Layer Critical Components and Copper for Minimum Footprint
Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as
close to the EP5358xUI package as possible. They should be connected to the device with very short and wide
traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The
+V and GND traces between the capacitors and the EP5358xUI should be as close to each other as possible
so that the gap between the two nodes is minimized, even under the capacitors.
Recommendation 2: Input and output grounds are separated until they connect at the PGND pins. The
separation shown on Figure 11 between the input and output GND circuits helps minimize noise coupling
between the converter input and output switching loops.
Recommendation 3: The system ground plane should be the first layer immediately below the surface layer.
This ground plane should be continuous and un-interrupted below the converter and the input/output
capacitors.
Recommendation 4: Multiple small vias should be used to connect the ground traces under the device to the
system ground plane on another layer for heat dissipation. The drill diameter of the vias should be 0.33mm,
and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around
0.20-0.26mm. Do not use thermal reliefs or spokes to connect the vias to the ground plane. It is preferred to
put these vias under the capacitors along the edge of the GND copper closest to the +V copper. Please see
Figure 11. These vias connect the input/output filter capacitors to the GND plane and help reduce parasitic
inductances in the input and output current loops. If the vias cannot be placed under CIN and COUT, then put
them just outside the capacitors along the GND. Do not use thermal reliefs or spokes to connect these vias to
the ground plane.
Recommendation 5: AVIN is the power supply for the internal small-signal control circuits. It should be
connected to the input voltage at a quiet point. In Figure 11 this connection is made at the input capacitor
close to the VIN connection.
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Page 25
RECOMMENDED PCB FOOTPRINT
Figure 12: EP5358xUI PCB Footprint (Top View)
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Page 26
PACKAGE DIMENSIONS
Figure 13: EP5358LUI Package Dimensions (Bottom View)
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Page 27
Figure 14: EP5358HUI Package Dimensions (Bottom View)
Packing and Marking Information: https://www.altera.com/support/quality-and-reliability/packing.html
03541 October 13, 2018 Rev K
Datasheet | Intel® Enpirion® Power Solutions: EP5358LUI/HUI
WHERE TO GET MORE INFORMATION
For more information about Intel® and Enpirion® PowerSoCs, visit:
www.altera.com/enpirion
© 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and
services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
* Other marks and brands may be claimed as the property of others.
Page 28
REVISION HISTORY
Rev
Date
Change(s)
I
Feb, 2018
Updated Derating Curves to show correct Theta JA value and illustration
Updated Enable Power Down illustration to show actual image with 500mA of
load current
Updated Soft-start discussion and maximum output capacitance
Updated Power Up Sequence recommendations
Updated Pre-Bias Startup discussion
Updated COUT_Max equation
New Datasheet format
J
Sep, 2018
Updated Format
K
Sep, 2018
Corrected some Typos
03541 October 13, 2018 Rev K