TCA9539 www.ti.com........................................................................................................................................... SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009 LOW VOLTAGE 16-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS FEATURES 1 * * * * * * * * * * * Low Standby-Current Consumption of 3 A Max I2C to Parallel Port Expander Open-Drain Active-Low Interrupt Output Active-Low Reset Input 5-V Tolerant I/O Ports Compatible With Most Microcontrollers 400-kHz Fast I2C Bus Polarity Inversion Register Address by Two Hardware Address Pins for Use of up to Four Devices Latched Outputs With High-Current Drive Capability for Directly Driving LEDs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 1000-V Charged-Device Model (C101) - 200-V Machine Model (A115-A) PW PACKAGE (TOP VIEW) INT A1 RESET P00 P01 P02 P03 P04 P05 P06 P07 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC SDA SCL A0 P17 P16 P15 P14 P13 P12 P11 P10 RTW PACKAGE (TOP VIEW) RESET A1 INT VCC SDA SCL * 24 P00 P01 P02 P03 P04 P05 23 22 21 20 19 1 18 2 17 Exposed Center Pad 3 4 16 15 5 14 6 13 8 9 10 11 12 P06 P07 GND P10 P11 P12 7 A0 P17 P16 P15 P14 P13 The exposed center pad, if used, must be connected as a secondary ground or left electrically open. DESCRIPTION/ORDERING INFORMATION This 16-bit I/O expander for the two-line bidirectional bus (I2C) is designed for 1.65-V to 5.5-V VCC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL), serial data (SDA)]. The TCA9539 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009, Texas Instruments Incorporated TCA9539 SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009........................................................................................................................................... www.ti.com The system master can reset the TCA9539 in the event of a time-out or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. Asserting RESET causes the same reset/initialization to occur without depowering the part. The TCA9539 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA9539 can remain a simple slave device. The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low current consumption. The TCA9539 is identical to the PCA9555, except for the removal of the internal I/O pullup resistor, which greatly reduces power consumption when the I/Os are held low, replacement of A2 with RESET, and a different address range. Two hardware pins (A0 and A1) are used to program and vary the fixed I2C address and allow up to four devices to share the same I2C bus or SMBus. ORDERING INFORMATION TA -40C to 85C (1) (2) 2 PACKAGE (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP - PW Reel of 2000 TCA9539PWR PW539 QFN - RTW Reel of 3000 TCA9539RTWR PW539 Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 TCA9539 www.ti.com........................................................................................................................................... SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009 TERMINAL FUNCTIONS NO. TSSOP (PW) QFN (RTW) BGA (ZQS) NAME DESCRIPTION 1 22 A3 INT Interrupt output. Connect to VCC through a pullup resistor. 2 23 B3 A1 Address input. Connect directly to VCC or ground. 3 24 A2 RESET 4 1 A1 P00 P-port input/output. Push-pull design structure. At power on, P00 is configured as an input. 5 2 C3 P01 P-port input/output. Push-pull design structure. At power on, P01 is configured as an input. 6 3 B1 P02 P-port input/output. Push-pull design structure. At power on, P02 is configured as an input. 7 4 C1 P03 P-port input/output. Push-pull design structure. At power on, P03 is configured as an input. 8 5 C2 P04 P-port input/output. Push-pull design structure. At power on, P04 is configured as an input. 9 6 D1 P05 P-port input/output. Push-pull design structure. At power on, P05 is configured as an input. 10 7 E1 P06 P-port input/output. Push-pull design structure. At power on, P06 is configured as an input. 11 8 D2 P07 P-port input/output. Push-pull design structure. At power on, P07 is configured as an input. 12 9 E2 GND Ground 13 10 E3 P10 P-port input/output. Push-pull design structure. At power on, P10 is configured as an input. 14 11 E4 P11 P-port input/output. Push-pull design structure. At power on, P11 is configured as an input. 15 12 D3 P12 P-port input/output. Push-pull design structure. At power on, P12 is configured as an input. 16 13 E5 P13 P-port input/output. Push-pull design structure. At power on, P13 is configured as an input. 17 14 D4 P14 P-port input/output. Push-pull design structure. At power on, P14 is configured as an input. 18 15 D5 P15 P-port input/output. Push-pull design structure. At power on, P15 is configured as an input. 19 16 C5 P16 P-port input/output. Push-pull design structure. At power on, P16 is configured as an input. 20 17 C4 P17 P-port input/output. Push-pull design structure. At power on, P17 is configured as an input. 21 18 B5 A0 Address input. Connect directly to VCC or ground. 22 19 A5 SCL Serial clock bus. Connect to VCC through a pullup resistor. 23 20 A4 SDA Serial data bus. Connect to VCC through a pullup resistor. 24 21 B4 VCC Supply voltage Active-low reset input. Connect to VCC through a pullup resistor if no active connection is used. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 3 TCA9539 SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009........................................................................................................................................... www.ti.com LOGIC DIAGRAM (POSITIVE LOGIC) TCA9539 1 INT Interrupt Logic LP Filter 21 A0 2 A1 P07-P00 22 SCL 23 SDA Input Filter I2C Bus Control Shift Register 16 Bits I/O Port P17-P10 RESET VCC GND 4 Write Pulse 3 24 12 Power-On Reset A. Pin numbers shown are for PW package. B. All I/Os are set to inputs at reset. Read Pulse Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 TCA9539 www.ti.com........................................................................................................................................... SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009 SIMPLIFIED SCHEMATIC OF P-PORT I/Os(1) Data From Shift Register Output Port Register Data Configuration Register Data From Shift Register D Q FF Write Configuration Pulse VCC Q1 CLK Q Write Pulse D Q FF I/O Pin CLK Q Output Port Register Q2 Input Port Register D Q FF Read Pulse GND Input Port Register Data CLK Q To INT Data From Shift Register D Q Polarity Register Data FF Write Polarity Pulse CLK Q Polarity Inversion Register (1) At power-on reset, all registers return to default values. I/O Port When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 5 TCA9539 SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009........................................................................................................................................... www.ti.com I2C Interface The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address byte is sent, MSB first, including the data direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during the high of the ACK-related clock pulse. The address inputs (A0 and A1) of the slave device must not be changed between the Start and Stop conditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 2). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 1). Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition. SDA SCL S P Start Condition Stop Condition Figure 1. Definition of Start and Stop Conditions SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 2. Bit Transfer 6 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 TCA9539 www.ti.com........................................................................................................................................... SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009 Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgment Start Condition Figure 3. Acknowledgment on I2C Bus Interface Definition BYTE BIT 7 (MSB) 6 5 4 3 2 1 0 (LSB) I2C slave address H H H L H A1 A0 R/W P0x I/O data bus P07 P06 P05 P04 P03 P02 P01 P00 P1x I/O data bus P17 P16 P15 P14 P13 P12 P11 P10 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 7 TCA9539 SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009........................................................................................................................................... www.ti.com Device Address Figure 4 shows the address byte of the TCA9539. R/W Slave Address 1 1 1 0 Fixed A1 A0 1 Programmable Figure 4. TCA9539 Address Address Reference INPUTS I2C BUS SLAVE ADDRESS A1 A0 L L 116 (decimal), 74 (hexadecimal) L H 117 (decimal), 75 (hexadecimal) H L 118 (decimal), 76 (hexadecimal) H H 119 (decimal), 77 (hexadecimal) The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation. Control Register and Command Byte Following the successful acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the TCA9539. Three bits of this data byte state the operation (read or write) and the internal register (input, output, Polarity Inversion or Configuration) that will be affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission. Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. 0 0 0 0 0 B2 B1 B0 Figure 5. Control Register Bits Command Byte CONTROL REGISTER BITS 8 B2 B1 B0 COMMAND BYTE (HEX) REGISTER PROTOCOL POWER-UP DEFAULT 0 0 0 0x00 Input Port 0 Read byte xxxx xxxx 0 0 1 0x01 Input Port 1 Read byte xxxx xxxx 0 1 0 0x02 Output Port 0 Read/write byte 1111 1111 0 1 1 0x03 Output Port 1 Read/write byte 1111 1111 1 0 0 0x04 Polarity Inversion Port 0 Read/write byte 0000 0000 1 0 1 0x05 Polarity Inversion Port 1 Read/write byte 0000 0000 1 1 0 0x06 Configuration Port 0 Read/write byte 1111 1111 1 1 1 0x07 Configuration Port 1 Read/write byte 1111 1111 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 TCA9539 www.ti.com........................................................................................................................................... SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009 Register Descriptions The Input Port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port register will be accessed next. Registers 0 and 1 (Input Port Registers) Bit Default Bit Default I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 X X X X X X X I0.0 X I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0 X X X X X X X X The Output Port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Registers 2 and 3 (Output Port Registers) Bit Default Bit Default O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0 1 1 1 1 1 1 1 1 O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0 1 1 1 1 1 1 1 1 The Polarity Inversion registers (registers 4 and 5) allow Polarity Inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is retained. Registers 4 and 5 (Polarity Inversion Registers) Bit Default Bit Default N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 0 0 0 0 0 0 0 N0.0 0 N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0 0 0 0 0 0 0 0 0 The Configuration registers (registers 6 and 7) configure the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. Registers 6 and 7 (Configuration Registers) Bit Default Bit Default C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0 1 1 1 1 1 1 1 1 C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0 1 1 1 1 1 1 1 1 Power-On Reset When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9539 in a reset condition until VCC has reached VPOR. At that point, the reset condition is released and the TCA9539 registers and I2C/SMBus state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to the operating voltage for a power-reset cycle. Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 9 TCA9539 SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009........................................................................................................................................... www.ti.com RESET Input A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TCA9539 registers and I2C/SMBus state machine are held in their default states until RESET is once again high. This input requires a pullup resistor to VCC, if no active connection is used. Interrupt (INT) Output An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit or not acknowledge (NACK) bit after the falling edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa. INT has an open-drain structure and requires a pullup resistor to VCC. Bus Transactions Data is exchanged between the master and TCA9539 through write and read commands. Writes Data is transmitted to the TCA9539 by sending the device address and setting the least-significant bit to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. The eight registers within the TCA9539 are configured to operate as four register pairs. The four pairs are Input Ports, Output Ports, Polarity Inversion ports, and Configuration ports. After sending data to one register, the next data byte is sent to the other register in the pair (see Figure 6 and Figure 7). For example, if the first byte is sent to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers. 1 SCL 2 3 4 5 6 7 8 9 Command Byte Slave Address SDA S 1 1 1 Start Condition 0 1 A1 A0 0 A 0 0 0 R/W Acknowledge From Slave 0 0 0 Data to Port 0 1 0 A 0.7 Data to Port 1 0.0 Data 0 Acknowledge From Slave A 1.7 Data 1 1.0 A P Acknowledge From Slave Write to Port Data Out from Port 0 tpv Data Valid Data Out from Port 1 tpv Figure 6. Write to Output Port Registers 10 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 TCA9539 www.ti.com........................................................................................................................................... SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009 1 SCL 2 3 4 5 6 7 8 9 1 2 3 Slave Address SDA S 1 1 1 0 1 4 5 6 7 8 9 1 2 3 Command Byte A1 A0 0 R/W Start Condition A 0 0 0 0 0 1 1 4 5 6 7 8 9 1 2 3 Data to Register 0 A MSB Data 0 5 Data to Register LSB Acknowledge From Slave Acknowledge From Slave 4 A MSB Data 1 LSB A P Acknowledge From Slave Figure 7. Write to Configuration Registers Reads The bus master first must send the TCA9539 address with the least-significant bit set to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again, but this time, the least-significant bit is set to a logic 1. Data from the register defined by the command byte then is sent by the TCA9539 (see Figure 8 through Figure 10). After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. Slave Address S 1 1 1 0 1 Acknowledge From Slave A1 A0 0 A R/W Slave Address Acknowledge From Slave Command Byte A S 1 1 1 0 1 Acknowledge From Slave A1 A0 At this moment, master transmitter becomes master receiver, and slave receiver becomes slave transmitter. 1 Data From Lower or Upper Byte of Register A MSB R/W Data LSB A First Byte Data From Upper or Lower Byte of Register MSB Acknowledge From Master Data No Acknowledge From Master LSB NA P Last Byte Figure 8. Read From Register Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 11 TCA9539 SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009........................................................................................................................................... www.ti.com 1 SCL 2 3 4 5 6 7 8 9 I0.x SDA S 1 1 1 0 1 A1 1 A0 A R/W 7 6 5 4 3 I1.x 2 1 0 A 7 6 5 4 3 Acknowledge From Master Acknowledge From Slave I0.x 2 1 0 A 7 6 5 4 3 I1.x 2 1 0 A 7 6 5 4 3 2 1 Acknowledge From Master Acknowledge From Master 0 1 P No Acknowledge From Master Read From Port 0 Data Into Port 0 Read From Port 1 Data Into Port 1 INT tiv tir A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read Input Port register). B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from the P port (see Figure 8 for these details). Figure 9. Read Input Port Register, Scenario 1 <br/> 1 SCL 2 3 4 5 6 7 8 9 I0.x SDA S 1 1 1 0 1 A1 A0 1 R/W A 00 Acknowledge From Slave I1.x A 10 I0.x A 03 Acknowledge From Master Acknowledge From Master I1.x A 12 P No Acknowledge From Master tps tph 1 Acknowledge From Master Read From Port 0 Data Into Port 0 Data 00 Data 01 Data 02 Data 03 tph tps Read From Port 1 Data 10 Data Into Port 1 Data 11 Data 12 INT tiv tir A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read Input Port register). B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from the P port (see Figure 8 for these details). Figure 10. Read Input Port Register, Scenario 2 12 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 TCA9539 www.ti.com........................................................................................................................................... SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range -0.5 6 V VI Input voltage range (2) -0.5 6 V (2) VO Output voltage range IIK Input clamp current VI < 0 -20 mA IOK Output clamp current VO < 0 -20 mA IIOK Input/output clamp current VO < 0 or VO > VCC 20 mA IOL Continuous output low current VO = 0 to VCC 50 mA IOH Continuous output high current VO = 0 to VCC -50 mA ICC -0.5 Continuous current through GND -250 Continuous current through VCC 160 JA Package thermal impedance, junction to free air (3) Tstg Storage temperature range (1) (2) (3) 6 UNIT PW package 88 RTW package 66 -65 150 V mA C/W C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS VCC MIN MAX 1.65 5.5 SCL, SDA 0.7 x VCC 5.5 A0, A1, RESET, P07-P00, P17-P10 0.7 x VCC 5.5 SCL, SDA -0.5 0.3 x VCC A0, A1, RESET, P07-P00, P17-P10 -0.5 0.3 x VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage IOH High-level output current P07-P00, P17-P10 IOL Low-level output current P07-P00, P17-P10 TA Operating free-air temperature -40 Product Folder Link(s): TCA9539 V V V -10 mA 25 mA 85 C Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated UNIT 13 TCA9539 SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009........................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN -1.2 VIK Input diode clamp voltage II = -18 mA 1.65 V to 5.5 V VPOR Power-on reset voltage VI = VCC or GND, IO = 0 1.65 V to 5.5 V IOH = -8 mA P-port high-level output voltage (2) VOH IOH = -10 mA 1.65 V 1.2 2.3 V 1.8 3V 2.6 4.75 V 4.1 1.65 V 1.8 2.3 V 1.7 3V 2.5 4.75 V SDA P port (3) IOL INT SCL, SDA II A0, A1, RESET VOL = 0.7 V MAX 1.5 1.65 UNIT V V V 4 VOL = 0.4 V VOL = 0.5 V TYP (1) 3 1.65 V to 5.5 V VOL = 0.4 V 8 20 10 24 mA 3 VI = VCC or GND 1.65 V to 5.5 V 1 1 A IIH P port VI = VCC 1.65 V to 5.5 V 1 A IIL P port VI = GND 1.65 V to 5.5 V -1 A Operating mode VI = VCC or GND, IO = 0, I/O = inputs, fSCL = 400 kHz ICC 5.5 V 100 200 3.6 V 30 75 2.7 V 20 50 1.95 V 10 45 5.5 V 1.1 1.5 3.6 V 0.7 1.3 2.7 V 0.5 1 1.95 V 0.3 0.9 Standby mode VI = GND, IO = 0, I/O = inputs, fSCL = 0 kHz ICC Additional current in standby mode One input at VCC - 0.6 V, Other inputs at VCC or GND 1.65 V to 5.5 V Ci SCL VI = VCC or GND 1.65 V to 5.5 V VIO = VCC or GND 1.65 V to 5.5 V Cio (1) (2) (3) 14 SDA P port 3 A 1.5 mA 7 pF 3 7 3.7 9.5 pF All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC) and TA = 25C. Each I/O must be externally limited to a maximum of 25 mA, and each octal (P07-P00 and P17-P10) must be limited to a maximum current of 100 mA, for a device total of 200 mA. The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07-P00 and 80 mA for P17-P10). Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 TCA9539 www.ti.com........................................................................................................................................... SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009 I2C INTERFACE TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 11) fscl I2C clock frequency tsch I2C clock high time I C clock low time tsp I2C spike time tsds I2C serial-data setup time MAX UNIT 0 400 kHz s 0.6 2 tscl MIN s 1.3 50 100 2 ns ns tsdh I C serial-data hold time ticr I2C input rise time 20 + 0.1Cb (1) 300 ns ticf I2C input fall time 20 + 0.1Cb (1) 300 ns (1) 300 2 0 10-pF to 400-pF bus 20 + 0.1Cb ns tocf I C output fall time tbuf I2C bus free time between Stop and Start 1.3 s tsts I2C Start or repeated Start condition setup 0.6 s tsth I2C Start or repeated Start condition hold 0.6 s 0.6 s 2 tsps I C Stop condition setup tvd(data) Valid-data time SCL low to SDA output valid 50 tvd(ack) Valid-data time of ACK condition ACK signal from SCL low to SDA (out) low 0.1 Cb I2C bus capacitive load (1) ns ns 0.9 s 400 pF Cb = total capacitance of one bus line in pF RESET TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 14) MIN MAX UNIT tW Reset pulse duration 6 ns tREC Reset recovery time 0 ns tRESET Time to reset 400 ns SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL 100 pF (unless otherwise noted) (see Figure 12 and Figure 13) PARAMETER FROM (INPUT) TO (OUTPUT) P port INT 4 s SCL INT 4 s 200 ns MIN MAX UNIT tiv Interrupt valid time tir Interrupt reset delay time tpv Output data valid SCL P port tps Input data setup time P port SCL 150 ns tph Input data hold time P port SCL 1 s Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 15 TCA9539 SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009........................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS TA = 25C (unless otherwise noted) SUPPLY CURRENT vs TEMPERATURE STANDBY SUPPLY CURRENT vs TEMPERATURE 22 14 12 10 VCC = 3.3 V 8 VCC = 2.5 V 6 4 VCC = 1.8 V 2 VCC = 1.65 V -15 10 35 VCC = 5.5 V 1600 VCC = 5 V 1400 1200 600 VCC = 1.8 V 400 VCC = 1.65 V 85 -15 10 35 60 Temperature, TA (C) I/O SINK CURRENT vs OUTPUT LOW VOLTAGE I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 35 Sink Current, ISINK (mA) 25 TA = -40C 20 TA = 25C 15 10 TA = 85C 5 0.1 0.2 0.3 0.4 0.5 0.6 VCC = 2.5 V 10 TA = 85C 5 0.3 0.4 0.5 40 30 TA = 25C 20 TA = 85C 10 0 0.0 0.6 TA = -40C 0.1 0.2 0.3 0.4 0.5 Output Low Voltage, VOL (V) Output Low Voltage, VOL (V) Output Low Voltage, VOL (V) I/O SINK CURRENT vs OUTPUT LOW VOLTAGE I/O SINK CURRENT vs OUTPUT LOW VOLTAGE I/O SINK CURRENT vs OUTPUT LOW VOLTAGE 60 70 40 TA = 25C 30 20 TA = 85C 10 0.1 0.2 0.3 0.4 0.5 0.6 Output Low Voltage, VOL (V) 60 VCC = 5.5 V TA = -40C Sink Current, ISINK (mA) Sink Current, ISINK (mA) TA = -40C 50 50 40 TA = 25C 30 20 TA = 85C 10 0 0.0 0.6 70 VCC = 5.0 V VCC = 3.3 V 0 0.0 6 4 50 TA = 25C 0.2 8 I/O SINK CURRENT vs OUTPUT LOW VOLTAGE TA = -40C 0.1 12 10 Supply Voltage, VCC (V) 15 0 0.0 0 85 25 20 16 14 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC = 1.8 V 30 18 2 Temperature, TA (C) VCC = 1.65 V Sink Current, ISINK (mA) VCC = 2.5 V 800 0 -40 30 0.0 VCC = 3.3 V 1000 200 60 20 Supply Current, ICC (A) VCC = 5 V 16 1800 Sink Current, ISINK (mA) Supply Current, ICC (nA) Supply Current, ICC (A) 18 0 -40 Sink Current, ISINK (mA) 22 2000 VCC = 5.5 V 20 16 SUPPLY CURRENT vs SUPPLY VOLTAGE 0.1 0.2 0.3 0.4 0.5 Output Low Voltage, VOL (V) Submit Documentation Feedback 0.6 60 TA = -40C 50 40 TA = 25C 30 20 TA = 85C 10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Output Low Voltage, VOL (V) Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 TCA9539 www.ti.com........................................................................................................................................... SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009 TYPICAL CHARACTERISTICS (continued) TA = 25C (unless otherwise noted) I/O LOW VOLTAGE vs TEMPERATURE I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 200 150 VCC = 5 V, ISINK = 10 mA 100 VCC = 1.8 V, ISINK = 1 mA VCC = 5 V, ISINK = 1 mA -15 10 35 60 15 TA = 25C 10 TA = 85C 5 0 85 0.1 0.0 Temperature, TA (C) Source Current, ISOURCE (mA) Source Current, ISOURCE (mA) TA = 25C 15 TA = 85C 10 5 0 0.0 0.1 0.2 0.4 0.5 0.3 0.4 TA = 25C 10 TA = 85C 5 0 0.1 0.0 0.2 0.5 0.6 0.3 40 30 TA = 25C 20 TA = 85C 0 0.0 0.1 0.2 0.3 0.4 0.6 0.5 TA = -40C VCC = 5.0 V 50 40 TA = 25C 30 20 TA = 85C 10 0 0.6 0.1 0.0 VCCP - VOH (V) I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 0.5 I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE TA = -40C 10 0.4 VCCP - VOH (V) 60 VCC = 3.3 V VCCP - VOH (V) 0.2 0.3 0.4 0.5 0.6 VCCP - VOH (V) I/O HIGH VOLTAGE vs TEMPERATURE 350 70 ISOURCE = -10 mA VCC = 5.5 V TA = -40C 60 300 VCC - VOH (mV) Source Current, ISOURCE (mA) 15 0.6 50 TA = -40C 25 20 0.3 TA = -40C 20 I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 35 30 0.2 VCC = 1.8 V VCCP - VOH (V) I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE VCC = 2.5 V TA = -40C Source Current, ISOURCE (mA) 50 VCC = 1.65 V Source Current, ISOURCE (mA) VCC = 1.8 V, ISINK = 10 mA 0 -40 25 20 Source Current, ISOURCE (mA) Output Low Voltage, VOL (mV) 250 I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 50 40 TA = 25C 30 20 TA = 85C 250 VCC = 1.8 V 200 VCC = 5 V 150 100 50 10 0 0.0 0.1 0.2 0.3 0.4 VCCP - VOH (V) 0.5 0.6 0 -40 -15 10 35 60 85 Temperature, TA (C) Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 17 TCA9539 SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009........................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION VCC RL = 1 k SDA DUT CL = 50 pF (see Note A) SDA LOAD CONFIGURATION Three Bytes for Complete Device Programming Stop Condition (P) Start Address Address Condition Bit 7 Bit 6 (S) (MSB) Address Bit 1 tscl R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Data Bit 0 (LSB) Stop Condition (P) tsch 0.7 x VCC SCL 0.3 x VCC ticr ticf tbuf tsts tPHL tPLH tsp 0.7 x VCC SDA 0.3 x VCC ticf ticr tsth tsdh tsds tsps Repeat Start Condition Start or Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS BYTE DESCRIPTION 1 I2C address 2, 3 P-port data A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 11. I2C Interface Load Circuit and Voltage Waveforms 18 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 TCA9539 www.ti.com........................................................................................................................................... SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009 PARAMETER MEASUREMENT INFORMATION (continued) VCC RL = 4.7 k INT DUT CL = 100 pF (see Note A) INTERRUPT LOAD CONFIGURATION ACK From Slave Start Condition 8 Bits (One Data Byte) From Port R/W Slave Address S 1 1 1 0 1 1 2 3 4 5 A1 A0 1 6 7 8 Data 1 A A ACK From Slave Data From Port A Data 2 1 P A tir tir B B INT A tiv tsps A Data Into Port Address Data 1 0.7 x VCC INT 0.3 x VCC SCL Data 2 0.7 x VCC R/W tiv A 0.3 x VCC tir 0.7 x VCC Pn 0.7 x VCC INT 0.3 x VCC 0.3 x VCC View A-A View B-B A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. C. All parameters and waveforms are not applicable to all devices. Figure 12. Interrupt Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 19 TCA9539 SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009........................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Pn 500 W DUT CL = 50 pF (see Note A) 2 x VCC 500 W P-PORT LOAD CONFIGURATION 0.7 x VCC SCL P0 A P3 0.3 x VCC Slave ACK III III III III III SDA Pn tpv (see Note B) Unstable Data Last Stable Bit WRITE MODE (R/W = 0) 0.7 x VCC SCL P0 A tps P3 0.3 x VCC tph 0.7 x VCC Pn 0.3 x VCC READ MODE (R/W = 1) A. CL includes probe and jig capacitance. B. tpv is measured from 0.7 x VCC on SCL to 50% I/O (Pn) output. C. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. D. The outputs are measured one at a time, with one transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 13. P-Port Load Circuit and Voltage Waveforms 20 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 TCA9539 www.ti.com........................................................................................................................................... SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009 PARAMETER MEASUREMENT INFORMATION (continued) VCC Pn RL = 1 k DUT 500 W 2 x VCC DUT SDA CL = 50 pF (see Note A) 500 W CL = 50 pF (see Note A) P-PORT LOAD CONFIGURATION SDA LOAD CONFIGURATION Start SCL ACK or Read Cycle SDA 0.3 y VCC tRESET RESET VCC/2 tREC tw Pn VCC/2 tRESET A. CL includes probe and jig capacitance. B. All inputs are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr/tf 30 ns. C. The outputs are measured one at a time, with one transition per measurement. D. I/Os are configured as inputs. E. All parameters and waveforms are not applicable to all devices. Figure 14. Reset Load Circuits and Voltage Waveforms Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 21 TCA9539 SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009........................................................................................................................................... www.ti.com APPLICATION INFORMATION Figure 15 shows an application in which the TCA9539 can be used. Subsystem 1 (e.g., Temperature Sensor) INT VCC (5 V) 10 k VCC 10 k 10 k 24 10 k 22 SCL Master Controller SDA 23 SCL SDA GND Subsystem 2 (e.g., Counter) 100 k VCC 1 3 INT RESET INT 2 k 4 P00 5 P01 6 P02 7 P03 8 P04 9 P05 100 k 100 k RESET A ENABLE B TCA9539 P06 P07 P10 P11 2 A1 P12 P13 21 A0 P14 P15 P16 GND P17 12 A. Device address is configured as 1110100 for this example. B. P00, P02, and P03 are configured as outputs. C. P01 and P04 to P17 are configured as inputs. D. Pin numbers shown are for the PW package. 10 11 13 14 15 16 17 18 19 20 VCC Controlled Switch (e.g., CBT Device) ALARM Keypad Subsystem 3 (e.g., Alarm) Figure 15. Typical Application 22 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 TCA9539 www.ti.com........................................................................................................................................... SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009 Minimizing ICC When I/O Is Used to Control LED When an I/O is used to control an LED, normally it is connected to VCC through a resistor (see Figure 15). Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ICC parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC. For battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC, when the LED is off, to minimize current consumption. Figure 16 shows a high-value resistor in parallel with the LED. Figure 17 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VCC at or above VCC and prevent additional supply-current consumption when the LED is off. VCC LED 100 kW VCC Pn Figure 16. High-Value Resistor in Parallel With LED 3.3 V VCC 5V LED Pn Figure 17. Device Supplied by Lower Voltage Power-On Reset Requirements In the event of a glitch or data corruption, TCA9539 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 18 and Figure 19. VCC Ramp-Up Ramp-Down Re-Ramp-Up VCC_TRR_GND Time VCC_RT VCC_FT Time to Re-Ramp VCC_RT Figure 18. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 23 TCA9539 SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009........................................................................................................................................... www.ti.com VCC Ramp-Down Ramp-Up VCC_TRR_VPOR50 VIN drops below POR levels Time Time to Re-Ramp VCC_FT VCC_RT Figure 19. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Table 1 specifies the performance of the power-on reset feature for TCA9539 for both types of power-on reset. Table 1. RECOMMENDED SUPPLY SEQUENCING AND RAMP RATES (1) MAX UNIT VCC_FT Fall rate PARAMETER See Figure 18 0.1 2000 ms VCC_RT Rise rate See Figure 18 0.1 2000 ms VCC_TRR_GND Time to re-ramp (when VCC drops to GND) See Figure 18 1 s VCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN - 50 mV) See Figure 19 1 s VCC_GH Level that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 s See Figure 20 1.2 V VCC_GW Glitch width that will not cause a functional disruption when VCCX_GH = 0.5 x VCCx See Figure 20 10 s VPORF Voltage trip point of POR on falling VCC VPORR Voltage trip point of POR on fising VCC (1) MIN TYP 0.7 V 1.4 V TA = -40C to 85C (unless otherwise noted) Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 20 and Table 1 provide more information on how to measure these specifications. VCC VCC_GH Time VCC_GW Figure 20. Glitch Width and Glitch Height VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 21 and Table 1 provide more details on this specification. 24 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 TCA9539 www.ti.com........................................................................................................................................... SCPS202A - AUGUST 2009 - REVISED SEPTEMBER 2009 VCC VPOR VPORF Time POR Time Figure 21. VPOR Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): TCA9539 25 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TCA9539PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA9539RTWR ACTIVE WQFN RTW 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TCA9539PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TCA9539RTWR WQFN RTW 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA9539PWR TCA9539RTWR TSSOP PW 24 2000 367.0 367.0 38.0 WQFN RTW 24 3000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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