DATASHEET RAA212422 FN9326 Rev.0.00 Nov 9, 2018 Wide VIN 1.1A with Low VIN 1.5A Synchronous Buck Regulators Features The RAA212422 is a dual output regulator combining a 1.1A synchronous buck regulator with an input range of 3V to 40V with a 1.5A synchronous buck regulator with an input voltage range of 2.7V to 5.5V. Because both high-side and low-side MOSFETs are integrated for both regulators, the RAA212422 provides an easy to use, high efficiency, low BOM count solution for a variety of applications. * Wide VIN buck regulator * Input voltage: 3V to 40V with 1.1A output current * Internal fixed (500kHz) frequency or adjustable switching frequencies of 300kHz to 2MHz * Internal or external soft-start * Low VIN buck regulator Both regulators feature internal and external compensation, thermal shutdown, and power-good functions. The wide VIN buck regulator switches at a default frequency of 500kHz; however, it can also be programmed using an external resistor from 300kHz to 2MHz. Other features include programmable soft-start and hiccup overcurrent protection. * Input voltage: 2.7V to 5.5V, with 1.5A output current * VOUT range: 0.6V to VIN * Fixed 1MHz switching frequency * Synchronous operation for high efficiency The low VIN buck regulator operates at 1MHz switching frequency, which provides fast load transient response allowing the use of small inductors. Because the high-side MOSFET of the low VIN buck regulator is a PMOS, a boot capacitor is not needed, reducing external component count. They operate at 100% duty cycle and in PWM mode only, reducing noise susceptibility and RF interference. * Integrated high-side and low-side MOS devices * Internal or external compensation option * Power-good and enable functions * Thermal shutdown Applications * Industrial control, medical devices, portable instrumentation, distributed power supplies, and cloud infrastructure The RAA212422 is available in a small RoHS compliant 3mmx6mm TDFN plastic package with a full-range industrial temperature of -40C to +125C. * General purpose point of load DC/DC, set-top boxes and cable modems, FPGA power, DVD, HDD drives, LCD panels, and TV Related Literature For a full list of related documents, visit our website: * RAA212422 device page / 9,1 /; (1 5 %227 &203 9,1 &%227 6<1& )6 &)) &287 )% 9287 100 66 90 5 &9&& *1' / 5$$ /; 9,1 9,1 (1 9,1 &)) &203 &287 )% *1' 5 3* 9287 80 Efficiency (%) 3* 9&& 70 60 50 40 VIN1=12V 30 VIN1=24V 20 VIN1=33V 10 0 5 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 Output Load (A) Figure 1. Typical Application FN9326 Rev.0.00 Nov 9, 2018 Figure 2. Efficiency vs Load, VOUT1 = 5V, L1 = 22H Page 1 of 33 RAA212422 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 1.2 1.3 1.4 1.5 2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 6 6 6 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 2.3 2.4 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 9 9 Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 3.2 4. Efficiency Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5. Power-On Reset /UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft-Start (Wide VIN and Low VIN Buck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Control Scheme (Wide VIN and Low VIN Buck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Discharge Mode/Soft-Stop (Low VIN Buck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100% Duty Cycle (Low VIN Buck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 19 20 20 21 22 22 23 Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Simplifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Frequency (Wide VIN Buck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronization Control (Wide VIN Buck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 24 24 25 25 26 6. Layout Suggestions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8. Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 FN9326 Rev.0.00 Nov 9, 2018 Page 2 of 33 RAA212422 1. 1.1 1. Overview Overview Typical Application Circuits / + 9,1 /; (1 %227 &203 9,1 &%227 6<1& )6 &)) ) 5 )% 66 3* 9&& &9&& ) *1' /; 9,1 9,1 (1 9,1 9287 / + 5$$ 5 &287 ) ) &)) &203 5 &287 ) )% *1' 3* 9287 5 Figure 3. Internal Default Parameter Selection FN9326 Rev.0.00 Nov 9, 2018 Page 3 of 33 RAA212422 1. Overview / + 9,1 /; (1 )6 9,1 %227 3* 5 &)) )% &203 9&& &9&& ) 5 5&203 66 *1' &66 &&203 5$$ / + 9,1 9287 &287 ) ) 6<1& 5)6 &%227 ) 9,1 /; (1 &203 9,1 5 &)) 5&203 3* *1' &&203 9287 &287 ) )% 5 Figure 4. User Programmable Parameter Selection Table 1. Wide VIN Buck Regulator - External Component Selection VOUT1 (V) L1 (H) COUT1 (F) R1 (k) R2 (k) CFF1 (pF) RFS (k) 12 33 2 x 22 90.9 4.75 4.7 115 RCOMP1 (k) CCOMP1 (pF) 200 470 5 22 47 + 22 90.9 12.4 22 DNP (Note 1) 130 470 3.3 22 47 + 22 90.9 20 22 DNP (Note 1) 120 470 2.5 22 47 + 22 90.9 28.7 22 DNP (Note 1) 110 470 1.8 10 47 + 22 90.9 45.5 22 DNP (Note 1) 90 470 Note: 1. Connect FS1 to VCC1. Table 2. Low VIN Buck Regulator - External Component Selection VOUT2 (V) L1 (H) COUT2 (F) R3 (k) R4 (k) CFF2 (pF) RCOMP1 (k) CCOMP1 (pF) 0.8 1.5 2x22 33 100 47 40 270 1.2 2.2 2x22 100 100 22 60 270 1.8 2.2 2x22 200 100 15 80 330 2.5 2.2 2x22 316 100 8.2 100 330 3.3 2.2 2x22 450 100 6.8 120 330 FN9326 Rev.0.00 Nov 9, 2018 Page 4 of 33 RAA212422 1.2 1. Overview Block Diagram 66 (1 3* )% 9,1 0 3RZHU*RRG /RJLF 9&& %LDV /'2 (16RIW6WDUW )% P995() )6 )DXOW /RJLF P9$ &XUUHQW6HQVH 2VFLOODWRU 3:0 *DWH'ULYH DQG 3:0 'HDGWLPH V 4 5 4 0 6<1& %227 /; 3*1' P976ORSH &RPSHQVDWLRQ N ,QWHUQDO $9 ([WHUQDO $9 S) ,QWHUQDO &RPSHQVDWLRQ 3DFNDJH 3DGGOH *1' &203 &203 6KXWGRZQ 6RIW 6WDUW N S) %DQGJDS (1 95() ($03 &203 2VFLOODWRU 9,1 3 3:0/RJLF &RQWUROOHU 3URWHFWLRQ +6'ULYHU 6KXWGRZQ S) /; 1 3*1' )% N 6ORSH &RPS [95() &6$ 29 2&3 [95() 89 9,1 0 1(*&XUUHQW 6HQVLQJ 3* PV 'HOD\ 6KXWGRZQ 9 6&3 Figure 5. Functional Block Diagram FN9326 Rev.0.00 Nov 9, 2018 Page 5 of 33 RAA212422 1.3 1. Overview Ordering Information Part Number (Notes 3, 4) Temp Range (C) Tape and Reel (Units) (Note 2) RAA212422 -40 to +125 - 22 Ld QFN L22.3x6 RAA2124224GNP#HA0 RAA212422 -40 to +125 6k 22 Ld QFN L22.3x6 RAA2124224GNP#MA0 RAA212422 -40 to +125 250 22 Ld QFN L22.3x6 RAA2124224GNP#AA0 Part Marking Package (RoHS Compliant) Pkg. Dwg. # Notes: 2. Refer to TB347 for details about reel specifications 3. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), see the RAA212422 device page. For more information about MSL, see TB363. 1.4 Pin Configurations 22 Ld 3x6 TQFN Top View 1.5 VIN2 1 22 LX2 EN2 2 21 GND2 VIN3 3 20 FB2 PG2 4 19 COMP2 SS1 5 SYNC1 6 BOOT1 7 16 FB1 VIN1 8 15 VCC1 LX1 9 14 PG1 GND1 10 13 EN1 NC1 11 12 NC2 GND (EPAD) 18 FS1 17 COMP1 Pin Descriptions Pin Number Pin Name Description 1 VIN2 Input supply for the power stage of the low VIN PWM regulator and the source for the internal linear regulator that provides bias for the low VIN buck regulator. Place a minimum of 10F ceramic capacitance from VIN2 to GND and as close as possible to the IC for decoupling. The input voltage range is 2.7V to 5.5V. 2 EN2 Device enable input for the low VIN buck regulator. When the input voltage on this pin rises above 1.4V, the device is enabled. The device is disabled when the pin is pulled to ground. A 100 resistor discharges the output through the LX2 pin when the device is disabled. See Figure 5 on page 5 for details. 3 VIN3 Connect VIN3 to VIN2. 4 PG2 Power-good output of the low VIN buck regulator. PG2 is pulled to ground during the soft-start interval and when the output voltage is below regulation limits. An internal 5M pull-up resistor is on this pin. 5 SS1 Controls the soft-start ramp time for the output of the wide VIN buck regulator. A single capacitor from the SS1 pin to ground determines the output ramp rate. See "Soft-Start (Wide VIN and Low VIN Buck)" on page 19 for soft-start details. If the SS1 pin is tied to VCC1, an internal soft-start of 2ms is used. FN9326 Rev.0.00 Nov 9, 2018 Page 6 of 33 RAA212422 1. Overview Pin Number Pin Name Description 6 SYNC1 Synchronization input. Connect to logic high or VCC1 for PWM mode if external synchronization is not used. Connect to an external clock source for synchronization with positive edge trigger. The sync source must be higher than the programmed IC frequency. Do not float this pin or short it to ground. 7 BOOT1 Floating bootstrap supply pin for the power MOSFET gate driver for the wide VIN buck regulator. The bootstrap capacitor provides the necessary charge to turn on the internal N-channel MOSFET. Connect an external 100nF capacitor from this pin to LX1. 8 VIN1 The input supply for the power stage of the wide VIN buck regulator and the source for the internal linear bias regulator. Place a minimum of 4.7F ceramic capacitance from VIN1 to GND1 and close to the IC for decoupling. The input voltage range is 3V to 40V. 9 LX1 Switch node output. It connects the switching FETs with the external output inductor. 10 GND1 Power ground connection. Connect directly to the system GND plane. 11 NC1 12 NC2 13 EN1 Wide VIN buck regulator enable input. The regulator and bias LDO are held off when the pin is pulled to ground. When the voltage on this pin rises above 1V, the chip is enabled. Connect this pin to VIN1 for automatic start-up. Do not connect EN1 pin to VCC1 because the LDO is controlled by EN1 voltage. 14 PG1 Open-drain, power-good output that is pulled to ground when the output voltage of the wide VIN buck regulator is below regulation limits or during the soft-start interval. An internal 5M pull-up resistor is on this pin. 15 VCC1 16 FB1 17 COMP1 18 FS1 19 COMP2 Low VIN buck regulator error amplifier. When COMP2 is tied high to VIN2, internal compensation is used. When COMP2 is connected with a series resistor and capacitor to GND, external compensation is used. See "Loop Compensation Design" on page 26 for more details. 20 FB2 Feedback pin for the low VIN buck regulator. FB2 is the negative input to the voltage loop error amplifier. The output voltage is set by an external resistor divider connected to FB2. In addition, the power-good PWM regulator's power-good and undervoltage protection circuits use FB2 to monitor the output voltage. 21 GND2 22 LX2 Power stage switching node for output voltage regulation of the low VIN buck regulator. Connect to the output inductor. This pin is discharged by a 100 resistor when the device is disabled. See Figure 5 on page 5 for details. EPAD GND Ground connection. Connect to the application board GND plane with at least five vias. All voltage levels are measured with respect to this pin. The EPAD MUST NOT float. FN9326 Rev.0.00 Nov 9, 2018 No connect Output of the wide VIN buck regulator's internal 5V linear bias regulator. Decouple to GND with a 1F ceramic capacitor at the pin. Feedback pin for the wide VIN buck regulator. FB1 is the inverting input to the voltage loop error amplifier. COMP1 is the output of the error amplifier. The output voltage is set by an external resistor divider connected to FB1. In addition, the PWM regulator's power-good and UVLO circuits use FB1 to monitor the regulator output voltage. Error amplifier output. When this pin is tied to VCC1, internal compensation is used. When only an RC network is connected from COMP1 to GND1, external compensation is used. See "Loop Compensation Design" on page 26 for more details. Frequency selection pin for the wide VIN buck regulator. Tie to VCC1 for 500kHz switching frequency. Connect a resistor to GND1 for adjustable frequency from 300kHz to 2MHz. Power ground for low VIN buck regulator. Connect directly to the system ground plane. Page 7 of 33 RAA212422 2. 2. Specifications Specifications 2.1 Absolute Maximum Ratings Parameter Minimum Maximum Unit VIN1 to GND -0.3 +43 V LX1 to GND (DC) -0.3 VIN1 + 0.3 V LX1 to GND (20ns) -2.0 +44 V EN1 to GND -0.3 +43 V BOOT1 to LX1 -0.3 +5.5 V COMP1, FS1, PG1, SYNC1, SS1 VCC1 to GND -0.3 +5.9 V FB1 to GND -0.3 +2.95 V VIN2 to GND (DC) -0.3 +6 V VIN2 to GND (20ms) -0.3 +7 V LX2 to GND (DC) -0.3 +6 V LX2 to GND (100ns) -1.5 +7 V LX2 to GND (20ms) -0.3 +7 V EN2, COMP2, PG2, MODE2 -0.3 VIN2 + 0.3 V FB2 -0.3 +2.7 V Value Unit Human Body Model (Tested per JS-001-2017) ESD Rating 2 kV Charged Device Model (Tested per JS-002-2014) 1 kV Latch-Up (Tested per JESD78E; Class 2, Level A) 100mA mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. 2.2 Thermal Information Thermal Resistance (Typical) 22 Ld 3x6 QFN Package (Notes 5, 6) JA (C/W) JC (C/W) 31.3 2.3 Notes: 5. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with "direct attach" features. See TB379. 6. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. Parameter Minimum Maximum Junction Temperature Maximum Unit +150 C Maximum Storage Temperature Range -65 +150 C Ambient Temperature Range -40 +125 C Pb-Free Reflow Profile FN9326 Rev.0.00 Nov 9, 2018 Refer to TB493 Page 8 of 33 RAA212422 2.3 2. Specifications Recommended Operating Conditions Minimum Maximum Unit Supply Voltage, VIN1 Parameter 3 40 V Supply Voltage, VIN2 2.7 5.5 V Junction Temperature -40 +125 C 2.4 Electrical Specifications VIN1 = 3V to 40V, unless otherwise noted. Typical values are at TA = +25C. Parameter Symbol Test Conditions Min (Note 9) Typ Max (Note 9) Unit Wide VIN Buck Regulator Supply Voltage VIN1 Voltage Range VIN1 VIN1 Quiescent Supply Current IQ1 VFB1 = 0.7V, SYNC1 = VCC1 3 8 VIN1 Shutdown Supply Current ISD1 EN1 = 0V, VIN1= 40V (Note 7) 2 6 A VCC1 Voltage VCC1 VIN1 = 6V, IOUT1 = 0 to 10mA 5.1 5.7 V 2.75 2.95 V 4.5 40 V mA Power-On Reset VCC1 POR Threshold Rising edge Falling edge 2.35 2.6 V Oscillator Nominal Switching Frequency fSW1 FS1 pin = VCC1 430 500 570 kHz Resistor from FS1 pin to GND = 340k 240 300 360 kHz Resistor from FS1 pin to GND = 32.4k 2000 kHz tOFF1 VIN1 = 3V 150 ns Minimum On-Time tON1 (Note 10) FS1 Voltage VFS1 RFS1 = 100k Minimum Off-Time Synchronization Frequency SYNC1 90 0.39 0.4 300 SYNC1 Pulse-Width ns 0.41 V 2000 kHz 100 ns Error Amplifier Error Amplifier Transconductance Gain gm1 FB1 Leakage Current Current Sense Amplifier Gain FB1 Voltage External compensation 165 230 Internal compensation 50 VFB1 = 0.6V 1 RT1 TA = -40C to +125C 295 A/V A/V 150 nA 0.44 0.5 0.55 V/A 0.590 0.599 0.607 V 90 94 % Power-Good Lower PG1 Threshold - VFB1 Rising Lower PG1 Threshold - VFB1 Falling 82.5 Upper PG1 Threshold - VFB1 Rising 116.5 Upper PG1 Threshold - VFB1 Falling PG1 Propagation Delay FN9326 Rev.0.00 Nov 9, 2018 86 107 Percentage of the soft-start time % 120 % 112 % 10 % Page 9 of 33 RAA212422 2. Specifications VIN1 = 3V to 40V, unless otherwise noted. Typical values are at TA = +25C. (Continued) Parameter Symbol PG1 Low Voltage Test Conditions Min (Note 9) ISINK = 3mA, EN1 = VCC, VFB1 = 0V Typ Max (Note 9) Unit 0.05 0.3 V Tracking and Soft-Start (SS1) Soft-Start Charging Current ISS1 Internal Soft-Start Ramp Time EN1/SS1 = VCC1 4.2 5.5 6.7 A 1.5 2.4 3.4 ms Fault Protection Thermal Shutdown Temperature TSD Rising threshold 150 THYS Hysteresis C 25 C Current Limit Blanking Time tOCON 17 Clock pulses Overcurrent and Auto Restart Period tOCOFF 8 SS cycle Positive Peak Current Limit IPLIMIT (Note 8) 1.3 1.6 INLIMIT (Note 8) -0.68 -0.6 High-Side RHDS ILX1 = 100mA, VCC = 5V 312 Low-Side RLDS ILX1 = 100mA, VCC = 5V 173.8 Zero Cross Threshold Negative Current Limit 1.8 15 A mA -0.53 A Power MOSFET PHASE Leakage Current PHASE Rise Time EN1 = LX1 = 0V tRISE m m 300 VIN1 = 40V 10 nA ns EN1/SYNC1 Input Threshold Falling edge, logic low 0.4 Rising edge, logic high 1 1.2 -0.65 V 1.4 V 0.65 A EN1 Logic Input Leakage Current EN1 = 0V/40V SYNC1 Logic Input Leakage Current SYNC1 = 0V 10 100 nA SYNC1 = 5V 1.0 1.55 A Rising, no load 2.5 2.7 V Low VIN Buck Regulator Input Supply VIN2 Undervoltage Lockout Threshold VUVLO2 Quiescent Supply Current IVIN2 fSW = 1MHz, no load at the output 7 15 mA Shut Down Supply Current ISD2 VIN2 = 5.5V, EN2 = low 5 10 A Falling, no load 2.2 2.4 V Output Regulation TJ = +25C 0.595 TJ = -40C to +125C 0.582 VFB2 = 2.7V. TJ = -40C to +125C -120 Line Regulation VIN2 = VO + 0.5V to 5.5V (minimal 2.7V) TJ = -40C to +125C -0.2 Load Regulation See Note 11 Feedback Voltage VFB2 Bias Current Soft-Start Ramp Time Cycle FN9326 Rev.0.00 Nov 9, 2018 VFB2 IVFB2 0.600 0.605 V 0.605 V 50 350 nA -0.05 0.1 %/V < -0.2 %/A 1 ms Page 10 of 33 RAA212422 2. Specifications VIN1 = 3V to 40V, unless otherwise noted. Typical values are at TA = +25C. (Continued) Parameter Symbol Test Conditions Min (Note 9) Typ Max (Note 9) Unit 2.1 2.5 2.9 A -170 -70 30 mA -2.3 -1.75 -1 A Protections Positive Peak Current Limit IPLIMIT 1.5A application Zero Cross Threshold Negative Current Limit INLIMIT Thermal Shutdown Temperature rising 150 C Thermal Shutdown Hysteresis Temperature falling 25 C COMP2 tied VIN2 40 A/V COMP2 with RC 160 A/V Compensation Error Amplifier Transconductance Transresistance RT 0.24 0.3 0.40 Power MOSFETs P-Channel MOSFET ON-Resistance VIN2 = 5V, IO2 = 200mA 117 m N-Channel MOSFET ON-Resistance VIN2 = 5V, IO2 = 200mA 86 m 100 % LX2 Maximum Duty Cycle LX2 Minimum On-Time (Note 10) 60 85 ns 850 1000 1150 kHz 0.5 1 Oscillator Nominal Switching Frequency fSW2 Power-Good Output Low Voltage 1mA sinking current Delay Time (Rising Edge) PGOOD Delay Time (Falling Edge) 0.3 V 2 ms 15 PG2 Pin Leakage Current PG2 = VIN2 OVP PG2 Rising Threshold 110 OVP PG2 Hysteresis s 0.01 0.1 A 119 122 % 5 UVP PG2 Rising Threshold 80 UVP PG2 Hysteresis 85 % 90 5 % % Enable Logic Logic Input Low 0.4 V Logic Input High Logic Input Leakage Current IMODE2 Pulled up to 5.5V 5.5 1.4 V 8 A Notes: 7. Test conditions: VIN1 = 40V, FB1 forced above regulation point (0.6V), no switching, and power MOSFET gate charging current not included. 8. Established by both current sense amplifier gain test and current sense amplifier output test at IL = 0A. 9. Parameters with Min and/or Max limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. Minimum On-Time required to maintain loop stability. 11. Not tested in production. Characterized using evaluation board. Refer to load regulation diagrams (Figures 12 through 15). +105C TA represents near worst case operating point. FN9326 Rev.0.00 Nov 9, 2018 Page 11 of 33 RAA212422 3. 3. Typical Performance Curves Typical Performance Curves 3.1 Efficiency Curves Wide VIN Buck fSW = 500kHz, TA = +25C 100 100 90 80 80 70 70 Efficiency (%) Efficiency (%) 90 60 50 40 VIN1=12V 30 VIN1=24V 20 VIN1=33V 10 60 50 40 VIN1=12V 30 VIN1=24V 20 VIN1=33V 10 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 1.1 0.0 Output Load (A) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Figure 6. Efficiency vs Load, VOUT1 = 5V, L1 = 22H, 0.9 1.0 1.1 Figure 7. Efficiency vs Load, VOUT1 = 3.3V, L1 = 22H 5.10 3.40 VIN1=12V 5.05 Output Voltage (V) VIN1=12V Output Voltage (V) 0.8 Output Load (A) VIN1=24V VIN1=33V 5.00 4.95 4.90 VIN1=24V 3.35 VIN1=33V 3.30 3.25 3.20 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 Output Load (A) Output Load (A) Figure 8. VOUT Regulation vs Load, VOUT1 = 5V Figure 9. VOUT Regulation vs Load vs Load, VOUT1 = 3.3V 110 100 90 80 70 60 50 40 30 20 10 0 3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 0 0.2 0.4 0.6 0.8 Efficiency (%) Efficiency (%) Low VIN Buck fSW = 1MHz, TA = +25C 0.9VOUT 1 1.2 1.4 1.6 Output Load (A) Figure 10. Efficiency vs Load, VIN2 = 5V, TA = +25C FN9326 Rev.0.00 Nov 9, 2018 110 100 90 80 70 60 50 40 30 20 10 0 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 0.9VOUT 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Output Load (A) Figure 11. Efficiency vs Load, VIN2 = 3.3V, TA = +25C Page 12 of 33 RAA212422 3. Typical Performance Curves Low VIN Buck fSW = 1MHz, TA = +25C (Continued) 1.9 Output Voltage (V) Output Voltage (V) 1.3 1.25 1.2 3.3VIN 1.15 1.85 1.8 3.3VIN 1.75 5VIN 5VIN 1.7 1.1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 1.6 0.2 0.4 Figure 12. VOUT Regulation vs Load, VOUT2 = 1.2V, TA = +25C 0.8 1 1.2 1.4 1.6 Figure 13. VOUT Regulation vs Load, VOUT2 = 1.8V, TA = +25C 3.4 Output Voltage (V) 2.6 Output Voltage (V) 0.6 Output Load (A) Output Load (A) 3.3VIN 2.55 5VIN 2.5 2.45 5VIN 3.35 3.3 3.25 3.2 2.4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Output Load (A) Figure 14. VOUT Regulation vs Load, VOUT2 = 2.5V, TA = +25C FN9326 Rev.0.00 Nov 9, 2018 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Output Load (A) Figure 15. VOUT Regulation vs Load, VOUT2 = 3.3V, TA = +25C Page 13 of 33 RAA212422 3.2 3. Typical Performance Curves Measurements Wide VIN Buck Measurements fSW = 500kHz, VIN1 = 24V, VOUT1 = 5V, TA = +25C LX1 20V/Div LX1 20V/Div VOUT1 2V/Div VOUT1 2V/Div EN1 5V/Div EN1 5V/Div PG1 5V/Div PG1 5V/Div 2ms/Div 100ms/Div Figure 16. Start-Up at No Load Figure 17. Shutdown at No Load LX1 20V/Div LX1 20V/Div VOUT1 2V/Div VOUT1 2V/Div IL1 1A/Div IL1 1A/Div PG1 5V/Div PG1 5V/Div 2ms/Div 200s/Div Figure 18. Start-Up at 1.1A Figure 19. Shutdown at 1.1A LX1 20V/Div LX1 20V/Div VOUT1 20mV/Div VOUT1 20mV/Div IL1 200mA/Div 1s/Div Figure 20. Steady State at No Load FN9326 Rev.0.00 Nov 9, 2018 IL1 1A/Div 1s/Div Figure 21. Steady State at 1.1A Load Page 14 of 33 RAA212422 3. Typical Performance Curves Wide VIN Buck Measurements fSW = 500kHz, VIN1 = 24V, VOUT1 = 5V, TA = +25C (Continued) VOUT1 100mV/Div LX1 20V/Div VOUT1 20mV/Div IL1 200mA/Div IOUT1 1A/Div 200s/Div 1s/Div Figure 22. Light Load Operation at 20mA Figure 23. Load Transient LX1 20V/Div LX1 20V/Div VOUT1 2V/Div VOUT1 2V/Div IL1 1A/Div IL1 1A/Div PG1 5V/Div PG1 5V/Div 40s/Div 10ms/Div Figure 24. Overcurrent Protection Figure 25. Overcurrent Protection Hiccup LX1 20V/Div LX1 20V/Div VOUT1 2V/Div SYNC1 2V/Div IL1 1A/Div PG1 5V/Div 1s/Div 20s/Div Figure 26. Sync at 550kHz, 1.1A Load Figure 27. Negative Current Limit FN9326 Rev.0.00 Nov 9, 2018 Page 15 of 33 RAA212422 3. Typical Performance Curves Wide VIN Buck Measurements fSW = 500kHz, VIN1 = 24V, VOUT1 = 5V, TA = +25C (Continued) LX1 20V/Div VOUT1 2V/Div IL1 1A/Div PG1 5V/Div 200s/Div Figure 28. Negative Current Limit Recovery Low VIN Buck Measurements Unless otherwise noted: VIN2 = 5V, VOUT2 = 1.2V, CIN2 = COUT2 = 2x22F, TJ = +25C, ILOAD = 0A LX2 5V/Div VOUT2 0.5V/Div EN2 5V/Div PG2 5V/Div 2ms/Div Figure 29. Start-Up by Enable at No Load, VIN2 = 5V, TA = +25C LX2 5V/Div LX2 5V/Div VOUT2 0.5V/Div VOUT2 0.5V/Div EN2 5V/Div EN2 5V/Div PG2 PG2 5V/Div 5V/Div 2ms/Div 2ms/Div Figure 30. Shutdown by Enable at No Load, VIN2 = 5V, TA = +25C Figure 31. Start-Up by Enable at 1.5A Load, VIN2 = 5V, TA = +25C FN9326 Rev.0.00 Nov 9, 2018 Page 16 of 33 RAA212422 3. Typical Performance Curves Low VIN Buck Measurements Unless otherwise noted: VIN2 = 5V, VOUT2 = 1.2V, CIN2 = COUT2 = 2x22F, TJ = +25C, ILOAD = 0A LX2 5V/Div LX2 5V/Div VOUT2 0.5V/Div VOUT2 0.5V/Div VIN2 5V/Div EN2 5V/Div PG2 PG2 5V/Div 5V/Div 2ms/Div 2ms/Div Figure 32. Shutdown by Enable at 1.5A Load, VIN2 = 5V, TA = +25C Figure 33. Start-Up by VIN2 at No Load, VIN2 = 5V, TA = +25C LX2 5V/Div LX2 5V/Div VOUT2 0.5V/Div VOUT2 0.5V/Div VIN2 5V/Div VIN2 5V/Div PG2 5V/Div PG2 5V/Div 2ms/Div 2ms/Div Figure 34. Start-Up by VIN2 at 1.5A Load, VIN2 = 5V, TA = +25C Figure 35. Shutdown by VIN2 at No Load, VIN2 = 5V, TA = +25C LX2 5V/Div LX2 5V/Div VOUT2 20mV/Div VOUT2 0.5V/Div VIN2 5V/Div IL2 PG2 0.5A/Div 5V/Div 2ms/Div 400ns/Div Figure 36. Shutdown by VIN2 at 1.5A Load, VIN2 = 5V, TA = +25C Figure 37. Steady State at No Load, VIN2 = 5V, TA = +25C FN9326 Rev.0.00 Nov 9, 2018 Page 17 of 33 RAA212422 3. Typical Performance Curves Low VIN Buck Measurements Unless otherwise noted: VIN2 = 5V, VOUT2 = 1.2V, CIN2 = COUT2 = 2x22F, TJ = +25C, ILOAD = 0A LX2 5V/Div VOUT2 50mV/Div VOUT2 0.5V/Div IL2 IOUT2 1A/Div 2A/Div PG2 5V/Div 200s/Div 2ms/Div Figure 38. Load Transient, VIN2 = 5V, TA = +25C Figure 39. Output Short-Circuit, VIN2 = 5V, TA = +25C LX2 5V/Div VOUT2 0.5V/Div IL2 VOUT2 1V/Div 1A/Div IL2 2A/Div PG2 5V/Div PG2 5V/Div 200s/Div 10s/Div Figure 40. Overcurrent Protection, VIN2 = 5V, TA = +25C Figure 41. Overvoltage Protection, VIN2 = 5V, TA = +25C TA=160 VOUT2 0.5V/Div PG2 5V/Div 800s/Div Figure 42. Over-Temperature Protection, VIN2 = 5V, TA = +160C FN9326 Rev.0.00 Nov 9, 2018 Page 18 of 33 RAA212422 4. 4. Detailed Description Detailed Description The RAA212422 consists of a constant frequency current mode wide VIN buck regulator and a low VIN buck regulator. The wide VIN buck regulator can operate from an unregulated DC source, such as a battery, with a voltage ranging from +3V to +40V. An internal linear regulator provides bias to the low voltage portions of the wide VIN buck regulator. Peak current mode control simplifies feedback loop compensation and rejects input voltage variation. User-selectable internal feedback loop compensation further simplifies design. The buck regulator is equipped with an internal current sensing circuit and the peak current limit threshold is typically set at 1.6A. The low VIN switching regulator operates at 1MHz switching frequency, which enables the use of smaller inductors resulting in small form factor while also providing excellent efficiency. The supply current is typically only 2A when the regulator is shut down. 4.1 Power-On Reset /UVLO The wide VIN buck regulator automatically initializes after receiving the input power supply and continually monitors the EN1 pin state. If EN1 is held below its logic rising threshold, the IC is held in shutdown and consumes typically 2A from the VIN1 supply. If EN1 exceeds its logic rising threshold, the regulator enables the bias linear regulator and begins to monitor the VCC1 pin voltage. When the VCC1 pin voltage passes its rising POR threshold, the controller initializes the switching regulator circuits. If VCC1 never passes the rising POR threshold, the controller does not allow the switching regulator to operate. If VCC1 falls below its falling POR threshold while the switching regulator is operating, the switching regulator shuts down until VCC1 returns. When the low VIN buck regulator's input voltage rises above a typical value of 2.5V, the regulator is allowed to turn on. When the input voltage falls below the Undervoltage Lockout (UVLO) threshold, the regulator is disabled. 4.2 Soft-Start (Wide VIN and Low VIN Buck) Both the wide VIN and low VIN buck converters feature soft-start to avoid large inrush current. For the buck converters, VOUT1 (VOUT2) is slowly increased at start-up to its final regulated value. For the wide VIN buck regulator, soft-start time is determined by the SS1 pin connection. If SS1 is pulled to VCC1, an internal 2ms timer is selected for soft-start. For other soft-start times, connect a capacitor from SS1 to GND. In this case, a 5.5A current pulls up the SS1 voltage and the FB1 pin follows this ramp until it reaches the 600mV reference level. The wide VIN buck regulator soft-start time is described by Equation 1: (EQ. 1) Time ms = C nF 0.109 For the low VIN buck regulator, when the VIN2 pin exceeds its rising POR trip point (nominal 2.5V), the device begins operation. If the EN2 pin is held low externally, nothing happens until this pin is released. When EN2 is released and is above the logic threshold, the internal default soft-start time is 1ms. The typical soft-start time for the low VIN buck regulator is 1ms. 4.3 Power-Good PG1 is the open-drain output of a window comparator that continuously monitors the wide VIN buck regulator output voltage using the FB1 pin. PG1 is actively held low when EN1 is low and during the buck regulator soft-start period. After the soft-start period completes, PG1 becomes high impedance if the FB1 pin is within the range specified in the "Electrical Specifications" on page 9. If FB1 exits the specified window, PG1 is pulled low until FB1 returns. Over-temperature faults also force PG1 low until the fault condition is cleared by an attempt to soft-start. An internal 5M pull-up resistor is on the PG1 pin. The window comparator output, PG2, continuously monitors the low VIN buck regulator output voltage. PG2 is actively held low when EN2 is low and during the buck regulator soft-start period. After 1ms delay of the soft-start period, PG2 becomes high impedance as long as the output voltage is within nominal regulation voltage set by VFB2. When VFB2 drops 15% below or raises 15% above the nominal regulation voltage, the device pulls PG2 low. Any fault condition forces PG2 low until the fault condition is cleared by attempts to soft-start. An internal FN9326 Rev.0.00 Nov 9, 2018 Page 19 of 33 RAA212422 4. Detailed Description 5M pull-up resistor is on the PG2 pin. You can add an external resistor from PG2 to VIN2 for more pull-up strength. 4.4 PWM Control Scheme (Wide VIN and Low VIN Buck) Both the wide VIN and low VIN buck regulators employ peak current-mode Pulse-Width Modulation (PWM) control for fast transient response and pulse-by-pulse current limiting, as shown in Figure 5 on page 5. The current loop consists of the current-sensing circuit, slope compensation ramp, PWM comparator, oscillator, and latch. The current sense gain for the wide VIN buck regulator is typically 500mV/A and the slope compensation rate, Se1, is typically 450mV/T, where T is the switching cycle period. The current sense gain for the low VIN buck regulator is typically 300mV/A and the slope compensation rate, Se2, is typically 900mV/s. The control reference for the current loop comes from the error amplifier's output (VCOMP1 for wide VIN and VCOMP2 for low VIN buck regulator). A PWM cycle begins when a clock pulse sets the PWM latch and the upper FET turns on. The current begins to ramp up in the upper FET and inductor. This current is sensed, converted to a voltage (VCSA), and summed with the slope compensation signal. This combined signal is compared to VCOMP1 (VCOMP2) and the latch is reset when the signal is equal to VCOMP1 (VCOMP2). Upon latch reset the upper FET turns off and the lower FET turns on, allowing current to ramp down in the inductor. The lower FET remains on until the clock initiates another PWM cycle. Figure 43 shows the typical operating waveforms during PWM operation. The dotted lines illustrate the sum of the current sense and slope compensation signal. VCOMP VCSA Duty Cycle IL VOUT Figure 43. PWM Operation Waveforms The output voltage is regulated as the error amplifier varies VCOMP1 (VCOMP2) and thus varies the output inductor current. The error amplifier is a transconductance type and its output (COMP1 or COMP2) is terminated with a series RC network to GND. This termination is internal (150k/54pF) if the COMP1 pin is tied to VCC1 for the wide VIN buck. For the low VIN buck, the termination is a 200k and 27pF series R-C network. In addition, the transconductance for COMP1 = VCC1 is 50A/V vs 230A/V for external R-C connection. Its non-inverting input is internally connected to a 600mV reference voltage and its inverting input is connected to the output voltage using the FB1 pin and its associated divider network. The maximum error amplfier voltage of the low VIN buck (COMP2) is clamped to 1.6V. 4.5 Output Voltage Selection The regulator output voltage is easily programmed using an external resistor divider to scale VOUT1 relative to the internal reference voltage. The scaled voltage is applied to the inverting input of the error amplifier; refer to Figure 44 on page 21 for more information. The output voltage programming resistor, R2, depends on the value chosen for the feedback resistor, R1, and the desired output voltage, VOUT1, of the regulator. Equation 2 describes the relationship between VOUT1 and the resistor values. FN9326 Rev.0.00 Nov 9, 2018 Page 20 of 33 RAA212422 4. Detailed Description R 1 0.6V R 2 = -------------------------------------V OUT1 - 0.6V (EQ. 2) If the output voltage is 0.6V, R2 is left unpopulated and R1 is 0. VOUT1 FB2 + - Wide VIN Buck EA R1 R2 0.6V Reference Low VIN Buck EA R3 + - FB1 VOUT2 R4 0.6V Reference Figure 44. External Resistor Divider Similarly, the output voltage of the low VIN buck can be set by an external resistor divider network. Calculate the values of resistors R3 and R4 using Equation 3. R 3 0.6V R 4 = -------------------------------------V OUT2 - 0.6V (EQ. 3) If the target output voltage is 0.6V, R4 is left unpopulated and R3 is shorted. There is a leakage current from VIN2 to LX2. Renesas recommends preloading the output with 10A minimum. For better performance, add a feedforward capacitor in parallel with R1Check loop analysis before use in an application. 4.6 Protection Features The RAA212422 is protected from overcurrent, negative overcurrent, over-temperature, and boot undervoltage. The protection circuits operate automatically. 4.6.1 Overcurrent Protection During PWM on-time of the wide VIN buck regulator, current through the upper FET is monitored and compared to a nominal 1.6A peak overcurrent limit. If the current reaches the limit, the upper FET turns off until the next switching cycle. In this way, FET peak current is always well limited. If the overcurrent condition persists for typically 17 sequential clock cycles, the regulator begins its hiccup sequence. In this case, both FETs turn off and PG1 is pulled low. This condition is maintained for eight soft-start periods, after which the regulator attempts a normal soft-start. If the output fault persists, the regulator repeats the hiccup sequence indefinitely. Output faults are not dangerous even if the output is shorted during soft-start. If VOUT1 is shorted very quickly, FB1 may collapse below 5/8 of its target value before the typical 17 cycles of overcurrent are detected. The RAA212422 recognizes this condition and begins to lower its switching frequency proportional to the FB1 pin voltage. This ensures that the current never runs away (even with VOUT1 near 0V). The low VIN buck regulator is protected from overcurrent by monitoring the CSA output with the OCP comparator, as shown in the Figure 5 on page 5. The current-sensing circuit has a gain of 300mV/A from the P-FET current to the CSA output. When the CSA output reaches a threshold, the OCP comparator is tripped to turn off the P-FET immediately. The overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper MOSFET. Upon detection of an overcurrent condition, the upper MOSFET immediately turns off and does not turn on again until the next switching cycle. If the overcurrent condition stops, the output resumes back into regulation point. FN9326 Rev.0.00 Nov 9, 2018 Page 21 of 33 RAA212422 4.6.2 4. Detailed Description Short-Circuit Protection (Low VIN Buck) The low VIN buck regulator Short-Circuit Protection (SCP) comparator monitors the VFB2 pin voltage for output short-circuit faults. When the VFB2 voltage is lower than 0.3V, the SCP comparator forces the PWM oscillator frequency to drop below the normal operation value. This comparator is effective during startup or an output short-circuit event. 4.6.3 Negative Current Limit For the wide VIN buck regulator, if an external source drives current into VOUT1, the controller attempts to regulate VOUT1 by reversing its inductor current to absorb the externally sourced current. If the external source is low impedance, the current may be reversed to unacceptable levels and the controller initiates its negative current limit protection. Similar to normal overcurrent, negative current protection is enabled by monitoring the current through the lower FET. When the valley point of the inductor current reaches negative current limit, the lower FET is turned off and the upper FET is forced on until current reaches the positive current limit or an internal clock signal is issued. At this point, the lower FET is allowed to operate. If the current is again pulled to the negative limit on the next cycle, the upper FET is forced on and the current is forced to 1/6 of the positive current limit. At this point, the controller turns off both FETs and waits for COMP1 to indicate return to normal operation. During this time, the controller applies a 100 load from LX1 to PGND and attempt to discharge the output. Negative current limit is a pulse-by-pulse style operation and recovery is automatic. For the low VIN buck regulator, similar to the overcurrent, the negative current protection is enabled by monitoring the current across the low-side N-FET, as shown in Figure 5 on page 5. When the valley point of the inductor current reaches -1.5A for two consecutive cycles, both P-FET and N-FET shut off. The 100 in parallel to the N-FET activates discharging the output into regulation. The control begins to switch when output is within regulation. 4.6.4 Over-Temperature Protection Over-temperature protection limits the maximum junction temperature of both the wide VIN and low VIN buck regulators in the RAA212422. When the junction temperature (TJ) of the wide VIN buck converter exceeds +150C, both FETs are turned off and the controller waits for the temperature to decrease by approximately 25C. During this time PG1 is pulled low. When the temperature is within an acceptable range, the controller initiates a normal soft-start sequence. For continuous operation, do not exceed the +125C junction temperature rating. For the low VIN buck regulator, when the internal temperature reaches +150C, the regulator is completely shut down. As the temperature drops by 25C, the device resumes operation by stepping through the soft-start. 4.6.5 Boot Undervoltage Protection (Wide VIN Buck) During PWM operation near dropout (VIN1 near VOUT1), the regulator may hold the upper FET on for multiple clock cycles. To prevent the boot capacitor from discharging, the lower FET is forced on for approximately 200ns every 10 clock cycles. 4.7 Discharge Mode/Soft-Stop (Low VIN Buck) When a transition to shutdown mode occurs or the VIN UVLO is set, the output discharges to GND through an internal 100 switch. 4.8 100% Duty Cycle (Low VIN Buck) The RAA212422 features 100% duty cycle operation to maximize the battery life. When the battery voltage drops to a level at which the device can no longer maintain the regulation at the output, the regulator completely turns on the P-FET. The maximum dropout voltage under the 100% duty cycle operation is the product of the load current and the ON-resistance of the P-FET. FN9326 Rev.0.00 Nov 9, 2018 Page 22 of 33 RAA212422 4.9 4. Detailed Description Power Derating Characteristics To prevent the buck regulators from exceeding the maximum junction temperature, some thermal analysis is required. The temperature rise is given by Equation 4: (EQ. 4) T RISE = PD JA where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by Equation 5: (EQ. 5) T J = T A + T RISE where TA is the ambient temperature. The actual junction temperature should not exceed the absolute maximum junction temperature of +125C when considering the thermal design. FN9326 Rev.0.00 Nov 9, 2018 Page 23 of 33 RAA212422 5. 5. Application Guidelines Application Guidelines 5.1 Simplifying the Design Although the wide VIN buck converter of RAA212422 offers user programmed options for most parameters, the easiest implementation with fewest components involves selecting internal settings for SS1, COMP1, and FS1. The low VIN buck converter offers both internal and external compensation options. Tables 1 and 2 on page 4 provide component value selections for a variety of output voltages for the wide VIN and low VIN buck regulators and allow the designer to implement solutions with minimal effort. X5R or X7R ceramic capacitors are recommended for small solution size and low profile designs. 5.2 Operating Frequency (Wide VIN Buck) The RAA212422 wide VIN buck converter operates at a default switching frequency of 500kHz if the FS1 pin is tied to VCC1. Tie a resistor from the FS1 pin to GND to program the switching frequency from 300kHz to 2MHz, as shown in Equation 6. (EQ. 6) R FS1 k = 108.75k t - 0.2s 1s where: t is the switching period in s Figure 45 shows the desired switching frequency and its corresponding RFS1. 400 RFS1 (k) 300 200 100 0 250 500 750 1000 1250 1500 1750 2000 fSW (kHz) Figure 45. RFS1 Selection vs fSW 5.3 Synchronization Control (Wide VIN Buck) The wide VIN buck converter operation frequency can be synchronized up to 2MHz by an external signal applied to the SYNC1 pin. The rising edge on the SYNC1 triggers the rising edge of LX1. To properly synchronize, the external source must be at least 10% greater than the programmed free running IC frequency. 5.4 Output Inductor Selection The inductor value determines the converter's ripple current. A reasonable starting point for choosing the ripple current, I, is 30% of the total load current. You can calculate the inductor value using Equation 7: (EQ. 7) FN9326 Rev.0.00 Nov 9, 2018 V IN - V OUT V OUT L = -------------------------------- ---------------V IN f SW I Page 24 of 33 RAA212422 5. Application Guidelines As an example, using VIN1 = 24V, VOUT1 = 5V, fsw = 500kHz, IOUT1 = 1.1A, and i/IOUT1 = 30%, the inductance is calculated as follows: (EQ. 8) 24V - 5V 5V L 1 = ------------------------------------------------------- ----------- = 24H 500kHz 0.3 1.1A 24V Choose a standard inductance value of 22H. Increasing the inductance value reduces the ripple current and thus the ripple voltage. However, the larger inductance value may reduce the converter's response time to a load transient. The inductor current rating should be such that it does not saturate in overcurrent conditions. For typical RAA212422 applications, inductor values are generally in the 10H to 47H range for the wide VIN buck regulator and 1H to 2.2H for the low VIN buck regulator. Generally, higher VOUT requires higher inductance. 5.5 Input Capacitor Selection The main functions for the input capacitor are to provide decoupling of the parasitic inductance and a filtering function to prevent the switching current from flowing back to the battery rail. A good starting point for input capacitor selection is to use at least two 10F for the wide VIN buck regulator and at least two 22F for the low VIN buck regulator, X5R or X7R ceramic capacitors. 5.6 Output Capacitor Selection An output capacitor is required to filter the inductor current. Output ripple voltage and transient response are two critical factors when considering an output capacitance choice. The current mode control loop allows the use of low ESR ceramic capacitors and enables small solution size on the PCB. You can also use electrolytic and polymer capacitors. Although ceramic capacitors offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered. Ceramic capacitors are rated using large peak-to-peak voltage swings and with no DC bias. In DC/DC converter applications, these conditions do not reflect reality. As a result, the actual capacitance may be considerably lower than the advertised value. Consult the manufacturer's datasheet to determine the actual in-application capacitance. Most manufacturers publish capacitance vs DC bias so that this effect can be easily accommodated. The effects of AC voltage are not frequently published. The result of these considerations may require an effective capacitance much lower than nominal and this value should be used in all design calculations. However, ceramic capacitors are a very good choice in many applications due to their reliability and extremely low ESR. Use Equation 9 to calculate the required capacitance to meet the ripple voltage level. Additional capacitance can be used. (EQ. 9) ESL V IN I V OUTripple = ------------------------------------------ + I ESR + --------------------------- L C 8 f SW OUT where: * I is the inductor's peak-to-peak ripple current * fSW is the switching frequency * COUT is the output capacitor * ESR is the equivalent series resistance of the output capacitor * ESL is the equivalent series inductance of the output capacitor * L is the output filter inductance FN9326 Rev.0.00 Nov 9, 2018 Page 25 of 33 RAA212422 5.7 5. Application Guidelines Loop Compensation Design When COMP1 is not connected to VCC1, the COMP1 pin is active for external loop compensation. The RAA212422 buck converter uses constant frequency peak current mode control architecture to achieve a fast loop transient response. An accurate current sensing pilot device in parallel with the upper MOSFET is used for peak current control signal and overcurrent protection. The inductor is not considered a state variable because its peak current is constant and the system becomes a single order system. It is much easier to design a Type II compensator to stabilize the loop than to implement voltage mode control. Peak current mode control has an inherent input voltage feed-forward function to achieve good line regulation. Figure 46 shows the small signal model of the synchronous buck regulator. + ^ iin ILd^ 1:D ^ Vin + ^ iL LP RLP Vin d^ RT Gain (VLOOP (S(fi)) vo^ Rc Co Ro Ti(S) d^ K Fm + Tv(S) He(S) ^ V comp -Av(S) Figure 46. Small Signal Model of Synchronous Buck Regulator Vo R1 C4 VFB R2 VREF - VCOMP GM + R6 C7 C6 Figure 47. Type II Compensator FN9326 Rev.0.00 Nov 9, 2018 Page 26 of 33 RAA212422 5. Application Guidelines Figure 47 on page 26 shows the Type II compensator and its transfer function is expressed as shown in Equation 10: (EQ. 10) S S 1 + ------------ 1 + ------------- GM R 2 cz1 cz2 v COMP A v S = -------------------- = ---------------------------------------------------------- -------------------------------------------------------------- C6 + C7 R1 + R2 S S v FB S 1 + ------------- 1 + ------------- cp2 cp1 where R1 + R2 C6 + C7 1 1 cz1 = --------------- , cz2 = --------------- cp1 = ----------------------- cp2 = ----------------------R6 C6 C7 C4 R1 R2 R6 C6 R1 C4 Compensator design goal: * High DC gain * Choose loop bandwidth fc less than 100kHz * Gain margin: >10dB * Phase margin: >40 The compensator design procedure is as follows: The loop gain at crossover frequency of fc has a unity gain; therefore, the compensator resistance R6 is determined by Equation 11. (EQ. 11) 2f c V o C o R cs k R 6 = ----------------------------------------- = k 1 f c V o C o GM V FB where: * GM is the transconductance, gm, of the voltage error amplifier in each phase * Rcs is the current sense trans-resistance * k is a constant to compensate for cross over frequency difference because the feed forward zero is placed at the vicinity of fc * k1 is a constant that depends on the internal parameters of the buck converter. For the wide VIN buck regulator, k1 is 16.1x103. For the low VIN buck regulator, k1 is 13.9x103 Place the compensator zero in the vicinity of the power stage pole at full load. As an example, the compensator zero is placed at twice the frequency of the power stage pole at full load. Compensator capacitor C6 is then given by Equation 12. (EQ. 12) Vo Co Ro Co C 6 = --------------- = ---------------2R 6 2I o R 6 An inherent integrator pole at DC by virtue of the compensation circuit helps to achieve high DC gain. Place another compensator pole at either ESR zero frequency or half switching frequency, whichever is lower, in Equation 13. An optional zero can boost the phase margin. CZ2 is a zero due to R1 and C4. (EQ. 13) Rc Co 1 C 7 = max (--------------,----------------------) R 6 f SW R 6 Put feedforward zero at fzff to boost the phase at cross-over. The fzff can be chosen in the vicinity of fc depending on the amount of phase boost required. (EQ. 14) FN9326 Rev.0.00 Nov 9, 2018 1 C 4 = ----------------------2f zff R 1 Page 27 of 33 RAA212422 5. Application Guidelines Example 1: If VIN1 = 24V, VO1 = 5V, IO1 = 1.1A, fSW = 500kHz, R2 = 90.9k, Co1 = 32.1F/5m, L1 = 22H, and fc = 50kHz, compensator resistance R6: 3 (EQ. 15) R 6 = 16.1 10 50 kHz 5V 32.1F = 129.3k Use 130k as the closest standard value for R6. (EQ. 16) 5V 32.1F C 6 = ---------------------------------------------- = 0.497nF 1.1A 130k 2 (EQ. 17) 5m 32.1F 1 C 7 = max (---------------------------------------,-------------------------------------------------------) = (1.2pF,4.9pF) 130k 500kHz 130k There is approximately 3pF parasitic capacitance from VCOMP1 to GND; Therefore, C7 is optional. Use C6 = 470pF and C7 = Open. Choose fzff to be 1.5 x fc. (EQ. 18) 1 C 4 = ----------------------------------------------------------------------- = 23.3pF 2 50kHz 1.5 90.9k Use C4 = 22pF. Figure 48 shows the simulated voltage loop gain, which has a 44kHz loop bandwidth with an 84 phase margin and 21dB gain margin. In the above example, 22F+47F 1206 case size ceramic capacitors are used. The effective output capacitance after voltage derating is 32.1F. In practice, ceramic capacitors have significant derating on voltage and temperature, depending on the type. Refer to the ceramic capacitor datasheet for more details. 60 180 50 160 40 140 120 30 Phase () Gain (dB) The previous description is one of the methodologies to design the compensation network and can be used as a general guideline. However, it is not the only way to choose compensation components. The optimal compensation components may vary depending on your requirements. 20 10 80 60 0 40 -10 -20 1.E+02 100 20 1.E+03 1.E+04 1.E+05 1.E+06 0 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 Frequency (Hz) Frequency (Hz) Gain vs Frequency Phase vs Frequency Figure 48. Simulated Loop Gain FN9326 Rev.0.00 Nov 9, 2018 Page 28 of 33 RAA212422 5. Application Guidelines Example 2: VIN2 = 5V, VO2 = 1.2V, IO2 = 1.5A, fSW = 1MHz, R1 = R2 = 100k, Co1 = 44.6F/5m, L1 = 2.2H, fc = 80kHz, then compensator resistance R6: 3 R 6 = 13.9x10 80kHz 1.2V 44.6F = 59.5k (EQ. 19) Use 60k as the closest standard value for R6. (EQ. 20) 1.2V 44.6F C 6 = ----------------------------------------- = 297pF 1.5A 60kx2 (EQ. 21) 5m 44.6F 1 C 7 = max (---------------------------------------,-----------------------------------------------) = (3.7pF,5.3pF) 60k 1MHz 60k There is approximately 3pF parasitic capacitance from VCOMP1 to GND; Therefore, C7 is optional. Use C6 = 270pF and C7 = OPEN. Choose fzff to be at fc. 1 C 4 = ------------------------------------------------------- = 20pF 2 80kHz 100k (EQ. 22) 70 180 60 160 50 140 40 120 Phase () Gain (dB) Use C4 = 22pF. Figure 49 shows the simulated voltage loop gain. It shows that it has a 81kHz loop bandwidth with a 62 phase margin and 22dB gain margin. 30 20 100 80 10 60 0 40 -10 20 -20 1.E+02 1.E+03 1.E+04 Frequency (Hz) 1.E+05 1.E+06 0 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 Frequency (Hz) Gain vs Frequency Phase vs Frequency Figure 49. Simulated Loop Gain FN9326 Rev.0.00 Nov 9, 2018 Page 29 of 33 RAA212422 6. 6. Layout Suggestions Layout Suggestions Proper layout of the power converter minimizes EMI and noise, and ensure first pass success of the design. Follow these layout guidelines to help optimize the design. (1) Place the input ceramic capacitors as close as possible to the IC VIN pin and power ground. Keep this loop (input ceramic capacitor, IC VIN pin, and power ground) as small as possible to reduce the trace parasitic inductance and hence reduce voltage spikes. (2) Place the input aluminum bulk capacitor close to the input ceramic capacitors. (3) Keep the phase node copper area small, but large enough to handle the load current. (4) Place the output capacitors close to the power stage components. (5) Place vias at the bottom pad of the IC. Place the bottom pad in a ground copper plane with an area as large as possible in multiple layers for better heat dissipation and removal. (6) One of the most critical connections is to connect the GND pin to the package GND pad. Use vias to directly connect the GND pad to the system GND plane. This connection ensures a low impedance path for all return current and an excellent thermal path to dissipate heat. (7) Place the 1F ceramic decoupling capacitor at the VCC1 pin (the closest place to the IC). Place vias close to the ground pad of this capacitor. (8) Keep the bootstrap capacitor close to the IC. (9) Place the feedback divider close to the FB1 pin and do not route any feedback components near LX1 or BOOT1. If external components are used for SS1, COMP1, or FS1, the same advice applies. (10) Similarly, for the low VIN buck regulator, place the feedback divider close to the FB2 pin and do not route any feedback components near LX2. If external components are used for COMP2, the same advice applies. (11) Connect the EPAD to the ground plane with low-thermal resistance vias. (12) Connect GND1, GND2, and EPAD to the ground plane. FN9326 Rev.0.00 Nov 9, 2018 Page 30 of 33 RAA212422 7. 7. Revision History Revision History Rev. Date 0.00 Nov 9, 2018 FN9326 Rev.0.00 Nov 9, 2018 Description Initial release. Page 31 of 33 RAA212422 8. Package Outline Drawing 8. Package Outline Drawing For the most recent package outline drawing, see L22.3x6. L22.3x6 22 Lead Thin Dual Flat No-Lead Plastic Package (TDFN) Rev 0, 3/18 FN9326 Rev.0.00 Nov 9, 2018 Page 32 of 33 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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