MF1112-02
Technical Manual
CMOS 4-BIT SINGLE CHIP MICROCOMPUTER
S1C60N04 Technical Hardware
S1C60N04
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
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© SEIK O EPSON CORPORATION 2001 All rights reserved.
The information of the product number change
Configuration of product number
Devices
Comparison table between new and previous number
S1C60 Family processors
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
S1 C60N01 F0A01 Packing specification
Specification
Package (D: die form; F: QFP)
Model number
Model name (C: microcomputer, digital products)
Product classification (S1: semiconductor)
Development tools
S5U1 C60R08 D1 1Packing specification
Version (1: Version 1 ∗2)
Tool type (D1: Development Tool ∗1)
Corresponding model number (60R08: for S1C60R08)
Tool classification (C: microcomputer use)
Product classification
(S5U1: development tool for semiconductor products)
∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)
∗2: Actual versions are not written in the manuals.
Previous No.
E0C6001
E0C6002
E0C6003
E0C6004
E0C6005
E0C6006
E0C6007
E0C6008
E0C6009
E0C6011
E0C6013
E0C6014
E0C60R08
New No.
S1C60N01
S1C60N02
S1C60N03
S1C60N04
S1C60N05
S1C60N06
S1C60N07
S1C60N08
S1C60N09
S1C60N11
S1C60N13
S1C60140
S1C60R08
S1C62 Family processors
Previous No.
E0C621A
E0C6215
E0C621C
E0C6S27
E0C6S37
E0C623A
E0C623E
E0C6S32
E0C6233
E0C6235
E0C623B
E0C6244
E0C624A
E0C6S46
New No.
S1C621A0
S1C62150
S1C621C0
S1C6S2N7
S1C6S3N7
S1C6N3A0
S1C6N3E0
S1C6S3N2
S1C62N33
S1C62N35
S1C6N3B0
S1C62440
S1C624A0
S1C6S460
Previous No.
E0C6247
E0C6248
E0C6S48
E0C624C
E0C6251
E0C6256
E0C6292
E0C6262
E0C6266
E0C6274
E0C6281
E0C6282
E0C62M2
E0C62T3
New No.
S1C62470
S1C62480
S1C6S480
S1C624C0
S1C62N51
S1C62560
S1C62920
S1C62N62
S1C62660
S1C62740
S1C62N81
S1C62N82
S1C62M20
S1C62T30
Comparison table between new and previous number of development tools
Development tools for the S1C60/62 Family
Previous No.
ASM62
DEV6001
DEV6002
DEV6003
DEV6004
DEV6005
DEV6006
DEV6007
DEV6008
DEV6009
DEV6011
DEV60R08
DEV621A
DEV621C
DEV623B
DEV6244
DEV624A
DEV624C
DEV6248
DEV6247
New No.
S5U1C62000A
S5U1C60N01D
S5U1C60N02D
S5U1C60N03D
S5U1C60N04D
S5U1C60N05D
S5U1C60N06D
S5U1C60N07D
S5U1C60N08D
S5U1C60N09D
S5U1C60N11D
S5U1C60R08D
S5U1C621A0D
S5U1C621C0D
S5U1C623B0D
S5U1C62440D
S5U1C624A0D
S5U1C624C0D
S5U1C62480D
S5U1C62470D
Previous No.
DEV6262
DEV6266
DEV6274
DEV6292
DEV62M2
DEV6233
DEV6235
DEV6251
DEV6256
DEV6281
DEV6282
DEV6S27
DEV6S32
DEV6S37
EVA6008
EVA6011
EVA621AR
EVA621C
EVA6237
EVA623A
New No.
S5U1C62620D
S5U1C62660D
S5U1C62740D
S5U1C62920D
S5U1C62M20D
S5U1C62N33D
S5U1C62N35D
S5U1C62N51D
S5U1C62560D
S5U1C62N81D
S5U1C62N82D
S5U1C6S2N7D
S5U1C6S3N2D
S5U1C6S3N7D
S5U1C60N08E
S5U1C60N11E
S5U1C621A0E2
S5U1C621C0E
S5U1C62N37E
S5U1C623A0E
Previous No.
EVA623B
EVA623E
EVA6247
EVA6248
EVA6251R
EVA6256
EVA6262
EVA6266
EVA6274
EVA6281
EVA6282
EVA62M1
EVA62T3
EVA6S27
EVA6S32R
ICE62R
KIT6003
KIT6004
KIT6007
New No.
S5U1C623B0E
S5U1C623E0E
S5U1C62470E
S5U1C62480E
S5U1C62N51E1
S5U1C62N56E
S5U1C62620E
S5U1C62660E
S5U1C62740E
S5U1C62N81E
S5U1C62N82E
S5U1C62M10E
S5U1C62T30E
S5U1C6S2N7E
S5U1C6S3N2E2
S5U1C62000H
S5U1C60N03K
S5U1C60N04K
S5U1C60N07K
00
00
S1C60N04 TECHNICAL MANUAL EPSON i
CONTENTS
CONTENTS
CHAPTER 1INTRODUCTION____________________________________________ 1
1.1 Features ........................................................................................................1
1.2 Block Diagram.............................................................................................. 2
1.3 Pin Layout ..................................................................................................... 3
1.4 Pin Description ............................................................................................. 3
CHAPTER 2POWER SUPPLY AND INITIAL RESET_____________________________ 4
2.1 Power Supply ................................................................................................4
2.2 Initial Reset ................................................................................................... 4
2.2.1 Power-on reset circuit ................................................................................ 5
2.2.2 Reset pin (RESET)...................................................................................... 5
2.2.3 Simultaneous high input to input ports (K00–K03) .................................. 5
2.2.4 Internal register following initialization ................................................... 5
2.3 Test Pin (TEST) ............................................................................................. 5
CHAPTER 3 CPU, ROM, RAM________________________________________ 6
3.1 CPU............................................................................................................... 6
3.2 ROM .............................................................................................................. 6
3.3 RAM .............................................................................................................. 6
CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION__________________________ 7
4.1 Memory Map ................................................................................................. 7
4.2 Oscillation Circuit ........................................................................................ 9
4.3 Input Ports (K00–K03) ................................................................................10
4.3.1 Configuration of input port ....................................................................... 10
4.3.2 Interrupt function ...................................................................................... 10
4.3.3 Mask option ............................................................................................... 11
4.3.4 I/O memory of input port .......................................................................... 12
4.3 .5 P rogrammi n g n o t e..................................................................................... 12
4.4 Output Ports (R00–R03) .............................................................................. 13
4.4.1 Configuration of output port..................................................................... 13
4.4.2 Mask option ............................................................................................... 13
4.4.3 I/O memory of output port ........................................................................ 14
4.4 .4 P rogrammi n g n o t e..................................................................................... 15
4.5 I/O Ports (P00–P03) ....................................................................................16
4.5. 1 C o n f i g u r a t i o n o f I / O p o rt .......................................................................... 16
4.5.2 I/O control register and I/O mode ............................................................ 16
4.5.3 Mask option ............................................................................................... 16
4.5.4 I/O memory of I/O port ............................................................................. 16
4.5 .5 P rogrammi n g n o t e..................................................................................... 17
4.6 LCD Driver (COM0–COM3, SEG0–SEG25) ............................................. 18
4.6.1 Configuration of LCD driver .................................................................... 18
4.6.2 Mask option ............................................................................................... 23
4.6.3 I/O memory of LCD driver........................................................................ 24
4.6 .4 P rogrammi n g n o t e..................................................................................... 24
ii EPSON S1C60N04 TECHNICAL MANUAL
CONTENTS
4.7 Clock Timer ..................................................................................................25
4.7. 1 C o n f i g u r a t i o n o f c l o c k t i m e r ..................................................................... 25
4.7.2 Interrupt function ...................................................................................... 25
4.7.3 I/O memory of clock timer ........................................................................ 26
4.7.4 Programming notes ................................................................................... 27
4.8 Interrupt and HALT/SLEEP ........................................................................ 28
4.8.1 Interrupt factors ........................................................................................ 30
4.8.2 Specific masks for interrupt ...................................................................... 30
4.8.3 Interrupt vectors ........................................................................................ 31
4.8.4 I/O memory of interrupt ............................................................................ 31
4.8.5 Programming notes ................................................................................... 32
CHAPTER 5BASIC EXTERNAL WIRING DIAGRAM ____________________________ 33
CHAPTER 6ELECTRICAL CHARACTERISTICS ________________________________ 34
6.1 Absolute Maximum Rating...........................................................................34
6.2 Recommended Operating Conditions.......................................................... 34
6.3 DC Characteristics ......................................................................................35
6.4 Current Consumption .................................................................................. 36
6.5 Oscillation Characteristics.......................................................................... 36
6.6 LCD Characteristic .....................................................................................36
CHAPTER 7PACKAGE ________________________________________________ 37
7.1 Plastic Package............................................................................................37
7.2 Ceramic Package for Test Samples ............................................................. 38
CHAPTER 8PAD LAYOUT _____________________________________________ 39
8.1 Diagram of Pad Layout ............................................................................... 39
8.2 Pad Coordinates ..........................................................................................39
CHAPTER 9PRECAUTIONS ON MOUNTING _________________________________ 40
S1C60N04 TECHNICAL MANUAL EPSON 1
CHAPTER 1: INTRODUCTION
CHAPTER 1INTRODUCTION
The S1C60N04 is a single-chip microcomputer which uses an S1C6200B CMOS 4-bit CPU as the core. It
contains a 1,536 (words) × 12 (bits) ROM, 144 (words) × 4 (bits) RAM, LCD driver, 4-bit input port (K00–
K03), 4-bit output port (R00–R03), 4-bit I/O port (P00–P03) and a timer.
1.1 Features
Core CPU........................................... S1C6200B
Built-in oscillation circuit ............. CR oscillation circuit, 2 MHz (Typ.) (VSS = -5 V)
Instruction set .................................. 100 instructions
ROM capacity................................... 1,536 words × 12 bits
RAM capacity................................... 144 words × 4 bits
Input port .......................................... 4 bits (pull-down resistors are available by mask option)
Output ports ..................................... 4 bits (clock and buzzer outputs are possible by mask option)
R03 output port drivability: 15 mA (VSS = -4.5 V)
I/O port .............................................. 4 b i t s
LCD driver ........................................ 26 segments × 4, 3 or 2 commons
(1/4, 1/3 or 1/2 duty are selectable by mask option)
Timer .................................................. 1 system built-in
Interrupt ............................................ External: Input port interrupt 1 system
Internal: Timer interrupt 1 system
Supply voltage ................................. 2.7 V t o 3 . 6 V, 4.5 V t o 5 . 5 V
Current consumption (Typ.) ......... During SLEEP: 100 nA (3 V)
100 nA (5 V)
During HALT: 330 µA (3 V)
(LCD ON) 1000 µA (5 V)
During operation: 450 µA (3 V)
(LCD ON) 1100 µA (5 V)
Supply form ..................................... Die form or QFP12-48pin plastic package
2EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 1: INTRODUCTION
1.2 Block Diagram
OSC1
OSC2
COM0–3
SEG0–25
V
DD
V
SS
V
L1
V
L2
K00–K03
TEST
RESET
P00–P03
R00 (FOUT, BUZZER)
∗1
R01 (BUZZER)
∗1
R02, R03
∗1: Terminal specifications can be selected by mask option.
Core CPU S1C6200B
ROM
1,536 words × 12 bits
System Reset
Control
Interrupt
Generator
RAM
144 words × 4 bits
LCD Driver
26 SEG × 4 COM
Power
Divider
OSC / SLEEP
Clock
Timer FOUT
& Buzzer
Input Port
I/O Port
Output Port
Fig. 1.2.1 S1C60N04 block diagram
S1C60N04 TECHNICAL MANUAL EPSON 3
CHAPTER 1: INTRODUCTION
1.3 Pin Layout
QFP12-48pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
Pin name
K02
K01
K00
P03
P02
P01
P00
R03
R02
R01
R00
SEG25
No.
13
14
15
16
17
18
19
20
21
22
23
24
Pin name
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
No.
25
26
27
28
29
30
31
32
33
34
35
36
Pin name
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
No.
37
38
39
40
41
42
43
44
45
46
47
48
Pin name
SEG0
COM0
COM1
COM2
COM3
TEST
RESET
V
DD
OSC1
OSC2
V
SS
K03
2536
121
13
24
INDEX
48
37
Fig. 1.3.1 S1C60N04 pin layout (QFP12-48pin)
1.4 Pin Description
Table 1.4.1 Pin description
Pin name
V
DD
V
SS
OSC1
OSC2
K00–K03
P00–P03
R00
R01
R02, R03
SEG0–25
COM0–3
RESET
TEST
Function
Power supply pin (+)
Power supply pin (-)
CR oscillation input pin
CR oscillation output pin
Input port pin
I/O port pin
Output port pin, BUZZER or FOUT output pin *
Output port pin or BUZZER output pin *
Output port pin
LCD segment output pin or DC output pin *
LCD common output pin (1/4 duty, 1/3 or 1/2 duty are selectable *)
Initial reset input pin
Input pin for test
Pin No.
44
47
45
46
3–1, 48
7–4
11
10
9, 8
37–12
38–41
43
42
I/O
(I)
(I)
I
O
I
I/O
O
O
O
O
O
I
I
∗ Can be selected by mask option
4EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER 2POWER SUPPLY AND INITIAL RESET
2.1 Power Supply
With a single external power supply (∗) supplied to VDD through VSS, the S1C60N04 generates the
necessary internal voltages with the power divider.
∗ Supply voltage: 2.7 to 3.6 V or 4.5 V to 5.5 V
The power divider generates the LCD drive voltages <VL1, VL2> by dividing the supply voltage as shown
in Figure 2.1.1.
The circuit configuration is set according to the LCD drive bias selection with a mask option.
When 1/3 bias is selected, the supply voltage is divided by 3 to generate VL1 and VL2.
When 1/2 bias is selected, the supply voltage is divided by 2 and VL1 and VL2 is shorted internally.
V
DD
3.0/5.0 V
V
L1
= 1/3·V
SS
V
L2
= 2/3·V
SS
V
SS
1/4, 1/3 or 1/2 duty, 1/3 bias
V
DD
3.0/5.0 V
V
L1
= 1/2·V
SS
V
L2
= 1/2·V
SS
V
SS
1/4, 1/3 or 1/2 duty, 1/2 bias
V
L1
and V
L2
are
shorted internally.
Note:
Fig. 2.1.1 Configuration of power divider
2.2 Initial Reset
To initialize the S1C60N04 circuits, an initial reset must be executed. There are three ways of doing this.
(1) Initial reset by the power-on reset circuit
(2) External initial reset via the RESET pin
(3) External initial reset by simultaneous high input to pins K00–K03 (depending on mask option)
Figure 2.2.1 shows the configuration of the initial reset circuit.
Vss
RESET
K03
K02
K01
K00
OSC2
OSC1 OSC1
Oscillation
circuit
Vss
Power-on
reset
circuit
Noise
rejection
circuit
Initial
reset
Noise
rejection
circuit
Fig. 2.2.1 Configuration of initial reset circuit
S1C60N04 TECHNICAL MANUAL EPSON 5
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2.1 Power-on reset circuit
The power-on reset circuit outputs the initial reset signal at power-on until the oscillation circuit starts
oscillating.
Note: The power-on reset circuit may not work properly due to unstable or lower voltage input. The
following two initial reset method are recommended to generate the initial reset signal.
2.2.2 Reset pin (RESET)
An initial reset can be invoked externally by making the reset pin high.
When the reset pin goes low the CPU begins to operate.
2.2.3 Simultaneous high input to input ports (K00–K03)
A Not used
B K00*K01
C K00*K01*K02
D K00*K01*K02*K03
When, for instance, mask option D (K00*K01*K02*K03) is selected, an initial reset is executed when the
signals input to the four ports K00–K03 are all high at the same time.
When this function is used, make sure that the specified ports do not go high at the same time during
normal operation.
2.2.4 Internal register following initialization
An initial reset initializes the CPU as shown in the table below.
Table 2.2.4.1 Initial values
∗ See Section 4.1, "Memory Map".
Name
Program counter step
Program counter page
New page pointer
Stack pointer
Index register X
Index register Y
Register pointer
General-purpose register A
General-purpose register B
Interrupt flag
Decimal flag
Zero flag
Carry flag
CPU Core
Symbol
PCS
PCP
NPP
SP
X
Y
RP
A
B
I
D
Z
C
Bit size
8
4
4
8
8
8
4
4
4
1
1
1
1
Initial value
00H
1H
1H
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
0
Undefined
Undefined
Name
RAM
Display memory
Other peripheral circuits
Peripheral Circuits
Bit size
144×4
26×4
–
Initial value
Undefined
Undefined
∗
2.3 Test Pin (TEST)
This pin is used when IC is inspected for shipment. During normal operation connect it to VSS.
Another way of invoking an initial reset externally is to input a
high signal simultaneously to the input ports (K00–K03) selected
with the mask option. The specified input port pins must be kept
high for at least 1 sec (when oscillating frequency fosc = 2 MHz),
tolerance is within 5%, because of the noise rejection circuit. Table
2.2.3.1 shows the combinations of input ports (K00–K03) that can be
selected with the mask option.
Table 2.2.3.1 Input port combinations
6EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 3: CPU, ROM, RAM
CHAPTER 3 CPU, ROM, RAM
3.1 CPU
The S1C60N04 employs the S1C6200B core CPU, so that register configuration, instructions, and so forth
are virtually identical to those in other processors in the family using the S1C6200/6200A/6200B.
Refer to the "S1C6200/6200A Core CPU Manual" for details of the S1C6200B, which is compatible with
the S1C6200A.
Note the following points with regard to the S1C60N04:
(1) Since the S1C60N04 provides the SLEEP function, the SLP instruction can be used.
(2) Because the ROM capacity is 1,536 words, 12 bits per word, bank bits are unnecessary, and PCB and
NBP are not used.
(3) The RAM page is set to 0 only, so the page part (XP, YP) of the index register that specifies addresses is
invalid.
PUSH XP POP XP LD XP,r LD r,XP
PUSH YP POP YP LD YP,r LD r,YP
3.2 ROM
The built-in ROM, a mask ROM for the program, has a capacity of 1,536 × 12-bit steps. The program area
is 6 pages (0–5), each consisting of 256 steps (00H–FFH). After an initial reset, the program start address is
set to page 1, step 00H. The interrupt vectors are allocated to page 1, steps 01H–07H.
Step 00H
Step 07H
Step 08H
Step FFH
12 bits
Program start address
Interrupt vector area
Bank 0
Program area
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Step 01H
Fig. 3.2.1 ROM configuration
3.3 RAM
The RAM, a data memory for storing a variety of data, has a capacity of 144 words, 4-bit words. When
programming, keep the following points in mind:
(1) Part of the data memory is used as stack area when saving subroutine return addresses and registers,
so be careful not to overlap the data area and stack area.
(2) Subroutine calls and interrupts take up three words on the stack.
(3) Data memory 000H–00FH is the memory area pointed by the register pointer (RP).
S1C60N04 TECHNICAL MANUAL EPSON 7
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION
Peripheral circuits (timer, I/O, and so on) of the S1C60N04 are memory mapped. Thus, all the peripheral
circuits can be controlled by using memory operations to access the I/O memory. The following sections
describe how the peripheral circuits operate.
4.1 Memory Map
The data memory of the S1C60N04 has an address space of 188 words, of which 32 words are allocated to
display memory and 12 words, to I/O memory. Figure 4.1.1 show the overall memory map for the
S1C60N04, and Table 4.1.1, the memory maps for the peripheral circuits (I/O space).
Address
Page High
Low 0123456789ABCDEF
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF
3
0
1
2
4
5
6
7
8
9
A
B
C
D
E
F
0
RAM area (000H–08FH)
144 words × 4 bits (R/W)
Display memory area (090H–0AFH)
32 words × 4 bits (W only)
Unused area
I/O memory See Table 4.1.1
Fig. 4.1.1 Memory map
Note: Memory is not mounted in unused area within the memory map and in memory area not indicated
in this chapter. For this reason, normal operation cannot be assured for programs that have been
prepared with access to these areas.
8EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 I/O memory map
Address Comment
D3 D2
Register
D1 D0 Name Init ∗110
0E0H
K03 K02 K01 K00
R
K03
K02
K01
K00
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
K0 input port data
0E4H
TM3 TM2 TM1 TM0
R
TM3
TM2
TM1
TM0
–
∗
2
–
∗
2
–
∗
2
–
∗
2
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
Clock timer data (16 Hz)
0E8H
EIK03 EIK02 EIK01 EIK00
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
0EBH
0 EIT2 EIT8 EIT32
RR/W
0
∗
3
EIT2
EIT8
EIT32
–
∗
2
0
0
0
–
Enable
Enable
Enable
–
Mask
Mask
Mask
Unused
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
0EDH
000IK0
R
0
∗
3
0
∗
3
0
∗
3
IK0
∗
4
–
∗
2
–
∗
2
–
∗
2
0
–
–
–
Yes
–
–
–
No
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
0EFH
0 IT2 IT8 IT32
R
0
∗
3
IT2
∗
4
IT8
∗
4
IT32
∗
4
–
∗
2
0
0
0
–
Yes
Yes
Yes
–
No
No
No
Unused
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
0F3H
R03 R02 R01
BUZZER
R00
FOUT
BUZZER
R/W
R03
R02
R01
BUZZER
R00
FOUT
BUZZER
0
0
0
0
0
0
0
0FBH
0 0 0 PDON
RR/W
0
∗
3
0
∗
3
0
∗
3
PDON
–
∗
2
–
∗
2
–
∗
2
0
–
–
–
On
–
–
–
Off
Unused
Unused
Unused
LCD power supply On/Off control
0FDH
XBZR 0 0 0
R/W R
XBZR
0
∗
3
0
∗
3
0
∗
3
0
–
∗
2
–
∗
2
–
∗
2
2 kHz
–
–
–
4 kHz
–
–
–
Buzzer frequency control
Unused
Unused
Unused
0FCH
000IOC
RR/W
0
∗
3
0
∗
3
0
∗
3
IOC
–
∗
2
–
∗
2
–
∗
2
0
–
–
–
Output
–
–
–
Input
Unused
Unused
Unused
I/O port I/O control
0F9H
0 TMRST 0 0
RW R
0
∗
3
TMRST
∗
3
0
∗
3
0
∗
3
–
∗
2
Reset
–
∗
2
–
∗
2
–
Reset
–
–
–
–
–
–
Unused
Clock timer reset
Unused
Unused
High
High
High
On
High
On
On
Low
Low
Low
Off
Low
Off
Off
R03 output port data
R02 output port data
R01 output port data
Buzzer output On/Off control
R00 output port data
FOUT output On/Off
control
Buzzer inverted output On/Off control
0F6H
P03 P02 P01 P00
R/W
P03
P02
P01
P00
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
P0 I/O port data
∗1
∗2Initial value at initial reset
Not set in the circuit ∗3
∗4Always "0" being read
Reset (0) immediately after being read
S1C60N04 TECHNICAL MANUAL EPSON 9
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.2 Oscillation Circuit
The S1C60N04 has a CR oscillation circuit.
The CR oscillation circuit generates the operating clock for the CPU and the peripheral circuits. The
oscillation frequency is 2 MHz (Typ.). Figure 4.2.1 is the circuit diagram of the CR oscillation circuit.
OSC2
OSC1 CPU
and peripheral circuits
CCR
RCR
Fig. 4.2.1 CR oscillation circuit
As shown in Figure 4.2.1, the CR oscillation circuit can be configured simply by connecting the resistor
RCR between the OSC1 and OSC2 terminals.
See Chapter 6, "Electrical Characteristics" for resistance value of RCR.
10 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.3 Input Ports (K00–K03)
4.3.1 Configuration of input port
The S1C60N04 has a 4-bit general-purpose input port. Each of the input port pins (K00–K03) has an
internal pull-down resistor. The pull-down resistor can be selected for each bit with the mask option.
Figure 4.3.1.1 shows the configuration of input port.
K0x
VSS
Mask option
Address
VDD
Interrupt
request
Data bus
Fig. 4.3.1.1 Configuration of input port
Selecting "pull-down resistor enabled" with the mask option allows input from a push button, key matrix,
and so forth. When "pull-down resistor disabled" is selected, the port can be used for slide switch input
and interfacing with other LSIs.
4.3.2 Interrupt function
All four input port bits (K00–K03) provide the interrupt function. The conditions for issuing an interrupt
can be set by the software for the four bits. Also, whether to mask the interrupt function can be selected
individually for all four bits by the software. Figure 4.3.2.1 shows the configuration of K00–K03.
Data bus
Address
Interrupt mask
register (EIK)
K0x
Mask option
(K00–K03)
Noise
rejector
Interrupt factor
flag (IK0)
Interrupt
request
Address Address
Fig. 4.3.2.1 Input interrupt circuit configuration (K00–K03)
The interrupt mask registers (EIK00–EIK03) enable the interrupt mask to be selected individually for
K00–K03. An interrupt occurs when the input value which are not masked change and the interrupt
factor flag (IK0) is set to 1.
S1C60N04 TECHNICAL MANUAL EPSON 11
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Input interrupt programming related precautions
Port K input
Factor flag set Not set
Mask register
Active status
➀
When the content of the mask register is rewritten, while the port
K input is in the active status. The input interrupt factor flag is
set at ➀.Fig. 4.3.2.2 Input interrupt timing
When using an input interrupt, if you rewrite the content of the mask register, when the value of the
input terminal which becomes the interrupt input is in the active status (input terminal = high status), the
factor flag for input interrupt may be set.
For example, a factor flag is set with the timing of ➀ shown in Figure 4.3.2.2. However, when clearing the
content of the mask register with the input terminal kept in the high status and then setting it, the factor
flag of the input interrupt is again set at the timing that has been set.
Consequently, when the input terminal is in the active status (high status), do not rewrite the mask
register (clearing, then setting the mask register), so that a factor flag will only set at the rising edge in
this case. When clearing, then setting the mask register, set the mask register, when the input terminal is
not in the active status (low status).
4.3.3 Mask option
The contents that can be selected with the input port mask option are as follows:
(1) An internal pull-down resistor can be selected for each of the four bits of the input ports (K00–K03).
Having selected "pull-down resistor disabled", take care that the input does not float. Select "pull-
down resistor enabled" for input ports that are not being used.
(2) The input interrupt circuit contains a noise rejection circuit to prevent interrupts form occurring
through noise. The mask option enables selection of the noise rejection circuit for each separate pin
series. When "use" is selected, a maximum delay of 0.5 msec (fosc = 2 MHz), tolerance is within 5%,
occurs from the time an interrupt condition is established until the interrupt factor flag (IK0) is set to
1.
12 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
4.3.4 I/O memory of input port
Table 4.3.4.1 list the input port control bits and their addresses.
Table 4.3.4.1 Input port control bits
Address Comment
D3 D2
Register
D1 D0 Name Init ∗110
0E0H
K03 K02 K01 K00
R
K03
K02
K01
K00
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
K0 input port data
0E8H
EIK03 EIK02 EIK01 EIK00
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
0EDH
000IK0
R
0
∗
3
0
∗
3
0
∗
3
IK0
∗
4
–
∗
2
–
∗
2
–
∗
2
0
–
–
–
Yes
–
–
–
No
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
∗1
∗2Initial value at initial reset
Not set in the circuit ∗3
∗4Always "0" being read
Reset (0) immediately after being read
K00–K03: Input port data (0E0H)
The input data of the input port pins can be read with these registers.
When 1 is read: High level
When 0 is read: Low level
Writing: Invalid
The value read is 1 when the pin voltage of the four bits of the input port (K00–K03) goes high (VDD), and
0 when the voltage goes low (VSS). These bits are reading, so writing cannot be done.
EIK00–EIK03: Interrupt mask registers (0E8H)
Masking the interrupt of the input port pins can be done with these registers.
When 1 is written: Enable
When 0 is written: Mask
Reading: Valid
With these registers, masking of the input port bits can be done for each of the four bits. After an initial
reset, these registers are all set to 0.
IK0: Interrupt factor flag (0EDH•D0)
This flag indicates the occurrence of an input interrupt.
When 1 is read: Interrupt has occurred
When 0 is read: Interrupt has not occurred
Writing: Invalid
The interrupt factor flag IK0 is associated with K00–K03. From the status of this flag, the software can
decide whether an input interrupt has occurred.
This flag is reset when the software has read it.
Reading of interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not
be generated.
After an initial reset, this flag is set to 0.
4.3.5 Programming note
When modifying the input port from high level to low level with pull-down resistor, a delay will occur at
the fall of the waveform due to time constant of the pull-down resistor and input gate capacities. Provide
appropriate waiting time in the program when performing input port reading.
S1C60N04 TECHNICAL MANUAL EPSON 13
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
4.4 Output Ports (R00–R03)
4.4.1 Configuration of output port
The S1C60N04 has a 4-bit general output port (R00–R03).
Output specification of the output port can be selected in a bit units with the mask option. Two kinds of
output specifications are available: complementary output and Pch open drain output. Also, the mask
option enables the output ports R00 and R01 to be used as special output ports. Figure 4.4.1.1 shows the
configuration of the output port.
Register
Data bus
Address
V
DD
V
SS
R0x
Complementary
Pch open drain
Mask option
Fig. 4.4.1.1 Configuration of output port
4.4.2 Mask option
The mask option enables the following output port selection.
(1)Output specification of output port
The output specifications for the output port (R00–R03) may be either complementary output or Pch
open drain output for each bit. However, even when Pch open drain output is selected, a voltage
exceeding the source voltage must not be applied to the output port.
(2)Special output
In addition to the regular DC output, special output can be selected for output ports R00 and R01, as
shown in Table 4.4.2.1. Figure 4.4.2.1 shows the structure of output ports R00–R03.
Table 4.4.2.1 Special output
Output port
R00
R01
Special output
FOUT or BUZZER output
BUZZER output
Register R03
Data bus
R03
Register R02 R02
Register R01 R01
R00
BUZZER
BUZZER
FOUT
Register R00
Address 0F3H Mask option
Fig. 4.4.2.1 Structure of output ports R00–R03
14 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
FOUT (R00)
When output port R00 is set for FOUT output, this port will generate fosc (CPU operating clock fre-
quency) clock.
BUZZER, BUZZER (R01, R00)
Output ports R01 and R00 may be set to BUZZER output and BUZZER output (BUZZER reverse output),
respectively, allowing for direct driving of the piezo-electric buzzer.
BUZZER output (R00) may only be set if R01 is set to BUZZER output. In such case, whether ON/OFF of
the BUZZER output is done through R00 register or is controlled through R01 simultaneously with
BUZZER output is also selected by mask option.
The frequency of buzzer output may be selected by software to be either 2 kHz or 4 kHz.
4.4.3 I/O memory of output port
Table 4.4.3.1 lists the output port control bits and their addresses.
Table 4.4.3.1 Control bits of output port
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
0F3H
R03 R02 R01
BUZZER
R00
FOUT
BUZZER
R/W
R03
R02
R01
BUZZER
R00
FOUT
BUZZER
0
0
0
0
0
0
0
0FDH
XBZR 0 0 0
R/W R
XBZR
0
∗
3
0
∗
3
0
∗
3
0
–
∗
2
–
∗
2
–
∗
2
2 kHz
–
–
–
4 kHz
–
–
–
Buzzer frequency control
Unused
Unused
Unused
High
High
High
On
High
On
On
Low
Low
Low
Off
Low
Off
Off
R03 output port data
R02 output port data
R01 output port data
Buzzer output On/Off control
R00 output port data
FOUT output On/Off
control
Buzzer inverted output On/Off control
∗1
∗2Initial value at initial reset
Not set in the circuit ∗3
∗4Always "0" being read
Reset (0) immediately after being read
R00–R03: Output port data (0F3H)
Sets the output data for the output ports.
When 1 is written: High output
When 0 is written: Low output
Reading: Valid
The output port pins output the data written to the corresponding registers (R00–R03) without changing
it. When 1 is written to the register, the output port pin goes high (VDD), and when 0 is written, the
output port pin goes low (VSS).
After an initial reset, all the registers are set to 0.
R00 (when FOUT is selected): Special output port data (0F3H•D0)
Controls the FOUT (fosc clock) output.
When 1 is written: Clock output
When 0 is written: Low level (DC) output
Reading: Valid
FOUT output can be controlled by writing data to R00.
After an initial reset, this register is set to 0.
Figure 4.4.3.1 shows the output waveform for FOUT output.
S1C60N04 TECHNICAL MANUAL EPSON 15
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
R00 register
FOUT output
waveform
01
Fig. 4.4.3.1 FOUT output waveform
Note
:
A hazard may occur when the FOUT signal is turned ON or OFF.
R00, R01 (when buzzer output is selected): Special output port data (0F3H•D0, D1)
Controls the buzzer output.
When 1 is written: Buzzer output
When 0 is written: Low level (DC) output
Reading: Valid
BUZZER and BUZZER output can be controlled by writing data to R00 and R01.
When BUZZER output by R01 register control is selected by mask option, BUZZER output and BUZZER
output can be controlled simultaneously by writing data to R01 register.
After an initial reset, these registers are set to 0.
Figure 4.4.3.2 shows the output waveform for buzzer output.
R01 (R00) register
BUZZER output
waveform
01
BUZZER output
waveform
Fig. 4.4.3.2 Buzzer output waveform
Note
:
A hazard may occur when the BUZZER or BUZZER signal is tur ned ON or OFF.
XBZR: Buzzer frequency control (0FDH•D3)
Selects the frequency of the buzzer signal.
When 1 is written: 2 kHz
When 0 is written: 4 kHz
Reading: Valid
When R00 and R01 port is set to buzzer output, the frequency of the buzzer signal can be selected by this
register.
When 1 is written to this register, the frequency is set in 2 kHz, and in 4 kHz when 0 is written.
After an initial reset, this register is set to 0.
4.4.4 Programming note
The buzzer output signal may produce hazards when the output ports R00 and R01 are turned on or off.
16 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
4.5 I/O Ports (P00–P03)
4.5.1 Configuration of I/O port
The S1C60N04 has a 4-bit general-purpose I/O port. Figure 4.5.1.1 shows the configuration of the I/O
port. The four bits of the I/O port P00–P03 can be set to either input mode or output mode. The mode can
be set by writing data to the I/O control register (IOC).
Address
Address
Register
Input
control
I/O control
register
(IOC)
Data bus
P0x
Vss
Fig. 4.5.1.1 Configuration of I/O port
4.5.2 I/O control register and I/O mode
Input or output mode can be set for the four bits of I/O port P00–P03 by writing data into I/O control
register IOC.
To set the input mode, 0 is written to the I/O control register. When an I/O port is set to input mode, its
impedance becomes high and it works as an input port. However, the input line is pulled down when
input data is read.
The output mode is set when 1 is written to the I/O control register (IOC). When an I/O port set to
output mode works as an output port, it outputs a high signal (VDD) when the port output data is 1, and
a low signal (VSS) when the port output data is 0.
After an initial reset, the I/O control register is set to 0, and the I/O port enters the input mode.
4.5.3 Mask option
The output specification during output mode (IOC = 1) of the I/O port can be set with the mask option
for either complementary output or Pch open drain output. This setting can be performed for each bit of
the I/O port. However, when Pch open drain output has been selected, voltage in excess of the supply
voltage must not be applied to the port.
4.5.4 I/O memory of I/O port
Table 4.5.4.1 lists the I/O port control bits and their addresses.
Table 4.5.4.1 I/O port control bits
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
0FCH
000IOC
RR/W
0
∗
3
0
∗
3
0
∗
3
IOC
–
∗
2
–
∗
2
–
∗
2
0
–
–
–
Output
–
–
–
Input
Unused
Unused
Unused
I/O port I/O control
0F6H
P03 P02 P01 P00
R/W
P03
P02
P01
P00
–
∗
2
–
∗
2
–
∗
2
–
∗
2
High
High
High
High
Low
Low
Low
Low
P0 I/O port data
∗1
∗2Initial value at initial reset
Not set in the circuit ∗3
∗4Always "0" being read
Reset (0) immediately after being read
S1C60N04 TECHNICAL MANUAL EPSON 17
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
P00–P03: I/O por t data (0F6H)
I/O port data can be read and output data can be written through the port.
When writing data
When 1 is written: High level
When 0 is written: Low level
When an I/O port is set to the output mode, the written data is output from the I/O port pin unchanged.
When 1 is written as the port data, the port pin goes high (VDD), and when 0 is written, the level goes low
(VSS). Port data can also be written in the input mode.
When reading data
When 1 is read: High level
When 0 is read: Low level
The pin voltage level of the I/O port is read. When the I/O port is in the input mode the voltage level
being input to the port pin can be read; in the output mode the output voltage level can be read. When
the pin voltage is high (VDD) the port data read is 1, and when the pin voltage is low (VSS) the data is 0.
Also, the built-in pull-down resistor functions during reading, so the I/O port pin is pulled down.
IOC: I/O control register (0FCH•D0)
The input or output I/O port mode can be set with this register.
When 1 is written: Output mode
When 0 is written: Input mode
Reading: Valid
The input or output mode of the I/O port is set in units of four bits. For instance, IOC sets the mode for
P00–P03.
Writing 1 to the I/O control register makes the I/O port enter the output mode, and writing 0, the input
mode.
After an initial reset, the IOC register is set to 0, so the I/O port is in the input mode.
4.5.5 Programming note
When in the input mode, I/O ports are changed from high to low by pull-down resistor, the fall of the
waveform is delayed on account of the time constant of the pull-down resistor and input gate capaci-
tance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10 × C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-down resistance 60 kΩ
18 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.6 LCD Driver (COM0–COM3, SEG0–SEG25)
4.6.1 Configuration of LCD driver
The S1C60N04 has four common pins and 26 (SEG0–SEG25) segment pins, so that an LCD with a maxi-
mum of 104 (26 × 4) segments can be driven. The power for driving the LCD is generated by the CPU
internal circuit, so there is no need to supply power externally.
The driving method is 1/4 duty (or 1/3, 1/2 duty by mask option) dynamic drive, adopting the four
types of potential (1/3 bias), VDD, VL1, VL2 and VSS. Moreover, the 1/2 bias dynamic drive that uses three
types of potential, VDD, VL1 = VL2 and VSS, can be selected by setting the mask option (drive duty can also
be selected from 1/4, 1/3 or 1/2).
The LCD drive voltages VL1 and VL2 are generated by the power divider inside the IC. However it is
necessary to turn the power divider on by writing 1 to the PDON register before starting LCD display.
The frame frequency is about 30.5 Hz for 1/4 duty and 1/2 duty, and 40.7 Hz for 1/3 duty (in the case of
fosc = 2 MHz), tolerance is within 5%.
Figures 4.6.1.1 to 4.6.1.6 show the drive waveform for each duty and bias.
Note: "fosc" indicates the oscillation frequency of the oscillation circuit.
S1C60N04 TECHNICAL MANUAL EPSON 19
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
COM0
COM1
COM2
COM3
V
V
V
V
DD
L1
L2
SS
V
V
V
V
DD
L1
L2
SS
SEG0
–SEG25
Frame frequency
Off
On
LCD lighting status
COM0
COM1
COM2
COM3
SEG0–25
Fig. 4.6.1.1 Drive waveform for 1/4 duty (1/3 bias)
20 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
COM0
COM1
COM2
COM3
V
V
V
V
DD
L1
L2
SS
V
V
V
V
DD
L1
L2
SS
Off
On
SEG0
–SEG25
Frame frequency
LCD lighting status
COM0
COM1
COM2
SEG0–25
Fig. 4.6.1.2 Drive waveform for 1/3 duty (1/3 bias)
COM0
COM1
COM2
COM3
V
V
V
V
DD
L1
L2
SS
V
V
V
V
DD
L1
L2
SS
Off
On
SEG0
–SEG25
Frame frequency
LCD lighting status
SEG0–25
COM0
COM1
Fig. 4.6.1.3 Drive waveform for 1/2 duty (1/3 bias)
S1C60N04 TECHNICAL MANUAL EPSON 21
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
LCD lighting status
SEG
0–25
SEG0–25
COM0
COM1
COM2
COM3
COM0
COM1
COM2
COM3
-VDD
-VL1, L2
-VSS
-VDD
-VL1, L2
-VSS
Frame frequency
Off
On
Fig. 4.6.1.4 Drive waveform for 1/4 duty (1/2 bias)
22 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
LCD lighting status
SEG
0–25
SEG0–25
COM0
COM1
COM2
COM0
COM1
COM2
COM3
-VDD
-VL1, L2
-VSS
-VDD
-VL1, L2
-VSS
Frame frequency
Off
On
Fig. 4.6.1.5 Drive waveform for 1/3 duty (1/2 bias)
COM0
COM1
COM0
COM1
COM2
COM3
-V
DD
-V
L1, L2
-V
SS
-V
DD
-V
L1, L2
-V
SS
LCD lighting status
SEG
0–25
SEG0–25
Frame frequency
Off
On
Fig. 4.6.1.6 Drive waveform for 1/2 duty (1/2 bias)
S1C60N04 TECHNICAL MANUAL EPSON 23
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.6.2 Mask option
(1)Segment allocation
As shown in Figure 4.l.1, the S1C60N04 display data is decided by the data written to the display
memory (write-only) at address 090H–0AFH.
The address and bits of the display memory can be made to correspond to the segment pins (SEG0–
SEG25) in any combination through mask option. This simplifies design by increasing the degree of
freedom with which the liquid crystal panel can be designed.
Figure 4.6.2.1 shows an example of the relationship between the LCD segments (on the panel) and the
display memory in the case of 1/3 duty.
aa'
ff'
g'
g
ee'
dd' p'
p
c'
b'
b
c
SEG10 SEG11 SEG12
Common 0
Common 1
Common 2
09AH
09BH
09CH
09DH
Address
d
p
d'
p'
D3
c
g
c'
g'
D2
b
f
b'
f'
D1
a
e
a'
e'
D0
Data
Display data memory allocation
SEG10
SEG11
SEG12
9A, D0
(a)
9A, D1
(b)
9D, D1
(f')
9B, D1
(f)
9B, D2
(g)
9A, D2
(c)
9B, D0
(e)
9A, D3
(d)
9B, D3
(p)
Pin address allocation
Common 0 Common 1 Common 2
Fig. 4.6.2.1 Segment allocation
(2)Drive duty
According to the mask option, either 1/4, 1/3 or 1/2 duty can be selected as the LCD drive duty.
Table 4.6.2.1 shows the differences in the number of segments according to the selected duty.
Table 4.6.2.1 Differences according to selected duty
Duty
1/4
1/3
1/2
COM used
COM0–COM3
COM0–COM2
COM0–COM1
Max. number of segments
104 (26 × 4)
78 (26 × 3)
52 (26 × 2)
Frame frequency *
30.5 Hz
40.7 Hz
30.5 Hz
∗ When f
OSC
= 2 MHz, tolerance is within 5%
(3)Output specification
➀ The segment pins (SEG0–SEG25) are selected by mask option in pairs for either segment signal output
or DC output (VDD and VSS binary output). When DC output is selected, the data corresponding to
COM0 of each segment pin is output.
➁ When DC output is selected, either complementary output or Pch open drain output can be selected
for each pin by mask option.
Note: The pin pairs are the combination of SEG (2
∗
n) and SEG (2
∗
n + 1) (where n is an integer from 0 to 12).
(4)Drive bias
For the drive bias of the S1C60N04, either 1/3 bias or 1/2 bias can be selected by the mask option.
24 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
4.6.3 I/O memory of LCD driver
Table 4.6.3.1 shows the control bits of the LCD driver and their addresses. Figure 4.6.3.1 shows the
display memory map.
Table 4.6.3.1 Control bits of LCD driver
Address Comment
D3 D2
Register
D1 D0 Name Init
∗1
10
∗1
∗2Initial value at initial reset
Not set in the circuit ∗3
∗4Always "0" being read
Reset (0) immediately after being read
0FBH
0 0 0 PDON
RR/W
0
∗
3
0
∗
3
0
∗
3
PDON
–
∗
2
–
∗
2
–
∗
2
0
–
–
–
On
–
–
–
Off
Unused
Unused
Unused
LCD power supply on/off control
Address 0123456789ABCDEF
090
0A0 Display memory (Write only)
32 words x 4 bits
Fig. 4.6.3.1 Display memory map
PDON: LCD power supply On/Off control (0FBH•D0)
Controls the power supply for LCD display.
When 1 is written: LCD power On
When 0 is written: LCD power Off
Reading: Valid
By writing 1 to PDON, the LCD display can work normally. When 0 is written, all the segment and
common signals will go to the same voltage level, and the LCD display goes off.
This control dose not affect the contents of display memory.
After an initial reset, this register is set to 0.
Display memory (090H–0AFH)
The LCD segments are turned on or off according to this data.
When 1 is written: On
When 0 is written: Off
Reading: Invalid
By writing data into the display memory allocated to the LCD segment (on the panel), the segment can be
turned on or off.
After an initial reset, the contents of the display memory are undefined.
4.6.4 Programming note
Because the display memory is for writing only, re-writing the contents with computing instructions (e.g.,
AND, OR, etc.) which come with read-out operations is not possible. To perform bit operations, a buffer
to hold the display data is required on the RAM.
S1C60N04 TECHNICAL MANUAL EPSON 25
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.7 Clock Timer
4.7.1 Configuration of clock timer
The S1C60N04 has a built-in clock timer that uses the oscillation circuit as the clock source. The clock
timer is configured as a 7-bit binary counter that counts with a 256 Hz source clock from the divider. The
high-order 4 bits of the counter (16 Hz–2 Hz) can be read by the software.
Figure 4.7.1.1 is the block diagram of the clock timer.
128 Hz–32 Hz
Data bus
32 Hz, 8 Hz, 2 Hz
256 Hz
Clock timer reset signal
Divider
Interrupt
request
Interrupt
control
16 Hz–2 Hz
Oscillation
circuit
Fig. 4.7.1.1 Block diagram of clock timer
Normally, this clock timer is used for all kinds of timing purpose, such as clocks.
4.7.2 Interrupt function
The clock timer can generate interrupts at the falling edge of the 32 Hz, 8 Hz, and 2 Hz signals. The
software can mask any of these interrupt signals.
Figure 4.7.2.1 is the timing chart of the clock timer.
Clock timer timing chartFrequency
Register
bits
Address
0E4H
D0 16 Hz
D1
D2
D3
8 Hz
4 Hz
2 Hz
Occurrence of
32 Hz interrupt request
Occurrence of
8 Hz interrupt request
Occurrence of
2 Hz interrupt request
Fig. 4.7.2.1 Timing chart of the clock timer
As shown in Figure 4.7.2.1, an interrupt is generated at the falling edge of the 32 Hz, 8 Hz, and 2 Hz
signals. At this point, the corresponding interrupt factor flag (IT32, IT8, IT2) is set to 1. The interrupts can
be masked individually with the interrupt mask register (EIT32, EIT8, EIT2). However, regardless of the
interrupt mask register setting, the interrupt factor flags will be set to 1 at the falling edge of their corre-
sponding signal (e.g. the falling edge of the 2 Hz signal sets the 2 Hz interrupt factor flag to 1).
26 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
4.7.3 I/O memory of clock timer
Table 4.7.3.1 shows the clock timer control bits and their addresses.
Table 4.7.3.1 Control bits of clock timer
Address Comment
D3 D2
Register
D1 D0 Name Init ∗110
0E4H
TM3 TM2 TM1 TM0
R
TM3
TM2
TM1
TM0
–
∗
2
–
∗
2
–
∗
2
–
∗
2
Clock timer data (2 Hz)
Clock timer data (4 Hz)
Clock timer data (8 Hz)
Clock timer data (16 Hz)
0EBH
0 EIT2 EIT8 EIT32
RR/W
0
∗
3
EIT2
EIT8
EIT32
–
∗
2
0
0
0
–
Enable
Enable
Enable
–
Mask
Mask
Mask
Unused
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
0EFH
0 IT2 IT8 IT32
R
0
∗
3
IT2
∗
4
IT8
∗
4
IT32
∗
4
–
∗
2
0
0
0
–
Yes
Yes
Yes
–
No
No
No
Unused
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
∗1
∗2Initial value at initial reset
Not set in the circuit ∗3
∗4Always "0" being read
Reset (0) immediately after being read
0F9H
0 TMRST 0 0
RW R
0
∗
3
TMRST
∗
3
0
∗
3
0
∗
3
–
∗
2
Reset
–
∗
2
–
∗
2
–
Reset
–
–
–
–
–
–
Unused
Clock timer reset
Unused
Unused
TM0–TM3: Timer data (0E4H)
The l6 Hz to 2 Hz timer data of the clock timer can be read from this register. These four bits are read-
only, and write operations are invalid.
At initial reset, the timer data is initialized to "0H".
EIT32, EIT8, EIT2: Interrupt mask registers (0EBH•D0–D2)
These registers are used to mask the clock timer interrupt.
When 1 is written: Enabled
When 0 is written: Masked
Reading: Valid
The interrupt mask registers (EIT32, EIT8, EIT2) mask the corresponding interrupt frequencies (32 Hz, 8
Hz, 2 Hz).
At initial reset, these registers are all set to 0.
IT32, IT8, IT2: Interrupt factor flags (0EFH•D0–D2)
These flags indicate the status of the clock timer interrupt.
When 1 is read: Interrupt has occurred
When 0 is read: Interrupt has not occurred
Writing: Invalid
The interrupt factor flags (IT32, IT8, IT2) correspond to the clock timer interrupts (32 Hz, 8 Hz, 2 Hz). The
software can determine from these flags whether there is a clock timer interrupt. However, even if the
interrupt is masked, the flags are set to 1 at the falling edge of the signal. These flags can be reset when
the register is read by the software.
Reading of interrupt factor flags is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not
be generated. Be very careful when interrupt factor flags are in the same address.
At initial reset, these flags are set to 0.
S1C60N04 TECHNICAL MANUAL EPSON 27
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
TMRST: Clock timer reset (0F9H•D2)
This bit resets the clock timer.
When 1 is written: Clock timer reset
When 0 is written: No operation
Reading: Always 0
The clock timer is reset by writing 1 to TMRST. The clock timer starts immediately after this. No opera-
tion results when 0 is written to TMRST.
This bit is write-only, and so is always 0 when read.
4.7.4 Programming notes
(1) Note that the frequencies and times differ from the description in this section when the oscillation
frequency is not 2 MHz. In the case of S1C60N04, tolerance is within 5%.
(2) Reading of interrupt factor flags is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will
not be generated. Be very careful when interrupt factor flags are in the same address.
28 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)
4.8 Interrupt and HALT/SLEEP
Interrupt types
The S1C60N04 provides the following interrupt settings, each of which is maskable.
External interrupt: Input port interrupt (one)
Internal interrupt: Timer interrupt (one)
To enable interrupts, the interrupt flag must be set to 1 (EI) and the necessary related interrupt mask
registers must be set to 1 (enable). When an interrupt occurs, the interrupt flag is automatically reset to 0
(DI) and interrupts after that are inhibited.
Figure 4.8.1 shows the configuration of the interrupt circuit.
K00
EIK00
K01
EIK01
K02
EIK02
K03
EIK03
IT2
EIT2
IT8
EIT8
IT32
EIT32
IK0
(MSB)
:
:
(LSB)
Program counter of CPU
(three low-order bits)
SLEEP
cancellation
Interrupt vector
Interrupt factor flag
Interrupt mask register
Interrupt flag
INT
(Interrupt request)
Fig. 4.8.1 Configuration of interrupt circuit
S1C60N04 TECHNICAL MANUAL EPSON 29
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)
HALT and SLEEP modes
When the HALT instruction is executed, the CPU stops operating and enters the HALT mode. The
oscillation circuit and the peripheral circuits operate in the HALT mode. By an interrupt, the CPU exits
the HALT mode and resumes operating.
Executing the SLP instruction set the IC in the SLEEP mode that stops operations of the CPU and oscilla-
tion circuit. The SLEEP mode will be canceled by an input interrupt request from the input port K00–K03.
Consequently, at least one input port (K00, K01, K02 or K03) interrupt must be enabled before shifting to
the SLEEP status. When the SLEEP status is canceled by a K0n input interrupt, the CPU waits for oscilla-
tion to stabilize then restarts operating.
Refer to the "S1C6200/6200A Core CPU Manual" for transition to the HALT/SLEEP status and timing of
its cancellation.
Figures 4.8.2, 4.8.3 and 4.8.4 show the sequence to enter and cancel the SLEEP mode, respectively.
Program counter
USLP (controlled by software
command "SLP")
CLK
K input
Interrupt mask register
PC PC+1 PC+2 PC+3 PC+4
Fig. 4.8.2 Entering SLEEP mode
Program counter
USLP (controlled by software
command "SLP")
CLK
K input
Interrupt mask register
PC+4 PC+4 104H PC+4 PC+5
Waiting for clock stabilization Execute K-input interrupt service routine
Key interrupt vector
Interrupt service routine
start address Interrupt service routine
end address
Fig. 4.8.3 Wakeup from SLEEP mode by K-input
Program counter
USLP
(controlled by software
command "SLP")
CLK
RESET input
Interrupt mask register
PC+4 100H 101H 102H 103H
Fig. 4.8.4 Wakeup from SLEEP mode by RESET pad
30 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)
4.8.1 Interrupt factors
Table 4.8.1.1 shows the factors that generate interrupt requests.
The interrupt factor flags are set to 1 depending on the corresponding interrupt factors.
The CPU is interrupted when the following two conditions occur and an interrupt factor flag is set to 1.
• The corresponding mask register is 1 (enabled)
• The interrupt flag is 1 (EI)
The interrupt factor flag is a read-only register, but can be reset to 0 when the register data is read.
At initial reset, the interrupt factor flags are reset to 0.
Note: Reading of interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1,
an interrupt request will be generated by the interrupt factor flag set timing, or an interr upt request
will not be generated. Be ver y careful when interrupt factor flags are in the same address.
Table 4.8.1.1 Interrupt factors
Interrupt factor
Clock timer 2 Hz falling edge
Clock timer 8 Hz falling edge
Clock timer 32 Hz falling edge
Input (K00–K03) port rising edge
Interrupt factor flag
IT2 (0EFH•D2)
IT8 (0EFH•D1)
IT32 (0EFH•D0)
IK0 (0EDH•D0)
4.8.2 Specific masks for interrupt
The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt
mask registers are read/write registers. The interrupts are enabled when 1 is written to them, and
masked (interrupt disabled) when 0 is written to them.
At initial reset, the interrupt mask register is set to 0.
Table 4.8.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags.
Table 4.8.2.1 Interrupt mask registers and interrupt factor flags
Interrupt mask register
EIT2 (0EBH•D2)
EIT8 (0EBH•D1)
EIT32 (0EBH•D0)
EIK03* (0E8H•D3)
EIK02* (0E8H•D2)
EIK01* (0E8H•D1)
EIK00* (0E8H•D0)
Interrupt factor flag
IT2 (0EFH•D2)
IT8 (0EFH•D1)
IT32 (0EFH•D0)
IK0 (0EDH•D0)
∗ There is an interrupt mask register for each input port pin.
S1C60N04 TECHNICAL MANUAL EPSON 31
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)
4.8.3 Interrupt vectors
When an interrupt request is input to the CPU, the CPU starts interrupt processing. After the program
being executed is suspended, interrupt processing is executed in the following order:
➀The address data (value of the program counter) of the program step to be executed next is saved on
the stack (RAM).
➁The interrupt request causes the value of the interrupt vector (page 1, 01H–07H) to be loaded into the
program counter.
➂The program at the specified address is executed (execution of interrupt processing routine).
Note: The processing in steps 1 and 2, above, takes 12 cycles of the CPU system clock.
Table 4.8.3.1 Interrupt vector addresses
Page
1Step
00H
01H
04H
05H
Interrupt vector
Initial reset
Clock timer interrupt
Input (K00–K03) interrupt
Clock timer & Input (K00–K03) interrupt
4.8.4 I/O memory of interrupt
Table 4.8.4.1 shows the interrupt control bits and their addresses.
Table 4.8.4.1 Control bits of interrupt
Address Comment
D3 D2
Register
D1 D0 Name Init ∗110
0E8H
EIK03 EIK02 EIK01 EIK00
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
0EBH
0 EIT2 EIT8 EIT32
RR/W
0
∗
3
EIT2
EIT8
EIT32
–
∗
2
0
0
0
–
Enable
Enable
Enable
–
Mask
Mask
Mask
Unused
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
0EDH
000IK0
R
0
∗
3
0
∗
3
0
∗
3
IK0
∗
4
–
∗
2
–
∗
2
–
∗
2
0
–
–
–
Yes
–
–
–
No
Unused
Unused
Unused
Interrupt factor flag (K00–K03)
0EFH
0 IT2 IT8 IT32
R
0
∗
3
IT2
∗
4
IT8
∗
4
IT32
∗
4
–
∗
2
0
0
0
–
Yes
Yes
Yes
–
No
No
No
Unused
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
∗1
∗2Initial value at initial reset
Not set in the circuit ∗3
∗4Always "0" being read
Reset (0) immediately after being read
EIT32, EIT8, EIT2: Interrupt mask registers (0EBH•D0–D2)
IT32, IT8, IT2: Interrupt factor flags (0EFH•D0–D2)
...See Section 4.7, "Clock Timer".
EIK00–EIK03: Interrupt mask registers (0E8H)
IK0: Interrupt factor flag (0EDH•D0)
...See Section 4.3, "Input Ports".
32 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT/SLEEP)
4.8.5 Programming notes
(1) Restart from the HALT mode is performed by an interrupt. The return address after completion of the
interrupt processing will be the address following the HALT instruction.
(2) Restart from the SLEEP mode is performed by an input interrupt from the input port (K00–K03). The
return address after completion of the interrupt processing will be the address following the SLP
instruction. At least one input port interrupt must be enabled before shifting to the SLEEP mode.
(3) When an interrupt occurs, the interrupt flag will be reset by the hardware and it will become DI
status. After completion of the interrupt processing, set to the EI status through the software as
needed.
Moreover, the nesting level may be set to be programmable by setting to the EI state at the beginning
of the interrupt processing routine.
(4) The interrupt factor flags must always be reset before setting the EI status. When the interrupt mask
register has been set to 1, the same interrupt will occur again if the EI status is set unless of resetting
the interrupt factor flag.
(5) The interrupt factor flag will be reset by reading through the software. Because of this, when multiple
interrupt factor flags are to be assigned to the same address, perform the flag check after the contents
of the address has been stored in the RAM. Direct checking with the FAN instruction will cause all the
interrupt factor flag to be reset.
(6) Reading of interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to 1, an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will
not be generated. Be very careful when interrupt factor flags are in the same address.
S1C60N04 TECHNICAL MANUAL EPSON 33
CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM
CHAPTER 5BASIC EXTERNAL WIRING D IAGRAM
Piezo Buzzer Single Terminal Driving
C
1
R
CR
Piezo
Buzzer
R01 (BZ)
K00
K03
P00
P03
R00 (FOUT)
R02
R03
I
I/O
O
SEG0
SEG25
COM0
COM3
LCD PANEL
Coil
VDD
OSC1
OSC2
RESET
TEST
VSS
Cp
S1C60N04
[The potential of the substrate
(back of the chip) is VDD.]
Piezo Buzzer Direct Driving
C
1
R
CR
R00 (BZ)
K00
K03
P00
P03
R02
R03
I
I/O
O
SEG0
SEG25
COM0
COM3
LCD PANEL
V
DD
OSC1
OSC2
RESET
TEST
VSS
Cp
Piezo
Buzzer
R01 (BZ)
S1C60N04
[The potential of the substrate
(back of the chip) is VDD.]
R
2
R
1
RCR
C1
Cp
R1, R2
Resistor
Capacitor
Capacitor
Resistor
50 kΩ (VSS = -5.0 V), 39 kΩ (VSS = -3.0 V)
0.1 µF
3.3 µF
100 Ω
Note: The above table is simply an example, and is not guaranteed to work.
34 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 6: ELECTRICAL CHARACTERISTICS
CHAPTER 6ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Rating
Item
Supply voltage
Input voltage (1)
Input voltage (2)
Permissible total output current
∗1
Operating temperature
Storage temperature
Soldering temperature / time
Permissible dissipation ∗2
∗1
∗2
(VDD=0V)
Symbol
VSS
VI
VIOSC
ΣIVSS
Topr
Tstg
Tsol
PD
Rated value
-7.0 to 0.5
VSS - 0.3 to 0.5
VS1 - 0.3 to 0.5
40
-20 to 70
-65 to 150
260°C, 10sec (lead section)
250
Unit
V
V
V
mA
°C
°C
–
mW
The permissible total output current is the sum total of the current (average current) that simultaneously flows from the
output pin (or is drawn in).
In case of plastic package (QFP12-48pin).
6.2 Recommended Operating Conditions
Item
Supply voltage
Oscillation frequency
(Ta=-20 to 70°C)
Symbol
VSS
fOSC
Unit
V
V
MHz
Max.
-2.7
-4.5
Typ.
-3.0
-5.0
2
Min.
-3.6
-5.5
Condition
3 V system, VDD=0V
5 V system, VDD=0V
CR oscillation, RCR=50kΩ, VSS=-5V
S1C60N04 TECHNICAL MANUAL EPSON 35
CHAPTER 6: ELECTRICAL CHARACTERISTICS
6.3 DC Characteristics
Item
High level input voltage (1)
High level input voltage (2)
Low level input voltage (1)
Low level input voltage (2)
High level input current (1)
High level input current (2)
High level input current (3)
Low level input current
High level output current (1)
High level output current (2)
High level output current (3)
Low level output current (1)
Low level output current (2)
Common output current
Segment output current
(during LCD output)
Segment output current
(during DC output)
Unless otherwise specified:
VDD=0V, VSS=-5.0V, fosc=2MHz, Ta=25°C
Symbol
VIH1
VIH2
VIL1
VIL2
IIH1
IIH2
IIH3
IIL
IOH1
IOH2
IOH3
IOL1
IOL2
IOH4
IOL4
IOH5
IOL5
IOH6
IOL6
Unit
V
V
V
V
µA
µA
µA
µA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
Max.
0
0
0.8·VSS
0.9·VSS
0.5
70
150
0
-3.0
-3.0
-15
-3
-3
-450
Typ.
40
100
Min.
0.2·VSS
0.1·VSS
VSS
VSS
0
20
50
-0.5
3.0
3.0
3
3
450
Condition
K00–03, P00–03
RESET
K00–03, P00–03
RESET
VIH1=0V, No pull-down K00–03, P00–P03
VIH2=0V, Pull-down K00–03
VIH3=0V, Pull-down P00–03, RESET
VIL=VSS K00–03, P00–03,
RESET, TEST
VOH1=0.1·VSS R02, R03, P00–03
VOH2=0.1·VSS R00, R01
(with protection resistor)
VOH3=0.1·VSS , VSS=-4.5V R03
VOL1=0.9·VSS R02, R03, P00–03
VOL2=0.9·VSS R00, R01
(with protection resistor)
VOH4=-0.05V COM0–3
VOL4=VSS+0.05V
VOH5=-0.05V SEG0–25
VOL5=VSS+0.05V
VOH6=0.1·VSS SEG0–25
VOL6=0.9·VSS
Item
High level input voltage (1)
High level input voltage (2)
Low level input voltage (1)
Low level input voltage (2)
High level input current (1)
High level input current (2)
High level input current (3)
Low level input current
High level output current (1)
High level output current (2)
High level output current (3)
Low level output current (1)
Low level output current (2)
Common output current
Segment output current
(during LCD output)
Segment output current
(during DC output)
Unless otherwise specified:
VDD=0V, VSS=-3.0V, fosc=2MHz, Ta=25°C
Symbol
VIH1
VIH2
VIL1
VIL2
IIH1
IIH2
IIH3
IIL
IOH1
IOH2
IOH3
IOL1
IOL2
IOH4
IOL4
IOH5
IOL5
IOH6
IOL6
Unit
V
V
V
V
µA
µA
µA
µA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
Max.
0
0
0.8·VSS
0.9·VSS
0.5
40
100
0
-1.0
-1.0
-5
-3
-3
-200
Typ.
25
60
Min.
0.2·VSS
0.1·VSS
VSS
VSS
0
10
30
-0.5
3.0
3.0
3
3
200
Condition
K00–03, P00–03
RESET
K00–03, P00–03
RESET
VIH1=0V, No pull-down K00–03, P00–P03
VIH2=0V, Pull-down K00–03
VIH3=0V, Pull-down P00–03, RESET
VIL=VSS K00–03, P00–03,
RESET, TEST
VOH1=0.1·VSS R02, R03, P00–03
VOH2=0.1·VSS R00, R01
(with protection resistor)
VOH3=0.1·VSS , VSS=-2.7V R03
VOL1=0.9·VSS R02, R03, P00–03
VOL2=0.9·VSS R00, R01
(with protection resistor)
VOH4=-0.05V COM0–3
VOL4=VSS+0.05V
VOH5=-0.05V SEG0–25
VOL5=VSS+0.05V
VOH6=0.1·VSS SEG0–25
VOL6=0.9·VSS
36 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 6: ELECTRICAL CHARACTERISTICS
6.4 Current Consumption
Item
Current consumption
Unless otherwise specified:
V
DD
=0V, fosc=2MHz, Ta=25°C
Symbol
I
SLP2
I
HALT2
I
HALT4
I
EXE2
I
EXE4
I
SLP1
I
HALT1
I
HALT3
I
EXE1
I
EXE3
Unit
nA
µA
µA
µA
µA
nA
µA
µA
µA
µA
Max.
100
800
800
1000
1000
100
1500
1500
1800
1800
Typ.
300
330
420
450
950
1000
1050
1100
Min.Condition
During SLEEP, LCD off Vss=-3.0V
During HALT, LCD off no panel load
During HALT, LCD on R
CR
=39kΩ
During operation, LCD off
During operation, LCD on
During SLEEP, LCD off Vss=-5.0V
During HALT, LCD off no panel load
During HALT, LCD on R
CR
=50kΩ
During operation, LCD off
During operation, LCD on
6.5 Oscillation Characteristics
Oscillation characteristics will vary according to different conditions (elements used, board pattern). Use
the following characteristics are as reference values.
CR Oscillation
Item
Frequency voltage dispersion
Frequency IC dispersion
Oscillation start time
Symbol
∆f/∆V1
∆f/∆IC1
tsta
Unit
%
%
mS
Max.
20
20
Typ.
(2MHz)
3
Min.
-20
Condition
VSS=-4.5 to -5.5V
VSS=-5V
VSS=-4.5 to -5.5V
Unless otherwise specified:
VDD=0V, VSS=-5.0V, RCR=50kΩ, Ta=25°C
Item
Frequency voltage dispersion
Frequency IC dispersion
Oscillation start time
Symbol
∆f/∆V2
∆f/∆IC2
tsta
Unit
%
%
mS
Max.
30
20
Typ.
(2MHz)
3
Min.
-20
Condition
VSS=-2.7 to -3.6V
VSS=-3V
VSS=-2.7 to -3.6V
Unless otherwise specified:
VDD=0V, VSS=-3.0V, RCR=39kΩ, Ta=25°C
6.6 LCD Characteristic
Item
Internal voltage Symbol
V
L1
Unit
V
Max.
(V
SS
/3)
×0.9
Typ.
V
SS
/3
Min.
(V
SS
/3)
-0.1
Condition
Connect 1 MΩ load resistor between V
DD
and
common pad (without panel load)
Unless otherwise specified:
V
DD
=0V, V
SS
=V
L3
, Ta=25°C
S1C60N04 TECHNICAL MANUAL EPSON 37
CHAPTER 7: PACKAGE
CHAPTER 7PACKAGE
7.1 Plastic Package
QFP12-48pin (Unit: mm)
7
±0.1
9
±0.4
2536
7
±0.1
9
±0.4
13
24
INDEX
0.18
121
48
37
1.4
±0.1
0.1
1.7max
1
0.5
±0.2
0°
10°
0.125
±0.05
0.5
+0.1
–0.05
38 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 7: PACKAGE
22.8
23.1
78.7
2.54
PIN NO. 1 2 31 32
34 3364 63
INDEX MARK
81.3
7.2 Ceramic Package for Test Samples
(Unit: mm)
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin name
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
N.C.
N.C.
N.C.
N.C.
N.C.
COM0
COM1
COM2
COM3
TEST
No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin name
RESET
V
DD
OSC1
OSC2
V
SS
K03
N.C.
N.C.
N.C.
N.C.
N.C.
K02
K01
K00
P03
P02
No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin name
P01
P00
R03
R02
R01
R00
N.C.
N.C.
N.C.
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
No.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Pin name
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
N.C.
N.C.
N.C.
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
N.C. = No Connection
S1C60N04 TECHNICAL MANUAL EPSON 39
CHAPTER 8: PAD LAYOUT
CHAPTER 8PAD LAYOUT
8.1 Diagram of Pad Layout
8.2 Pad Coordinates
X
(0, 0)
1510
Die No.
15
20
25 40
45
48
Y
30 35
2.44 mm
2.79 mm
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pad name
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
X
885
755
625
495
365
211
82
-48
-178
-308
-438
-568
-698
-828
-1226
-1226
Y
1053
1053
1053
1053
1053
1053
1053
1053
1053
1053
1053
1053
1053
1053
670
540
No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pad name
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM0
COM1
COM2
COM3
TEST
RESET
X
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1226
-1054
-924
-794
-664
-14
116
Y
410
280
150
20
-109
-240
-370
-500
-630
-760
-1053
-1053
-1053
-1053
-1053
-1053
No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pad name
V
DD
OSC1
OSC2
V
SS
K03
K02
K01
K00
P03
P02
P01
P00
R03
R02
R01
R00
X
667
797
927
1057
1187
1226
1226
1226
1226
1226
1226
1226
1226
1226
1226
1226
Y
-1053
-1053
-1053
-1053
-1053
-776
-646
-516
-67
63
193
323
469
603
742
960
Unit: µm
40 EPSON S1C60N04 TECHNICAL MANUAL
CHAPTER 9: PRECAUTIONS ON MOUNTING
CHAPTER 9PRECAUTIONS ON MOUNTING
<Oscillation Circuit>
●Oscillation characteristics change depending on conditions (board pattern, components used, etc.).
In particular, when a ceramic oscillator or crystal oscillator is used, use the oscillator manufacturer’s
recommended values for constants such as capacitance and resistance.
●Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following
points to prevent this:
(1) Components which are connected to the OSC1
and OSC2 terminals, such as oscillators,
resistors and capacitors, should be connected in
the shortest line.
(2) As shown in the right hand figure, make a VDD
pattern as large as possible at circumscription
of the OSC1 and OSC2 terminals and the
components connected to these terminals.
Furthermore, do not use this VDD pattern for
any purpose other than the oscillation system.
OSC1
OSC2
VDD
Sample VDD pattern
●In order to prevent unstable operation of the oscillation circuit due to current leak between OSC1 and
VSS, please keep enough distance between OSC1 and VSS or other signals on the board pattern.
<Reset Circuit>
●The power-on reset signal which is input to the RESET terminal changes depending on conditions
(power rise time, components used, board pattern, etc.).
Decide the time constant of the capacitor and resistor after enough tests have been completed with the
application product.
When the built-in pull-down resistor of the RESET terminal, take into consideration dispersion of the
resistance for setting the constant.
●In order to prevent any occurrences of unnecessary resetting caused by noise during operating,
components such as capacitors and resistors should be connected to the RESET terminal in the
shortest line.
<Power Supply Circuit>
●Sudden power supply variation due to noise may cause malfunction. Consider the following points to
prevent this:
(1) The power supply should be connected to the VDD and VSS terminal with patterns as short and
large as possible.
(2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals
should be connected as short as possible.
V
DD
V
SS
Bypass capacitor connection example
V
DD
V
SS
S1C60N04 TECHNICAL MANUAL EPSON 41
CHAPTER 9: PRECAUTIONS ON MOUNTING
<Arrangement of Signal Lines>
●In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do
not arrange a large current signal line near the circuits that are sensitive to noise such as the oscilla-
tion unit.
●When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line,
noise may generated by mutual interference between the signals and it may cause a malfunction.
Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the
oscillation unit.
OSC1
OSC2
Large current signal line
High-speed signal line
Prohibited pattern
<Precautions for Visible Radiation (when bare chip is mounted)>
●Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause
this IC to malfunction. When developing products which use this IC, consider the following precau-
tions to prevent malfunctions caused by visible radiations.
(1) Design the product and implement the IC on the board so that it is shielded from visible radiation
in actual use.
(2) The inspection process of the product needs an environment that shields the IC from visible
radiation.
(3) As well as the face of the IC, shield the back and side too.
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Electronic Device Marketing Department
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Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624
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International Sales Operations
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http://www.epson.co.jp/device/
Technical Manual
S1C60N04
EPSON Electronic Devices Website
ELECTRONIC DEVICES MARKETING DIVISION
First issue September, 1998
Printed February, 2001 in Japan A
M
