Copyright ©2008 by Zilog®, Inc. All rights reserved.
www.zilog.com
Product Block Diagram
Features
•Two independent fu ll-duplex channels with a
crystal oscillator, a baud rate generator (BRG)
and a digital phase locked loop (DPLL) in each
channel
•Pin-compatible with the Z8030/Z85 30 an d t he
Z80C30/Z85C30
•4-Byte transmit FIFO and 8-Byte receive FIFO
for each channel
•Asynchronous capabilities:
–5, 6, 7, or 8 bits/character
–1, 1.5, or 2 Stop bits
–Odd or Even parity
–Parity, Overrun, and Framing Error detec-
tion
•Synchronous/Isosynchronous data rates:
–Up to 1/4 of PCLK using an external clock
–Up to 1/8 of PCLK using DPLL in FM
mode
–Up to 1/16 of PCLK using DPLL in NRZI
mode
•Character-oriented synchronous capabilities:
–Internal or external synchronization
–1 or 2 SYNC characters (6 or 8 bits/charac-
ter)
–NRZ, NRZI, or FM encoding/decoding, as
well as Manchester decoding
–Cyclic redundancy check (CRC-16,
CRC-CCITT) generation/detection
•SDLC/HDLC Capabilities:
–Automatic zero insertion and detection
–Automatic flag insertion between mesages
–Address field recognition
–CRC generation/detection
General Description
Zilog’s Enhanced Serial Communications Control-
lers (ESCC, Z80230/Z85230) are pin- and soft-
ware-compatible members of the SCC family. The
ESCC is a dual-channel, full-duplex multiprotocol
data communication peripheral, designed for use
with both 8- and 16-bit microprocessors. The
ESCC is an enhanced version of Zilog’s industry
standard SCC core (Z8030/Z8530) which was
introduced by Zilog in 1981.
The ESCC handles asynchronous formats, byte-
oriented synchronous protocols such as MONO-
SYNC and BISYNC, and bit-oriented synchronous
protocols such as HDLC and SDLC.
The device can generate and check CRC codes in
any synchronous mode, and can be prog rammed to
check data integrity in various modes. The ESCC
also has facilities for modem control in both chan-
nels. In applications where these controls are not
needed, the modem controls can be used for gen-
eral-purpose I/O.
With access to 16 WRITE REGISTERS and 10
READ REGISTERS per channel, the user can
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ESCC™ ENHANCED SERIAL COMMUNICATION CONTROLLERS
PB000401-0608
Z80230/Z85230
Product Brief
PB000401-0608 Page 2 of 4
Z80230/Z85230 ESCC™ Enhanced Serial Communication Controller
configure the ESCC to hand le all synchronous for-
mats regardless of data size, number of stop bits, or
parity requirements.
W ithin each operating mode, the ESCC al so allows
for protocol variations by checking odd or even
parity bits, character insertion or deletion, CRC
generation, checking break and abort generation
and detection, and man y oth er protocol-dependent
features.
The ESCC has many improvements that signifi-
cantly reduce CPU overhead. The addition of a
4-byte transmit FIFO and an 8-byte receive FIFO
significantly reduces the overhead required to pro-
vide data to the transmitters, and to get data from
the receivers.
The ESCC also has many features that improve
packet handling in SDLC mode. The combination
of these features, along with the deeper data FIFOs,
significantly simplifies SDLC driver software.
Related Products
Similar communication controllers available from
Zilog’s SCC family include:
Ordering Information
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Z8030
Z8530 NMOS SCC (Serial Communication
Controller)
Z80C30
Z85C30 CMOS SCC (Serial Communication
Controller)
Z16C35 ISCC Single-Channel SCC with Built-in
DMA Controllers
Z16C30 USC (Un iversal Communication Control-
ler)
Z16C32 IUSC Single-Channel USC with Built-in
DMA Controllers
PSI Description
ESCC with Multiplex Bus Interface
Z8023010PSC 10MHz 40-Pin DIP ESCC
Z8023010VSC 10MHz 44-Pin PLCC ESCC
Z8023016PSC 16MHz 40-Pin DIP ESCC
Z8023016VSC 16MHz 44-Pin PLCC ESCC
ESCC with Non-Multiplex Bus Interface
Z8523008PSC 8MHz 40-Pin DIP ESCC
Z8523008VSC 8MHz 44-Pin PLCC ESCC
PB000401-0608 Page 3 of 4
Z80230/Z85230 ESCC™ Enhanced Serial Communication Controller
To order, contact your nearest Zilog sales office or
visit Zilog’s Technical Support at
http://support.zilog.com.
Z8523010PSC 10MHz 40-Pin DIP ESCC
Z8523010VSC 10MHz 44-Pin PLCC ESCC
Z8523016PSC 16MHz 40-Pin DIP ESCC
Z8523016VSC 16MHz 44-Pin PLCC ESCC
Z8523020PSC 20MHz 40-Pin DIP ESCC
Z8523020VSC 20MHz 44-Pin PLCC ESCC
ESCC Evaluation Boards
Z8523000ZCO ISA Bus Evaluation Board
Z8018000ZCO Z180 Evaluation Board
Z8018600ZCO 80186 Evaluation Board
PB000401-0608 Page 4 of 4
Z80230/Z85230 ESCC™ Enhanced Serial Communication Controller
DO NOT USE IN LIFE SUPPORT
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICA L COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.
Document Disclaimer
©2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this
document has be en verified according to the gene ral pr inciples of electrical and mechanical engineering.
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