SN54LVTH240, SN74LVTH240
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DSupport Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
DSupport Unregulated Battery Operation
Down to 2.7 V
DTypical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
DIoff and Power-Up 3-State Support Hot
Insertion
DBus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
DLatch-Up Performance Exceeds 500 mA Per
JESD 17
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
SN54LVTH240 ...J OR W PACKAGE
SN74LVTH240 . . . DB, DW, NS,
OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
SN54LVTH240 . . . FK PACKAGE
(TOP VIEW)
2Y4
1A1
1OE
1Y4
2A2 2OE
2Y1
GND
2A1
VCC
SN74LVTH240 . . . RGY PACKAGE
(TOP VIEW)
120
10 11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
2A1 V
GND
CC
1OE
description/ordering information
These octal buffers and line drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY Tape and reel SN74LVTH240RGYR LXH240
SOIC DW
Tube SN74LVTH240DW
LVTH240
SOIC − DW Tape and reel SN74LVTH240DWR LVTH240
SOP − NS Tape and reel SN74LVTH240NSR LVTH240
−40°C to 85°CSSOP − DB Tape and reel SN74LVTH240DBR LXH240
40 C
to
85 C
TSSOP PW
Tube SN74LVTH240PW
LXH240
TSSOP − PW Tape and reel SN74LVTH240PWR LXH240
VFBGA − GQN
Tape and reel
SN74LVTH240GQNR
LXH240
VFBGA − ZQN (Pb-free) Tape and reel SN74LVTH240ZQNR LXH240
CDIP − J Tube SNJ54LVTH240J SNJ54LVTH240J
−55°C to 125°CCFP − W Tube SNJ54LVTH240W SNJ54LVTH240W
55 C
to
125 C
LCCC − FK Tube SNJ54LVTH240FK SNJ54LVTH240FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright © 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LVTH240, SN74LVTH240
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
These devices are organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When OE
is low, the devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
terminal assignments
1234
A1A1 1OE VCC 2OE
B1A2 2A4 2Y4 1Y1
C1A3 2Y3 2A3 1Y2
D1A4 2A2 2Y2 1Y3
EGND 2Y1 2A1 1Y4
FUNCTION TABLE
(each 4-bit buffer)
INPUTS OUTPUT
OE A
OUTPUT
Y
L H L
LLH
H X Z
SN74LVTH240 . . . GQN OR ZQN PACKAGE
(TOP VIEW)
1234
A
B
C
D
E
SN54LVTH240, SN74LVTH240
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
218
1Y1
1OE
1A1
416
1Y2
1A2
614
1Y3
1A3
812
1Y4
1A4
19
11 9 2Y1
2OE
2A1
13 7 2Y2
2A2
15 5 2Y3
2A3
17 3 2Y4
2A4
Pin numbers shown are for the DB, DW, FK, J, NS, PW, RGY, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . .
Current into any output in the low state, IO: SN54LVTH240 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVTH240 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, IO (see Note 2): SN54LVTH240 48 mA. . . . . . . . . . . . . . . . . . . . . . .
SN74LVTH240 64 mA. . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): GQN/ZQN package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 4): RGY package 37°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
SN54LVTH240, SN74LVTH240
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 5)
SN54LVTH240 SN74LVTH240
UNIT
MIN MAX MIN MAX UNIT
VCC Supply voltage 2.7 3.6 2.7 3.6 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 5.5 5.5 V
IOH High-level output current −24 −32 mA
IOL Low-level output current 48 64 mA
Δt/ΔvInput transition rise or fall rate Outputs enabled 10 10 ns/V
Δt/ΔVCC Power-up ramp rate 200 200 μs/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 5: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54LVTH240, SN74LVTH240
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LVTH240 SN74LVTH240
UNIT
PARAMETER TEST CONDITIONS MIN TYP†MAX MIN TYP†MAX UNIT
VIK VCC = 2.7 V, II = −18 mA −1.2 −1.2 V
VCC = 2.7 V to 3.6 V, IOH = −100 μA VCC−0.2 VCC−0.2
V
VCC = 2.7 V, IOH = −8 mA 2.4 2.4
V
VOH
IOH = −24 mA 2V
VCC = 3 V IOH = −32 mA 2
IOL = 100 μA 0.2 0.2
VCC = 2.7 V IOL = 24 mA 0.5 0.5
V
IOL = 16 mA 0.4 0.4
V
VOL
IOL = 32 mA 0.5 0.5 V
VCC = 3 V IOL = 48 mA 0.55
IOL = 64 mA 0.55
Control inputs
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
I
Control inputs VCC = 3.6 V, VI = VCC or GND ±1±1
A
II
Data inputs
VI = VCC 1 1 μA
Data inputs VCC = 3.6 V VI = 0 −5 −5
Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 μA
VI = 0.8 V 75 75
II(h ld)
Data inputs
VCC = 3 V VI = 2 V −75 −75
μA
I
I(hold)
D
ata
i
nputs
VCC = 3.6 V‡, VI = 0 to 3.6 V 500
−750
μ
A
IOZH VCC = 3.6 V, VO = 3 V 5 5 μA
IOZL VCC = 3.6 V, VO = 0.5 V −5 −5 μA
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don’t care ±100∗±100 μA
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don’t care ±100∗±100 μA
=
Outputs high 0.19 0.19
ICC
CC =
.
,
IO = 0, Outputs low 5 5 mA
ICC
VI = VCC or GND Outputs disabled 0.19 0.19
mA
ΔICC§
VCC = 3 V to 3.6 V,
One input at VCC − 0.6 V,
Other inputs at VCC or GND
0.2 0.2 mA
CiVI = 3 V or 0 3 3 pF
CoVO = 3 V or 0 7 7 pF
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
SN54LVTH240, SN74LVTH240
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVTH240 SN74LVTH240
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V VCC = 2.7 V UNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
tPLH
A
Y
0.9 4.3 5.1 1.1 2.2 3.8 4.6
ns
tPHL
A Y 1.2 4.7 4.9 1.3 2.6 4 4.2 ns
tPZH
OE
Y
1 5.7 6.7 1.1 2.6 4.6 5.6
ns
tPZL
OE Y1.2 5.5 6.2 1.4 2.7 4.4 5 ns
tPHZ
OE
Y
1 5.1 5.2 2 2.9 4.4 4.6
ns
tPLZ
OE Y1.1 5.4 5.4 1.8 3 4.3 4.3 ns
†All typical values are at VCC = 3.3 V, TA = 25°C.
SN54LVTH240, SN74LVTH240
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS679K − DECEMBER 1996 − REVISED SEPTEMBER 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V
2.7 V
0 V
1.5 V 1.5 V
2.7 V
0 V
2.7 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V
2.7 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
3 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH − 0.3 V
≈0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9950801Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9950801Q2A
SNJ54LVTH
240FK
5962-9950801QRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9950801QR
A
SNJ54LVTH240J
5962-9950801QSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9950801QS
A
SNJ54LVTH240W
5962-9950801V2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 5962-
9950801V2A
SNV54LVTH
240FK
5962-9950801VRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type 5962-9950801VR
A
SNV54LVTH240J
SN74LVTH240DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI -40 to 85
SN74LVTH240DBR ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LXH240
SN74LVTH240DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LXH240
SN74LVTH240DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LXH240
SN74LVTH240DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH240
SN74LVTH240DWE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH240
SN74LVTH240DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH240
SN74LVTH240DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH240
SN74LVTH240DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH240
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVTH240DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH240
SN74LVTH240GQNR OBSOLETE BGA
MICROSTAR
JUNIOR
GQN 20 TBD Call TI Call TI -40 to 85 LXH240
SN74LVTH240NSR ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH240
SN74LVTH240NSRE4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH240
SN74LVTH240NSRG4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH240
SN74LVTH240PW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LXH240
SN74LVTH240PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LXH240
SN74LVTH240PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LXH240
SN74LVTH240PWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI -40 to 85
SN74LVTH240PWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LXH240
SN74LVTH240PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LXH240
SN74LVTH240PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 LXH240
SNJ54LVTH240FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
9950801Q2A
SNJ54LVTH
240FK
SNJ54LVTH240J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9950801QR
A
SNJ54LVTH240J
SNJ54LVTH240W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9950801QS
A
SNJ54LVTH240W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVTH240, SN54LVTH240-SP, SN74LVTH240 :
•Catalog: SN74LVTH240, SN54LVTH240
•Enhanced Product: SN74LVTH240-EP, SN74LVTH240-EP
•Military: SN54LVTH240
•Space: SN54LVTH240-SP
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 4
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVTH240DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74LVTH240DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN74LVTH240NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1
SN74LVTH240PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Oct-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVTH240DBR SSOP DB 20 2000 367.0 367.0 38.0
SN74LVTH240DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74LVTH240NSR SO NS 20 2000 367.0 367.0 45.0
SN74LVTH240PWR TSSOP PW 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Oct-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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