MP86963
High Efficiency, 20A, 27V Intelli-PhaseTM Solution
(Integrated HS/LS FETs and Driver) in a 5x5mm QFN
MP86963 Rev.1.22 www.MonolithicPower.com 1
12/26/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
The Future of Analog IC Technology
DESCRIPTION
The MP86963 is a monolithic Half Bridge with
built-in internal power MOSFETs and gate
driver. It achieves 20A continuous output
current over a wide input supply range.
Integrating the Driver and MOSFETs results in
high efficiency due to optimal dead time control
and parasitic inductance reduction.
The MP86963 is a Monolithic IC designed to
drive up to 20A per phase. Housed in a very
small 5x5mm TQFN Packge, this device can be
operated from 100kHz to 1MHz operation.
The IC is intended to work with 3.3V tri-state
output controllers.
The MP86963 is ideal for notebook applications
where efficiency and small size are a premium.
FEATURES
• Wide 4.5V to 21V Operating Input Range
• 20A Output Current
• Simple Logic Interface (3.3V)
• Operate from 100kHz to 1MHz
• Accepts 3-state PWM Input
• Suitable for single-/multi-phase operation
• Available in a 5mm x 5mm TQFN Package
• ROHS6 Compliant
APPLICATIONS
• Power modules
• Notebook, Core Voltage
• Graphic Card Core Regulators
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithi
c
Power Systems, Inc.
This Product is Patent Pending.
TYPICAL APPLICATION
EN
IN
BST
SW
VCC
GND
PWM
SYNC
AGND
MP86963
4
6
5
3
10-18
2
8
7
9
L
C
IN
V
IN
4.5V-21V
ON/OFF
C
OUT
0.8V to 1.2V @ 20A
C6
100nF
Cs
1F
VCC
5V
VCC IO
EFFICIENCY (%)
OUTPUT CURRENT (A)
50
55
60
65
70
75
80
85
90
95
100
2 4 6 8 10 12 14 16 18 20
V
IN
=12V
V
OUT
=1.2V
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
MP86963 Rev.1.22 www.MonolithicPower.com 2
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© 2013 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number* Package Top Marking Free Air Temperature(TA)
MP86963DUT 5x5 TQFN 86963UT -40°C to +85°C
* For Tape & Reel, add suffix –Z (e.g. MP86963DUT–Z);
For RoHS compliant packaging, add suffix –LF (e.g. MP86963DUT–LF–Z)
PACKAGE REFERENCE
EXPOSED PAD
CONNECT TO PIN
PIN 1 ID
GND
GND
GND
GND
GND
GND
GND
GND
GND
N/C
VCC
EN
SYNC
PWM
VCC IO
BST
IN
AGND
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
GND
GND
GND
GND
SW
IN
IN
IN
IN
SW
SW
SW
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN ....................................... 27V
VSW(DC) .................................-0.3V to VIN +0.3V
VSW(20ns) ....................................-3V to VIN +3V
VBST ...................................................... VSW + 6V
All Other Pins..................................-0.3V to +6V
Continuous Power Dissipation (TA = +25°C) (2)
............................................................. 3.8W
Junction Temperature...............................150°C
Lead Temperature ....................................260°C
Storage Temperature............... -65°C to +150°C
Recommended Operating Conditions (3)
Supply Voltage VIN ...........................4.5V to 21V
VCC Driver Voltage………………….4.5V to 5.5V
Operating Junct. Temp (TJ)...... -40°C to +125°C
Thermal Resistance (4) θJA θJC
5x5 TQFN ............................... 33 ....... 8.... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
TA)/ θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
MP86963 Rev.1.22 www.MonolithicPower.com 3
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© 2013 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameters Symbol Condition Min Typ Max Units
ICC Standby ICC_Stdby VCC =5V, PWM=EN=LO 550 610 μA
IIN (Shutdown) IIN (Off) V
CC = 0V 1 5 μA
IIN Standby IIN_Stdby V
CC =5V, PWM=EN=LO 1 μA
Rise Time IOUT = 20A 5 ns
Fall Time IOUT = 20A 3 ns
Minimum On-Time 55 ns
Dead-Time Rising 5 ns
Dead-Time Falling 10 ns
VCC Under Voltage Lockout Threshold
Rising 3.7 4.2 V
VCC Under Voltage Lockout Threshold
Hysteresis 470 mV
SYNC Pull-Up Current ISYNC SYNC=0V -14 μA
SYNC Logic High Voltage 2 V
SYNC Logic Low Voltage 0.4 V
EN Input Low Voltage 0.4 V
En Input High Voltage 2 V
PWM Input
VPWM=3.3V 370 μA
Input Current IPWM VPWM=0V -370 μA
VCCIO 2.9 3.3 3.6 V
PWM Low to Tri-State Threshold 1.10 V
PWM Tri-State to High Threshold 2.25 V
PWM High to Tri-State Threshold 2.10 V
PWM Tri-State to Low Threshold 0.75 V
Tri-State Shutdown Holdoff Time tTSSHD VCC=5V,
Temperature=25°C 100 ns
UG/LG Three-State Propagation Delay tPTS 20 ns
USW Turn-Off Propagation Delay tPDUL V
CC=5V 40 ns
LSW Turn-Off Propagation Delay tPDLL V
CC=5V 25 ns
USW Turn-On Propagation Delay tPDUH V
CC=5V 30 ns
LSW Turn-On Propagation Delay tPDLH V
CC=5V 50 ns
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
MP86963 Rev.1.22 www.MonolithicPower.com 4
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© 2013 MPS. All Rights Reserved.
t
PDUH
t
PDLL
0V
SW
PWM
V
OUT
t
PDUL
t
PDLH
t
TSSHD
Figure 1—Timing Diagram
PIN FUNCTIONS
Pin # Name Description
1 NC Not Connected.
2 VCC Low-Side Driver Bias Supply. Decouple with a 1µF ceramic capacitor.
3 AGND Signal Ground.
4 EN
Active High On/Off Control. Pulling this Pin Low forces the SW Pin to be in a high
impedance state.
5 SYNC
Leaving this pin Open enables theLower Synchronous Switch. Pulling it Low forces
the Lower Switch into Diode Emulation mode.
6 PWM
Pulse Width Modulation Control. Accepts three-state input. Force PWM to midstate or
open to place SW into high impedance state.
7 VCC IO Reference voltage that connects to PWM driver supply.
8 BST
Bootstrap. This capacitor is needed to drive the power switch’s gate above the supply
voltage. It is connected between SW and BST pins to form a floating supply across
the power switch driver.
9
Exposed Pad IN Supply Voltage. CIN is needed to prevent large voltage spikes from appearing at the
input.
10–18
Exposed Pad GND Power Ground.
Exposed Pad SW Switch Output. These pins are fused together.
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
MP86963 Rev.1.22 www.MonolithicPower.com 5
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© 2013 MPS. All Rights Reserved.
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VCC = 5V, VOUT = 1.2V, TA = +25ºC, unless otherwise noted.
EFFICIENCY (%)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
EFFICIENCY (%)
OUTPUT CURRENT (A)
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20
POWER LOSS (W)POWER LOSS (W)
POWER LOSS (W)
POWER LOSS (W)
OUTPUT CURRENT (A)
POWER LOSS (W)
OUTPUT CURRENT (A)
POWER LOSS (W)
0
0.5
1
1.5
2
2.5
3
3.5
4
0 5 10 15 20
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0 5 10 15 20
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
0
0.5
1
1.5
2
3
3.5
4
8 101214161820
INPUT VOLTAGE (V)
0
1
2
2.5
3
4
8 101214161820
1.9
1.95
2
2.05
2.1
2.15
2.2
2.25
2.3
2.35
0.8 1 1.2 1.4 1.6 1.8 2 2.2
OUTPUT VOLTAGE (V)
20A
15A 300kHz
600kHz
1.0MHz
I
OUT
=15A, Fsw=600kHz
I
OUT
=15A
2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 18 20
EFFICIENCY (%)
OUTPUT CURRENT (A)
50
55
60
65
70
75
80
85
90
95
100
2 4 6 8 10 12 14 16 18 20
50
55
60
65
70
75
80
85
90
95
100
50
55
60
65
70
75
80
85
90
95
100
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
MP86963 Rev.1.22 www.MonolithicPower.com 6
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© 2013 MPS. All Rights Reserved.
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VCC = 5V, VOUT = 1.2V, TA = +25ºC, unless otherwise noted.
Temperature Rise vs.
Output Current
No airflow
V
SW
500mV/div.
SW Rising Edge Dead Time
I
OUT
= 15A
V
SW
1V/div.
SW Falling Edge Dead Time
I
OUT
= 15A
V
SW
5V/div.
Output Waveform
I
OUT
= 20A
V
SW
10V/div.
V
OUT
1V/div.
I
OUT
25A/div.
SOA Waveform
V
IN
= 19V, V
OUT
= 1.2V
I
OUT
= 20Α to 80A, F
SW
= 600kHz
0
10
20
30
40
50
60
70
0 5 10 15 20
OUTPUT CURRENT (A)
CASE TEMPERATURE RISE (
O
C)
300kHz
600kHz
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
MP86963 Rev.1.22 www.MonolithicPower.com 7
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© 2013 MPS. All Rights Reserved.
EFFICIENCY MEASUREMENT SETUP
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
MP86963 Rev.1.22 www.MonolithicPower.com 8
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BLOCK DIAGRAM
HGate
EN
V
OUT
LGate
Tri-State
PWM
VCCIO
V
CC
IO
SYNC M2
SW
IN
BST
GND
V
CC
PWM PWM
Logic
LGate
Diode
Emulation
Logic
EN
V
CC
V
cc
V
cc
150
10.8
5.4
EN
EN
Figure 2—Function Block Diagram
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
MP86963 Rev.1.22 www.MonolithicPower.com 9
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© 2013 MPS. All Rights Reserved.
OPERATION
The MP86963 is a 20A Monolithic Half Bridge
driver with MOSFETs ideally suited for single-
/multi-phase Buck regulators.
Once the EN, VIN, VCCIO, VCC and VBST signals
are sufficiently high, operation begins. BST
voltage has a typical rising UVLO of 2.2V and a
falling UVLO of 2.0V. When BST is below the
UVLO voltage, the device will be off.
MP86963 can work with most PWM controllers.
The device accepts PWM signal from 100kHz up
to 1MHz. There is an internal resistor divider to
put PWM voltage to tri-state region if the PWM
pin is open.
Internally, SYNC is tied to VCC through a resistor.
By default, the device will operate in synchronous
mode. To enter Diode Emulation mode, drive
SYNC pin LOW.
Startup and Shutdown Sequence
MP86963 can work with any startup or shutdown
sequencing combination of VIN, VCC, VCCIO and
EN. If PWM signal is present, the MP86963 will
start working whenever VIN, VCC, VCCIO and EN
are ready. On the other hand, if any of these
signals is not ready, the MP86963 will stop
working. However, it is recommended to turn on
and turn off the device through the EN pin.
PCB Layout Guideline
PCB layout is very important to achieve stable
operation. Please follow these guidelines to
achieve optimal performance.
1) Keep the path of switching current short and
minimize the loop area formed by input capacitor.
Keep the connection between SW pin and input
power ground as short and wide as possible.
2) Always place some input bypass ceramic
capacitors next to the device and on the same
layer as the device. Do not put all of the input
bypass capacitors on the back side of the device.
Use as many vias and input voltage planes as
possible to reduce the switching spike. BST
capacitor and VCC capacitor should also be as
close to the device as possible.
3) The recommended external BST cap is 100nF.
Do not use a capacitance value lower than
100nF. Place a 1.0Ω resistor between the BST
capacitor and BST pin for optimized performance.
4) Do not place via on the pad or on the pin
footprint. Doing so may cause soldering issue
during the assembling process. Use Figure 3 as
a via placement reference.
5) Connect IN, SW and GND to large copper
area and use vias to cool the chip to improve
thermal performance and long-term reliability.
See Figure 4 as an example.
Figure 3—Via Placement Guideline
Do not put via on the device’s pad footprint or pin
footprint to avoid assembly issue. Use as many
vias as possible to cool down the device.
6) Place the VCC decouple capacitor close to the
IC. Connect AGND and PGND at the point of
VCC capacitor's ground connection.
Recommended SMT Setting
Stencil thickness: 0.12mm
EP Pad Opening: (Stencil opening : Real PCB
Size)
Length: 0.85:1
Width: 1:1
Note: The EP pad for Intelli-Phase are IN,
SW and GND pad on the bottom.
Solder type: #3
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
MP86963 Rev.1.22 www.MonolithicPower.com 10
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Figure 4—Copper Area Guideline
Use large copper area, many vias and many IN, SW and GND inner layer planes to achieve optimal
thermal performance.
Input Capacitors
Output
Capacitors
Inductor
Intelli
Phase
(Vin Plane)
(GND Plane)
(SW Plane)
C
V
CC
RBST
CBST
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP86963 Rev.1.22 www.MonolithicPower.com 11
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© 2013 MPS. All Rights Reserved.
PACKAGE INFORMATION
FCTQFN18L (EXPOSED PAD)
SI DE VIEW
TOP VI EW
1
10 9
BOTTOM VIEW
4.90
5.10
4.90
5.10 0.50
BSC
0.70
0.80
0.00
0.05
0.20 R EF
PIN 1 ID
MARKING
RECOMMENDED LAND PATTERN
NOTE:
1) A LL DIMENSIONS AR E IN MILLIMETERS.
2) EXPOSED PA DD LE SIZE DOES NOT INCLUD E
MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 M IL L I M ET ER
MAX.
4) JEDEC REFEREN CE IS MO-229 , VA R IATION WJJD.
5) DRAWING IS NOT TO SCALE.
PIN 1 ID
SEE DETAIL A
PIN 1 ID OPTION B
R0.20 TYP.
PIN 1 ID OPT I ON A
0.20x45” TYP.
DETAIL A
PIN 1 ID
INDEX AREA
18
9
0.30
0.40
0.50
1.50
0.70
0.18
0.30
0.59
BSC1.77
BSC 4.13
BSC
2.95
BSC
1.30
1.50
2.80
BSC
0.40
0.60
0.50
0.70
0.40
0.60
0.25
2.80
4.90
0.60
0.70
0.60
0.59 1.77 2.95 4.13
