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MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD23C16040BL, 23C16080BL
16M-BIT MASK-PROGRAMMABLE ROM
2M-WORD BY 8-BIT (BYTE MODE) / 1M-WORD BY 16-BIT (WORD MODE)
PAGE ACCESS MODE
Document No. M15720EJ3V0DS00 (3rd edition)
Date Published March 2003 NS CP(K)
Printed in Japan
DATA SHEET
The mark shows major revised points.
2001
Description
The
µ
PD23C16040BL and
µ
PD23C16080BL are 16,777,216 bits mask-programmable ROM. The word organization is
selectable (BYTE mode : 2,097,152 words by 8 bits, WORD mode : 1,048,576 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The
µ
PD23C16040BL and
µ
PD23C16080BL are packed in 48-pin PLASTIC TSOP(I) and 44-pin PLASTIC SOP.
Features
• Word organization
2,097,152 words by 8 bits (BYTE mode)
1,048,576 words by 16 bits (WORD mode)
• Page access mode
BYTE mode : 8 byte random page access (
µ
PD23C16040BL)
16 byte random page access (
µ
PD23C16080BL)
WORD mode : 4 word random page access (
µ
PD23C16040BL)
8 word random page access (
µ
PD23C16080BL)
• Operating supply voltage : VCC = 2.7 V to 3.6 V
Operating supply Access time / Power supply current (Active mode) Standby current
voltage Page access time mA (MAX.) (CMOS level input)
VCC ns (MAX.)
µ
PD23C16040BL
µ
PD23C16080BL
µ
A (MAX.)
3.0 V ± 0.3 V 90 / 25 40 55 30
3.3 V ± 0.3 V 85 / 25
2
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
Ordering Information
Part Number Package
µ
PD23C16040BLGY-xxx-MJH 48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent)
µ
PD23C16040BLGY-xxx-MKH 48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent)
µ
PD23C16040BLGX-xxx
Note 44-pin PLASTIC SOP (15.24 mm (600))
µ
PD23C16080BLGY-xxx-MJH 48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent)
µ
PD23C16080BLGY-xxx-MKH 48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent)
µ
PD23C16080BLGX-xxx
Note 44-pin PLASTIC SOP (15.24 mm (600))
Note Under development
(xxx : ROM code suffix No.)
3
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
Pin Configurations
/xxx indicates active low signal.
48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent)
[
µ
µµ
µ
PD23C16040BLGY-xxx-MJH ]
[
µ
µµ
µ
PD23C16080BLGY-xxx-MJH ]
Marking Side
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
/CE
GND
GND
O15, A−1
O7
O14
O6
O13
O5
O12
O4
V
CC
V
CC
NC
O11
O3
O10
O2
O9
O1
O8
O0
/OE or OE or DC
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A0 to A19 : Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1 : Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE : Mode select
/CE : Chip Enable
/OE or OE : Output Enable
VCC : Supply voltage
GND : Ground
NC Note : No Connection
DC : Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
4
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent)
[
µ
µµ
µ
PD23C16040BLGY-xxx-MKH ]
[
µ
µµ
µ
PD23C16080BLGY-xxx-MKH ]
Marking Side
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
/CE
GND
GND
O15, A−1
O7
O14
O6
O13
O5
O12
O4
VCC
VCC
NC
O11
O3
O10
O2
O9
O1
O8
O0
/OE or OE or DC
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A0 to A19 : Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1 : Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE : Mode select
/CE : Chip Enable
/OE or OE : Output Enable
VCC : Supply voltage
GND : Ground
NC Note : No Connection
DC : Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
5
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
44-pin PLASTIC SOP (15.24 mm (600))
[
µ
µµ
µ
PD23C16040BLGX-xxx ]
[
µ
µµ
µ
PD23C16080BLGX-xxx ]
Marking Side
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
/CE
GND
/OE or OE or DC
O0
O8
O1
O9
O2
O10
O3
O11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
WORD, /BYTE
GND
O15, A−1
O7
O14
O6
O13
O5
O12
O4
V
CC
A0 to A19 : Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1 : Data output 15 (WORD mode),
LSB Address input (BYTE mode)
WORD, /BYTE : Mode select
/CE : Chip Enable
/OE or OE : Output Enable
VCC : Supply voltage
GND : Ground
NC Note : No Connection
DC : Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
6
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
Input / Output Pin Functions
Pin name Input / Output Function
WORD, /BYTE Input The pin for switching WORD mode and BYTE mode.
High level : WORD mode (1M-word by 16-bit)
Low level : BYTE mode (2M-word by 8-bit)
A0 to A19
(Address inputs)
Input Address input pins.
A0 to A19 are used differently in the WORD mode and the BYTE mode.
WORD mode (1M-word by 16-bit)
A0 to A19 are used as 20 bits address signals.
BYTE mode (2M-word by 8-bit)
A0 to A19 are used as the upper 20 bits of total 21 bits of address signal.
(The least significant bit (A−1) is combined to O15.)
O0 to O7, O8 to O14
(Data outputs)
Output Data output pins.
O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode.
WORD mode (1M-word by 16-bit)
The lower 15 bits of 16 bits data outputs to O0 to O14.
(The most significant bit (O15) combined to A−1.)
BYTE mode (2M-word by 8-bit)
8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance.
O15, A−1
(Data output 15,
LSB Address input)
Output, Input O15, A−1 are used differently in the WORD mode and the BYTE mode.
WORD mode (1M-word by 16-bit)
The most significant output data bus (O15).
BYTE mode (2M-word by 8-bit)
The least significant address bus (A−1).
/CE
(Chip Enable)
Input Chip activating signal.
When the OE is active, output states are following.
High level : High-Z
Low level : Data out
/OE or OE or DC
(Output Enable, Don't care)
Input Output enable signal. The active level of OE is mask option. The active level of OE
can be selected from high active, low active and Don’t care at order.
VCC −Supply voltage
GND −Ground
NC −Not internally connected. (The signal can be connected.)
7
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
O15, A 1
WORD, /BYTE
/OE or OE or DC
/CE
Output Buffer
Y-Selector
Memory Cell Matrix
1,048,576 words by 16 bits /
2,097,152 words by 8 bits
Address Input Buffer
X-Decoder
Logic/InputInput Buffer
Y-Decoder
A19
O14O13
O12O11
O10O9
O8
O0 O1 O2 O3 O4 O5 O6 O7
8
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
Mask Option
The active levels of output enable pin (/OE or OE or DC) are mask programmable and optional, and can be selected
from among " 0 " " 1 " " x " shown in the table below.
Option /OE or OE or DC OE active level
0/OE L
1OE H
x DC Don’t care
Operation modes for each option are shown in the tables below.
Operation mode (Option : 0)
/CE /OE Mode Output state
L L Active Data out
H High-Z
H H or L Standby High-Z
Operation mode (Option : 1)
/CE OE Mode Output state
L L Active High-Z
H Data out
H H or L Standby High-Z
Operation mode (Option : x)
/CE DC Mode Output state
L H or L Active Data out
H H or L Standby High-Z
Remark L : Low level input
H : High level input
9
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Supply voltage VCC –0.3 to +4.6 V
Input voltage VI–0.3 to VCC+0.3 V
Output voltage VO–0.3 to VCC+0.3 V
Operating ambient temperature TA–10 to +70 °C
Storage temperature Tstg –65 to +150 °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Capacitance (TA = 25 °C)
Parameter Symbol Test condition MIN. TYP. MAX. Unit
Input capacitance CIf = 1 MHz 10 pF
Output capacitance CO12 pF
DC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter Symbol Test conditions MIN. TYP. MAX. Unit
High level input voltage VIH 2.0 VCC + 0.3 V
Low level input voltage VIL VCC = 3.0 V ± 0.3 V –0.3 +0.5 V
VCC = 3.3 V ± 0.3 V –0.3 +0.8
High level output voltage VOH IOH = –100
µ
A2.4V
Low level output voltage VOL IOL = 2.1 mA 0.4 V
Input leakage current ILI VI = 0 V to VCC –10 +10
µ
A
Output leakage current ILO VO = 0 V to VCC, Chip deselected –10 +10
µ
A
Power supply current ICC1 /CE = VIL (Active
µ
PD23C16040BL VCC = 3.0 V ± 0.3 V 40 mA
mode), IO = 0 mA VCC = 3.3 V ± 0.3 V 40
µ
PD23C16080BL VCC = 3.0 V ± 0.3 V 55
VCC = 3.3 V ± 0.3 V 55
Standby current ICC3 /CE = VCC – 0.2 V (Standby mode) 30
µ
A
10
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
AC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter Symbol Test condition VCC = 3.0 V ± 0.3 V VCC = 3.3 V ± 0.3 V Unit
MIN. TYP. MAX. MIN. TYP. MAX.
Address access time tACC 90 85 ns
Page access time tPAC 25 25 ns
Address skew time tSKEW Note 10 10 ns
Chip enable access time tCE 90 85 ns
Output enable access time tOE 25 25 ns
Output hold time tOH 00ns
Output disable time tDF 0 25 0 25 ns
WORD, /BYTE access time tWB 90 85 ns
Note tSKEW indicates the following three types of time depending on the condition.
1) When switching /CE from high level to low level, tSKEW is the time from the /CE low level input point until the
next address is determined.
2) When switching /CE from low level to high level, tSKEW is the time from the address change start point to the
/CE high level input point.
3) When /CE is fixed to low level, tSKEW is the time from the address change start point until the next address is
determined.
Since specs are defined for tSKEW only when /CE is active, tSKEW is not subject to limitations when /CE is switched
from high level to low level following address determination, or when the address is changed after /CE is switched
from low level to high level.
Remark tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
AC Test Conditions
Input waveform (Rise / Fall time ≤
≤≤
≤ 5 ns)
Test points1.4 V 1.4 V
Output waveform
Test points1.4 V 1.4 V
Output load
1TTL + 100 pF
11
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
Cautions on power application
To ensure normal operation, always apply power using /CE following the procedure shown below.
1) Input a high level to /CE during and after power application.
2) Hold the high level input to /CE for 200 ns or longer (wait time).
3) Start normal operation after the wait time has elapsed.
Power Application Timing Chart 1 (When /CE is made high at power application)
Wait time
200 ns or longer
Normal operation
/CE (Input)
V
CC
Power Application Timing Chart 2 (When /CE is made high after power application)
Wait time
200 ns or longer
Normal operation
/CE (Input)
V
CC
Caution Other signals can be either high or low during the wait time.
12
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
Read Cycle Timing Chart 1
t
ACC
t
OH
t
CE
t
OE
t
SKEW
t
SKEW
t
SKEW
t
OH
t
OH
t
DF Note2
t
DF Note2
t
ACC
t
ACC
Data out Data out Data out
(Input)
(Input)
(Input)
(Input)
A0 to A19,
A−1
Note1
O0 to O7,
O8 to O15
Note3
/CE
/OE or OE
High-ZHigh-Z
Notes 1. During WORD mode, A–1 is O15.
2. tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
3. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.
13
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
Read Cycle Timing Chart 2 (Page Access Mode)
(Input)
/CE (Input)
/OE or OE (Input)
tACC
Data Out
tCE
tOE
t
PAC
Note 5
tPAC Note 5
O0 to O7,
O8 to O15 Note 4
(Input)
(Output) Data Out Data Out
High-Z High-Z
tOH tOH tOH
tDF Note 3
A2 to A19
A3 to A19
Upper address Note 1
A–1 Note 2, A0, A1
A–1 Note 2, A0, A1, A2
Page address Note 1
Notes 1. The address differs depending on the product as follows.
Part Number Upper address Page address
µ
PD23C16040BL A2 to A19 A–1, A0, A1
µ
PD23C16080BL A3 to A19 A–1, A0, A1, A2
2. During WORD mode, A–1 is O15.
3. tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
4. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.
5. The definition of page access time is as follows.
[
µ
µµ
µ
PD23C16040BL ]
Page access time Upper address (A2 to A19) /CE input condition /OE or OE input condition
inputs condition
tPAC Before tACC – tPAC Before tCE – tPAC Before stabilizing of page
address (A–1, A0, A1)
[
µ
µµ
µ
PD23C16080BL ]
Page access time Upper address (A3 to A19) /CE input condition /OE or OE input condition
inputs condition
tPAC Before tACC – tPAC Before tCE – tPAC Before stabilizing of page
address (A–1, A0, A1, A2)
14
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
WORD, /BYTE Switch Timing Chart
Data Out
A–1 (Input)
WORD, /BYTE (Input)
Data Out Data Out
O0 to O7 (Output)
O8 to O15 (Output)
t
OH
t
ACC
t
OH
t
WB
Data Out Data Out
t
DF
High-Z
High-Z
High-Z
Remark Chip Enable (/CE) and Output Enable (/OE or OE) : Active.
15
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
Package Drawings
NOTES
48-PIN PLASTIC TSOP(I) (12x18)
ITEM MILLIMETERS
A
B
C
E
I
12.0±0.1
0.5 (T.P.)
0.1±0.05
0.45 MAX.
K
1.2 MAX.
16.4±0.1
0.145±0.05
F
0.10M
D 0.22±0.05
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
R
K
L
1.0±0.05G
L 0.5
0.10N
P 18.0±0.2
Q3°+5°
−3°
0.25R
S48GY-50-MJH1-1
S 0.60±0.15
J 0.8±0.2
S
Q
SN
E
G
F
J
detail of lead end
C
D
M
MB
A
I
P
1
24
48
25
S
16
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
0.145±0.05
NOTES
48-PIN PLASTIC TSOP(I) (12x18)
ITEM MILLIMETERS
A
B
C
E
I
12.0±0.1
0.5 (T.P.)
0.1±0.05
0.45 MAX.
K
1.2 MAX.
16.4±0.1
F
0.10M
D 0.22±0.05
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
CB
R
KD
M
M
1.0±0.05G
L 0.5
0.10N
P 18.0±0.2
Q3°+5°
−3°
0.25R
S48GY-50-MKH1-1
S 0.60±0.15
J 0.8±0.2
SN
J
G
F
L
S
Q
E
detail of lead end
1
24
48
25
S
A
I
P
17
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
44-PIN PLASTIC SOP (15.24 mm (600))
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
C0.78 MAX.
B1.27 (T.P.)
E 0.15±0.1
F 3.0 MAX.
G 2.7±0.05
H16.04±0.3
I13.24±0.1
J1.4±0.2
M0.12
N0.10
L 0.8±0.2
K 0.22+0.08
−0.07
P3°+7°
−3°
D 0.42+0.08
−0.07
A 27.83+0.4
−0.05
P44GX-50-600A-4
K
L
G
P
DM
B
J
detail of lead end
SN
M
F
E
C
44 23
122
S
H
I
A
18
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
µ
PD23C16040BL and
µ
PD23C16080BL.
Types of Surface Mount Device
µ
PD23C16040BLGY-MJH : 48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent)
µ
PD23C16040BLGY-MKH : 48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent)
µ
PD23C16040BLGX : 44-pin PLASTIC SOP (15.24 mm (600))
µ
PD23C16080BLGY-MJH : 48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent)
µ
PD23C16080BLGY-MKH : 48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent)
µ
PD23C16080BLGX : 44-pin PLASTIC SOP (15.24 mm (600))
19
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
Revision History
Edition/ Page Type of Location Description
Date This Previous revision (Previous edition → This edition)
edition edition
3rd edition/ Throughout Throughout Modification Preliminary Data Sheet → Data Sheet
Mar. 2003 p.2 p.2 Addition Ordering Information Under development (44-pin PLASTIC SOP)
p.10 p.10 Addition AC Characteristics Address skew time (tSKEW)
Note
p.11 – Addition Cautions on power application
p.12 p.11 Modification Read Cycle Timing Chart 1
20
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
[MEMO]
21
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
[MEMO]
22
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
[MEMO]
23
µ
µµ
µ
PD23C16040BL, 23C16080BL
Data Sheet M15720EJ3V0DS
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
Note:
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
HANDLING OF THE APPLIED WAVEFORM OF INPUT PINS AND THE UNUSED INPUT PINS
FOR CMOS
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Input levels of CMOS devices must be fixed. CMOS devices behave differently than Bipolar or
NMOS devices. If the input of a CMOS device stays in an area that is between V
IL
(MAX.) and
V
IH
(MIN.) due to the effects of noise or some other irregularity, malfunction may result.
Therefore, not only the input waveform is fixed, but also the waveform changes, it is important
to use the CMOS device under AC test conditions. For unused input pins in particular, CMOS
devices should not be operated in a state where nothing is connected, so input levels of CMOS
devices must be fixed to high or low by using pull-up or pull-down circuitry. Each unused pin
should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device
and related specifications governing the devices.
µ
µµ
µ
PD23C16040BL, 23C16080BL
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M8E 02. 11-1
